1#ifndef HDMI_XML
   2#define HDMI_XML
   3
   4/* Autogenerated file, DO NOT EDIT manually!
   5
   6This file was generated by the rules-ng-ng headergen tool in this git repository:
   7http://github.com/freedreno/envytools/
   8git clone https://github.com/freedreno/envytools.git
   9
  10The rules-ng-ng source files this header was generated from are:
  11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2015-05-20 20:03:14)
  12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2016-02-10 17:07:21)
  13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-05-20 20:03:14)
  14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2015-09-18 12:07:28)
  15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  37194 bytes, from 2015-09-18 12:07:28)
  16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  27887 bytes, from 2015-10-22 16:34:52)
  17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2015-10-22 16:35:02)
  18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2015-05-20 20:03:14)
  19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2015-05-20 20:03:07)
  20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  41472 bytes, from 2016-01-22 18:18:18)
  21- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-20 20:03:14)
 
 
 
 
 
 
 
 
  22
  23Copyright (C) 2013-2016 by the following authors:
  24- Rob Clark <robdclark@gmail.com> (robclark)
  25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26
  27Permission is hereby granted, free of charge, to any person obtaining
  28a copy of this software and associated documentation files (the
  29"Software"), to deal in the Software without restriction, including
  30without limitation the rights to use, copy, modify, merge, publish,
  31distribute, sublicense, and/or sell copies of the Software, and to
  32permit persons to whom the Software is furnished to do so, subject to
  33the following conditions:
  34
  35The above copyright notice and this permission notice (including the
  36next paragraph) shall be included in all copies or substantial
  37portions of the Software.
  38
  39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46*/
  47
  48
  49enum hdmi_hdcp_key_state {
  50	HDCP_KEYS_STATE_NO_KEYS = 0,
  51	HDCP_KEYS_STATE_NOT_CHECKED = 1,
  52	HDCP_KEYS_STATE_CHECKING = 2,
  53	HDCP_KEYS_STATE_VALID = 3,
  54	HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
  55	HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
  56	HDCP_KEYS_STATE_PROD_AKSV = 6,
  57	HDCP_KEYS_STATE_RESERVED = 7,
  58};
  59
  60enum hdmi_ddc_read_write {
  61	DDC_WRITE = 0,
  62	DDC_READ = 1,
  63};
  64
  65enum hdmi_acr_cts {
  66	ACR_NONE = 0,
  67	ACR_32 = 1,
  68	ACR_44 = 2,
  69	ACR_48 = 3,
  70};
  71
  72#define REG_HDMI_CTRL						0x00000000
  73#define HDMI_CTRL_ENABLE					0x00000001
  74#define HDMI_CTRL_HDMI						0x00000002
  75#define HDMI_CTRL_ENCRYPTED					0x00000004
  76
  77#define REG_HDMI_AUDIO_PKT_CTRL1				0x00000020
  78#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND			0x00000001
  79
  80#define REG_HDMI_ACR_PKT_CTRL					0x00000024
  81#define HDMI_ACR_PKT_CTRL_CONT					0x00000001
  82#define HDMI_ACR_PKT_CTRL_SEND					0x00000002
  83#define HDMI_ACR_PKT_CTRL_SELECT__MASK				0x00000030
  84#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT				4
  85static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
  86{
  87	return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
  88}
  89#define HDMI_ACR_PKT_CTRL_SOURCE				0x00000100
  90#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK			0x00070000
  91#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT			16
  92static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
  93{
  94	return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
  95}
  96#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY			0x80000000
  97
  98#define REG_HDMI_VBI_PKT_CTRL					0x00000028
  99#define HDMI_VBI_PKT_CTRL_GC_ENABLE				0x00000010
 100#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME			0x00000020
 101#define HDMI_VBI_PKT_CTRL_ISRC_SEND				0x00000100
 102#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS			0x00000200
 103#define HDMI_VBI_PKT_CTRL_ACP_SEND				0x00001000
 104#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW				0x00002000
 105
 106#define REG_HDMI_INFOFRAME_CTRL0				0x0000002c
 107#define HDMI_INFOFRAME_CTRL0_AVI_SEND				0x00000001
 108#define HDMI_INFOFRAME_CTRL0_AVI_CONT				0x00000002
 109#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND			0x00000010
 110#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT			0x00000020
 111#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE			0x00000040
 112#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE			0x00000080
 113
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 114#define REG_HDMI_GEN_PKT_CTRL					0x00000034
 115#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND				0x00000001
 116#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT				0x00000002
 117#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK			0x0000000c
 118#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT		2
 119static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
 120{
 121	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
 122}
 123#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND				0x00000010
 124#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT				0x00000020
 125#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK			0x003f0000
 126#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT			16
 127static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
 128{
 129	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
 130}
 131#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK			0x3f000000
 132#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT			24
 133static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
 134{
 135	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
 136}
 137
 138#define REG_HDMI_GC						0x00000040
 139#define HDMI_GC_MUTE						0x00000001
 140
 141#define REG_HDMI_AUDIO_PKT_CTRL2				0x00000044
 142#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE				0x00000001
 143#define HDMI_AUDIO_PKT_CTRL2_LAYOUT				0x00000002
 144
 145static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
 146
 147#define REG_HDMI_GENERIC0_HDR					0x00000084
 148
 149static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
 150
 151#define REG_HDMI_GENERIC1_HDR					0x000000a4
 152
 153static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
 154
 155static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
 156
 157static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
 158#define HDMI_ACR_0_CTS__MASK					0xfffff000
 159#define HDMI_ACR_0_CTS__SHIFT					12
 160static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
 161{
 162	return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
 163}
 164
 165static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
 166#define HDMI_ACR_1_N__MASK					0xffffffff
 167#define HDMI_ACR_1_N__SHIFT					0
 168static inline uint32_t HDMI_ACR_1_N(uint32_t val)
 169{
 170	return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
 171}
 172
 173#define REG_HDMI_AUDIO_INFO0					0x000000e4
 174#define HDMI_AUDIO_INFO0_CHECKSUM__MASK				0x000000ff
 175#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT			0
 176static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
 177{
 178	return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
 179}
 180#define HDMI_AUDIO_INFO0_CC__MASK				0x00000700
 181#define HDMI_AUDIO_INFO0_CC__SHIFT				8
 182static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
 183{
 184	return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
 185}
 186
 187#define REG_HDMI_AUDIO_INFO1					0x000000e8
 188#define HDMI_AUDIO_INFO1_CA__MASK				0x000000ff
 189#define HDMI_AUDIO_INFO1_CA__SHIFT				0
 190static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
 191{
 192	return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
 193}
 194#define HDMI_AUDIO_INFO1_LSV__MASK				0x00007800
 195#define HDMI_AUDIO_INFO1_LSV__SHIFT				11
 196static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
 197{
 198	return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
 199}
 200#define HDMI_AUDIO_INFO1_DM_INH					0x00008000
 201
 202#define REG_HDMI_HDCP_CTRL					0x00000110
 203#define HDMI_HDCP_CTRL_ENABLE					0x00000001
 204#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE			0x00000100
 205
 206#define REG_HDMI_HDCP_DEBUG_CTRL				0x00000114
 207#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER				0x00000004
 208
 209#define REG_HDMI_HDCP_INT_CTRL					0x00000118
 210#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT			0x00000001
 211#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK			0x00000002
 212#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK			0x00000004
 213#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT			0x00000010
 214#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK			0x00000020
 215#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK			0x00000040
 216#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK			0x00000080
 217#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT			0x00000100
 218#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK			0x00000200
 219#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK			0x00000400
 220#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT			0x00001000
 221#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK			0x00002000
 222#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK			0x00004000
 223
 224#define REG_HDMI_HDCP_LINK0_STATUS				0x0000011c
 225#define HDMI_HDCP_LINK0_STATUS_AN_0_READY			0x00000100
 226#define HDMI_HDCP_LINK0_STATUS_AN_1_READY			0x00000200
 227#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES			0x00001000
 228#define HDMI_HDCP_LINK0_STATUS_V_MATCHES			0x00100000
 229#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK			0x70000000
 230#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT			28
 231static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
 232{
 233	return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
 234}
 235
 236#define REG_HDMI_HDCP_DDC_CTRL_0				0x00000120
 237#define HDMI_HDCP_DDC_CTRL_0_DISABLE				0x00000001
 238
 239#define REG_HDMI_HDCP_DDC_CTRL_1				0x00000124
 240#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK				0x00000001
 241
 242#define REG_HDMI_HDCP_DDC_STATUS				0x00000128
 243#define HDMI_HDCP_DDC_STATUS_XFER_REQ				0x00000010
 244#define HDMI_HDCP_DDC_STATUS_XFER_DONE				0x00000400
 245#define HDMI_HDCP_DDC_STATUS_ABORTED				0x00001000
 246#define HDMI_HDCP_DDC_STATUS_TIMEOUT				0x00002000
 247#define HDMI_HDCP_DDC_STATUS_NACK0				0x00004000
 248#define HDMI_HDCP_DDC_STATUS_NACK1				0x00008000
 249#define HDMI_HDCP_DDC_STATUS_FAILED				0x00010000
 250
 251#define REG_HDMI_HDCP_ENTROPY_CTRL0				0x0000012c
 252
 253#define REG_HDMI_HDCP_ENTROPY_CTRL1				0x0000025c
 254
 255#define REG_HDMI_HDCP_RESET					0x00000130
 256#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE			0x00000001
 257
 258#define REG_HDMI_HDCP_RCVPORT_DATA0				0x00000134
 259
 260#define REG_HDMI_HDCP_RCVPORT_DATA1				0x00000138
 261
 262#define REG_HDMI_HDCP_RCVPORT_DATA2_0				0x0000013c
 263
 264#define REG_HDMI_HDCP_RCVPORT_DATA2_1				0x00000140
 265
 266#define REG_HDMI_HDCP_RCVPORT_DATA3				0x00000144
 267
 268#define REG_HDMI_HDCP_RCVPORT_DATA4				0x00000148
 269
 270#define REG_HDMI_HDCP_RCVPORT_DATA5				0x0000014c
 271
 272#define REG_HDMI_HDCP_RCVPORT_DATA6				0x00000150
 273
 274#define REG_HDMI_HDCP_RCVPORT_DATA7				0x00000154
 275
 276#define REG_HDMI_HDCP_RCVPORT_DATA8				0x00000158
 277
 278#define REG_HDMI_HDCP_RCVPORT_DATA9				0x0000015c
 279
 280#define REG_HDMI_HDCP_RCVPORT_DATA10				0x00000160
 281
 282#define REG_HDMI_HDCP_RCVPORT_DATA11				0x00000164
 283
 284#define REG_HDMI_HDCP_RCVPORT_DATA12				0x00000168
 285
 286#define REG_HDMI_VENSPEC_INFO0					0x0000016c
 287
 288#define REG_HDMI_VENSPEC_INFO1					0x00000170
 289
 290#define REG_HDMI_VENSPEC_INFO2					0x00000174
 291
 292#define REG_HDMI_VENSPEC_INFO3					0x00000178
 293
 294#define REG_HDMI_VENSPEC_INFO4					0x0000017c
 295
 296#define REG_HDMI_VENSPEC_INFO5					0x00000180
 297
 298#define REG_HDMI_VENSPEC_INFO6					0x00000184
 299
 300#define REG_HDMI_AUDIO_CFG					0x000001d0
 301#define HDMI_AUDIO_CFG_ENGINE_ENABLE				0x00000001
 302#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK			0x000000f0
 303#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT			4
 304static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
 305{
 306	return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
 307}
 308
 309#define REG_HDMI_USEC_REFTIMER					0x00000208
 310
 311#define REG_HDMI_DDC_CTRL					0x0000020c
 312#define HDMI_DDC_CTRL_GO					0x00000001
 313#define HDMI_DDC_CTRL_SOFT_RESET				0x00000002
 314#define HDMI_DDC_CTRL_SEND_RESET				0x00000004
 315#define HDMI_DDC_CTRL_SW_STATUS_RESET				0x00000008
 316#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK			0x00300000
 317#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT			20
 318static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
 319{
 320	return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
 321}
 322
 323#define REG_HDMI_DDC_ARBITRATION				0x00000210
 324#define HDMI_DDC_ARBITRATION_HW_ARBITRATION			0x00000010
 325
 326#define REG_HDMI_DDC_INT_CTRL					0x00000214
 327#define HDMI_DDC_INT_CTRL_SW_DONE_INT				0x00000001
 328#define HDMI_DDC_INT_CTRL_SW_DONE_ACK				0x00000002
 329#define HDMI_DDC_INT_CTRL_SW_DONE_MASK				0x00000004
 330
 331#define REG_HDMI_DDC_SW_STATUS					0x00000218
 332#define HDMI_DDC_SW_STATUS_NACK0				0x00001000
 333#define HDMI_DDC_SW_STATUS_NACK1				0x00002000
 334#define HDMI_DDC_SW_STATUS_NACK2				0x00004000
 335#define HDMI_DDC_SW_STATUS_NACK3				0x00008000
 336
 337#define REG_HDMI_DDC_HW_STATUS					0x0000021c
 338#define HDMI_DDC_HW_STATUS_DONE					0x00000008
 339
 340#define REG_HDMI_DDC_SPEED					0x00000220
 341#define HDMI_DDC_SPEED_THRESHOLD__MASK				0x00000003
 342#define HDMI_DDC_SPEED_THRESHOLD__SHIFT				0
 343static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
 344{
 345	return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
 346}
 347#define HDMI_DDC_SPEED_PRESCALE__MASK				0xffff0000
 348#define HDMI_DDC_SPEED_PRESCALE__SHIFT				16
 349static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
 350{
 351	return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
 352}
 353
 354#define REG_HDMI_DDC_SETUP					0x00000224
 355#define HDMI_DDC_SETUP_TIMEOUT__MASK				0xff000000
 356#define HDMI_DDC_SETUP_TIMEOUT__SHIFT				24
 357static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
 358{
 359	return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
 360}
 361
 362static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
 363
 364static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
 365#define HDMI_I2C_TRANSACTION_REG_RW__MASK			0x00000001
 366#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT			0
 367static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
 368{
 369	return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
 370}
 371#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK			0x00000100
 372#define HDMI_I2C_TRANSACTION_REG_START				0x00001000
 373#define HDMI_I2C_TRANSACTION_REG_STOP				0x00002000
 374#define HDMI_I2C_TRANSACTION_REG_CNT__MASK			0x00ff0000
 375#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT			16
 376static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
 377{
 378	return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
 379}
 380
 381#define REG_HDMI_DDC_DATA					0x00000238
 382#define HDMI_DDC_DATA_DATA_RW__MASK				0x00000001
 383#define HDMI_DDC_DATA_DATA_RW__SHIFT				0
 384static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
 385{
 386	return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
 387}
 388#define HDMI_DDC_DATA_DATA__MASK				0x0000ff00
 389#define HDMI_DDC_DATA_DATA__SHIFT				8
 390static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
 391{
 392	return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
 393}
 394#define HDMI_DDC_DATA_INDEX__MASK				0x00ff0000
 395#define HDMI_DDC_DATA_INDEX__SHIFT				16
 396static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
 397{
 398	return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
 399}
 400#define HDMI_DDC_DATA_INDEX_WRITE				0x80000000
 401
 402#define REG_HDMI_HDCP_SHA_CTRL					0x0000023c
 403
 404#define REG_HDMI_HDCP_SHA_STATUS				0x00000240
 405#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE				0x00000001
 406#define HDMI_HDCP_SHA_STATUS_COMP_DONE				0x00000010
 407
 408#define REG_HDMI_HDCP_SHA_DATA					0x00000244
 409#define HDMI_HDCP_SHA_DATA_DONE					0x00000001
 410
 411#define REG_HDMI_HPD_INT_STATUS					0x00000250
 412#define HDMI_HPD_INT_STATUS_INT					0x00000001
 413#define HDMI_HPD_INT_STATUS_CABLE_DETECTED			0x00000002
 414
 415#define REG_HDMI_HPD_INT_CTRL					0x00000254
 416#define HDMI_HPD_INT_CTRL_INT_ACK				0x00000001
 417#define HDMI_HPD_INT_CTRL_INT_CONNECT				0x00000002
 418#define HDMI_HPD_INT_CTRL_INT_EN				0x00000004
 419#define HDMI_HPD_INT_CTRL_RX_INT_ACK				0x00000010
 420#define HDMI_HPD_INT_CTRL_RX_INT_EN				0x00000020
 421#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK			0x00000200
 422
 423#define REG_HDMI_HPD_CTRL					0x00000258
 424#define HDMI_HPD_CTRL_TIMEOUT__MASK				0x00001fff
 425#define HDMI_HPD_CTRL_TIMEOUT__SHIFT				0
 426static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
 427{
 428	return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
 429}
 430#define HDMI_HPD_CTRL_ENABLE					0x10000000
 431
 432#define REG_HDMI_DDC_REF					0x0000027c
 433#define HDMI_DDC_REF_REFTIMER_ENABLE				0x00010000
 434#define HDMI_DDC_REF_REFTIMER__MASK				0x0000ffff
 435#define HDMI_DDC_REF_REFTIMER__SHIFT				0
 436static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
 437{
 438	return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
 439}
 440
 441#define REG_HDMI_HDCP_SW_UPPER_AKSV				0x00000284
 442
 443#define REG_HDMI_HDCP_SW_LOWER_AKSV				0x00000288
 444
 445#define REG_HDMI_CEC_CTRL					0x0000028c
 446
 447#define REG_HDMI_CEC_WR_DATA					0x00000290
 448
 449#define REG_HDMI_CEC_CEC_RETRANSMIT				0x00000294
 450
 451#define REG_HDMI_CEC_STATUS					0x00000298
 452
 453#define REG_HDMI_CEC_INT					0x0000029c
 454
 455#define REG_HDMI_CEC_ADDR					0x000002a0
 456
 457#define REG_HDMI_CEC_TIME					0x000002a4
 458
 459#define REG_HDMI_CEC_REFTIMER					0x000002a8
 460
 461#define REG_HDMI_CEC_RD_DATA					0x000002ac
 462
 463#define REG_HDMI_CEC_RD_FILTER					0x000002b0
 464
 465#define REG_HDMI_ACTIVE_HSYNC					0x000002b4
 466#define HDMI_ACTIVE_HSYNC_START__MASK				0x00000fff
 467#define HDMI_ACTIVE_HSYNC_START__SHIFT				0
 468static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
 469{
 470	return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
 471}
 472#define HDMI_ACTIVE_HSYNC_END__MASK				0x0fff0000
 473#define HDMI_ACTIVE_HSYNC_END__SHIFT				16
 474static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
 475{
 476	return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
 477}
 478
 479#define REG_HDMI_ACTIVE_VSYNC					0x000002b8
 480#define HDMI_ACTIVE_VSYNC_START__MASK				0x00000fff
 481#define HDMI_ACTIVE_VSYNC_START__SHIFT				0
 482static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
 483{
 484	return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
 485}
 486#define HDMI_ACTIVE_VSYNC_END__MASK				0x0fff0000
 487#define HDMI_ACTIVE_VSYNC_END__SHIFT				16
 488static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
 489{
 490	return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
 491}
 492
 493#define REG_HDMI_VSYNC_ACTIVE_F2				0x000002bc
 494#define HDMI_VSYNC_ACTIVE_F2_START__MASK			0x00000fff
 495#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT			0
 496static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
 497{
 498	return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
 499}
 500#define HDMI_VSYNC_ACTIVE_F2_END__MASK				0x0fff0000
 501#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT				16
 502static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
 503{
 504	return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
 505}
 506
 507#define REG_HDMI_TOTAL						0x000002c0
 508#define HDMI_TOTAL_H_TOTAL__MASK				0x00000fff
 509#define HDMI_TOTAL_H_TOTAL__SHIFT				0
 510static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
 511{
 512	return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
 513}
 514#define HDMI_TOTAL_V_TOTAL__MASK				0x0fff0000
 515#define HDMI_TOTAL_V_TOTAL__SHIFT				16
 516static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
 517{
 518	return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
 519}
 520
 521#define REG_HDMI_VSYNC_TOTAL_F2					0x000002c4
 522#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK			0x00000fff
 523#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT			0
 524static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
 525{
 526	return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
 527}
 528
 529#define REG_HDMI_FRAME_CTRL					0x000002c8
 530#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR				0x00001000
 531#define HDMI_FRAME_CTRL_VSYNC_LOW				0x10000000
 532#define HDMI_FRAME_CTRL_HSYNC_LOW				0x20000000
 533#define HDMI_FRAME_CTRL_INTERLACED_EN				0x80000000
 534
 535#define REG_HDMI_AUD_INT					0x000002cc
 536#define HDMI_AUD_INT_AUD_FIFO_URUN_INT				0x00000001
 537#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK				0x00000002
 538#define HDMI_AUD_INT_AUD_SAM_DROP_INT				0x00000004
 539#define HDMI_AUD_INT_AUD_SAM_DROP_MASK				0x00000008
 540
 541#define REG_HDMI_PHY_CTRL					0x000002d4
 542#define HDMI_PHY_CTRL_SW_RESET_PLL				0x00000001
 543#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW				0x00000002
 544#define HDMI_PHY_CTRL_SW_RESET					0x00000004
 545#define HDMI_PHY_CTRL_SW_RESET_LOW				0x00000008
 546
 547#define REG_HDMI_CEC_WR_RANGE					0x000002dc
 548
 549#define REG_HDMI_CEC_RD_RANGE					0x000002e0
 550
 551#define REG_HDMI_VERSION					0x000002e4
 552
 553#define REG_HDMI_CEC_COMPL_CTL					0x00000360
 554
 555#define REG_HDMI_CEC_RD_START_RANGE				0x00000364
 556
 557#define REG_HDMI_CEC_RD_TOTAL_RANGE				0x00000368
 558
 559#define REG_HDMI_CEC_RD_ERR_RESP_LO				0x0000036c
 560
 561#define REG_HDMI_CEC_WR_CHECK_CONFIG				0x00000370
 562
 563#define REG_HDMI_8x60_PHY_REG0					0x00000000
 564#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK			0x0000001c
 565#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT		2
 566static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
 567{
 568	return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
 569}
 570
 571#define REG_HDMI_8x60_PHY_REG1					0x00000004
 572#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK			0x000000f0
 573#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT			4
 574static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
 575{
 576	return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
 577}
 578#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK		0x0000000f
 579#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT		0
 580static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
 581{
 582	return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
 583}
 584
 585#define REG_HDMI_8x60_PHY_REG2					0x00000008
 586#define HDMI_8x60_PHY_REG2_PD_DESER				0x00000001
 587#define HDMI_8x60_PHY_REG2_PD_DRIVE_1				0x00000002
 588#define HDMI_8x60_PHY_REG2_PD_DRIVE_2				0x00000004
 589#define HDMI_8x60_PHY_REG2_PD_DRIVE_3				0x00000008
 590#define HDMI_8x60_PHY_REG2_PD_DRIVE_4				0x00000010
 591#define HDMI_8x60_PHY_REG2_PD_PLL				0x00000020
 592#define HDMI_8x60_PHY_REG2_PD_PWRGEN				0x00000040
 593#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN				0x00000080
 594
 595#define REG_HDMI_8x60_PHY_REG3					0x0000000c
 596#define HDMI_8x60_PHY_REG3_PLL_ENABLE				0x00000001
 597
 598#define REG_HDMI_8x60_PHY_REG4					0x00000010
 599
 600#define REG_HDMI_8x60_PHY_REG5					0x00000014
 601
 602#define REG_HDMI_8x60_PHY_REG6					0x00000018
 603
 604#define REG_HDMI_8x60_PHY_REG7					0x0000001c
 605
 606#define REG_HDMI_8x60_PHY_REG8					0x00000020
 607
 608#define REG_HDMI_8x60_PHY_REG9					0x00000024
 609
 610#define REG_HDMI_8x60_PHY_REG10					0x00000028
 611
 612#define REG_HDMI_8x60_PHY_REG11					0x0000002c
 613
 614#define REG_HDMI_8x60_PHY_REG12					0x00000030
 615#define HDMI_8x60_PHY_REG12_RETIMING_EN				0x00000001
 616#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN			0x00000002
 617#define HDMI_8x60_PHY_REG12_FORCE_LOCK				0x00000010
 618
 619#define REG_HDMI_8960_PHY_REG0					0x00000000
 620
 621#define REG_HDMI_8960_PHY_REG1					0x00000004
 622
 623#define REG_HDMI_8960_PHY_REG2					0x00000008
 624
 625#define REG_HDMI_8960_PHY_REG3					0x0000000c
 626
 627#define REG_HDMI_8960_PHY_REG4					0x00000010
 628
 629#define REG_HDMI_8960_PHY_REG5					0x00000014
 630
 631#define REG_HDMI_8960_PHY_REG6					0x00000018
 632
 633#define REG_HDMI_8960_PHY_REG7					0x0000001c
 634
 635#define REG_HDMI_8960_PHY_REG8					0x00000020
 636
 637#define REG_HDMI_8960_PHY_REG9					0x00000024
 638
 639#define REG_HDMI_8960_PHY_REG10					0x00000028
 640
 641#define REG_HDMI_8960_PHY_REG11					0x0000002c
 642
 643#define REG_HDMI_8960_PHY_REG12					0x00000030
 644#define HDMI_8960_PHY_REG12_SW_RESET				0x00000020
 645#define HDMI_8960_PHY_REG12_PWRDN_B				0x00000080
 646
 647#define REG_HDMI_8960_PHY_REG_BIST_CFG				0x00000034
 648
 649#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL				0x00000038
 650
 651#define REG_HDMI_8960_PHY_REG_MISC0				0x0000003c
 652
 653#define REG_HDMI_8960_PHY_REG13					0x00000040
 654
 655#define REG_HDMI_8960_PHY_REG14					0x00000044
 656
 657#define REG_HDMI_8960_PHY_REG15					0x00000048
 658
 659#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG			0x00000000
 660
 661#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG			0x00000004
 662
 663#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0			0x00000008
 664
 665#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1			0x0000000c
 666
 667#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG			0x00000010
 668
 669#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG			0x00000014
 670
 671#define REG_HDMI_8960_PHY_PLL_PWRDN_B				0x00000018
 672#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL			0x00000002
 673#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B			0x00000008
 674
 675#define REG_HDMI_8960_PHY_PLL_SDM_CFG0				0x0000001c
 676
 677#define REG_HDMI_8960_PHY_PLL_SDM_CFG1				0x00000020
 678
 679#define REG_HDMI_8960_PHY_PLL_SDM_CFG2				0x00000024
 680
 681#define REG_HDMI_8960_PHY_PLL_SDM_CFG3				0x00000028
 682
 683#define REG_HDMI_8960_PHY_PLL_SDM_CFG4				0x0000002c
 684
 685#define REG_HDMI_8960_PHY_PLL_SSC_CFG0				0x00000030
 686
 687#define REG_HDMI_8960_PHY_PLL_SSC_CFG1				0x00000034
 688
 689#define REG_HDMI_8960_PHY_PLL_SSC_CFG2				0x00000038
 690
 691#define REG_HDMI_8960_PHY_PLL_SSC_CFG3				0x0000003c
 692
 693#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0			0x00000040
 694
 695#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1			0x00000044
 696
 697#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2			0x00000048
 698
 699#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0			0x0000004c
 700
 701#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1			0x00000050
 702
 703#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2			0x00000054
 704
 705#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3			0x00000058
 706
 707#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4			0x0000005c
 708
 709#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5			0x00000060
 710
 711#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6			0x00000064
 712
 713#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7			0x00000068
 714
 715#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL				0x0000006c
 716
 717#define REG_HDMI_8960_PHY_PLL_MISC0				0x00000070
 718
 719#define REG_HDMI_8960_PHY_PLL_MISC1				0x00000074
 720
 721#define REG_HDMI_8960_PHY_PLL_MISC2				0x00000078
 722
 723#define REG_HDMI_8960_PHY_PLL_MISC3				0x0000007c
 724
 725#define REG_HDMI_8960_PHY_PLL_MISC4				0x00000080
 726
 727#define REG_HDMI_8960_PHY_PLL_MISC5				0x00000084
 728
 729#define REG_HDMI_8960_PHY_PLL_MISC6				0x00000088
 730
 731#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0			0x0000008c
 732
 733#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1			0x00000090
 734
 735#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2			0x00000094
 736
 737#define REG_HDMI_8960_PHY_PLL_STATUS0				0x00000098
 738#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK			0x00000001
 739
 740#define REG_HDMI_8960_PHY_PLL_STATUS1				0x0000009c
 741
 742#define REG_HDMI_8x74_ANA_CFG0					0x00000000
 743
 744#define REG_HDMI_8x74_ANA_CFG1					0x00000004
 745
 746#define REG_HDMI_8x74_PD_CTRL0					0x00000010
 747
 748#define REG_HDMI_8x74_PD_CTRL1					0x00000014
 749
 750#define REG_HDMI_8x74_BIST_CFG0					0x00000034
 751
 752#define REG_HDMI_8x74_BIST_PATN0				0x0000003c
 753
 754#define REG_HDMI_8x74_BIST_PATN1				0x00000040
 755
 756#define REG_HDMI_8x74_BIST_PATN2				0x00000044
 757
 758#define REG_HDMI_8x74_BIST_PATN3				0x00000048
 759
 760#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG			0x00000000
 761
 762#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG			0x00000004
 763
 764#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG			0x00000008
 765
 766#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG			0x0000000c
 767
 768#define REG_HDMI_28nm_PHY_PLL_VREG_CFG				0x00000010
 769
 770#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG			0x00000014
 771
 772#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG				0x00000018
 773
 774#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG				0x0000001c
 775
 776#define REG_HDMI_28nm_PHY_PLL_GLB_CFG				0x00000020
 777#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B			0x00000001
 778#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B		0x00000002
 779#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B		0x00000004
 780#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE			0x00000008
 781
 782#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG			0x00000024
 783
 784#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG			0x00000028
 785
 786#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG				0x0000002c
 787
 788#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG				0x00000030
 789
 790#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG				0x00000034
 791
 792#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0				0x00000038
 793
 794#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1				0x0000003c
 795
 796#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2				0x00000040
 797
 798#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3				0x00000044
 799
 800#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4				0x00000048
 801
 802#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0				0x0000004c
 803
 804#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1				0x00000050
 805
 806#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2				0x00000054
 807
 808#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3				0x00000058
 809
 810#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0			0x0000005c
 811
 812#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1			0x00000060
 813
 814#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2			0x00000064
 815
 816#define REG_HDMI_28nm_PHY_PLL_TEST_CFG				0x00000068
 817#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET			0x00000001
 818
 819#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0				0x0000006c
 820
 821#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1				0x00000070
 822
 823#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2				0x00000074
 824
 825#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3				0x00000078
 826
 827#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4				0x0000007c
 828
 829#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5				0x00000080
 830
 831#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6				0x00000084
 832
 833#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7				0x00000088
 834
 835#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8				0x0000008c
 836
 837#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9				0x00000090
 838
 839#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10				0x00000094
 840
 841#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11				0x00000098
 842
 843#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG				0x0000009c
 844
 845#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL			0x000000a0
 846
 847#define REG_HDMI_8996_PHY_CFG					0x00000000
 848
 849#define REG_HDMI_8996_PHY_PD_CTL				0x00000004
 850
 851#define REG_HDMI_8996_PHY_MODE					0x00000008
 852
 853#define REG_HDMI_8996_PHY_MISR_CLEAR				0x0000000c
 854
 855#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0			0x00000010
 856
 857#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1			0x00000014
 858
 859#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0		0x00000018
 860
 861#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1		0x0000001c
 862
 863#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0			0x00000020
 864
 865#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1			0x00000024
 866
 867#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0			0x00000028
 868
 869#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1			0x0000002c
 870
 871#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0		0x00000030
 872
 873#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1		0x00000034
 874
 875#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0			0x00000038
 876
 877#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1			0x0000003c
 878
 879#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL				0x00000040
 880
 881#define REG_HDMI_8996_PHY_TXCAL_CFG0				0x00000044
 882
 883#define REG_HDMI_8996_PHY_TXCAL_CFG1				0x00000048
 884
 885#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL			0x0000004c
 886
 887#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL			0x00000050
 888
 889#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG			0x00000054
 890
 891#define REG_HDMI_8996_PHY_CLOCK					0x00000058
 892
 893#define REG_HDMI_8996_PHY_MISC1					0x0000005c
 894
 895#define REG_HDMI_8996_PHY_MISC2					0x00000060
 896
 897#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0			0x00000064
 898
 899#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1			0x00000068
 900
 901#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2			0x0000006c
 902
 903#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0			0x00000070
 904
 905#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1			0x00000074
 906
 907#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2			0x00000078
 908
 909#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0			0x0000007c
 910
 911#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1			0x00000080
 912
 913#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2			0x00000084
 914
 915#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3			0x00000088
 916
 917#define REG_HDMI_8996_PHY_POST_MISR_STATUS0			0x0000008c
 918
 919#define REG_HDMI_8996_PHY_POST_MISR_STATUS1			0x00000090
 920
 921#define REG_HDMI_8996_PHY_POST_MISR_STATUS2			0x00000094
 922
 923#define REG_HDMI_8996_PHY_POST_MISR_STATUS3			0x00000098
 924
 925#define REG_HDMI_8996_PHY_STATUS				0x0000009c
 926
 927#define REG_HDMI_8996_PHY_MISC3_STATUS				0x000000a0
 928
 929#define REG_HDMI_8996_PHY_MISC4_STATUS				0x000000a4
 930
 931#define REG_HDMI_8996_PHY_DEBUG_BUS0				0x000000a8
 932
 933#define REG_HDMI_8996_PHY_DEBUG_BUS1				0x000000ac
 934
 935#define REG_HDMI_8996_PHY_DEBUG_BUS2				0x000000b0
 936
 937#define REG_HDMI_8996_PHY_DEBUG_BUS3				0x000000b4
 938
 939#define REG_HDMI_8996_PHY_PHY_REVISION_ID0			0x000000b8
 940
 941#define REG_HDMI_8996_PHY_PHY_REVISION_ID1			0x000000bc
 942
 943#define REG_HDMI_8996_PHY_PHY_REVISION_ID2			0x000000c0
 944
 945#define REG_HDMI_8996_PHY_PHY_REVISION_ID3			0x000000c4
 946
 947#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1			0x00000000
 948
 949#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2			0x00000004
 950
 951#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE			0x00000008
 952
 953#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER			0x0000000c
 954
 955#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER			0x00000010
 956
 957#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1			0x00000014
 958
 959#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2			0x00000018
 960
 961#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1			0x0000001c
 962
 963#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2			0x00000020
 964
 965#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1			0x00000024
 966
 967#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2			0x00000028
 968
 969#define REG_HDMI_PHY_QSERDES_COM_POST_DIV			0x0000002c
 970
 971#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX			0x00000030
 972
 973#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x00000034
 974
 975#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1			0x00000038
 976
 977#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL			0x0000003c
 978
 979#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE		0x00000040
 980
 981#define REG_HDMI_PHY_QSERDES_COM_PLL_EN				0x00000044
 982
 983#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO			0x00000048
 984
 985#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0		0x0000004c
 986
 987#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0		0x00000050
 988
 989#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0		0x00000054
 990
 991#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1		0x00000058
 992
 993#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1		0x0000005c
 994
 995#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1		0x00000060
 996
 997#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2		0x00000064
 998
 999#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0			0x00000064
1000
1001#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2		0x00000068
1002
1003#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x00000068
1004
1005#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2		0x0000006c
1006
1007#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x0000006c
1008
1009#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM			0x00000070
1010
1011#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV			0x00000074
1012
1013#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0			0x00000078
1014
1015#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1			0x0000007c
1016
1017#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2			0x00000080
1018
1019#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1			0x00000080
1020
1021#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0		0x00000084
1022
1023#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1		0x00000088
1024
1025#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2		0x0000008c
1026
1027#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2			0x0000008c
1028
1029#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0		0x00000090
1030
1031#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1		0x00000094
1032
1033#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2		0x00000098
1034
1035#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3			0x00000098
1036
1037#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL			0x0000009c
1038
1039#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL			0x000000a0
1040
1041#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC			0x000000a4
1042
1043#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL		0x000000a8
1044
1045#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x000000a8
1046
1047#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL			0x000000ac
1048
1049#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL			0x000000b0
1050
1051#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL			0x000000b4
1052
1053#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2			0x000000b8
1054
1055#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL			0x000000bc
1056
1057#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2			0x000000c0
1058
1059#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM		0x000000c4
1060
1061#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN			0x000000c8
1062
1063#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG			0x000000cc
1064
1065#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0		0x000000d0
1066
1067#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1		0x000000d4
1068
1069#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2		0x000000d8
1070
1071#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x000000d8
1072
1073#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0		0x000000dc
1074
1075#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0		0x000000e0
1076
1077#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0		0x000000e4
1078
1079#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1		0x000000e8
1080
1081#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1		0x000000ec
1082
1083#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1		0x000000f0
1084
1085#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2		0x000000f4
1086
1087#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1		0x000000f4
1088
1089#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2		0x000000f8
1090
1091#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2		0x000000f8
1092
1093#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2		0x000000fc
1094
1095#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4			0x000000fc
1096
1097#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL		0x00000100
1098
1099#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN			0x00000104
1100
1101#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x00000108
1102
1103#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0000010c
1104
1105#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x00000110
1106
1107#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x00000114
1108
1109#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2		0x00000118
1110
1111#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1		0x00000118
1112
1113#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2		0x0000011c
1114
1115#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2		0x0000011c
1116
1117#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2		0x00000120
1118
1119#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL			0x00000124
1120
1121#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP			0x00000128
1122
1123#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0		0x0000012c
1124
1125#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0		0x00000130
1126
1127#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1		0x00000134
1128
1129#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1		0x00000138
1130
1131#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2		0x0000013c
1132
1133#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1		0x0000013c
1134
1135#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2		0x00000140
1136
1137#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2		0x00000140
1138
1139#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1		0x00000144
1140
1141#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2		0x00000148
1142
1143#define REG_HDMI_PHY_QSERDES_COM_SAR				0x0000014c
1144
1145#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK			0x00000150
1146
1147#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS		0x00000154
1148
1149#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS		0x00000158
1150
1151#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS			0x0000015c
1152
1153#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS		0x00000160
1154
1155#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS		0x00000164
1156
1157#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS		0x00000168
1158
1159#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS		0x0000016c
1160
1161#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL			0x00000170
1162
1163#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT			0x00000174
1164
1165#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL			0x00000178
1166
1167#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x0000017c
1168
1169#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG			0x00000180
1170
1171#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV			0x00000184
1172
1173#define REG_HDMI_PHY_QSERDES_COM_SW_RESET			0x00000188
1174
1175#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN			0x0000018c
1176
1177#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS			0x00000190
1178
1179#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG			0x00000194
1180
1181#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE		0x00000198
1182
1183#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL		0x0000019c
1184
1185#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0			0x000001a0
1186
1187#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1			0x000001a4
1188
1189#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2			0x000001a8
1190
1191#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3			0x000001ac
1192
1193#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL			0x000001b0
1194
1195#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1			0x000001b4
1196
1197#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2			0x000001b8
1198
1199#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1		0x000001bc
1200
1201#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2		0x000001c0
1202
1203#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5			0x000001c4
1204
1205#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO		0x00000000
1206
1207#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT			0x00000004
1208
1209#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE		0x00000008
1210
1211#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE		0x0000000c
1212
1213#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO		0x00000010
1214
1215#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE		0x00000014
1216
1217#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL		0x00000018
1218
1219#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH		0x0000001c
1220
1221#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN		0x00000020
1222
1223#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES		0x00000024
1224
1225#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP	0x00000028
1226
1227#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL			0x0000002c
1228
1229#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET		0x00000030
1230
1231#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN		0x00000034
1232
1233#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN	0x00000038
1234
1235#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND			0x0000003c
1236
1237#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL			0x00000040
1238
1239#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT		0x00000044
1240
1241#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN			0x00000048
1242
1243#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX		0x0000004c
1244
1245#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX		0x00000050
1246
1247#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET		0x00000054
1248
1249#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1			0x00000058
1250
1251#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2			0x0000005c
1252
1253#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT		0x00000060
1254
1255#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL		0x00000064
1256
1257#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x00000068
1258
1259#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV			0x0000006c
1260
1261#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN	0x00000070
1262
1263#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1		0x00000074
1264
1265#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2		0x00000078
1266
1267#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3		0x0000007c
1268
1269#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4		0x00000080
1270
1271#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5		0x00000084
1272
1273#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6		0x00000088
1274
1275#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7		0x0000008c
1276
1277#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8		0x00000090
1278
1279#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE			0x00000094
1280
1281#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE		0x00000098
1282
1283#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION	0x0000009c
1284
1285#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1			0x000000a0
1286
1287#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2			0x000000a4
1288
1289#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL		0x000000a8
1290
1291#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2		0x000000ac
1292
1293#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1			0x000000b0
1294
1295#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2			0x000000b4
1296
1297#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3			0x000000b8
1298
1299#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4			0x000000bc
1300
1301#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN			0x000000c0
1302
1303#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES		0x000000c4
1304
1305#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN		0x000000c8
1306
1307#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE		0x000000cc
1308
1309#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL			0x000000d0
1310
1311#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA		0x000000d4
1312
1313#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2	0x000000d8
1314
1315#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2	0x000000dc
1316
1317#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2	0x000000e0
1318
1319#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2	0x000000e4
1320
1321#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1	0x000000e8
1322
1323#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1	0x000000ec
1324
1325#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1	0x000000f0
1326
1327#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1	0x000000f4
1328
1329#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1			0x000000f8
1330
1331#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2			0x000000fc
1332
1333#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL	0x00000100
1334
1335#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS			0x00000104
1336
1337#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1		0x00000108
1338
1339#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2		0x0000010c
1340
1341#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV		0x00000110
1342
1343
1344#endif /* HDMI_XML */

   1#ifndef HDMI_XML
   2#define HDMI_XML
   3
   4/* Autogenerated file, DO NOT EDIT manually!
   5
   6This file was generated by the rules-ng-ng headergen tool in this git repository:
   7http://github.com/freedreno/envytools/
   8git clone https://github.com/freedreno/envytools.git
   9
  10The rules-ng-ng source files this header was generated from are:
  11- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml                   (    981 bytes, from 2021-06-05 21:37:42)
  12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2021-02-18 16:45:44)
  13- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-02-18 16:45:44)
  14- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-02-18 16:45:44)
  15- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-02-18 16:45:44)
  16- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml               (  15291 bytes, from 2021-06-15 22:36:13)
  17- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-06-05 21:37:42)
  18- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-05-21 19:18:08)
  19- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-05-21 19:18:08)
  20- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-05-21 19:18:08)
  21- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-05-21 19:18:08)
  22- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-05-21 19:18:08)
  23- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  10953 bytes, from 2021-05-21 19:18:08)
  24- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml       (  10900 bytes, from 2021-05-21 19:18:08)
  25- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-02-18 16:45:44)
  26- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-02-18 16:45:44)
  27- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-02-18 16:45:44)
  28- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-02-18 16:45:44)
  29- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-02-18 16:45:44)
  30
  31Copyright (C) 2013-2021 by the following authors:
  32- Rob Clark <robdclark@gmail.com> (robclark)
  33- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  34
  35Permission is hereby granted, free of charge, to any person obtaining
  36a copy of this software and associated documentation files (the
  37"Software"), to deal in the Software without restriction, including
  38without limitation the rights to use, copy, modify, merge, publish,
  39distribute, sublicense, and/or sell copies of the Software, and to
  40permit persons to whom the Software is furnished to do so, subject to
  41the following conditions:
  42
  43The above copyright notice and this permission notice (including the
  44next paragraph) shall be included in all copies or substantial
  45portions of the Software.
  46
  47THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  48EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  49MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  50IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  51LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  52OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  53WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  54*/
  55
  56
  57enum hdmi_hdcp_key_state {
  58	HDCP_KEYS_STATE_NO_KEYS = 0,
  59	HDCP_KEYS_STATE_NOT_CHECKED = 1,
  60	HDCP_KEYS_STATE_CHECKING = 2,
  61	HDCP_KEYS_STATE_VALID = 3,
  62	HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
  63	HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
  64	HDCP_KEYS_STATE_PROD_AKSV = 6,
  65	HDCP_KEYS_STATE_RESERVED = 7,
  66};
  67
  68enum hdmi_ddc_read_write {
  69	DDC_WRITE = 0,
  70	DDC_READ = 1,
  71};
  72
  73enum hdmi_acr_cts {
  74	ACR_NONE = 0,
  75	ACR_32 = 1,
  76	ACR_44 = 2,
  77	ACR_48 = 3,
  78};
  79
  80#define REG_HDMI_CTRL						0x00000000
  81#define HDMI_CTRL_ENABLE					0x00000001
  82#define HDMI_CTRL_HDMI						0x00000002
  83#define HDMI_CTRL_ENCRYPTED					0x00000004
  84
  85#define REG_HDMI_AUDIO_PKT_CTRL1				0x00000020
  86#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND			0x00000001
  87
  88#define REG_HDMI_ACR_PKT_CTRL					0x00000024
  89#define HDMI_ACR_PKT_CTRL_CONT					0x00000001
  90#define HDMI_ACR_PKT_CTRL_SEND					0x00000002
  91#define HDMI_ACR_PKT_CTRL_SELECT__MASK				0x00000030
  92#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT				4
  93static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
  94{
  95	return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
  96}
  97#define HDMI_ACR_PKT_CTRL_SOURCE				0x00000100
  98#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK			0x00070000
  99#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT			16
 100static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
 101{
 102	return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
 103}
 104#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY			0x80000000
 105
 106#define REG_HDMI_VBI_PKT_CTRL					0x00000028
 107#define HDMI_VBI_PKT_CTRL_GC_ENABLE				0x00000010
 108#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME			0x00000020
 109#define HDMI_VBI_PKT_CTRL_ISRC_SEND				0x00000100
 110#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS			0x00000200
 111#define HDMI_VBI_PKT_CTRL_ACP_SEND				0x00001000
 112#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW				0x00002000
 113
 114#define REG_HDMI_INFOFRAME_CTRL0				0x0000002c
 115#define HDMI_INFOFRAME_CTRL0_AVI_SEND				0x00000001
 116#define HDMI_INFOFRAME_CTRL0_AVI_CONT				0x00000002
 117#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND			0x00000010
 118#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT			0x00000020
 119#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE			0x00000040
 120#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE			0x00000080
 121
 122#define REG_HDMI_INFOFRAME_CTRL1				0x00000030
 123#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK		0x0000003f
 124#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT		0
 125static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
 126{
 127	return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
 128}
 129#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK		0x00003f00
 130#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT		8
 131static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
 132{
 133	return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
 134}
 135#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK		0x003f0000
 136#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT		16
 137static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
 138{
 139	return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
 140}
 141#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK		0x3f000000
 142#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT		24
 143static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
 144{
 145	return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
 146}
 147
 148#define REG_HDMI_GEN_PKT_CTRL					0x00000034
 149#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND				0x00000001
 150#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT				0x00000002
 151#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK			0x0000000c
 152#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT		2
 153static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
 154{
 155	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
 156}
 157#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND				0x00000010
 158#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT				0x00000020
 159#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK			0x003f0000
 160#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT			16
 161static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
 162{
 163	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
 164}
 165#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK			0x3f000000
 166#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT			24
 167static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
 168{
 169	return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
 170}
 171
 172#define REG_HDMI_GC						0x00000040
 173#define HDMI_GC_MUTE						0x00000001
 174
 175#define REG_HDMI_AUDIO_PKT_CTRL2				0x00000044
 176#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE				0x00000001
 177#define HDMI_AUDIO_PKT_CTRL2_LAYOUT				0x00000002
 178
 179static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
 180
 181#define REG_HDMI_GENERIC0_HDR					0x00000084
 182
 183static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
 184
 185#define REG_HDMI_GENERIC1_HDR					0x000000a4
 186
 187static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
 188
 189static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
 190
 191static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
 192#define HDMI_ACR_0_CTS__MASK					0xfffff000
 193#define HDMI_ACR_0_CTS__SHIFT					12
 194static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
 195{
 196	return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
 197}
 198
 199static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
 200#define HDMI_ACR_1_N__MASK					0xffffffff
 201#define HDMI_ACR_1_N__SHIFT					0
 202static inline uint32_t HDMI_ACR_1_N(uint32_t val)
 203{
 204	return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
 205}
 206
 207#define REG_HDMI_AUDIO_INFO0					0x000000e4
 208#define HDMI_AUDIO_INFO0_CHECKSUM__MASK				0x000000ff
 209#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT			0
 210static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
 211{
 212	return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
 213}
 214#define HDMI_AUDIO_INFO0_CC__MASK				0x00000700
 215#define HDMI_AUDIO_INFO0_CC__SHIFT				8
 216static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
 217{
 218	return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
 219}
 220
 221#define REG_HDMI_AUDIO_INFO1					0x000000e8
 222#define HDMI_AUDIO_INFO1_CA__MASK				0x000000ff
 223#define HDMI_AUDIO_INFO1_CA__SHIFT				0
 224static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
 225{
 226	return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
 227}
 228#define HDMI_AUDIO_INFO1_LSV__MASK				0x00007800
 229#define HDMI_AUDIO_INFO1_LSV__SHIFT				11
 230static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
 231{
 232	return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
 233}
 234#define HDMI_AUDIO_INFO1_DM_INH					0x00008000
 235
 236#define REG_HDMI_HDCP_CTRL					0x00000110
 237#define HDMI_HDCP_CTRL_ENABLE					0x00000001
 238#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE			0x00000100
 239
 240#define REG_HDMI_HDCP_DEBUG_CTRL				0x00000114
 241#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER				0x00000004
 242
 243#define REG_HDMI_HDCP_INT_CTRL					0x00000118
 244#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT			0x00000001
 245#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK			0x00000002
 246#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK			0x00000004
 247#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT			0x00000010
 248#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK			0x00000020
 249#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK			0x00000040
 250#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK			0x00000080
 251#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT			0x00000100
 252#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK			0x00000200
 253#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK			0x00000400
 254#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT			0x00001000
 255#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK			0x00002000
 256#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK			0x00004000
 257
 258#define REG_HDMI_HDCP_LINK0_STATUS				0x0000011c
 259#define HDMI_HDCP_LINK0_STATUS_AN_0_READY			0x00000100
 260#define HDMI_HDCP_LINK0_STATUS_AN_1_READY			0x00000200
 261#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES			0x00001000
 262#define HDMI_HDCP_LINK0_STATUS_V_MATCHES			0x00100000
 263#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK			0x70000000
 264#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT			28
 265static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
 266{
 267	return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
 268}
 269
 270#define REG_HDMI_HDCP_DDC_CTRL_0				0x00000120
 271#define HDMI_HDCP_DDC_CTRL_0_DISABLE				0x00000001
 272
 273#define REG_HDMI_HDCP_DDC_CTRL_1				0x00000124
 274#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK				0x00000001
 275
 276#define REG_HDMI_HDCP_DDC_STATUS				0x00000128
 277#define HDMI_HDCP_DDC_STATUS_XFER_REQ				0x00000010
 278#define HDMI_HDCP_DDC_STATUS_XFER_DONE				0x00000400
 279#define HDMI_HDCP_DDC_STATUS_ABORTED				0x00001000
 280#define HDMI_HDCP_DDC_STATUS_TIMEOUT				0x00002000
 281#define HDMI_HDCP_DDC_STATUS_NACK0				0x00004000
 282#define HDMI_HDCP_DDC_STATUS_NACK1				0x00008000
 283#define HDMI_HDCP_DDC_STATUS_FAILED				0x00010000
 284
 285#define REG_HDMI_HDCP_ENTROPY_CTRL0				0x0000012c
 286
 287#define REG_HDMI_HDCP_ENTROPY_CTRL1				0x0000025c
 288
 289#define REG_HDMI_HDCP_RESET					0x00000130
 290#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE			0x00000001
 291
 292#define REG_HDMI_HDCP_RCVPORT_DATA0				0x00000134
 293
 294#define REG_HDMI_HDCP_RCVPORT_DATA1				0x00000138
 295
 296#define REG_HDMI_HDCP_RCVPORT_DATA2_0				0x0000013c
 297
 298#define REG_HDMI_HDCP_RCVPORT_DATA2_1				0x00000140
 299
 300#define REG_HDMI_HDCP_RCVPORT_DATA3				0x00000144
 301
 302#define REG_HDMI_HDCP_RCVPORT_DATA4				0x00000148
 303
 304#define REG_HDMI_HDCP_RCVPORT_DATA5				0x0000014c
 305
 306#define REG_HDMI_HDCP_RCVPORT_DATA6				0x00000150
 307
 308#define REG_HDMI_HDCP_RCVPORT_DATA7				0x00000154
 309
 310#define REG_HDMI_HDCP_RCVPORT_DATA8				0x00000158
 311
 312#define REG_HDMI_HDCP_RCVPORT_DATA9				0x0000015c
 313
 314#define REG_HDMI_HDCP_RCVPORT_DATA10				0x00000160
 315
 316#define REG_HDMI_HDCP_RCVPORT_DATA11				0x00000164
 317
 318#define REG_HDMI_HDCP_RCVPORT_DATA12				0x00000168
 319
 320#define REG_HDMI_VENSPEC_INFO0					0x0000016c
 321
 322#define REG_HDMI_VENSPEC_INFO1					0x00000170
 323
 324#define REG_HDMI_VENSPEC_INFO2					0x00000174
 325
 326#define REG_HDMI_VENSPEC_INFO3					0x00000178
 327
 328#define REG_HDMI_VENSPEC_INFO4					0x0000017c
 329
 330#define REG_HDMI_VENSPEC_INFO5					0x00000180
 331
 332#define REG_HDMI_VENSPEC_INFO6					0x00000184
 333
 334#define REG_HDMI_AUDIO_CFG					0x000001d0
 335#define HDMI_AUDIO_CFG_ENGINE_ENABLE				0x00000001
 336#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK			0x000000f0
 337#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT			4
 338static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
 339{
 340	return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
 341}
 342
 343#define REG_HDMI_USEC_REFTIMER					0x00000208
 344
 345#define REG_HDMI_DDC_CTRL					0x0000020c
 346#define HDMI_DDC_CTRL_GO					0x00000001
 347#define HDMI_DDC_CTRL_SOFT_RESET				0x00000002
 348#define HDMI_DDC_CTRL_SEND_RESET				0x00000004
 349#define HDMI_DDC_CTRL_SW_STATUS_RESET				0x00000008
 350#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK			0x00300000
 351#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT			20
 352static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
 353{
 354	return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
 355}
 356
 357#define REG_HDMI_DDC_ARBITRATION				0x00000210
 358#define HDMI_DDC_ARBITRATION_HW_ARBITRATION			0x00000010
 359
 360#define REG_HDMI_DDC_INT_CTRL					0x00000214
 361#define HDMI_DDC_INT_CTRL_SW_DONE_INT				0x00000001
 362#define HDMI_DDC_INT_CTRL_SW_DONE_ACK				0x00000002
 363#define HDMI_DDC_INT_CTRL_SW_DONE_MASK				0x00000004
 364
 365#define REG_HDMI_DDC_SW_STATUS					0x00000218
 366#define HDMI_DDC_SW_STATUS_NACK0				0x00001000
 367#define HDMI_DDC_SW_STATUS_NACK1				0x00002000
 368#define HDMI_DDC_SW_STATUS_NACK2				0x00004000
 369#define HDMI_DDC_SW_STATUS_NACK3				0x00008000
 370
 371#define REG_HDMI_DDC_HW_STATUS					0x0000021c
 372#define HDMI_DDC_HW_STATUS_DONE					0x00000008
 373
 374#define REG_HDMI_DDC_SPEED					0x00000220
 375#define HDMI_DDC_SPEED_THRESHOLD__MASK				0x00000003
 376#define HDMI_DDC_SPEED_THRESHOLD__SHIFT				0
 377static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
 378{
 379	return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
 380}
 381#define HDMI_DDC_SPEED_PRESCALE__MASK				0xffff0000
 382#define HDMI_DDC_SPEED_PRESCALE__SHIFT				16
 383static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
 384{
 385	return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
 386}
 387
 388#define REG_HDMI_DDC_SETUP					0x00000224
 389#define HDMI_DDC_SETUP_TIMEOUT__MASK				0xff000000
 390#define HDMI_DDC_SETUP_TIMEOUT__SHIFT				24
 391static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
 392{
 393	return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
 394}
 395
 396static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
 397
 398static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
 399#define HDMI_I2C_TRANSACTION_REG_RW__MASK			0x00000001
 400#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT			0
 401static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
 402{
 403	return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
 404}
 405#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK			0x00000100
 406#define HDMI_I2C_TRANSACTION_REG_START				0x00001000
 407#define HDMI_I2C_TRANSACTION_REG_STOP				0x00002000
 408#define HDMI_I2C_TRANSACTION_REG_CNT__MASK			0x00ff0000
 409#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT			16
 410static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
 411{
 412	return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
 413}
 414
 415#define REG_HDMI_DDC_DATA					0x00000238
 416#define HDMI_DDC_DATA_DATA_RW__MASK				0x00000001
 417#define HDMI_DDC_DATA_DATA_RW__SHIFT				0
 418static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
 419{
 420	return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
 421}
 422#define HDMI_DDC_DATA_DATA__MASK				0x0000ff00
 423#define HDMI_DDC_DATA_DATA__SHIFT				8
 424static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
 425{
 426	return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
 427}
 428#define HDMI_DDC_DATA_INDEX__MASK				0x00ff0000
 429#define HDMI_DDC_DATA_INDEX__SHIFT				16
 430static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
 431{
 432	return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
 433}
 434#define HDMI_DDC_DATA_INDEX_WRITE				0x80000000
 435
 436#define REG_HDMI_HDCP_SHA_CTRL					0x0000023c
 437
 438#define REG_HDMI_HDCP_SHA_STATUS				0x00000240
 439#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE				0x00000001
 440#define HDMI_HDCP_SHA_STATUS_COMP_DONE				0x00000010
 441
 442#define REG_HDMI_HDCP_SHA_DATA					0x00000244
 443#define HDMI_HDCP_SHA_DATA_DONE					0x00000001
 444
 445#define REG_HDMI_HPD_INT_STATUS					0x00000250
 446#define HDMI_HPD_INT_STATUS_INT					0x00000001
 447#define HDMI_HPD_INT_STATUS_CABLE_DETECTED			0x00000002
 448
 449#define REG_HDMI_HPD_INT_CTRL					0x00000254
 450#define HDMI_HPD_INT_CTRL_INT_ACK				0x00000001
 451#define HDMI_HPD_INT_CTRL_INT_CONNECT				0x00000002
 452#define HDMI_HPD_INT_CTRL_INT_EN				0x00000004
 453#define HDMI_HPD_INT_CTRL_RX_INT_ACK				0x00000010
 454#define HDMI_HPD_INT_CTRL_RX_INT_EN				0x00000020
 455#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK			0x00000200
 456
 457#define REG_HDMI_HPD_CTRL					0x00000258
 458#define HDMI_HPD_CTRL_TIMEOUT__MASK				0x00001fff
 459#define HDMI_HPD_CTRL_TIMEOUT__SHIFT				0
 460static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
 461{
 462	return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
 463}
 464#define HDMI_HPD_CTRL_ENABLE					0x10000000
 465
 466#define REG_HDMI_DDC_REF					0x0000027c
 467#define HDMI_DDC_REF_REFTIMER_ENABLE				0x00010000
 468#define HDMI_DDC_REF_REFTIMER__MASK				0x0000ffff
 469#define HDMI_DDC_REF_REFTIMER__SHIFT				0
 470static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
 471{
 472	return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
 473}
 474
 475#define REG_HDMI_HDCP_SW_UPPER_AKSV				0x00000284
 476
 477#define REG_HDMI_HDCP_SW_LOWER_AKSV				0x00000288
 478
 479#define REG_HDMI_CEC_CTRL					0x0000028c
 480
 481#define REG_HDMI_CEC_WR_DATA					0x00000290
 482
 483#define REG_HDMI_CEC_CEC_RETRANSMIT				0x00000294
 484
 485#define REG_HDMI_CEC_STATUS					0x00000298
 486
 487#define REG_HDMI_CEC_INT					0x0000029c
 488
 489#define REG_HDMI_CEC_ADDR					0x000002a0
 490
 491#define REG_HDMI_CEC_TIME					0x000002a4
 492
 493#define REG_HDMI_CEC_REFTIMER					0x000002a8
 494
 495#define REG_HDMI_CEC_RD_DATA					0x000002ac
 496
 497#define REG_HDMI_CEC_RD_FILTER					0x000002b0
 498
 499#define REG_HDMI_ACTIVE_HSYNC					0x000002b4
 500#define HDMI_ACTIVE_HSYNC_START__MASK				0x00001fff
 501#define HDMI_ACTIVE_HSYNC_START__SHIFT				0
 502static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
 503{
 504	return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
 505}
 506#define HDMI_ACTIVE_HSYNC_END__MASK				0x0fff0000
 507#define HDMI_ACTIVE_HSYNC_END__SHIFT				16
 508static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
 509{
 510	return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
 511}
 512
 513#define REG_HDMI_ACTIVE_VSYNC					0x000002b8
 514#define HDMI_ACTIVE_VSYNC_START__MASK				0x00001fff
 515#define HDMI_ACTIVE_VSYNC_START__SHIFT				0
 516static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
 517{
 518	return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
 519}
 520#define HDMI_ACTIVE_VSYNC_END__MASK				0x1fff0000
 521#define HDMI_ACTIVE_VSYNC_END__SHIFT				16
 522static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
 523{
 524	return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
 525}
 526
 527#define REG_HDMI_VSYNC_ACTIVE_F2				0x000002bc
 528#define HDMI_VSYNC_ACTIVE_F2_START__MASK			0x00001fff
 529#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT			0
 530static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
 531{
 532	return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
 533}
 534#define HDMI_VSYNC_ACTIVE_F2_END__MASK				0x1fff0000
 535#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT				16
 536static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
 537{
 538	return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
 539}
 540
 541#define REG_HDMI_TOTAL						0x000002c0
 542#define HDMI_TOTAL_H_TOTAL__MASK				0x00001fff
 543#define HDMI_TOTAL_H_TOTAL__SHIFT				0
 544static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
 545{
 546	return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
 547}
 548#define HDMI_TOTAL_V_TOTAL__MASK				0x1fff0000
 549#define HDMI_TOTAL_V_TOTAL__SHIFT				16
 550static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
 551{
 552	return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
 553}
 554
 555#define REG_HDMI_VSYNC_TOTAL_F2					0x000002c4
 556#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK			0x00001fff
 557#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT			0
 558static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
 559{
 560	return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
 561}
 562
 563#define REG_HDMI_FRAME_CTRL					0x000002c8
 564#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR				0x00001000
 565#define HDMI_FRAME_CTRL_VSYNC_LOW				0x10000000
 566#define HDMI_FRAME_CTRL_HSYNC_LOW				0x20000000
 567#define HDMI_FRAME_CTRL_INTERLACED_EN				0x80000000
 568
 569#define REG_HDMI_AUD_INT					0x000002cc
 570#define HDMI_AUD_INT_AUD_FIFO_URUN_INT				0x00000001
 571#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK				0x00000002
 572#define HDMI_AUD_INT_AUD_SAM_DROP_INT				0x00000004
 573#define HDMI_AUD_INT_AUD_SAM_DROP_MASK				0x00000008
 574
 575#define REG_HDMI_PHY_CTRL					0x000002d4
 576#define HDMI_PHY_CTRL_SW_RESET_PLL				0x00000001
 577#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW				0x00000002
 578#define HDMI_PHY_CTRL_SW_RESET					0x00000004
 579#define HDMI_PHY_CTRL_SW_RESET_LOW				0x00000008
 580
 581#define REG_HDMI_CEC_WR_RANGE					0x000002dc
 582
 583#define REG_HDMI_CEC_RD_RANGE					0x000002e0
 584
 585#define REG_HDMI_VERSION					0x000002e4
 586
 587#define REG_HDMI_CEC_COMPL_CTL					0x00000360
 588
 589#define REG_HDMI_CEC_RD_START_RANGE				0x00000364
 590
 591#define REG_HDMI_CEC_RD_TOTAL_RANGE				0x00000368
 592
 593#define REG_HDMI_CEC_RD_ERR_RESP_LO				0x0000036c
 594
 595#define REG_HDMI_CEC_WR_CHECK_CONFIG				0x00000370
 596
 597#define REG_HDMI_8x60_PHY_REG0					0x00000000
 598#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK			0x0000001c
 599#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT		2
 600static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
 601{
 602	return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
 603}
 604
 605#define REG_HDMI_8x60_PHY_REG1					0x00000004
 606#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK			0x000000f0
 607#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT			4
 608static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
 609{
 610	return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
 611}
 612#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK		0x0000000f
 613#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT		0
 614static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
 615{
 616	return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
 617}
 618
 619#define REG_HDMI_8x60_PHY_REG2					0x00000008
 620#define HDMI_8x60_PHY_REG2_PD_DESER				0x00000001
 621#define HDMI_8x60_PHY_REG2_PD_DRIVE_1				0x00000002
 622#define HDMI_8x60_PHY_REG2_PD_DRIVE_2				0x00000004
 623#define HDMI_8x60_PHY_REG2_PD_DRIVE_3				0x00000008
 624#define HDMI_8x60_PHY_REG2_PD_DRIVE_4				0x00000010
 625#define HDMI_8x60_PHY_REG2_PD_PLL				0x00000020
 626#define HDMI_8x60_PHY_REG2_PD_PWRGEN				0x00000040
 627#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN				0x00000080
 628
 629#define REG_HDMI_8x60_PHY_REG3					0x0000000c
 630#define HDMI_8x60_PHY_REG3_PLL_ENABLE				0x00000001
 631
 632#define REG_HDMI_8x60_PHY_REG4					0x00000010
 633
 634#define REG_HDMI_8x60_PHY_REG5					0x00000014
 635
 636#define REG_HDMI_8x60_PHY_REG6					0x00000018
 637
 638#define REG_HDMI_8x60_PHY_REG7					0x0000001c
 639
 640#define REG_HDMI_8x60_PHY_REG8					0x00000020
 641
 642#define REG_HDMI_8x60_PHY_REG9					0x00000024
 643
 644#define REG_HDMI_8x60_PHY_REG10					0x00000028
 645
 646#define REG_HDMI_8x60_PHY_REG11					0x0000002c
 647
 648#define REG_HDMI_8x60_PHY_REG12					0x00000030
 649#define HDMI_8x60_PHY_REG12_RETIMING_EN				0x00000001
 650#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN			0x00000002
 651#define HDMI_8x60_PHY_REG12_FORCE_LOCK				0x00000010
 652
 653#define REG_HDMI_8960_PHY_REG0					0x00000000
 654
 655#define REG_HDMI_8960_PHY_REG1					0x00000004
 656
 657#define REG_HDMI_8960_PHY_REG2					0x00000008
 658
 659#define REG_HDMI_8960_PHY_REG3					0x0000000c
 660
 661#define REG_HDMI_8960_PHY_REG4					0x00000010
 662
 663#define REG_HDMI_8960_PHY_REG5					0x00000014
 664
 665#define REG_HDMI_8960_PHY_REG6					0x00000018
 666
 667#define REG_HDMI_8960_PHY_REG7					0x0000001c
 668
 669#define REG_HDMI_8960_PHY_REG8					0x00000020
 670
 671#define REG_HDMI_8960_PHY_REG9					0x00000024
 672
 673#define REG_HDMI_8960_PHY_REG10					0x00000028
 674
 675#define REG_HDMI_8960_PHY_REG11					0x0000002c
 676
 677#define REG_HDMI_8960_PHY_REG12					0x00000030
 678#define HDMI_8960_PHY_REG12_SW_RESET				0x00000020
 679#define HDMI_8960_PHY_REG12_PWRDN_B				0x00000080
 680
 681#define REG_HDMI_8960_PHY_REG_BIST_CFG				0x00000034
 682
 683#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL				0x00000038
 684
 685#define REG_HDMI_8960_PHY_REG_MISC0				0x0000003c
 686
 687#define REG_HDMI_8960_PHY_REG13					0x00000040
 688
 689#define REG_HDMI_8960_PHY_REG14					0x00000044
 690
 691#define REG_HDMI_8960_PHY_REG15					0x00000048
 692
 693#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG			0x00000000
 694
 695#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG			0x00000004
 696
 697#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0			0x00000008
 698
 699#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1			0x0000000c
 700
 701#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG			0x00000010
 702
 703#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG			0x00000014
 704
 705#define REG_HDMI_8960_PHY_PLL_PWRDN_B				0x00000018
 706#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL			0x00000002
 707#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B			0x00000008
 708
 709#define REG_HDMI_8960_PHY_PLL_SDM_CFG0				0x0000001c
 710
 711#define REG_HDMI_8960_PHY_PLL_SDM_CFG1				0x00000020
 712
 713#define REG_HDMI_8960_PHY_PLL_SDM_CFG2				0x00000024
 714
 715#define REG_HDMI_8960_PHY_PLL_SDM_CFG3				0x00000028
 716
 717#define REG_HDMI_8960_PHY_PLL_SDM_CFG4				0x0000002c
 718
 719#define REG_HDMI_8960_PHY_PLL_SSC_CFG0				0x00000030
 720
 721#define REG_HDMI_8960_PHY_PLL_SSC_CFG1				0x00000034
 722
 723#define REG_HDMI_8960_PHY_PLL_SSC_CFG2				0x00000038
 724
 725#define REG_HDMI_8960_PHY_PLL_SSC_CFG3				0x0000003c
 726
 727#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0			0x00000040
 728
 729#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1			0x00000044
 730
 731#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2			0x00000048
 732
 733#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0			0x0000004c
 734
 735#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1			0x00000050
 736
 737#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2			0x00000054
 738
 739#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3			0x00000058
 740
 741#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4			0x0000005c
 742
 743#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5			0x00000060
 744
 745#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6			0x00000064
 746
 747#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7			0x00000068
 748
 749#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL				0x0000006c
 750
 751#define REG_HDMI_8960_PHY_PLL_MISC0				0x00000070
 752
 753#define REG_HDMI_8960_PHY_PLL_MISC1				0x00000074
 754
 755#define REG_HDMI_8960_PHY_PLL_MISC2				0x00000078
 756
 757#define REG_HDMI_8960_PHY_PLL_MISC3				0x0000007c
 758
 759#define REG_HDMI_8960_PHY_PLL_MISC4				0x00000080
 760
 761#define REG_HDMI_8960_PHY_PLL_MISC5				0x00000084
 762
 763#define REG_HDMI_8960_PHY_PLL_MISC6				0x00000088
 764
 765#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0			0x0000008c
 766
 767#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1			0x00000090
 768
 769#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2			0x00000094
 770
 771#define REG_HDMI_8960_PHY_PLL_STATUS0				0x00000098
 772#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK			0x00000001
 773
 774#define REG_HDMI_8960_PHY_PLL_STATUS1				0x0000009c
 775
 776#define REG_HDMI_8x74_ANA_CFG0					0x00000000
 777
 778#define REG_HDMI_8x74_ANA_CFG1					0x00000004
 779
 780#define REG_HDMI_8x74_PD_CTRL0					0x00000010
 781
 782#define REG_HDMI_8x74_PD_CTRL1					0x00000014
 783
 784#define REG_HDMI_8x74_BIST_CFG0					0x00000034
 785
 786#define REG_HDMI_8x74_BIST_PATN0				0x0000003c
 787
 788#define REG_HDMI_8x74_BIST_PATN1				0x00000040
 789
 790#define REG_HDMI_8x74_BIST_PATN2				0x00000044
 791
 792#define REG_HDMI_8x74_BIST_PATN3				0x00000048
 793
 794#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG			0x00000000
 795
 796#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG			0x00000004
 797
 798#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG			0x00000008
 799
 800#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG			0x0000000c
 801
 802#define REG_HDMI_28nm_PHY_PLL_VREG_CFG				0x00000010
 803
 804#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG			0x00000014
 805
 806#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG				0x00000018
 807
 808#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG				0x0000001c
 809
 810#define REG_HDMI_28nm_PHY_PLL_GLB_CFG				0x00000020
 811#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B			0x00000001
 812#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B		0x00000002
 813#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B		0x00000004
 814#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE			0x00000008
 815
 816#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG			0x00000024
 817
 818#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG			0x00000028
 819
 820#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG				0x0000002c
 821
 822#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG				0x00000030
 823
 824#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG				0x00000034
 825
 826#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0				0x00000038
 827
 828#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1				0x0000003c
 829
 830#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2				0x00000040
 831
 832#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3				0x00000044
 833
 834#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4				0x00000048
 835
 836#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0				0x0000004c
 837
 838#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1				0x00000050
 839
 840#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2				0x00000054
 841
 842#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3				0x00000058
 843
 844#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0			0x0000005c
 845
 846#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1			0x00000060
 847
 848#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2			0x00000064
 849
 850#define REG_HDMI_28nm_PHY_PLL_TEST_CFG				0x00000068
 851#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET			0x00000001
 852
 853#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0				0x0000006c
 854
 855#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1				0x00000070
 856
 857#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2				0x00000074
 858
 859#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3				0x00000078
 860
 861#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4				0x0000007c
 862
 863#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5				0x00000080
 864
 865#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6				0x00000084
 866
 867#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7				0x00000088
 868
 869#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8				0x0000008c
 870
 871#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9				0x00000090
 872
 873#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10				0x00000094
 874
 875#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11				0x00000098
 876
 877#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG				0x0000009c
 878
 879#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL			0x000000a0
 880
 881#define REG_HDMI_8996_PHY_CFG					0x00000000
 882
 883#define REG_HDMI_8996_PHY_PD_CTL				0x00000004
 884
 885#define REG_HDMI_8996_PHY_MODE					0x00000008
 886
 887#define REG_HDMI_8996_PHY_MISR_CLEAR				0x0000000c
 888
 889#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0			0x00000010
 890
 891#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1			0x00000014
 892
 893#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0		0x00000018
 894
 895#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1		0x0000001c
 896
 897#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0			0x00000020
 898
 899#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1			0x00000024
 900
 901#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0			0x00000028
 902
 903#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1			0x0000002c
 904
 905#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0		0x00000030
 906
 907#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1		0x00000034
 908
 909#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0			0x00000038
 910
 911#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1			0x0000003c
 912
 913#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL				0x00000040
 914
 915#define REG_HDMI_8996_PHY_TXCAL_CFG0				0x00000044
 916
 917#define REG_HDMI_8996_PHY_TXCAL_CFG1				0x00000048
 918
 919#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL			0x0000004c
 920
 921#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL			0x00000050
 922
 923#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG			0x00000054
 924
 925#define REG_HDMI_8996_PHY_CLOCK					0x00000058
 926
 927#define REG_HDMI_8996_PHY_MISC1					0x0000005c
 928
 929#define REG_HDMI_8996_PHY_MISC2					0x00000060
 930
 931#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0			0x00000064
 932
 933#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1			0x00000068
 934
 935#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2			0x0000006c
 936
 937#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0			0x00000070
 938
 939#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1			0x00000074
 940
 941#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2			0x00000078
 942
 943#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0			0x0000007c
 944
 945#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1			0x00000080
 946
 947#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2			0x00000084
 948
 949#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3			0x00000088
 950
 951#define REG_HDMI_8996_PHY_POST_MISR_STATUS0			0x0000008c
 952
 953#define REG_HDMI_8996_PHY_POST_MISR_STATUS1			0x00000090
 954
 955#define REG_HDMI_8996_PHY_POST_MISR_STATUS2			0x00000094
 956
 957#define REG_HDMI_8996_PHY_POST_MISR_STATUS3			0x00000098
 958
 959#define REG_HDMI_8996_PHY_STATUS				0x0000009c
 960
 961#define REG_HDMI_8996_PHY_MISC3_STATUS				0x000000a0
 962
 963#define REG_HDMI_8996_PHY_MISC4_STATUS				0x000000a4
 964
 965#define REG_HDMI_8996_PHY_DEBUG_BUS0				0x000000a8
 966
 967#define REG_HDMI_8996_PHY_DEBUG_BUS1				0x000000ac
 968
 969#define REG_HDMI_8996_PHY_DEBUG_BUS2				0x000000b0
 970
 971#define REG_HDMI_8996_PHY_DEBUG_BUS3				0x000000b4
 972
 973#define REG_HDMI_8996_PHY_PHY_REVISION_ID0			0x000000b8
 974
 975#define REG_HDMI_8996_PHY_PHY_REVISION_ID1			0x000000bc
 976
 977#define REG_HDMI_8996_PHY_PHY_REVISION_ID2			0x000000c0
 978
 979#define REG_HDMI_8996_PHY_PHY_REVISION_ID3			0x000000c4
 980
 981#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1			0x00000000
 982
 983#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2			0x00000004
 984
 985#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE			0x00000008
 986
 987#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER			0x0000000c
 988
 989#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER			0x00000010
 990
 991#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1			0x00000014
 992
 993#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2			0x00000018
 994
 995#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1			0x0000001c
 996
 997#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2			0x00000020
 998
 999#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1			0x00000024
1000
1001#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2			0x00000028
1002
1003#define REG_HDMI_PHY_QSERDES_COM_POST_DIV			0x0000002c
1004
1005#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX			0x00000030
1006
1007#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x00000034
1008
1009#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1			0x00000038
1010
1011#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL			0x0000003c
1012
1013#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE		0x00000040
1014
1015#define REG_HDMI_PHY_QSERDES_COM_PLL_EN				0x00000044
1016
1017#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO			0x00000048
1018
1019#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0		0x0000004c
1020
1021#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0		0x00000050
1022
1023#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0		0x00000054
1024
1025#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1		0x00000058
1026
1027#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1		0x0000005c
1028
1029#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1		0x00000060
1030
1031#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2		0x00000064
1032
1033#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0			0x00000064
1034
1035#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2		0x00000068
1036
1037#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x00000068
1038
1039#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2		0x0000006c
1040
1041#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x0000006c
1042
1043#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM			0x00000070
1044
1045#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV			0x00000074
1046
1047#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0			0x00000078
1048
1049#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1			0x0000007c
1050
1051#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2			0x00000080
1052
1053#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1			0x00000080
1054
1055#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0		0x00000084
1056
1057#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1		0x00000088
1058
1059#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2		0x0000008c
1060
1061#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2			0x0000008c
1062
1063#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0		0x00000090
1064
1065#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1		0x00000094
1066
1067#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2		0x00000098
1068
1069#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3			0x00000098
1070
1071#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL			0x0000009c
1072
1073#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL			0x000000a0
1074
1075#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC			0x000000a4
1076
1077#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL		0x000000a8
1078
1079#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x000000a8
1080
1081#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL			0x000000ac
1082
1083#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL			0x000000b0
1084
1085#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL			0x000000b4
1086
1087#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2			0x000000b8
1088
1089#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL			0x000000bc
1090
1091#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2			0x000000c0
1092
1093#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM		0x000000c4
1094
1095#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN			0x000000c8
1096
1097#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG			0x000000cc
1098
1099#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0		0x000000d0
1100
1101#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1		0x000000d4
1102
1103#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2		0x000000d8
1104
1105#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x000000d8
1106
1107#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0		0x000000dc
1108
1109#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0		0x000000e0
1110
1111#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0		0x000000e4
1112
1113#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1		0x000000e8
1114
1115#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1		0x000000ec
1116
1117#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1		0x000000f0
1118
1119#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2		0x000000f4
1120
1121#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1		0x000000f4
1122
1123#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2		0x000000f8
1124
1125#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2		0x000000f8
1126
1127#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2		0x000000fc
1128
1129#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4			0x000000fc
1130
1131#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL		0x00000100
1132
1133#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN			0x00000104
1134
1135#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x00000108
1136
1137#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0000010c
1138
1139#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x00000110
1140
1141#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x00000114
1142
1143#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2		0x00000118
1144
1145#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1		0x00000118
1146
1147#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2		0x0000011c
1148
1149#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2		0x0000011c
1150
1151#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2		0x00000120
1152
1153#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL			0x00000124
1154
1155#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP			0x00000128
1156
1157#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0		0x0000012c
1158
1159#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0		0x00000130
1160
1161#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1		0x00000134
1162
1163#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1		0x00000138
1164
1165#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2		0x0000013c
1166
1167#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1		0x0000013c
1168
1169#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2		0x00000140
1170
1171#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2		0x00000140
1172
1173#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1		0x00000144
1174
1175#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2		0x00000148
1176
1177#define REG_HDMI_PHY_QSERDES_COM_SAR				0x0000014c
1178
1179#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK			0x00000150
1180
1181#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS		0x00000154
1182
1183#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS		0x00000158
1184
1185#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS			0x0000015c
1186
1187#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS		0x00000160
1188
1189#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS		0x00000164
1190
1191#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS		0x00000168
1192
1193#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS		0x0000016c
1194
1195#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL			0x00000170
1196
1197#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT			0x00000174
1198
1199#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL			0x00000178
1200
1201#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x0000017c
1202
1203#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG			0x00000180
1204
1205#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV			0x00000184
1206
1207#define REG_HDMI_PHY_QSERDES_COM_SW_RESET			0x00000188
1208
1209#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN			0x0000018c
1210
1211#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS			0x00000190
1212
1213#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG			0x00000194
1214
1215#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE		0x00000198
1216
1217#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL		0x0000019c
1218
1219#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0			0x000001a0
1220
1221#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1			0x000001a4
1222
1223#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2			0x000001a8
1224
1225#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3			0x000001ac
1226
1227#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL			0x000001b0
1228
1229#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1			0x000001b4
1230
1231#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2			0x000001b8
1232
1233#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1		0x000001bc
1234
1235#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2		0x000001c0
1236
1237#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5			0x000001c4
1238
1239#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO		0x00000000
1240
1241#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT			0x00000004
1242
1243#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE		0x00000008
1244
1245#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE		0x0000000c
1246
1247#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO		0x00000010
1248
1249#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE		0x00000014
1250
1251#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL		0x00000018
1252
1253#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH		0x0000001c
1254
1255#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN		0x00000020
1256
1257#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES		0x00000024
1258
1259#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP	0x00000028
1260
1261#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL			0x0000002c
1262
1263#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET		0x00000030
1264
1265#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN		0x00000034
1266
1267#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN	0x00000038
1268
1269#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND			0x0000003c
1270
1271#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL			0x00000040
1272
1273#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT		0x00000044
1274
1275#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN			0x00000048
1276
1277#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX		0x0000004c
1278
1279#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX		0x00000050
1280
1281#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET		0x00000054
1282
1283#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1			0x00000058
1284
1285#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2			0x0000005c
1286
1287#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT		0x00000060
1288
1289#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL		0x00000064
1290
1291#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x00000068
1292
1293#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV			0x0000006c
1294
1295#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN	0x00000070
1296
1297#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1		0x00000074
1298
1299#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2		0x00000078
1300
1301#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3		0x0000007c
1302
1303#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4		0x00000080
1304
1305#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5		0x00000084
1306
1307#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6		0x00000088
1308
1309#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7		0x0000008c
1310
1311#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8		0x00000090
1312
1313#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE			0x00000094
1314
1315#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE		0x00000098
1316
1317#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION	0x0000009c
1318
1319#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1			0x000000a0
1320
1321#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2			0x000000a4
1322
1323#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL		0x000000a8
1324
1325#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2		0x000000ac
1326
1327#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1			0x000000b0
1328
1329#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2			0x000000b4
1330
1331#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3			0x000000b8
1332
1333#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4			0x000000bc
1334
1335#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN			0x000000c0
1336
1337#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES		0x000000c4
1338
1339#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN		0x000000c8
1340
1341#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE		0x000000cc
1342
1343#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL			0x000000d0
1344
1345#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA		0x000000d4
1346
1347#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2	0x000000d8
1348
1349#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2	0x000000dc
1350
1351#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2	0x000000e0
1352
1353#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2	0x000000e4
1354
1355#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1	0x000000e8
1356
1357#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1	0x000000ec
1358
1359#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1	0x000000f0
1360
1361#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1	0x000000f4
1362
1363#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1			0x000000f8
1364
1365#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2			0x000000fc
1366
1367#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL	0x00000100
1368
1369#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS			0x00000104
1370
1371#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1		0x00000108
1372
1373#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2		0x0000010c
1374
1375#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV		0x00000110
1376
1377
1378#endif /* HDMI_XML */