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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4 */
5
6#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
7
8#include <linux/types.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/phy/phy.h>
12#include <linux/phy/phy-dp.h>
13#include <linux/pm_opp.h>
14#include <drm/drm_fixed.h>
15#include <drm/drm_dp_helper.h>
16#include <drm/drm_print.h>
17
18#include "dp_reg.h"
19#include "dp_ctrl.h"
20#include "dp_link.h"
21
22#define DP_KHZ_TO_HZ 1000
23#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
24#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
25
26#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
27#define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
28
29#define MR_LINK_TRAINING1 0x8
30#define MR_LINK_SYMBOL_ERM 0x80
31#define MR_LINK_PRBS7 0x100
32#define MR_LINK_CUSTOM80 0x200
33#define MR_LINK_TRAINING4 0x40
34
35enum {
36 DP_TRAINING_NONE,
37 DP_TRAINING_1,
38 DP_TRAINING_2,
39};
40
41struct dp_tu_calc_input {
42 u64 lclk; /* 162, 270, 540 and 810 */
43 u64 pclk_khz; /* in KHz */
44 u64 hactive; /* active h-width */
45 u64 hporch; /* bp + fp + pulse */
46 int nlanes; /* no.of.lanes */
47 int bpp; /* bits */
48 int pixel_enc; /* 444, 420, 422 */
49 int dsc_en; /* dsc on/off */
50 int async_en; /* async mode */
51 int fec_en; /* fec */
52 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
53 int num_of_dsc_slices; /* number of slices per line */
54};
55
56struct dp_vc_tu_mapping_table {
57 u32 vic;
58 u8 lanes;
59 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
60 u8 bpp;
61 u8 valid_boundary_link;
62 u16 delay_start_link;
63 bool boundary_moderation_en;
64 u8 valid_lower_boundary_link;
65 u8 upper_boundary_count;
66 u8 lower_boundary_count;
67 u8 tu_size_minus1;
68};
69
70struct dp_ctrl_private {
71 struct dp_ctrl dp_ctrl;
72 struct device *dev;
73 struct drm_dp_aux *aux;
74 struct dp_panel *panel;
75 struct dp_link *link;
76 struct dp_power *power;
77 struct dp_parser *parser;
78 struct dp_catalog *catalog;
79
80 struct completion idle_comp;
81 struct completion video_comp;
82};
83
84static int dp_aux_link_configure(struct drm_dp_aux *aux,
85 struct dp_link_info *link)
86{
87 u8 values[2];
88 int err;
89
90 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
91 values[1] = link->num_lanes;
92
93 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
94 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
95
96 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
97 if (err < 0)
98 return err;
99
100 return 0;
101}
102
103void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
104{
105 struct dp_ctrl_private *ctrl;
106
107 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
108
109 reinit_completion(&ctrl->idle_comp);
110 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
111
112 if (!wait_for_completion_timeout(&ctrl->idle_comp,
113 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
114 pr_warn("PUSH_IDLE pattern timedout\n");
115
116 pr_debug("mainlink off done\n");
117}
118
119static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
120{
121 u32 config = 0, tbd;
122 u8 *dpcd = ctrl->panel->dpcd;
123
124 /* Default-> LSCLK DIV: 1/4 LCLK */
125 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
126
127 /* Scrambler reset enable */
128 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP)
129 config |= DP_CONFIGURATION_CTRL_ASSR;
130
131 tbd = dp_link_get_test_bits_depth(ctrl->link,
132 ctrl->panel->dp_mode.bpp);
133
134 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
135 pr_debug("BIT_DEPTH not set. Configure default\n");
136 tbd = DP_TEST_BIT_DEPTH_8;
137 }
138
139 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
140
141 /* Num of Lanes */
142 config |= ((ctrl->link->link_params.num_lanes - 1)
143 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
144
145 if (drm_dp_enhanced_frame_cap(dpcd))
146 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
147
148 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
149
150 /* sync clock & static Mvid */
151 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
152 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
153
154 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
155}
156
157static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
158{
159 u32 cc, tb;
160
161 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
162 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
163
164 dp_ctrl_config_ctrl(ctrl);
165
166 tb = dp_link_get_test_bits_depth(ctrl->link,
167 ctrl->panel->dp_mode.bpp);
168 cc = dp_link_get_colorimetry_config(ctrl->link);
169 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
170 dp_panel_timing_cfg(ctrl->panel);
171}
172
173/*
174 * The structure and few functions present below are IP/Hardware
175 * specific implementation. Most of the implementation will not
176 * have coding comments
177 */
178struct tu_algo_data {
179 s64 lclk_fp;
180 s64 pclk_fp;
181 s64 lwidth;
182 s64 lwidth_fp;
183 s64 hbp_relative_to_pclk;
184 s64 hbp_relative_to_pclk_fp;
185 int nlanes;
186 int bpp;
187 int pixelEnc;
188 int dsc_en;
189 int async_en;
190 int bpc;
191
192 uint delay_start_link_extra_pixclk;
193 int extra_buffer_margin;
194 s64 ratio_fp;
195 s64 original_ratio_fp;
196
197 s64 err_fp;
198 s64 n_err_fp;
199 s64 n_n_err_fp;
200 int tu_size;
201 int tu_size_desired;
202 int tu_size_minus1;
203
204 int valid_boundary_link;
205 s64 resulting_valid_fp;
206 s64 total_valid_fp;
207 s64 effective_valid_fp;
208 s64 effective_valid_recorded_fp;
209 int n_tus;
210 int n_tus_per_lane;
211 int paired_tus;
212 int remainder_tus;
213 int remainder_tus_upper;
214 int remainder_tus_lower;
215 int extra_bytes;
216 int filler_size;
217 int delay_start_link;
218
219 int extra_pclk_cycles;
220 int extra_pclk_cycles_in_link_clk;
221 s64 ratio_by_tu_fp;
222 s64 average_valid2_fp;
223 int new_valid_boundary_link;
224 int remainder_symbols_exist;
225 int n_symbols;
226 s64 n_remainder_symbols_per_lane_fp;
227 s64 last_partial_tu_fp;
228 s64 TU_ratio_err_fp;
229
230 int n_tus_incl_last_incomplete_tu;
231 int extra_pclk_cycles_tmp;
232 int extra_pclk_cycles_in_link_clk_tmp;
233 int extra_required_bytes_new_tmp;
234 int filler_size_tmp;
235 int lower_filler_size_tmp;
236 int delay_start_link_tmp;
237
238 bool boundary_moderation_en;
239 int boundary_mod_lower_err;
240 int upper_boundary_count;
241 int lower_boundary_count;
242 int i_upper_boundary_count;
243 int i_lower_boundary_count;
244 int valid_lower_boundary_link;
245 int even_distribution_BF;
246 int even_distribution_legacy;
247 int even_distribution;
248 int min_hblank_violated;
249 s64 delay_start_time_fp;
250 s64 hbp_time_fp;
251 s64 hactive_time_fp;
252 s64 diff_abs_fp;
253
254 s64 ratio;
255};
256
257static int _tu_param_compare(s64 a, s64 b)
258{
259 u32 a_sign;
260 u32 b_sign;
261 s64 a_temp, b_temp, minus_1;
262
263 if (a == b)
264 return 0;
265
266 minus_1 = drm_fixp_from_fraction(-1, 1);
267
268 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
269
270 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
271
272 if (a_sign > b_sign)
273 return 2;
274 else if (b_sign > a_sign)
275 return 1;
276
277 if (!a_sign && !b_sign) { /* positive */
278 if (a > b)
279 return 1;
280 else
281 return 2;
282 } else { /* negative */
283 a_temp = drm_fixp_mul(a, minus_1);
284 b_temp = drm_fixp_mul(b, minus_1);
285
286 if (a_temp > b_temp)
287 return 2;
288 else
289 return 1;
290 }
291}
292
293static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
294 struct tu_algo_data *tu)
295{
296 int nlanes = in->nlanes;
297 int dsc_num_slices = in->num_of_dsc_slices;
298 int dsc_num_bytes = 0;
299 int numerator;
300 s64 pclk_dsc_fp;
301 s64 dwidth_dsc_fp;
302 s64 hbp_dsc_fp;
303
304 int tot_num_eoc_symbols = 0;
305 int tot_num_hor_bytes = 0;
306 int tot_num_dummy_bytes = 0;
307 int dwidth_dsc_bytes = 0;
308 int eoc_bytes = 0;
309
310 s64 temp1_fp, temp2_fp, temp3_fp;
311
312 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
313 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
314 tu->lwidth = in->hactive;
315 tu->hbp_relative_to_pclk = in->hporch;
316 tu->nlanes = in->nlanes;
317 tu->bpp = in->bpp;
318 tu->pixelEnc = in->pixel_enc;
319 tu->dsc_en = in->dsc_en;
320 tu->async_en = in->async_en;
321 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
322 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
323
324 if (tu->pixelEnc == 420) {
325 temp1_fp = drm_fixp_from_fraction(2, 1);
326 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
327 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
328 tu->hbp_relative_to_pclk_fp =
329 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
330 }
331
332 if (tu->pixelEnc == 422) {
333 switch (tu->bpp) {
334 case 24:
335 tu->bpp = 16;
336 tu->bpc = 8;
337 break;
338 case 30:
339 tu->bpp = 20;
340 tu->bpc = 10;
341 break;
342 default:
343 tu->bpp = 16;
344 tu->bpc = 8;
345 break;
346 }
347 } else {
348 tu->bpc = tu->bpp/3;
349 }
350
351 if (!in->dsc_en)
352 goto fec_check;
353
354 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
355 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
356 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
357 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
358
359 temp1_fp = drm_fixp_from_fraction(8, 1);
360 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
361
362 numerator = drm_fixp2int(temp3_fp);
363
364 dsc_num_bytes = numerator / dsc_num_slices;
365 eoc_bytes = dsc_num_bytes % nlanes;
366 tot_num_eoc_symbols = nlanes * dsc_num_slices;
367 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
368 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
369
370 if (dsc_num_bytes == 0)
371 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
372
373 dwidth_dsc_bytes = (tot_num_hor_bytes +
374 tot_num_eoc_symbols +
375 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
376
377 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
378
379 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
380 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
381 pclk_dsc_fp = temp1_fp;
382
383 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
384 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
385 hbp_dsc_fp = temp2_fp;
386
387 /* output */
388 tu->pclk_fp = pclk_dsc_fp;
389 tu->lwidth_fp = dwidth_dsc_fp;
390 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
391
392fec_check:
393 if (in->fec_en) {
394 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
395 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
396 }
397}
398
399static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
400{
401 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
402 int compare_result_1, compare_result_2, compare_result_3;
403
404 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
405 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
406
407 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
408
409 temp = (tu->i_upper_boundary_count *
410 tu->new_valid_boundary_link +
411 tu->i_lower_boundary_count *
412 (tu->new_valid_boundary_link-1));
413 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
414 (tu->i_upper_boundary_count +
415 tu->i_lower_boundary_count));
416
417 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
418 temp2_fp = tu->lwidth_fp;
419 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
420 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
421 tu->n_tus = drm_fixp2int(temp2_fp);
422 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
423 tu->n_tus += 1;
424
425 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
426 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
427 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
428 temp2_fp = temp1_fp - temp2_fp;
429 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
430 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
431 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
432
433 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
434 tu->last_partial_tu_fp =
435 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
436 temp1_fp);
437
438 if (tu->n_remainder_symbols_per_lane_fp != 0)
439 tu->remainder_symbols_exist = 1;
440 else
441 tu->remainder_symbols_exist = 0;
442
443 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
444 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
445
446 tu->paired_tus = (int)((tu->n_tus_per_lane) /
447 (tu->i_upper_boundary_count +
448 tu->i_lower_boundary_count));
449
450 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
451 (tu->i_upper_boundary_count +
452 tu->i_lower_boundary_count);
453
454 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
455 tu->remainder_tus_upper = tu->i_upper_boundary_count;
456 tu->remainder_tus_lower = tu->remainder_tus -
457 tu->i_upper_boundary_count;
458 } else {
459 tu->remainder_tus_upper = tu->remainder_tus;
460 tu->remainder_tus_lower = 0;
461 }
462
463 temp = tu->paired_tus * (tu->i_upper_boundary_count *
464 tu->new_valid_boundary_link +
465 tu->i_lower_boundary_count *
466 (tu->new_valid_boundary_link - 1)) +
467 (tu->remainder_tus_upper *
468 tu->new_valid_boundary_link) +
469 (tu->remainder_tus_lower *
470 (tu->new_valid_boundary_link - 1));
471 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
472
473 if (tu->remainder_symbols_exist) {
474 temp1_fp = tu->total_valid_fp +
475 tu->n_remainder_symbols_per_lane_fp;
476 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
477 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
478 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
479 } else {
480 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
481 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
482 }
483 tu->effective_valid_fp = temp1_fp;
484
485 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
486 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
487 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
488
489 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
490 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
491 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
492
493 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
494
495 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
496 temp2_fp = tu->lwidth_fp;
497 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
498 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
499
500 if (temp2_fp)
501 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
502 else
503 tu->n_tus_incl_last_incomplete_tu = 0;
504
505 temp1 = 0;
506 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
507 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
508 temp1_fp = tu->average_valid2_fp - temp2_fp;
509 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
510 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
511
512 if (temp1_fp)
513 temp1 = drm_fixp2int_ceil(temp1_fp);
514
515 temp = tu->i_upper_boundary_count * tu->nlanes;
516 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
517 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
518 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
519 temp2_fp = temp1_fp - temp2_fp;
520 temp1_fp = drm_fixp_from_fraction(temp, 1);
521 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
522
523 if (temp2_fp)
524 temp2 = drm_fixp2int_ceil(temp2_fp);
525 else
526 temp2 = 0;
527 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
528
529 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
530 temp2_fp = drm_fixp_from_fraction(
531 tu->extra_required_bytes_new_tmp, 1);
532 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
533
534 if (temp1_fp)
535 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
536 else
537 tu->extra_pclk_cycles_tmp = 0;
538
539 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
540 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
541 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
542
543 if (temp1_fp)
544 tu->extra_pclk_cycles_in_link_clk_tmp =
545 drm_fixp2int_ceil(temp1_fp);
546 else
547 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
548
549 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
550
551 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
552
553 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
554 tu->lower_filler_size_tmp +
555 tu->extra_buffer_margin;
556
557 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
558 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
559
560 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
561 if (compare_result_1 == 2)
562 compare_result_1 = 1;
563 else
564 compare_result_1 = 0;
565
566 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
567 if (compare_result_2 == 2)
568 compare_result_2 = 1;
569 else
570 compare_result_2 = 0;
571
572 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
573 tu->delay_start_time_fp);
574 if (compare_result_3 == 2)
575 compare_result_3 = 0;
576 else
577 compare_result_3 = 1;
578
579 if (((tu->even_distribution == 1) ||
580 ((tu->even_distribution_BF == 0) &&
581 (tu->even_distribution_legacy == 0))) &&
582 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
583 compare_result_2 &&
584 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
585 (tu->new_valid_boundary_link - 1) > 0 &&
586 compare_result_3 &&
587 (tu->delay_start_link_tmp <= 1023)) {
588 tu->upper_boundary_count = tu->i_upper_boundary_count;
589 tu->lower_boundary_count = tu->i_lower_boundary_count;
590 tu->err_fp = tu->n_n_err_fp;
591 tu->boundary_moderation_en = true;
592 tu->tu_size_desired = tu->tu_size;
593 tu->valid_boundary_link = tu->new_valid_boundary_link;
594 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
595 tu->even_distribution_BF = 1;
596 tu->delay_start_link = tu->delay_start_link_tmp;
597 } else if (tu->boundary_mod_lower_err == 0) {
598 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
599 tu->diff_abs_fp);
600 if (compare_result_1 == 2)
601 tu->boundary_mod_lower_err = 1;
602 }
603}
604
605static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in,
606 struct dp_vc_tu_mapping_table *tu_table)
607{
608 struct tu_algo_data *tu;
609 int compare_result_1, compare_result_2;
610 u64 temp = 0;
611 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
612
613 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
614 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
615 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
616 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
617
618 u8 DP_BRUTE_FORCE = 1;
619 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
620 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
621 uint HBLANK_MARGIN = 4;
622
623 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
624 if (!tu)
625 return;
626
627 dp_panel_update_tu_timings(in, tu);
628
629 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
630
631 temp1_fp = drm_fixp_from_fraction(4, 1);
632 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
633 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
634 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
635
636 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
637 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
638 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
639 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
640 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
641
642 tu->original_ratio_fp = tu->ratio_fp;
643 tu->boundary_moderation_en = false;
644 tu->upper_boundary_count = 0;
645 tu->lower_boundary_count = 0;
646 tu->i_upper_boundary_count = 0;
647 tu->i_lower_boundary_count = 0;
648 tu->valid_lower_boundary_link = 0;
649 tu->even_distribution_BF = 0;
650 tu->even_distribution_legacy = 0;
651 tu->even_distribution = 0;
652 tu->delay_start_time_fp = 0;
653
654 tu->err_fp = drm_fixp_from_fraction(1000, 1);
655 tu->n_err_fp = 0;
656 tu->n_n_err_fp = 0;
657
658 tu->ratio = drm_fixp2int(tu->ratio_fp);
659 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
660 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
661 if (temp2_fp != 0 &&
662 !tu->ratio && tu->dsc_en == 0) {
663 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
664 tu->ratio = drm_fixp2int(tu->ratio_fp);
665 if (tu->ratio)
666 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
667 }
668
669 if (tu->ratio > 1)
670 tu->ratio = 1;
671
672 if (tu->ratio == 1)
673 goto tu_size_calc;
674
675 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
676 if (!compare_result_1 || compare_result_1 == 1)
677 compare_result_1 = 1;
678 else
679 compare_result_1 = 0;
680
681 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
682 if (!compare_result_2 || compare_result_2 == 2)
683 compare_result_2 = 1;
684 else
685 compare_result_2 = 0;
686
687 if (tu->dsc_en && compare_result_1 && compare_result_2) {
688 HBLANK_MARGIN += 4;
689 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n",
690 HBLANK_MARGIN);
691 }
692
693tu_size_calc:
694 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
695 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
696 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
697 temp = drm_fixp2int_ceil(temp2_fp);
698 temp1_fp = drm_fixp_from_fraction(temp, 1);
699 tu->n_err_fp = temp1_fp - temp2_fp;
700
701 if (tu->n_err_fp < tu->err_fp) {
702 tu->err_fp = tu->n_err_fp;
703 tu->tu_size_desired = tu->tu_size;
704 }
705 }
706
707 tu->tu_size_minus1 = tu->tu_size_desired - 1;
708
709 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
710 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
711 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
712
713 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
714 temp2_fp = tu->lwidth_fp;
715 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
716
717 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
718 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
719 tu->n_tus = drm_fixp2int(temp2_fp);
720 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
721 tu->n_tus += 1;
722
723 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
724 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n",
725 tu->valid_boundary_link, tu->n_tus);
726
727 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
728 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
729 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
730 temp2_fp = temp1_fp - temp2_fp;
731 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
732 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
733
734 temp = drm_fixp2int(temp2_fp);
735 if (temp && temp2_fp)
736 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
737 else
738 tu->extra_bytes = 0;
739
740 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
741 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
742 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
743
744 if (temp && temp1_fp)
745 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
746 else
747 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
748
749 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
750 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
751 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
752
753 if (temp1_fp)
754 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
755 else
756 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
757
758 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
759
760 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
761 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
762
763 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
764 tu->filler_size + tu->extra_buffer_margin;
765
766 tu->resulting_valid_fp =
767 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
768
769 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
770 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
771 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
772
773 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
774 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
775 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
776
777 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
778 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
779
780 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
781 tu->delay_start_time_fp);
782 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
783 tu->min_hblank_violated = 1;
784
785 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
786
787 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
788 tu->delay_start_time_fp);
789 if (compare_result_2 == 2)
790 tu->min_hblank_violated = 1;
791
792 tu->delay_start_time_fp = 0;
793
794 /* brute force */
795
796 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
797 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
798
799 temp = drm_fixp2int(tu->diff_abs_fp);
800 if (!temp && tu->diff_abs_fp <= 0xffff)
801 tu->diff_abs_fp = 0;
802
803 /* if(diff_abs < 0) diff_abs *= -1 */
804 if (tu->diff_abs_fp < 0)
805 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
806
807 tu->boundary_mod_lower_err = 0;
808 if ((tu->diff_abs_fp != 0 &&
809 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
810 (tu->even_distribution_legacy == 0) ||
811 (DP_BRUTE_FORCE == 1))) ||
812 (tu->min_hblank_violated == 1)) {
813 do {
814 tu->err_fp = drm_fixp_from_fraction(1000, 1);
815
816 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
817 temp2_fp = drm_fixp_from_fraction(
818 tu->delay_start_link_extra_pixclk, 1);
819 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
820
821 if (temp1_fp)
822 tu->extra_buffer_margin =
823 drm_fixp2int_ceil(temp1_fp);
824 else
825 tu->extra_buffer_margin = 0;
826
827 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
828 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
829
830 if (temp1_fp)
831 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
832 else
833 tu->n_symbols = 0;
834
835 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
836 for (tu->i_upper_boundary_count = 1;
837 tu->i_upper_boundary_count <= 15;
838 tu->i_upper_boundary_count++) {
839 for (tu->i_lower_boundary_count = 1;
840 tu->i_lower_boundary_count <= 15;
841 tu->i_lower_boundary_count++) {
842 _tu_valid_boundary_calc(tu);
843 }
844 }
845 }
846 tu->delay_start_link_extra_pixclk--;
847 } while (tu->boundary_moderation_en != true &&
848 tu->boundary_mod_lower_err == 1 &&
849 tu->delay_start_link_extra_pixclk != 0);
850
851 if (tu->boundary_moderation_en == true) {
852 temp1_fp = drm_fixp_from_fraction(
853 (tu->upper_boundary_count *
854 tu->valid_boundary_link +
855 tu->lower_boundary_count *
856 (tu->valid_boundary_link - 1)), 1);
857 temp2_fp = drm_fixp_from_fraction(
858 (tu->upper_boundary_count +
859 tu->lower_boundary_count), 1);
860 tu->resulting_valid_fp =
861 drm_fixp_div(temp1_fp, temp2_fp);
862
863 temp1_fp = drm_fixp_from_fraction(
864 tu->tu_size_desired, 1);
865 tu->ratio_by_tu_fp =
866 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
867
868 tu->valid_lower_boundary_link =
869 tu->valid_boundary_link - 1;
870
871 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
872 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
873 temp2_fp = drm_fixp_div(temp1_fp,
874 tu->resulting_valid_fp);
875 tu->n_tus = drm_fixp2int(temp2_fp);
876
877 tu->tu_size_minus1 = tu->tu_size_desired - 1;
878 tu->even_distribution_BF = 1;
879
880 temp1_fp =
881 drm_fixp_from_fraction(tu->tu_size_desired, 1);
882 temp2_fp =
883 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
884 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
885 }
886 }
887
888 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
889
890 if (temp2_fp)
891 temp = drm_fixp2int_ceil(temp2_fp);
892 else
893 temp = 0;
894
895 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
896 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
897 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
898 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
899 temp1_fp = drm_fixp_from_fraction(temp, 1);
900 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
901 temp = drm_fixp2int(temp2_fp);
902
903 if (tu->async_en)
904 tu->delay_start_link += (int)temp;
905
906 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
907 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
908
909 /* OUTPUTS */
910 tu_table->valid_boundary_link = tu->valid_boundary_link;
911 tu_table->delay_start_link = tu->delay_start_link;
912 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
913 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
914 tu_table->upper_boundary_count = tu->upper_boundary_count;
915 tu_table->lower_boundary_count = tu->lower_boundary_count;
916 tu_table->tu_size_minus1 = tu->tu_size_minus1;
917
918 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n",
919 tu_table->valid_boundary_link);
920 DRM_DEBUG_DP("TU: delay_start_link: %d\n",
921 tu_table->delay_start_link);
922 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n",
923 tu_table->boundary_moderation_en);
924 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n",
925 tu_table->valid_lower_boundary_link);
926 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n",
927 tu_table->upper_boundary_count);
928 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n",
929 tu_table->lower_boundary_count);
930 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1);
931
932 kfree(tu);
933}
934
935static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
936 struct dp_vc_tu_mapping_table *tu_table)
937{
938 struct dp_tu_calc_input in;
939 struct drm_display_mode *drm_mode;
940
941 drm_mode = &ctrl->panel->dp_mode.drm_mode;
942
943 in.lclk = ctrl->link->link_params.rate / 1000;
944 in.pclk_khz = drm_mode->clock;
945 in.hactive = drm_mode->hdisplay;
946 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
947 in.nlanes = ctrl->link->link_params.num_lanes;
948 in.bpp = ctrl->panel->dp_mode.bpp;
949 in.pixel_enc = 444;
950 in.dsc_en = 0;
951 in.async_en = 0;
952 in.fec_en = 0;
953 in.num_of_dsc_slices = 0;
954 in.compress_ratio = 100;
955
956 _dp_ctrl_calc_tu(&in, tu_table);
957}
958
959static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
960{
961 u32 dp_tu = 0x0;
962 u32 valid_boundary = 0x0;
963 u32 valid_boundary2 = 0x0;
964 struct dp_vc_tu_mapping_table tu_calc_table;
965
966 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
967
968 dp_tu |= tu_calc_table.tu_size_minus1;
969 valid_boundary |= tu_calc_table.valid_boundary_link;
970 valid_boundary |= (tu_calc_table.delay_start_link << 16);
971
972 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
973 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
974 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
975
976 if (tu_calc_table.boundary_moderation_en)
977 valid_boundary2 |= BIT(0);
978
979 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
980 dp_tu, valid_boundary, valid_boundary2);
981
982 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
983 dp_tu, valid_boundary, valid_boundary2);
984}
985
986static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
987{
988 int ret = 0;
989
990 if (!wait_for_completion_timeout(&ctrl->video_comp,
991 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
992 DRM_ERROR("wait4video timedout\n");
993 ret = -ETIMEDOUT;
994 }
995 return ret;
996}
997
998static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
999{
1000 struct dp_link *link = ctrl->link;
1001 int ret = 0, lane, lane_cnt;
1002 u8 buf[4];
1003 u32 max_level_reached = 0;
1004 u32 voltage_swing_level = link->phy_params.v_level;
1005 u32 pre_emphasis_level = link->phy_params.p_level;
1006
1007 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1008 voltage_swing_level, pre_emphasis_level);
1009
1010 if (ret)
1011 return ret;
1012
1013 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1014 DRM_DEBUG_DP("max. voltage swing level reached %d\n",
1015 voltage_swing_level);
1016 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1017 }
1018
1019 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1020 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n",
1021 pre_emphasis_level);
1022 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1023 }
1024
1025 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1026
1027 lane_cnt = ctrl->link->link_params.num_lanes;
1028 for (lane = 0; lane < lane_cnt; lane++)
1029 buf[lane] = voltage_swing_level | pre_emphasis_level
1030 | max_level_reached;
1031
1032 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level
1033 | pre_emphasis_level);
1034 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1035 buf, lane_cnt);
1036 if (ret == lane_cnt)
1037 ret = 0;
1038
1039 return ret;
1040}
1041
1042static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1043 u8 pattern)
1044{
1045 u8 buf;
1046 int ret = 0;
1047
1048 DRM_DEBUG_DP("sink: pattern=%x\n", pattern);
1049
1050 buf = pattern;
1051
1052 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1053 buf |= DP_LINK_SCRAMBLING_DISABLE;
1054
1055 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1056 return ret == 1;
1057}
1058
1059static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1060 u8 *link_status)
1061{
1062 int ret = 0, len;
1063
1064 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1065 if (len != DP_LINK_STATUS_SIZE) {
1066 DRM_ERROR("DP link status read failed, err: %d\n", len);
1067 ret = -EINVAL;
1068 }
1069
1070 return ret;
1071}
1072
1073static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1074 int *training_step)
1075{
1076 int tries, old_v_level, ret = 0;
1077 u8 link_status[DP_LINK_STATUS_SIZE];
1078 int const maximum_retries = 4;
1079
1080 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1081
1082 *training_step = DP_TRAINING_1;
1083
1084 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1);
1085 if (ret)
1086 return ret;
1087 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1088 DP_LINK_SCRAMBLING_DISABLE);
1089
1090 ret = dp_ctrl_update_vx_px(ctrl);
1091 if (ret)
1092 return ret;
1093
1094 tries = 0;
1095 old_v_level = ctrl->link->phy_params.v_level;
1096 for (tries = 0; tries < maximum_retries; tries++) {
1097 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1098
1099 ret = dp_ctrl_read_link_status(ctrl, link_status);
1100 if (ret)
1101 return ret;
1102
1103 if (drm_dp_clock_recovery_ok(link_status,
1104 ctrl->link->link_params.num_lanes)) {
1105 return 0;
1106 }
1107
1108 if (ctrl->link->phy_params.v_level >=
1109 DP_TRAIN_VOLTAGE_SWING_MAX) {
1110 DRM_ERROR_RATELIMITED("max v_level reached\n");
1111 return -EAGAIN;
1112 }
1113
1114 if (old_v_level != ctrl->link->phy_params.v_level) {
1115 tries = 0;
1116 old_v_level = ctrl->link->phy_params.v_level;
1117 }
1118
1119 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n");
1120
1121 dp_link_adjust_levels(ctrl->link, link_status);
1122 ret = dp_ctrl_update_vx_px(ctrl);
1123 if (ret)
1124 return ret;
1125 }
1126
1127 DRM_ERROR("max tries reached\n");
1128 return -ETIMEDOUT;
1129}
1130
1131static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1132{
1133 int ret = 0;
1134
1135 switch (ctrl->link->link_params.rate) {
1136 case 810000:
1137 ctrl->link->link_params.rate = 540000;
1138 break;
1139 case 540000:
1140 ctrl->link->link_params.rate = 270000;
1141 break;
1142 case 270000:
1143 ctrl->link->link_params.rate = 162000;
1144 break;
1145 case 162000:
1146 default:
1147 ret = -EINVAL;
1148 break;
1149 }
1150
1151 if (!ret)
1152 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate);
1153
1154 return ret;
1155}
1156
1157static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1158{
1159
1160 if (ctrl->link->link_params.num_lanes == 1)
1161 return -1;
1162
1163 ctrl->link->link_params.num_lanes /= 2;
1164 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1165
1166 ctrl->link->phy_params.p_level = 0;
1167 ctrl->link->phy_params.v_level = 0;
1168
1169 return 0;
1170}
1171
1172static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1173{
1174 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1175 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1176}
1177
1178static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1179 int *training_step)
1180{
1181 int tries = 0, ret = 0;
1182 char pattern;
1183 int const maximum_retries = 5;
1184 u8 link_status[DP_LINK_STATUS_SIZE];
1185
1186 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1187
1188 *training_step = DP_TRAINING_2;
1189
1190 if (drm_dp_tps3_supported(ctrl->panel->dpcd))
1191 pattern = DP_TRAINING_PATTERN_3;
1192 else
1193 pattern = DP_TRAINING_PATTERN_2;
1194
1195 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern);
1196 if (ret)
1197 return ret;
1198
1199 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);
1200
1201 for (tries = 0; tries <= maximum_retries; tries++) {
1202 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1203
1204 ret = dp_ctrl_read_link_status(ctrl, link_status);
1205 if (ret)
1206 return ret;
1207
1208 if (drm_dp_channel_eq_ok(link_status,
1209 ctrl->link->link_params.num_lanes)) {
1210 return 0;
1211 }
1212
1213 dp_link_adjust_levels(ctrl->link, link_status);
1214 ret = dp_ctrl_update_vx_px(ctrl);
1215 if (ret)
1216 return ret;
1217
1218 }
1219
1220 return -ETIMEDOUT;
1221}
1222
1223static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1224
1225static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1226 int *training_step)
1227{
1228 int ret = 0;
1229 u8 encoding = DP_SET_ANSI_8B10B;
1230 struct dp_link_info link_info = {0};
1231
1232 dp_ctrl_config_ctrl(ctrl);
1233
1234 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1235 link_info.rate = ctrl->link->link_params.rate;
1236 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1237
1238 dp_aux_link_configure(ctrl->aux, &link_info);
1239 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1240 &encoding, 1);
1241
1242 ret = dp_ctrl_link_train_1(ctrl, training_step);
1243 if (ret) {
1244 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1245 goto end;
1246 }
1247
1248 /* print success info as this is a result of user initiated action */
1249 DRM_DEBUG_DP("link training #1 successful\n");
1250
1251 ret = dp_ctrl_link_train_2(ctrl, training_step);
1252 if (ret) {
1253 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1254 goto end;
1255 }
1256
1257 /* print success info as this is a result of user initiated action */
1258 DRM_DEBUG_DP("link training #2 successful\n");
1259
1260end:
1261 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1262
1263 return ret;
1264}
1265
1266static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1267 int *training_step)
1268{
1269 int ret = 0;
1270
1271 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1272
1273 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1274 return ret;
1275
1276 /*
1277 * As part of previous calls, DP controller state might have
1278 * transitioned to PUSH_IDLE. In order to start transmitting
1279 * a link training pattern, we have to first do soft reset.
1280 */
1281
1282 ret = dp_ctrl_link_train(ctrl, training_step);
1283
1284 return ret;
1285}
1286
1287static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1288 enum dp_pm_type module, char *name, unsigned long rate)
1289{
1290 u32 num = ctrl->parser->mp[module].num_clk;
1291 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1292
1293 while (num && strcmp(cfg->clk_name, name)) {
1294 num--;
1295 cfg++;
1296 }
1297
1298 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
1299
1300 if (num)
1301 cfg->rate = rate;
1302 else
1303 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1304 name, rate);
1305}
1306
1307static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1308{
1309 int ret = 0;
1310 struct dp_io *dp_io = &ctrl->parser->io;
1311 struct phy *phy = dp_io->phy;
1312 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1313
1314 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1315 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1316 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1317 ctrl->link->link_params.rate * 1000);
1318
1319 phy_configure(phy, &dp_io->phy_opts);
1320 phy_power_on(phy);
1321
1322 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1323 if (ret)
1324 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1325
1326 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1327 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1328
1329 return ret;
1330}
1331
1332static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1333{
1334 int ret = 0;
1335
1336 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1337 ctrl->dp_ctrl.pixel_rate * 1000);
1338
1339 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1340 if (ret)
1341 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1342
1343 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1344 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1345
1346 return ret;
1347}
1348
1349int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
1350{
1351 struct dp_ctrl_private *ctrl;
1352 struct dp_io *dp_io;
1353 struct phy *phy;
1354
1355 if (!dp_ctrl) {
1356 DRM_ERROR("Invalid input data\n");
1357 return -EINVAL;
1358 }
1359
1360 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1361 dp_io = &ctrl->parser->io;
1362 phy = dp_io->phy;
1363
1364 ctrl->dp_ctrl.orientation = flip;
1365
1366 if (reset)
1367 dp_catalog_ctrl_reset(ctrl->catalog);
1368
1369 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1370 phy_init(phy);
1371 dp_catalog_ctrl_enable_irq(ctrl->catalog, true);
1372
1373 return 0;
1374}
1375
1376/**
1377 * dp_ctrl_host_deinit() - Uninitialize DP controller
1378 * @dp_ctrl: Display Port Driver data
1379 *
1380 * Perform required steps to uninitialize DP controller
1381 * and its resources.
1382 */
1383void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
1384{
1385 struct dp_ctrl_private *ctrl;
1386 struct dp_io *dp_io;
1387 struct phy *phy;
1388
1389 if (!dp_ctrl) {
1390 DRM_ERROR("Invalid input data\n");
1391 return;
1392 }
1393
1394 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1395 dp_io = &ctrl->parser->io;
1396 phy = dp_io->phy;
1397
1398 dp_catalog_ctrl_enable_irq(ctrl->catalog, false);
1399 phy_exit(phy);
1400
1401 DRM_DEBUG_DP("Host deinitialized successfully\n");
1402}
1403
1404static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1405{
1406 u8 *dpcd = ctrl->panel->dpcd;
1407
1408 /*
1409 * For better interop experience, used a fixed NVID=0x8000
1410 * whenever connected to a VGA dongle downstream.
1411 */
1412 if (drm_dp_is_branch(dpcd))
1413 return (drm_dp_has_quirk(&ctrl->panel->desc,
1414 DP_DPCD_QUIRK_CONSTANT_N));
1415
1416 return false;
1417}
1418
1419static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1420{
1421 int ret = 0;
1422 struct dp_io *dp_io = &ctrl->parser->io;
1423 struct phy *phy = dp_io->phy;
1424 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1425
1426 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1427 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1428 phy_configure(phy, &dp_io->phy_opts);
1429 /*
1430 * Disable and re-enable the mainlink clock since the
1431 * link clock might have been adjusted as part of the
1432 * link maintenance.
1433 */
1434 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1435 if (ret) {
1436 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1437 return ret;
1438 }
1439 phy_power_off(phy);
1440 /* hw recommended delay before re-enabling clocks */
1441 msleep(20);
1442
1443 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1444 if (ret) {
1445 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1446 return ret;
1447 }
1448
1449 return ret;
1450}
1451
1452static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1453{
1454 struct dp_io *dp_io;
1455 struct phy *phy;
1456 int ret;
1457
1458 dp_io = &ctrl->parser->io;
1459 phy = dp_io->phy;
1460
1461 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1462
1463 dp_catalog_ctrl_reset(ctrl->catalog);
1464
1465 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1466 if (ret) {
1467 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1468 }
1469
1470 phy_power_off(phy);
1471 phy_exit(phy);
1472
1473 return 0;
1474}
1475
1476static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1477{
1478 int ret = 0;
1479 int training_step = DP_TRAINING_NONE;
1480
1481 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1482
1483 ctrl->link->phy_params.p_level = 0;
1484 ctrl->link->phy_params.v_level = 0;
1485
1486 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1487
1488 ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1489 if (ret)
1490 goto end;
1491
1492 dp_ctrl_clear_training_pattern(ctrl);
1493
1494 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1495
1496 ret = dp_ctrl_wait4video_ready(ctrl);
1497end:
1498 return ret;
1499}
1500
1501static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1502{
1503 int ret = 0;
1504
1505 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1506 DRM_DEBUG_DP("no test pattern selected by sink\n");
1507 return ret;
1508 }
1509
1510 /*
1511 * The global reset will need DP link related clocks to be
1512 * running. Add the global reset just before disabling the
1513 * link clocks and core clocks.
1514 */
1515 ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl);
1516 if (ret) {
1517 DRM_ERROR("failed to disable DP controller\n");
1518 return ret;
1519 }
1520
1521 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1522 if (!ret)
1523 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1524 else
1525 DRM_ERROR("failed to enable DP link controller\n");
1526
1527 return ret;
1528}
1529
1530static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1531{
1532 bool success = false;
1533 u32 pattern_sent = 0x0;
1534 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1535
1536 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested);
1537
1538 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1539 ctrl->link->phy_params.v_level,
1540 ctrl->link->phy_params.p_level)) {
1541 DRM_ERROR("Failed to set v/p levels\n");
1542 return false;
1543 }
1544 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1545 dp_ctrl_update_vx_px(ctrl);
1546 dp_link_send_test_response(ctrl->link);
1547
1548 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1549
1550 switch (pattern_sent) {
1551 case MR_LINK_TRAINING1:
1552 success = (pattern_requested ==
1553 DP_PHY_TEST_PATTERN_D10_2);
1554 break;
1555 case MR_LINK_SYMBOL_ERM:
1556 success = ((pattern_requested ==
1557 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1558 (pattern_requested ==
1559 DP_PHY_TEST_PATTERN_CP2520));
1560 break;
1561 case MR_LINK_PRBS7:
1562 success = (pattern_requested ==
1563 DP_PHY_TEST_PATTERN_PRBS7);
1564 break;
1565 case MR_LINK_CUSTOM80:
1566 success = (pattern_requested ==
1567 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1568 break;
1569 case MR_LINK_TRAINING4:
1570 success = (pattern_requested ==
1571 DP_PHY_TEST_PATTERN_SEL_MASK);
1572 break;
1573 default:
1574 success = false;
1575 }
1576
1577 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed",
1578 pattern_requested);
1579 return success;
1580}
1581
1582void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1583{
1584 struct dp_ctrl_private *ctrl;
1585 u32 sink_request = 0x0;
1586
1587 if (!dp_ctrl) {
1588 DRM_ERROR("invalid input\n");
1589 return;
1590 }
1591
1592 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1593 sink_request = ctrl->link->sink_request;
1594
1595 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1596 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n");
1597 if (dp_ctrl_process_phy_test_request(ctrl)) {
1598 DRM_ERROR("process phy_test_req failed\n");
1599 return;
1600 }
1601 }
1602
1603 if (sink_request & DP_LINK_STATUS_UPDATED) {
1604 if (dp_ctrl_link_maintenance(ctrl)) {
1605 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1606 return;
1607 }
1608 }
1609
1610 if (sink_request & DP_TEST_LINK_TRAINING) {
1611 dp_link_send_test_response(ctrl->link);
1612 if (dp_ctrl_link_maintenance(ctrl)) {
1613 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1614 return;
1615 }
1616 }
1617}
1618
1619static bool dp_ctrl_clock_recovery_any_ok(
1620 const u8 link_status[DP_LINK_STATUS_SIZE],
1621 int lane_count)
1622{
1623 int reduced_cnt;
1624
1625 if (lane_count <= 1)
1626 return false;
1627
1628 /*
1629 * only interested in the lane number after reduced
1630 * lane_count = 4, then only interested in 2 lanes
1631 * lane_count = 2, then only interested in 1 lane
1632 */
1633 reduced_cnt = lane_count >> 1;
1634
1635 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1636}
1637
1638static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1639{
1640 u8 link_status[DP_LINK_STATUS_SIZE];
1641 int num_lanes = ctrl->link->link_params.num_lanes;
1642
1643 dp_ctrl_read_link_status(ctrl, link_status);
1644
1645 return drm_dp_channel_eq_ok(link_status, num_lanes);
1646}
1647
1648int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1649{
1650 int rc = 0;
1651 struct dp_ctrl_private *ctrl;
1652 u32 rate = 0;
1653 int link_train_max_retries = 5;
1654 u32 const phy_cts_pixel_clk_khz = 148500;
1655 u8 link_status[DP_LINK_STATUS_SIZE];
1656 unsigned int training_step;
1657
1658 if (!dp_ctrl)
1659 return -EINVAL;
1660
1661 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1662
1663 rate = ctrl->panel->link_info.rate;
1664
1665 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1666
1667 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1668 DRM_DEBUG_DP("using phy test link parameters\n");
1669 if (!ctrl->panel->dp_mode.drm_mode.clock)
1670 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1671 } else {
1672 ctrl->link->link_params.rate = rate;
1673 ctrl->link->link_params.num_lanes =
1674 ctrl->panel->link_info.num_lanes;
1675 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1676 }
1677
1678 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1679 ctrl->link->link_params.rate,
1680 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1681
1682 ctrl->link->phy_params.p_level = 0;
1683 ctrl->link->phy_params.v_level = 0;
1684
1685 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1686 if (rc)
1687 return rc;
1688
1689 while (--link_train_max_retries) {
1690 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1691 if (rc) {
1692 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1693 rc);
1694 break;
1695 }
1696
1697 training_step = DP_TRAINING_NONE;
1698 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1699 if (rc == 0) {
1700 /* training completed successfully */
1701 break;
1702 } else if (training_step == DP_TRAINING_1) {
1703 /* link train_1 failed */
1704 if (!dp_catalog_link_is_connected(ctrl->catalog))
1705 break;
1706
1707 dp_ctrl_read_link_status(ctrl, link_status);
1708
1709 rc = dp_ctrl_link_rate_down_shift(ctrl);
1710 if (rc < 0) { /* already in RBR = 1.6G */
1711 if (dp_ctrl_clock_recovery_any_ok(link_status,
1712 ctrl->link->link_params.num_lanes)) {
1713 /*
1714 * some lanes are ready,
1715 * reduce lane number
1716 */
1717 rc = dp_ctrl_link_lane_down_shift(ctrl);
1718 if (rc < 0) { /* lane == 1 already */
1719 /* end with failure */
1720 break;
1721 }
1722 } else {
1723 /* end with failure */
1724 break; /* lane == 1 already */
1725 }
1726 }
1727 } else if (training_step == DP_TRAINING_2) {
1728 /* link train_2 failed */
1729 if (!dp_catalog_link_is_connected(ctrl->catalog))
1730 break;
1731
1732 dp_ctrl_read_link_status(ctrl, link_status);
1733
1734 if (!drm_dp_clock_recovery_ok(link_status,
1735 ctrl->link->link_params.num_lanes))
1736 rc = dp_ctrl_link_rate_down_shift(ctrl);
1737 else
1738 rc = dp_ctrl_link_lane_down_shift(ctrl);
1739
1740 if (rc < 0) {
1741 /* end with failure */
1742 break; /* lane == 1 already */
1743 }
1744 }
1745 }
1746
1747 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1748 return rc;
1749
1750 if (rc == 0) { /* link train successfully */
1751 /*
1752 * do not stop train pattern here
1753 * stop link training at on_stream
1754 * to pass compliance test
1755 */
1756 } else {
1757 /*
1758 * link training failed
1759 * end txing train pattern here
1760 */
1761 dp_ctrl_clear_training_pattern(ctrl);
1762
1763 dp_ctrl_deinitialize_mainlink(ctrl);
1764 rc = -ECONNRESET;
1765 }
1766
1767 return rc;
1768}
1769
1770static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1771{
1772 int training_step = DP_TRAINING_NONE;
1773
1774 return dp_ctrl_setup_main_link(ctrl, &training_step);
1775}
1776
1777int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1778{
1779 int ret = 0;
1780 bool mainlink_ready = false;
1781 struct dp_ctrl_private *ctrl;
1782
1783 if (!dp_ctrl)
1784 return -EINVAL;
1785
1786 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1787
1788 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1789
1790 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1791 ctrl->link->link_params.rate,
1792 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1793
1794 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1795 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1796 if (ret) {
1797 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1798 goto end;
1799 }
1800 }
1801
1802 if (!dp_ctrl_channel_eq_ok(ctrl))
1803 dp_ctrl_link_retrain(ctrl);
1804
1805 /* stop txing train pattern to end link training */
1806 dp_ctrl_clear_training_pattern(ctrl);
1807
1808 ret = dp_ctrl_enable_stream_clocks(ctrl);
1809 if (ret) {
1810 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1811 goto end;
1812 }
1813
1814 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1815 dp_ctrl_send_phy_test_pattern(ctrl);
1816 return 0;
1817 }
1818
1819 /*
1820 * Set up transfer unit values and set controller state to send
1821 * video.
1822 */
1823 reinit_completion(&ctrl->video_comp);
1824
1825 dp_ctrl_configure_source_params(ctrl);
1826
1827 dp_catalog_ctrl_config_msa(ctrl->catalog,
1828 ctrl->link->link_params.rate,
1829 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl));
1830
1831 dp_ctrl_setup_tr_unit(ctrl);
1832
1833 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1834
1835 ret = dp_ctrl_wait4video_ready(ctrl);
1836 if (ret)
1837 return ret;
1838
1839 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1840 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1841
1842end:
1843 return ret;
1844}
1845
1846int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1847{
1848 struct dp_ctrl_private *ctrl;
1849 struct dp_io *dp_io;
1850 struct phy *phy;
1851 int ret;
1852
1853 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1854 dp_io = &ctrl->parser->io;
1855 phy = dp_io->phy;
1856
1857 /* set dongle to D3 (power off) mode */
1858 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1859
1860 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1861
1862 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1863 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1864 if (ret) {
1865 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1866 return ret;
1867 }
1868 }
1869
1870 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1871 if (ret) {
1872 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1873 return ret;
1874 }
1875
1876 phy_power_off(phy);
1877
1878 /* aux channel down, reinit phy */
1879 phy_exit(phy);
1880 phy_init(phy);
1881
1882 DRM_DEBUG_DP("DP off link/stream done\n");
1883 return ret;
1884}
1885
1886void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl)
1887{
1888 struct dp_ctrl_private *ctrl;
1889 struct dp_io *dp_io;
1890 struct phy *phy;
1891
1892 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1893 dp_io = &ctrl->parser->io;
1894 phy = dp_io->phy;
1895
1896 dp_catalog_ctrl_reset(ctrl->catalog);
1897
1898 phy_exit(phy);
1899
1900 DRM_DEBUG_DP("DP off phy done\n");
1901}
1902
1903int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1904{
1905 struct dp_ctrl_private *ctrl;
1906 struct dp_io *dp_io;
1907 struct phy *phy;
1908 int ret = 0;
1909
1910 if (!dp_ctrl)
1911 return -EINVAL;
1912
1913 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1914 dp_io = &ctrl->parser->io;
1915 phy = dp_io->phy;
1916
1917 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1918
1919 dp_catalog_ctrl_reset(ctrl->catalog);
1920
1921 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1922 if (ret)
1923 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
1924
1925 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1926 if (ret) {
1927 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1928 }
1929
1930 phy_power_off(phy);
1931 phy_exit(phy);
1932
1933 DRM_DEBUG_DP("DP off done\n");
1934 return ret;
1935}
1936
1937void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
1938{
1939 struct dp_ctrl_private *ctrl;
1940 u32 isr;
1941
1942 if (!dp_ctrl)
1943 return;
1944
1945 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1946
1947 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
1948
1949 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
1950 DRM_DEBUG_DP("dp_video_ready\n");
1951 complete(&ctrl->video_comp);
1952 }
1953
1954 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
1955 DRM_DEBUG_DP("idle_patterns_sent\n");
1956 complete(&ctrl->idle_comp);
1957 }
1958}
1959
1960struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
1961 struct dp_panel *panel, struct drm_dp_aux *aux,
1962 struct dp_power *power, struct dp_catalog *catalog,
1963 struct dp_parser *parser)
1964{
1965 struct dp_ctrl_private *ctrl;
1966 int ret;
1967
1968 if (!dev || !panel || !aux ||
1969 !link || !catalog) {
1970 DRM_ERROR("invalid input\n");
1971 return ERR_PTR(-EINVAL);
1972 }
1973
1974 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1975 if (!ctrl) {
1976 DRM_ERROR("Mem allocation failure\n");
1977 return ERR_PTR(-ENOMEM);
1978 }
1979
1980 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1981 if (ret) {
1982 dev_err(dev, "invalid DP OPP table in device tree\n");
1983 /* caller do PTR_ERR(opp_table) */
1984 return (struct dp_ctrl *)ERR_PTR(ret);
1985 }
1986
1987 /* OPP table is optional */
1988 ret = devm_pm_opp_of_add_table(dev);
1989 if (ret)
1990 dev_err(dev, "failed to add DP OPP table\n");
1991
1992 init_completion(&ctrl->idle_comp);
1993 init_completion(&ctrl->video_comp);
1994
1995 /* in parameters */
1996 ctrl->parser = parser;
1997 ctrl->panel = panel;
1998 ctrl->power = power;
1999 ctrl->aux = aux;
2000 ctrl->link = link;
2001 ctrl->catalog = catalog;
2002 ctrl->dev = dev;
2003
2004 return &ctrl->dp_ctrl;
2005}