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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5#include "msm_gem.h"
6#include "msm_mmu.h"
7#include "msm_gpu_trace.h"
8#include "a6xx_gpu.h"
9#include "a6xx_gmu.xml.h"
10
11#include <linux/bitfield.h>
12#include <linux/devfreq.h>
13#include <linux/nvmem-consumer.h>
14#include <linux/soc/qcom/llcc-qcom.h>
15
16#define GPU_PAS_ID 13
17
18static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
19{
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
22
23 /* Check that the GMU is idle */
24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
25 return false;
26
27 /* Check tha the CX master is idle */
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
30 return false;
31
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
34}
35
36static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
37{
38 /* wait for CP to drain ringbuffer: */
39 if (!adreno_idle(gpu, ring))
40 return false;
41
42 if (spin_until(_a6xx_check_idle(gpu))) {
43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
44 gpu->name, __builtin_return_address(0),
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
49 return false;
50 }
51
52 return true;
53}
54
55static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
56{
57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
59 uint32_t wptr;
60 unsigned long flags;
61
62 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
63 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
64 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
65
66 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
67 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
68 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
69 }
70
71 spin_lock_irqsave(&ring->preempt_lock, flags);
72
73 /* Copy the shadow to the actual register */
74 ring->cur = ring->next;
75
76 /* Make sure to wrap wptr if we need to */
77 wptr = get_wptr(ring);
78
79 spin_unlock_irqrestore(&ring->preempt_lock, flags);
80
81 /* Make sure everything is posted before making a decision */
82 mb();
83
84 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
85}
86
87static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
88 u64 iova)
89{
90 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
91 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
92 CP_REG_TO_MEM_0_CNT(2) |
93 CP_REG_TO_MEM_0_64B);
94 OUT_RING(ring, lower_32_bits(iova));
95 OUT_RING(ring, upper_32_bits(iova));
96}
97
98static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
99 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
100{
101 phys_addr_t ttbr;
102 u32 asid;
103 u64 memptr = rbmemptr(ring, ttbr0);
104
105 if (ctx->seqno == a6xx_gpu->cur_ctx_seqno)
106 return;
107
108 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
109 return;
110
111 /* Execute the table update */
112 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
113 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
114
115 OUT_RING(ring,
116 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
117 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
118 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
119 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
120
121 /*
122 * Write the new TTBR0 to the memstore. This is good for debugging.
123 */
124 OUT_PKT7(ring, CP_MEM_WRITE, 4);
125 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
126 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
127 OUT_RING(ring, lower_32_bits(ttbr));
128 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
129
130 /*
131 * And finally, trigger a uche flush to be sure there isn't anything
132 * lingering in that part of the GPU
133 */
134
135 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
136 OUT_RING(ring, 0x31);
137
138 a6xx_gpu->cur_ctx_seqno = ctx->seqno;
139}
140
141static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
142{
143 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
144 struct msm_drm_private *priv = gpu->dev->dev_private;
145 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
146 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
147 struct msm_ringbuffer *ring = submit->ring;
148 unsigned int i;
149
150 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
151
152 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
153 rbmemptr_stats(ring, index, cpcycles_start));
154
155 /*
156 * For PM4 the GMU register offsets are calculated from the base of the
157 * GPU registers so we need to add 0x1a800 to the register value on A630
158 * to get the right value from PM4.
159 */
160 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
161 rbmemptr_stats(ring, index, alwayson_start));
162
163 /* Invalidate CCU depth and color */
164 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
165 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
166
167 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
168 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
169
170 /* Submit the commands */
171 for (i = 0; i < submit->nr_cmds; i++) {
172 switch (submit->cmd[i].type) {
173 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
174 break;
175 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
176 if (priv->lastctx == submit->queue->ctx)
177 break;
178 fallthrough;
179 case MSM_SUBMIT_CMD_BUF:
180 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
181 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
182 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
183 OUT_RING(ring, submit->cmd[i].size);
184 break;
185 }
186 }
187
188 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
189 rbmemptr_stats(ring, index, cpcycles_end));
190 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191 rbmemptr_stats(ring, index, alwayson_end));
192
193 /* Write the fence to the scratch register */
194 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
195 OUT_RING(ring, submit->seqno);
196
197 /*
198 * Execute a CACHE_FLUSH_TS event. This will ensure that the
199 * timestamp is written to the memory and then triggers the interrupt
200 */
201 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
202 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
203 CP_EVENT_WRITE_0_IRQ);
204 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
205 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
206 OUT_RING(ring, submit->seqno);
207
208 trace_msm_gpu_submit_flush(submit,
209 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
210 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
211
212 a6xx_flush(gpu, ring);
213}
214
215const struct adreno_reglist a630_hwcg[] = {
216 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
217 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
218 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
219 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
221 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
222 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
223 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
224 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
225 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
226 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
227 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
228 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
229 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
230 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
231 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
232 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
233 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
234 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
235 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
237 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
238 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
239 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
241 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
242 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
243 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
245 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
246 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
247 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
248 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
249 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
250 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
251 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
252 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
253 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
254 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
255 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
256 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
257 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
258 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
259 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
260 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
261 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
262 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
263 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
264 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
265 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
266 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
267 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
269 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
270 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
271 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
273 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
274 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
275 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
277 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
278 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
279 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
280 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
281 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
282 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
283 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
284 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
285 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
286 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
287 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
289 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
291 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
292 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
293 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
295 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
296 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
297 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
299 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
300 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
301 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
302 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
303 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
304 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
305 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
306 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
307 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
308 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
309 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
310 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
311 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
312 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
313 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
314 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
315 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
316 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
317 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
318 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
319 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
320 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
321 {},
322};
323
324const struct adreno_reglist a640_hwcg[] = {
325 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
326 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
327 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
328 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
329 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
330 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
331 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
332 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
334 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
335 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
336 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
337 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
338 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
339 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
340 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
341 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
342 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
343 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
344 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
345 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
346 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
347 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
348 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
349 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
350 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
351 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
352 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
353 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
354 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
355 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
357 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
358 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
359 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
360 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
361 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
362 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
363 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
364 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
365 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
366 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
367 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
368 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
369 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
370 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
371 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
372 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
373 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
374 {},
375};
376
377const struct adreno_reglist a650_hwcg[] = {
378 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
379 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
380 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
381 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
382 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
383 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
384 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
385 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
387 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
388 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
389 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
390 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
391 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
392 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
393 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
394 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
395 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
396 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
397 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
398 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
399 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
400 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
401 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
402 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
403 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
404 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
405 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
406 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
407 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
408 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
410 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
411 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
412 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
413 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
414 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
415 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
416 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
417 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
418 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
419 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
420 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
421 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
422 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
423 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
424 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
425 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
426 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
427 {},
428};
429
430const struct adreno_reglist a660_hwcg[] = {
431 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
432 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
433 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
434 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
435 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
436 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
437 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
438 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
439 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
440 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
441 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
442 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
443 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
444 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
445 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
446 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
447 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
448 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
449 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
450 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
451 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
452 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
453 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
454 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
455 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
456 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
457 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
458 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
459 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
460 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
461 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
462 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
463 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
464 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
465 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
466 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
467 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
468 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
469 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
470 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
471 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
472 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
473 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
474 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
475 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
476 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
477 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
478 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
479 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
480 {},
481};
482
483static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
484{
485 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
486 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
487 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
488 const struct adreno_reglist *reg;
489 unsigned int i;
490 u32 val, clock_cntl_on;
491
492 if (!adreno_gpu->info->hwcg)
493 return;
494
495 if (adreno_is_a630(adreno_gpu))
496 clock_cntl_on = 0x8aa8aa02;
497 else
498 clock_cntl_on = 0x8aa8aa82;
499
500 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
501
502 /* Don't re-program the registers if they are already correct */
503 if ((!state && !val) || (state && (val == clock_cntl_on)))
504 return;
505
506 /* Disable SP clock before programming HWCG registers */
507 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
508
509 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
510 gpu_write(gpu, reg->offset, state ? reg->value : 0);
511
512 /* Enable SP clock */
513 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
514
515 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
516}
517
518/* For a615, a616, a618, A619, a630, a640 and a680 */
519static const u32 a6xx_protect[] = {
520 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
521 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
522 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
523 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
524 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
525 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
526 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
527 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
528 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
529 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
530 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
531 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
532 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
533 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
534 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
535 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
536 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
537 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
538 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
539 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
540 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
541 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
542 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
543 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
544 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
545 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
546 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
547 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
548 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
549 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
550 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
551 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
552};
553
554/* These are for a620 and a650 */
555static const u32 a650_protect[] = {
556 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
557 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
558 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
559 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
560 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
561 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
562 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
563 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
564 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
565 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
566 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
567 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
568 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
569 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
570 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
571 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
572 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
573 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
574 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
575 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
576 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
577 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
578 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
579 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
580 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
581 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
582 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
583 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
584 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
585 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
586 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
587 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
588 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
589 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
590 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
591 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
592 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
593 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
594 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
595};
596
597/* These are for a635 and a660 */
598static const u32 a660_protect[] = {
599 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
600 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
601 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
602 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
603 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
604 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
605 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
606 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
607 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
608 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
609 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
610 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
611 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
612 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
613 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
614 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
615 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
616 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
617 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
618 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
619 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
620 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
621 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
622 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
623 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
624 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
625 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
626 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
627 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
628 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
629 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
630 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
631 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
632 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
633 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
634 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
635 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
636 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
637 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
638 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
639 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
640};
641
642static void a6xx_set_cp_protect(struct msm_gpu *gpu)
643{
644 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
645 const u32 *regs = a6xx_protect;
646 unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
647
648 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
649 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
650
651 if (adreno_is_a650(adreno_gpu)) {
652 regs = a650_protect;
653 count = ARRAY_SIZE(a650_protect);
654 count_max = 48;
655 } else if (adreno_is_a660(adreno_gpu)) {
656 regs = a660_protect;
657 count = ARRAY_SIZE(a660_protect);
658 count_max = 48;
659 }
660
661 /*
662 * Enable access protection to privileged registers, fault on an access
663 * protect violation and select the last span to protect from the start
664 * address all the way to the end of the register address space
665 */
666 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
667
668 for (i = 0; i < count - 1; i++)
669 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
670 /* last CP_PROTECT to have "infinite" length on the last entry */
671 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
672}
673
674static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
675{
676 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
677 u32 lower_bit = 2;
678 u32 amsbc = 0;
679 u32 rgb565_predicator = 0;
680 u32 uavflagprd_inv = 0;
681
682 /* a618 is using the hw default values */
683 if (adreno_is_a618(adreno_gpu))
684 return;
685
686 if (adreno_is_a640(adreno_gpu))
687 amsbc = 1;
688
689 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
690 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
691 lower_bit = 3;
692 amsbc = 1;
693 rgb565_predicator = 1;
694 uavflagprd_inv = 2;
695 }
696
697 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
698 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
699 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
700 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
701 uavflagprd_inv << 4 | lower_bit << 1);
702 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
703}
704
705static int a6xx_cp_init(struct msm_gpu *gpu)
706{
707 struct msm_ringbuffer *ring = gpu->rb[0];
708
709 OUT_PKT7(ring, CP_ME_INIT, 8);
710
711 OUT_RING(ring, 0x0000002f);
712
713 /* Enable multiple hardware contexts */
714 OUT_RING(ring, 0x00000003);
715
716 /* Enable error detection */
717 OUT_RING(ring, 0x20000000);
718
719 /* Don't enable header dump */
720 OUT_RING(ring, 0x00000000);
721 OUT_RING(ring, 0x00000000);
722
723 /* No workarounds enabled */
724 OUT_RING(ring, 0x00000000);
725
726 /* Pad rest of the cmds with 0's */
727 OUT_RING(ring, 0x00000000);
728 OUT_RING(ring, 0x00000000);
729
730 a6xx_flush(gpu, ring);
731 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
732}
733
734/*
735 * Check that the microcode version is new enough to include several key
736 * security fixes. Return true if the ucode is safe.
737 */
738static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
739 struct drm_gem_object *obj)
740{
741 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
742 struct msm_gpu *gpu = &adreno_gpu->base;
743 u32 *buf = msm_gem_get_vaddr(obj);
744 bool ret = false;
745
746 if (IS_ERR(buf))
747 return false;
748
749 /*
750 * Targets up to a640 (a618, a630 and a640) need to check for a
751 * microcode version that is patched to support the whereami opcode or
752 * one that is new enough to include it by default.
753 *
754 * a650 tier targets don't need whereami but still need to be
755 * equal to or newer than 0.95 for other security fixes
756 *
757 * a660 targets have all the critical security fixes from the start
758 */
759 if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
760 adreno_is_a640(adreno_gpu)) {
761 /*
762 * If the lowest nibble is 0xa that is an indication that this
763 * microcode has been patched. The actual version is in dword
764 * [3] but we only care about the patchlevel which is the lowest
765 * nibble of dword [3]
766 *
767 * Otherwise check that the firmware is greater than or equal
768 * to 1.90 which was the first version that had this fix built
769 * in
770 */
771 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
772 (buf[0] & 0xfff) >= 0x190) {
773 a6xx_gpu->has_whereami = true;
774 ret = true;
775 goto out;
776 }
777
778 DRM_DEV_ERROR(&gpu->pdev->dev,
779 "a630 SQE ucode is too old. Have version %x need at least %x\n",
780 buf[0] & 0xfff, 0x190);
781 } else if (adreno_is_a650(adreno_gpu)) {
782 if ((buf[0] & 0xfff) >= 0x095) {
783 ret = true;
784 goto out;
785 }
786
787 DRM_DEV_ERROR(&gpu->pdev->dev,
788 "a650 SQE ucode is too old. Have version %x need at least %x\n",
789 buf[0] & 0xfff, 0x095);
790 } else if (adreno_is_a660(adreno_gpu)) {
791 ret = true;
792 } else {
793 DRM_DEV_ERROR(&gpu->pdev->dev,
794 "unknown GPU, add it to a6xx_ucode_check_version()!!\n");
795 }
796out:
797 msm_gem_put_vaddr(obj);
798 return ret;
799}
800
801static int a6xx_ucode_init(struct msm_gpu *gpu)
802{
803 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
804 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
805
806 if (!a6xx_gpu->sqe_bo) {
807 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
808 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
809
810 if (IS_ERR(a6xx_gpu->sqe_bo)) {
811 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
812
813 a6xx_gpu->sqe_bo = NULL;
814 DRM_DEV_ERROR(&gpu->pdev->dev,
815 "Could not allocate SQE ucode: %d\n", ret);
816
817 return ret;
818 }
819
820 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
821 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
822 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
823 drm_gem_object_put(a6xx_gpu->sqe_bo);
824
825 a6xx_gpu->sqe_bo = NULL;
826 return -EPERM;
827 }
828 }
829
830 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
831 REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
832
833 return 0;
834}
835
836static int a6xx_zap_shader_init(struct msm_gpu *gpu)
837{
838 static bool loaded;
839 int ret;
840
841 if (loaded)
842 return 0;
843
844 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
845
846 loaded = !ret;
847 return ret;
848}
849
850#define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
851 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
852 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
853 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
854 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
855 A6XX_RBBM_INT_0_MASK_CP_RB | \
856 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
857 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
858 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
859 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
860 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
861
862static int hw_init(struct msm_gpu *gpu)
863{
864 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
865 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
866 int ret;
867
868 /* Make sure the GMU keeps the GPU on while we set it up */
869 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
870
871 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
872
873 /*
874 * Disable the trusted memory range - we don't actually supported secure
875 * memory rendering at this point in time and we don't want to block off
876 * part of the virtual memory space.
877 */
878 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
879 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
880 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
881
882 /* Turn on 64 bit addressing for all blocks */
883 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
884 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
885 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
886 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
887 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
888 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
889 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
890 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
891 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
892 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
893 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
894 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
895
896 /* enable hardware clockgating */
897 a6xx_set_hwcg(gpu, true);
898
899 /* VBIF/GBIF start*/
900 if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
901 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
902 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
903 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
904 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
905 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
906 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
907 } else {
908 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
909 }
910
911 if (adreno_is_a630(adreno_gpu))
912 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
913
914 /* Make all blocks contribute to the GPU BUSY perf counter */
915 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
916
917 /* Disable L2 bypass in the UCHE */
918 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
919 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
920 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
921 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
922 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
923 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
924
925 if (!adreno_is_a650_family(adreno_gpu)) {
926 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
927 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
928 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
929
930 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
931 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
932 0x00100000 + adreno_gpu->gmem - 1);
933 }
934
935 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
936 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
937
938 if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
939 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
940 else
941 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
942 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
943
944 if (adreno_is_a660(adreno_gpu))
945 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
946
947 /* Setting the mem pool size */
948 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
949
950 /* Setting the primFifo thresholds default values,
951 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
952 */
953 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
954 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
955 else if (adreno_is_a640(adreno_gpu))
956 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
957 else
958 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
959
960 /* Set the AHB default slave response to "ERROR" */
961 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
962
963 /* Turn on performance counters */
964 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
965
966 /* Select CP0 to always count cycles */
967 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
968
969 a6xx_set_ubwc_config(gpu);
970
971 /* Enable fault detection */
972 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
973 (1 << 30) | 0x1fffff);
974
975 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
976
977 /* Set weights for bicubic filtering */
978 if (adreno_is_a650_family(adreno_gpu)) {
979 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
980 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
981 0x3fe05ff4);
982 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
983 0x3fa0ebee);
984 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
985 0x3f5193ed);
986 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
987 0x3f0243f0);
988 }
989
990 /* Protect registers from the CP */
991 a6xx_set_cp_protect(gpu);
992
993 if (adreno_is_a660(adreno_gpu)) {
994 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
995 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
996 /* Set dualQ + disable afull for A660 GPU but not for A635 */
997 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
998 }
999
1000 /* Enable expanded apriv for targets that support it */
1001 if (gpu->hw_apriv) {
1002 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1003 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
1004 }
1005
1006 /* Enable interrupts */
1007 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
1008
1009 ret = adreno_hw_init(gpu);
1010 if (ret)
1011 goto out;
1012
1013 ret = a6xx_ucode_init(gpu);
1014 if (ret)
1015 goto out;
1016
1017 /* Set the ringbuffer address */
1018 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
1019 gpu->rb[0]->iova);
1020
1021 /* Targets that support extended APRIV can use the RPTR shadow from
1022 * hardware but all the other ones need to disable the feature. Targets
1023 * that support the WHERE_AM_I opcode can use that instead
1024 */
1025 if (adreno_gpu->base.hw_apriv)
1026 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
1027 else
1028 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
1029 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
1030
1031 /*
1032 * Expanded APRIV and targets that support WHERE_AM_I both need a
1033 * privileged buffer to store the RPTR shadow
1034 */
1035
1036 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
1037 if (!a6xx_gpu->shadow_bo) {
1038 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
1039 sizeof(u32) * gpu->nr_rings,
1040 MSM_BO_WC | MSM_BO_MAP_PRIV,
1041 gpu->aspace, &a6xx_gpu->shadow_bo,
1042 &a6xx_gpu->shadow_iova);
1043
1044 if (IS_ERR(a6xx_gpu->shadow))
1045 return PTR_ERR(a6xx_gpu->shadow);
1046 }
1047
1048 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
1049 REG_A6XX_CP_RB_RPTR_ADDR_HI,
1050 shadowptr(a6xx_gpu, gpu->rb[0]));
1051 }
1052
1053 /* Always come up on rb 0 */
1054 a6xx_gpu->cur_ring = gpu->rb[0];
1055
1056 a6xx_gpu->cur_ctx_seqno = 0;
1057
1058 /* Enable the SQE_to start the CP engine */
1059 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
1060
1061 ret = a6xx_cp_init(gpu);
1062 if (ret)
1063 goto out;
1064
1065 /*
1066 * Try to load a zap shader into the secure world. If successful
1067 * we can use the CP to switch out of secure mode. If not then we
1068 * have no resource but to try to switch ourselves out manually. If we
1069 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
1070 * be blocked and a permissions violation will soon follow.
1071 */
1072 ret = a6xx_zap_shader_init(gpu);
1073 if (!ret) {
1074 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
1075 OUT_RING(gpu->rb[0], 0x00000000);
1076
1077 a6xx_flush(gpu, gpu->rb[0]);
1078 if (!a6xx_idle(gpu, gpu->rb[0]))
1079 return -EINVAL;
1080 } else if (ret == -ENODEV) {
1081 /*
1082 * This device does not use zap shader (but print a warning
1083 * just in case someone got their dt wrong.. hopefully they
1084 * have a debug UART to realize the error of their ways...
1085 * if you mess this up you are about to crash horribly)
1086 */
1087 dev_warn_once(gpu->dev->dev,
1088 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
1089 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1090 ret = 0;
1091 } else {
1092 return ret;
1093 }
1094
1095out:
1096 /*
1097 * Tell the GMU that we are done touching the GPU and it can start power
1098 * management
1099 */
1100 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1101
1102 if (a6xx_gpu->gmu.legacy) {
1103 /* Take the GMU out of its special boot mode */
1104 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
1105 }
1106
1107 return ret;
1108}
1109
1110static int a6xx_hw_init(struct msm_gpu *gpu)
1111{
1112 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1113 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1114 int ret;
1115
1116 mutex_lock(&a6xx_gpu->gmu.lock);
1117 ret = hw_init(gpu);
1118 mutex_unlock(&a6xx_gpu->gmu.lock);
1119
1120 return ret;
1121}
1122
1123static void a6xx_dump(struct msm_gpu *gpu)
1124{
1125 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
1126 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
1127 adreno_dump(gpu);
1128}
1129
1130#define VBIF_RESET_ACK_TIMEOUT 100
1131#define VBIF_RESET_ACK_MASK 0x00f0
1132
1133static void a6xx_recover(struct msm_gpu *gpu)
1134{
1135 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1136 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1137 int i;
1138
1139 adreno_dump_info(gpu);
1140
1141 for (i = 0; i < 8; i++)
1142 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1143 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1144
1145 if (hang_debug)
1146 a6xx_dump(gpu);
1147
1148 /*
1149 * Turn off keep alive that might have been enabled by the hang
1150 * interrupt
1151 */
1152 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1153
1154 gpu->funcs->pm_suspend(gpu);
1155 gpu->funcs->pm_resume(gpu);
1156
1157 msm_gpu_hw_init(gpu);
1158}
1159
1160static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1161{
1162 static const char *uche_clients[7] = {
1163 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1164 };
1165 u32 val;
1166
1167 if (mid < 1 || mid > 3)
1168 return "UNKNOWN";
1169
1170 /*
1171 * The source of the data depends on the mid ID read from FSYNR1.
1172 * and the client ID read from the UCHE block
1173 */
1174 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1175
1176 /* mid = 3 is most precise and refers to only one block per client */
1177 if (mid == 3)
1178 return uche_clients[val & 7];
1179
1180 /* For mid=2 the source is TP or VFD except when the client id is 0 */
1181 if (mid == 2)
1182 return ((val & 7) == 0) ? "TP" : "TP|VFD";
1183
1184 /* For mid=1 just return "UCHE" as a catchall for everything else */
1185 return "UCHE";
1186}
1187
1188static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1189{
1190 if (id == 0)
1191 return "CP";
1192 else if (id == 4)
1193 return "CCU";
1194 else if (id == 6)
1195 return "CDP Prefetch";
1196
1197 return a6xx_uche_fault_block(gpu, id);
1198}
1199
1200#define ARM_SMMU_FSR_TF BIT(1)
1201#define ARM_SMMU_FSR_PF BIT(3)
1202#define ARM_SMMU_FSR_EF BIT(4)
1203
1204static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1205{
1206 struct msm_gpu *gpu = arg;
1207 struct adreno_smmu_fault_info *info = data;
1208 const char *type = "UNKNOWN";
1209 const char *block;
1210 bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
1211
1212 /*
1213 * If we aren't going to be resuming later from fault_worker, then do
1214 * it now.
1215 */
1216 if (!do_devcoredump) {
1217 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
1218 }
1219
1220 /*
1221 * Print a default message if we couldn't get the data from the
1222 * adreno-smmu-priv
1223 */
1224 if (!info) {
1225 pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
1226 iova, flags,
1227 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1228 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1229 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1230 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1231
1232 return 0;
1233 }
1234
1235 if (info->fsr & ARM_SMMU_FSR_TF)
1236 type = "TRANSLATION";
1237 else if (info->fsr & ARM_SMMU_FSR_PF)
1238 type = "PERMISSION";
1239 else if (info->fsr & ARM_SMMU_FSR_EF)
1240 type = "EXTERNAL";
1241
1242 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1243
1244 pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
1245 info->ttbr0, iova,
1246 flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
1247 type, block,
1248 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1249 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1250 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1251 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1252
1253 if (do_devcoredump) {
1254 /* Turn off the hangcheck timer to keep it from bothering us */
1255 del_timer(&gpu->hangcheck_timer);
1256
1257 gpu->fault_info.ttbr0 = info->ttbr0;
1258 gpu->fault_info.iova = iova;
1259 gpu->fault_info.flags = flags;
1260 gpu->fault_info.type = type;
1261 gpu->fault_info.block = block;
1262
1263 kthread_queue_work(gpu->worker, &gpu->fault_work);
1264 }
1265
1266 return 0;
1267}
1268
1269static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
1270{
1271 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
1272
1273 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1274 u32 val;
1275
1276 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1277 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1278 dev_err_ratelimited(&gpu->pdev->dev,
1279 "CP | opcode error | possible opcode=0x%8.8X\n",
1280 val);
1281 }
1282
1283 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1284 dev_err_ratelimited(&gpu->pdev->dev,
1285 "CP ucode error interrupt\n");
1286
1287 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1288 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1289 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1290
1291 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1292 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1293
1294 dev_err_ratelimited(&gpu->pdev->dev,
1295 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1296 val & (1 << 20) ? "READ" : "WRITE",
1297 (val & 0x3ffff), val);
1298 }
1299
1300 if (status & A6XX_CP_INT_CP_AHB_ERROR)
1301 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1302
1303 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1304 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1305
1306 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1307 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1308
1309}
1310
1311static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1312{
1313 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1314 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1315 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1316
1317 /*
1318 * If stalled on SMMU fault, we could trip the GPU's hang detection,
1319 * but the fault handler will trigger the devcore dump, and we want
1320 * to otherwise resume normally rather than killing the submit, so
1321 * just bail.
1322 */
1323 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1324 return;
1325
1326 /*
1327 * Force the GPU to stay on until after we finish
1328 * collecting information
1329 */
1330 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1331
1332 DRM_DEV_ERROR(&gpu->pdev->dev,
1333 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1334 ring ? ring->id : -1, ring ? ring->seqno : 0,
1335 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1336 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1337 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1338 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1339 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1340 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1341 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1342
1343 /* Turn off the hangcheck timer to keep it from bothering us */
1344 del_timer(&gpu->hangcheck_timer);
1345
1346 kthread_queue_work(gpu->worker, &gpu->recover_work);
1347}
1348
1349static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1350{
1351 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1352
1353 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1354
1355 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1356 a6xx_fault_detect_irq(gpu);
1357
1358 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1359 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1360
1361 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1362 a6xx_cp_hw_err_irq(gpu);
1363
1364 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1365 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1366
1367 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1368 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1369
1370 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1371 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1372
1373 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1374 msm_gpu_retire(gpu);
1375
1376 return IRQ_HANDLED;
1377}
1378
1379static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
1380{
1381 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
1382}
1383
1384static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
1385{
1386 return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
1387}
1388
1389static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1390{
1391 llcc_slice_deactivate(a6xx_gpu->llc_slice);
1392 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1393}
1394
1395static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1396{
1397 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1398 struct msm_gpu *gpu = &adreno_gpu->base;
1399 u32 gpu_scid, cntl1_regval = 0;
1400
1401 if (IS_ERR(a6xx_gpu->llc_mmio))
1402 return;
1403
1404 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1405 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1406
1407 gpu_scid &= 0x1f;
1408 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1409 (gpu_scid << 15) | (gpu_scid << 20);
1410 }
1411
1412 /*
1413 * For targets with a MMU500, activate the slice but don't program the
1414 * register. The XBL will take care of that.
1415 */
1416 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1417 if (!a6xx_gpu->have_mmu500) {
1418 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1419
1420 gpuhtw_scid &= 0x1f;
1421 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1422 }
1423 }
1424
1425 if (!cntl1_regval)
1426 return;
1427
1428 /*
1429 * Program the slice IDs for the various GPU blocks and GPU MMU
1430 * pagetables
1431 */
1432 if (!a6xx_gpu->have_mmu500) {
1433 a6xx_llc_write(a6xx_gpu,
1434 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1435
1436 /*
1437 * Program cacheability overrides to not allocate cache
1438 * lines on a write miss
1439 */
1440 a6xx_llc_rmw(a6xx_gpu,
1441 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1442 return;
1443 }
1444
1445 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
1446
1447 /* On A660, the SCID programming for UCHE traffic is done in
1448 * A6XX_GBIF_SCACHE_CNTL0[14:10]
1449 */
1450 if (adreno_is_a660(adreno_gpu))
1451 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
1452 (1 << 8), (gpu_scid << 10) | (1 << 8));
1453}
1454
1455static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1456{
1457 llcc_slice_putd(a6xx_gpu->llc_slice);
1458 llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1459}
1460
1461static void a6xx_llc_slices_init(struct platform_device *pdev,
1462 struct a6xx_gpu *a6xx_gpu)
1463{
1464 struct device_node *phandle;
1465
1466 /*
1467 * There is a different programming path for targets with an mmu500
1468 * attached, so detect if that is the case
1469 */
1470 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1471 a6xx_gpu->have_mmu500 = (phandle &&
1472 of_device_is_compatible(phandle, "arm,mmu-500"));
1473 of_node_put(phandle);
1474
1475 if (a6xx_gpu->have_mmu500)
1476 a6xx_gpu->llc_mmio = NULL;
1477 else
1478 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
1479
1480 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1481 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1482
1483 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1484 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1485}
1486
1487static int a6xx_pm_resume(struct msm_gpu *gpu)
1488{
1489 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1490 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1491 int ret;
1492
1493 gpu->needs_hw_init = true;
1494
1495 trace_msm_gpu_resume(0);
1496
1497 mutex_lock(&a6xx_gpu->gmu.lock);
1498 ret = a6xx_gmu_resume(a6xx_gpu);
1499 mutex_unlock(&a6xx_gpu->gmu.lock);
1500 if (ret)
1501 return ret;
1502
1503 msm_gpu_resume_devfreq(gpu);
1504
1505 a6xx_llc_activate(a6xx_gpu);
1506
1507 return 0;
1508}
1509
1510static int a6xx_pm_suspend(struct msm_gpu *gpu)
1511{
1512 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1513 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1514 int i, ret;
1515
1516 trace_msm_gpu_suspend(0);
1517
1518 a6xx_llc_deactivate(a6xx_gpu);
1519
1520 devfreq_suspend_device(gpu->devfreq.devfreq);
1521
1522 mutex_lock(&a6xx_gpu->gmu.lock);
1523 ret = a6xx_gmu_stop(a6xx_gpu);
1524 mutex_unlock(&a6xx_gpu->gmu.lock);
1525 if (ret)
1526 return ret;
1527
1528 if (a6xx_gpu->shadow_bo)
1529 for (i = 0; i < gpu->nr_rings; i++)
1530 a6xx_gpu->shadow[i] = 0;
1531
1532 return 0;
1533}
1534
1535static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1536{
1537 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1538 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1539
1540 mutex_lock(&a6xx_gpu->gmu.lock);
1541
1542 /* Force the GPU power on so we can read this register */
1543 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1544
1545 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1546 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1547
1548 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1549
1550 mutex_unlock(&a6xx_gpu->gmu.lock);
1551
1552 return 0;
1553}
1554
1555static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1556{
1557 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1558 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1559
1560 return a6xx_gpu->cur_ring;
1561}
1562
1563static void a6xx_destroy(struct msm_gpu *gpu)
1564{
1565 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1566 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1567
1568 if (a6xx_gpu->sqe_bo) {
1569 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1570 drm_gem_object_put(a6xx_gpu->sqe_bo);
1571 }
1572
1573 if (a6xx_gpu->shadow_bo) {
1574 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1575 drm_gem_object_put(a6xx_gpu->shadow_bo);
1576 }
1577
1578 a6xx_llc_slices_destroy(a6xx_gpu);
1579
1580 a6xx_gmu_remove(a6xx_gpu);
1581
1582 adreno_gpu_cleanup(adreno_gpu);
1583
1584 kfree(a6xx_gpu);
1585}
1586
1587static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
1588{
1589 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1590 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1591 u64 busy_cycles, busy_time;
1592
1593
1594 /* Only read the gpu busy if the hardware is already active */
1595 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1596 return 0;
1597
1598 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1599 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1600 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1601
1602 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1603 do_div(busy_time, 192);
1604
1605 gpu->devfreq.busy_cycles = busy_cycles;
1606
1607 pm_runtime_put(a6xx_gpu->gmu.dev);
1608
1609 if (WARN_ON(busy_time > ~0LU))
1610 return ~0LU;
1611
1612 return (unsigned long)busy_time;
1613}
1614
1615void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
1616{
1617 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1618 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1619
1620 mutex_lock(&a6xx_gpu->gmu.lock);
1621 a6xx_gmu_set_freq(gpu, opp);
1622 mutex_unlock(&a6xx_gpu->gmu.lock);
1623}
1624
1625static struct msm_gem_address_space *
1626a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
1627{
1628 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1629 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1630 struct iommu_domain *iommu;
1631 struct msm_mmu *mmu;
1632 struct msm_gem_address_space *aspace;
1633 u64 start, size;
1634
1635 iommu = iommu_domain_alloc(&platform_bus_type);
1636 if (!iommu)
1637 return NULL;
1638
1639 /*
1640 * This allows GPU to set the bus attributes required to use system
1641 * cache on behalf of the iommu page table walker.
1642 */
1643 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1644 adreno_set_llc_attributes(iommu);
1645
1646 mmu = msm_iommu_new(&pdev->dev, iommu);
1647 if (IS_ERR(mmu)) {
1648 iommu_domain_free(iommu);
1649 return ERR_CAST(mmu);
1650 }
1651
1652 /*
1653 * Use the aperture start or SZ_16M, whichever is greater. This will
1654 * ensure that we align with the allocated pagetable range while still
1655 * allowing room in the lower 32 bits for GMEM and whatnot
1656 */
1657 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
1658 size = iommu->geometry.aperture_end - start + 1;
1659
1660 aspace = msm_gem_address_space_create(mmu, "gpu",
1661 start & GENMASK_ULL(48, 0), size);
1662
1663 if (IS_ERR(aspace) && !IS_ERR(mmu))
1664 mmu->funcs->destroy(mmu);
1665
1666 return aspace;
1667}
1668
1669static struct msm_gem_address_space *
1670a6xx_create_private_address_space(struct msm_gpu *gpu)
1671{
1672 struct msm_mmu *mmu;
1673
1674 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1675
1676 if (IS_ERR(mmu))
1677 return ERR_CAST(mmu);
1678
1679 return msm_gem_address_space_create(mmu,
1680 "gpu", 0x100000000ULL, 0x1ffffffffULL);
1681}
1682
1683static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1684{
1685 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1686 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1687
1688 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1689 return a6xx_gpu->shadow[ring->id];
1690
1691 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1692}
1693
1694static u32 a618_get_speed_bin(u32 fuse)
1695{
1696 if (fuse == 0)
1697 return 0;
1698 else if (fuse == 169)
1699 return 1;
1700 else if (fuse == 174)
1701 return 2;
1702
1703 return UINT_MAX;
1704}
1705
1706static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse)
1707{
1708 u32 val = UINT_MAX;
1709
1710 if (revn == 618)
1711 val = a618_get_speed_bin(fuse);
1712
1713 if (val == UINT_MAX) {
1714 DRM_DEV_ERROR(dev,
1715 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
1716 fuse);
1717 return UINT_MAX;
1718 }
1719
1720 return (1 << val);
1721}
1722
1723static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
1724 u32 revn)
1725{
1726 u32 supp_hw = UINT_MAX;
1727 u16 speedbin;
1728 int ret;
1729
1730 ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);
1731 /*
1732 * -ENOENT means that the platform doesn't support speedbin which is
1733 * fine
1734 */
1735 if (ret == -ENOENT) {
1736 return 0;
1737 } else if (ret) {
1738 DRM_DEV_ERROR(dev,
1739 "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
1740 ret);
1741 goto done;
1742 }
1743 speedbin = le16_to_cpu(speedbin);
1744
1745 supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
1746
1747done:
1748 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1749 if (ret)
1750 return ret;
1751
1752 return 0;
1753}
1754
1755static const struct adreno_gpu_funcs funcs = {
1756 .base = {
1757 .get_param = adreno_get_param,
1758 .hw_init = a6xx_hw_init,
1759 .pm_suspend = a6xx_pm_suspend,
1760 .pm_resume = a6xx_pm_resume,
1761 .recover = a6xx_recover,
1762 .submit = a6xx_submit,
1763 .active_ring = a6xx_active_ring,
1764 .irq = a6xx_irq,
1765 .destroy = a6xx_destroy,
1766#if defined(CONFIG_DRM_MSM_GPU_STATE)
1767 .show = a6xx_show,
1768#endif
1769 .gpu_busy = a6xx_gpu_busy,
1770 .gpu_get_freq = a6xx_gmu_get_freq,
1771 .gpu_set_freq = a6xx_gpu_set_freq,
1772#if defined(CONFIG_DRM_MSM_GPU_STATE)
1773 .gpu_state_get = a6xx_gpu_state_get,
1774 .gpu_state_put = a6xx_gpu_state_put,
1775#endif
1776 .create_address_space = a6xx_create_address_space,
1777 .create_private_address_space = a6xx_create_private_address_space,
1778 .get_rptr = a6xx_get_rptr,
1779 },
1780 .get_timestamp = a6xx_get_timestamp,
1781};
1782
1783struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1784{
1785 struct msm_drm_private *priv = dev->dev_private;
1786 struct platform_device *pdev = priv->gpu_pdev;
1787 struct adreno_platform_config *config = pdev->dev.platform_data;
1788 const struct adreno_info *info;
1789 struct device_node *node;
1790 struct a6xx_gpu *a6xx_gpu;
1791 struct adreno_gpu *adreno_gpu;
1792 struct msm_gpu *gpu;
1793 int ret;
1794
1795 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1796 if (!a6xx_gpu)
1797 return ERR_PTR(-ENOMEM);
1798
1799 adreno_gpu = &a6xx_gpu->base;
1800 gpu = &adreno_gpu->base;
1801
1802 adreno_gpu->registers = NULL;
1803
1804 /*
1805 * We need to know the platform type before calling into adreno_gpu_init
1806 * so that the hw_apriv flag can be correctly set. Snoop into the info
1807 * and grab the revision number
1808 */
1809 info = adreno_info(config->rev);
1810
1811 if (info && (info->revn == 650 || info->revn == 660))
1812 adreno_gpu->base.hw_apriv = true;
1813
1814 a6xx_llc_slices_init(pdev, a6xx_gpu);
1815
1816 ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn);
1817 if (ret) {
1818 a6xx_destroy(&(a6xx_gpu->base.base));
1819 return ERR_PTR(ret);
1820 }
1821
1822 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1823 if (ret) {
1824 a6xx_destroy(&(a6xx_gpu->base.base));
1825 return ERR_PTR(ret);
1826 }
1827
1828 /* Check if there is a GMU phandle and set it up */
1829 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1830
1831 /* FIXME: How do we gracefully handle this? */
1832 BUG_ON(!node);
1833
1834 ret = a6xx_gmu_init(a6xx_gpu, node);
1835 if (ret) {
1836 a6xx_destroy(&(a6xx_gpu->base.base));
1837 return ERR_PTR(ret);
1838 }
1839
1840 if (gpu->aspace)
1841 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1842 a6xx_fault_handler);
1843
1844 return gpu;
1845}