1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
  3
  4#ifndef _A6XX_GMU_H_
  5#define _A6XX_GMU_H_
  6
  7#include <linux/iopoll.h>
  8#include <linux/interrupt.h>
  9#include "msm_drv.h"
 10#include "a6xx_hfi.h"
 11
 12struct a6xx_gmu_bo {
 13	struct drm_gem_object *obj;
 14	void *virt;
 15	size_t size;
 16	u64 iova;
 17};
 18
 19/*
 20 * These define the different GMU wake up options - these define how both the
 21 * CPU and the GMU bring up the hardware
 22 */
 23
 24/* THe GMU has already been booted and the rentention registers are active */
 25#define GMU_WARM_BOOT 0
 26
 27/* the GMU is coming up for the first time or back from a power collapse */
 28#define GMU_COLD_BOOT 1
 29
 30/*
 31 * These define the level of control that the GMU has - the higher the number
 32 * the more things that the GMU hardware controls on its own.
 33 */
 34
 35/* The GMU does not do any idle state management */
 36#define GMU_IDLE_STATE_ACTIVE 0
 37
 38/* The GMU manages SPTP power collapse */
 39#define GMU_IDLE_STATE_SPTP 2
 40
 41/* The GMU does automatic IFPC (intra-frame power collapse) */
 42#define GMU_IDLE_STATE_IFPC 3
 43
 44struct a6xx_gmu {
 45	struct device *dev;
 46
 47	/* For serializing communication with the GMU: */
 48	struct mutex lock;
 49
 50	struct msm_gem_address_space *aspace;
 51
 52	void * __iomem mmio;
 53	void * __iomem rscc;
 54
 55	int hfi_irq;
 56	int gmu_irq;
 57
 58	struct device *gxpd;
 59
 60	int idle_level;
 61
 62	struct a6xx_gmu_bo hfi;
 63	struct a6xx_gmu_bo debug;
 64	struct a6xx_gmu_bo icache;
 65	struct a6xx_gmu_bo dcache;
 66	struct a6xx_gmu_bo dummy;
 67	struct a6xx_gmu_bo log;
 68
 69	int nr_clocks;
 70	struct clk_bulk_data *clocks;
 71	struct clk *core_clk;
 72
 73	/* current performance index set externally */
 74	int current_perf_index;
 75
 76	int nr_gpu_freqs;
 77	unsigned long gpu_freqs[16];
 78	u32 gx_arc_votes[16];
 79
 80	int nr_gmu_freqs;
 81	unsigned long gmu_freqs[4];
 82	u32 cx_arc_votes[4];
 83
 84	unsigned long freq;
 85
 86	struct a6xx_hfi_queue queues[2];
 87
 88	bool initialized;
 89	bool hung;
 90	bool legacy; /* a618 or a630 */
 91};
 92
 93static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
 94{
 95	return msm_readl(gmu->mmio + (offset << 2));
 96}
 97
 98static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
 99{
100	return msm_writel(value, gmu->mmio + (offset << 2));
101}
102
103static inline void
104gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
105{
106	memcpy_toio(gmu->mmio + (offset << 2), data, size);
107	wmb();
108}
109
110static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
111{
112	u32 val = gmu_read(gmu, reg);
113
114	val &= ~mask;
115
116	gmu_write(gmu, reg, val | or);
117}
118
119static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
120{
121	u64 val;
122
123	val = (u64) msm_readl(gmu->mmio + (lo << 2));
124	val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
125
126	return val;
127}
128
129#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
130	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
131		interval, timeout)
132
133static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
134{
135	return msm_readl(gmu->rscc + (offset << 2));
136}
137
138static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
139{
140	return msm_writel(value, gmu->rscc + (offset << 2));
141}
142
143#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
144	readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
145		interval, timeout)
146
147/*
148 * These are the available OOB (out of band requests) to the GMU where "out of
149 * band" means that the CPU talks to the GMU directly and not through HFI.
150 * Normally this works by writing a ITCM/DTCM register and then triggering a
151 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
152 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
153 *
154 * These are used to force the GMU/GPU to stay on during a critical sequence or
155 * for hardware workarounds.
156 */
157
158enum a6xx_gmu_oob_state {
159	/*
160	 * Let the GMU know that a boot or slumber operation has started. The value in
161	 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
162	 * doing
163	 */
164	GMU_OOB_BOOT_SLUMBER = 0,
165	/*
166	 * Let the GMU know to not turn off any GPU registers while the CPU is in a
167	 * critical section
168	 */
169	GMU_OOB_GPU_SET,
170	/*
171	 * Set a new power level for the GPU when the CPU is doing frequency scaling
172	 */
173	GMU_OOB_DCVS_SET,
174	/*
175	 * Used to keep the GPU on for CPU-side reads of performance counters.
176	 */
177	GMU_OOB_PERFCOUNTER_SET,
178};
179
180void a6xx_hfi_init(struct a6xx_gmu *gmu);
181int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
182void a6xx_hfi_stop(struct a6xx_gmu *gmu);
183int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
184int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
185
186bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
187bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
188
189#endif