1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#include <linux/cpufreq.h>
  7
  8#include "i915_drv.h"
  9#include "intel_gt.h"
 10#include "intel_llc.h"
 11#include "intel_sideband.h"
 12
 13struct ia_constants {
 14	unsigned int min_gpu_freq;
 15	unsigned int max_gpu_freq;
 16
 17	unsigned int min_ring_freq;
 18	unsigned int max_ia_freq;
 19};
 20
 21static struct intel_gt *llc_to_gt(struct intel_llc *llc)
 22{
 23	return container_of(llc, struct intel_gt, llc);
 24}
 25
 26static unsigned int cpu_max_MHz(void)
 27{
 28	struct cpufreq_policy *policy;
 29	unsigned int max_khz;
 30
 31	policy = cpufreq_cpu_get(0);
 32	if (policy) {
 33		max_khz = policy->cpuinfo.max_freq;
 34		cpufreq_cpu_put(policy);
 35	} else {
 36		/*
 37		 * Default to measured freq if none found, PCU will ensure we
 38		 * don't go over
 39		 */
 40		max_khz = tsc_khz;
 41	}
 42
 43	return max_khz / 1000;
 44}
 45
 46static bool get_ia_constants(struct intel_llc *llc,
 47			     struct ia_constants *consts)
 48{
 49	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
 50	struct intel_rps *rps = &llc_to_gt(llc)->rps;
 51
 52	if (!HAS_LLC(i915) || IS_DGFX(i915))
 53		return false;
 54
 55	if (rps->max_freq <= rps->min_freq)
 56		return false;
 57
 58	consts->max_ia_freq = cpu_max_MHz();
 59
 60	consts->min_ring_freq =
 61		intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
 62	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 63	consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
 64
 65	consts->min_gpu_freq = rps->min_freq;
 66	consts->max_gpu_freq = rps->max_freq;
 67	if (GRAPHICS_VER(i915) >= 9) {
 68		/* Convert GT frequency to 50 HZ units */
 69		consts->min_gpu_freq /= GEN9_FREQ_SCALER;
 70		consts->max_gpu_freq /= GEN9_FREQ_SCALER;
 71	}
 72
 73	return true;
 74}
 75
 76static void calc_ia_freq(struct intel_llc *llc,
 77			 unsigned int gpu_freq,
 78			 const struct ia_constants *consts,
 79			 unsigned int *out_ia_freq,
 80			 unsigned int *out_ring_freq)
 81{
 82	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
 83	const int diff = consts->max_gpu_freq - gpu_freq;
 84	unsigned int ia_freq = 0, ring_freq = 0;
 85
 86	if (GRAPHICS_VER(i915) >= 9) {
 87		/*
 88		 * ring_freq = 2 * GT. ring_freq is in 100MHz units
 89		 * No floor required for ring frequency on SKL.
 90		 */
 91		ring_freq = gpu_freq;
 92	} else if (GRAPHICS_VER(i915) >= 8) {
 93		/* max(2 * GT, DDR). NB: GT is 50MHz units */
 94		ring_freq = max(consts->min_ring_freq, gpu_freq);
 95	} else if (IS_HASWELL(i915)) {
 96		ring_freq = mult_frac(gpu_freq, 5, 4);
 97		ring_freq = max(consts->min_ring_freq, ring_freq);
 98		/* leave ia_freq as the default, chosen by cpufreq */
 99	} else {
100		const int min_freq = 15;
101		const int scale = 180;
102
103		/*
104		 * On older processors, there is no separate ring
105		 * clock domain, so in order to boost the bandwidth
106		 * of the ring, we need to upclock the CPU (ia_freq).
107		 *
108		 * For GPU frequencies less than 750MHz,
109		 * just use the lowest ring freq.
110		 */
111		if (gpu_freq < min_freq)
112			ia_freq = 800;
113		else
114			ia_freq = consts->max_ia_freq - diff * scale / 2;
115		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
116	}
117
118	*out_ia_freq = ia_freq;
119	*out_ring_freq = ring_freq;
120}
121
122static void gen6_update_ring_freq(struct intel_llc *llc)
123{
124	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
125	struct ia_constants consts;
126	unsigned int gpu_freq;
127
128	if (!get_ia_constants(llc, &consts))
129		return;
130
131	/*
132	 * For each potential GPU frequency, load a ring frequency we'd like
133	 * to use for memory access.  We do this by specifying the IA frequency
134	 * the PCU should use as a reference to determine the ring frequency.
135	 */
136	for (gpu_freq = consts.max_gpu_freq;
137	     gpu_freq >= consts.min_gpu_freq;
138	     gpu_freq--) {
139		unsigned int ia_freq, ring_freq;
140
141		calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
142		sandybridge_pcode_write(i915,
143					GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
144					ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
145					ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
146					gpu_freq);
147	}
148}
149
150void intel_llc_enable(struct intel_llc *llc)
151{
152	gen6_update_ring_freq(llc);
153}
154
155void intel_llc_disable(struct intel_llc *llc)
156{
157	/* Currently there is no HW configuration to be done to disable. */
158}
159
160#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
161#include "selftest_llc.c"
162#endif