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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu_amdkfd.h"
24#include "amd_shared.h"
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include <linux/module.h>
28
29const struct kfd2kgd_calls *kfd2kgd;
30const struct kgd2kfd_calls *kgd2kfd;
31bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
32
33int amdgpu_amdkfd_init(void)
34{
35 int ret;
36
37#if defined(CONFIG_HSA_AMD_MODULE)
38 int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
39
40 kgd2kfd_init_p = symbol_request(kgd2kfd_init);
41
42 if (kgd2kfd_init_p == NULL)
43 return -ENOENT;
44
45 ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
46 if (ret) {
47 symbol_put(kgd2kfd_init);
48 kgd2kfd = NULL;
49 }
50
51#elif defined(CONFIG_HSA_AMD)
52 ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
53 if (ret)
54 kgd2kfd = NULL;
55
56#else
57 ret = -ENOENT;
58#endif
59
60 return ret;
61}
62
63bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev)
64{
65 switch (rdev->asic_type) {
66#ifdef CONFIG_DRM_AMDGPU_CIK
67 case CHIP_KAVERI:
68 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
69 break;
70#endif
71 case CHIP_CARRIZO:
72 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
73 break;
74 default:
75 return false;
76 }
77
78 return true;
79}
80
81void amdgpu_amdkfd_fini(void)
82{
83 if (kgd2kfd) {
84 kgd2kfd->exit();
85 symbol_put(kgd2kfd_init);
86 }
87}
88
89void amdgpu_amdkfd_device_probe(struct amdgpu_device *rdev)
90{
91 if (kgd2kfd)
92 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev,
93 rdev->pdev, kfd2kgd);
94}
95
96void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev)
97{
98 if (rdev->kfd) {
99 struct kgd2kfd_shared_resources gpu_resources = {
100 .compute_vmid_bitmap = 0xFF00,
101
102 .first_compute_pipe = 1,
103 .compute_pipe_count = 4 - 1,
104 };
105
106 amdgpu_doorbell_get_kfd_info(rdev,
107 &gpu_resources.doorbell_physical_address,
108 &gpu_resources.doorbell_aperture_size,
109 &gpu_resources.doorbell_start_offset);
110
111 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
112 }
113}
114
115void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev)
116{
117 if (rdev->kfd) {
118 kgd2kfd->device_exit(rdev->kfd);
119 rdev->kfd = NULL;
120 }
121}
122
123void amdgpu_amdkfd_interrupt(struct amdgpu_device *rdev,
124 const void *ih_ring_entry)
125{
126 if (rdev->kfd)
127 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
128}
129
130void amdgpu_amdkfd_suspend(struct amdgpu_device *rdev)
131{
132 if (rdev->kfd)
133 kgd2kfd->suspend(rdev->kfd);
134}
135
136int amdgpu_amdkfd_resume(struct amdgpu_device *rdev)
137{
138 int r = 0;
139
140 if (rdev->kfd)
141 r = kgd2kfd->resume(rdev->kfd);
142
143 return r;
144}
145
146u32 pool_to_domain(enum kgd_memory_pool p)
147{
148 switch (p) {
149 case KGD_POOL_FRAMEBUFFER: return AMDGPU_GEM_DOMAIN_VRAM;
150 default: return AMDGPU_GEM_DOMAIN_GTT;
151 }
152}
153
154int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
155 void **mem_obj, uint64_t *gpu_addr,
156 void **cpu_ptr)
157{
158 struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;
159 struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
160 int r;
161
162 BUG_ON(kgd == NULL);
163 BUG_ON(gpu_addr == NULL);
164 BUG_ON(cpu_ptr == NULL);
165
166 *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
167 if ((*mem) == NULL)
168 return -ENOMEM;
169
170 r = amdgpu_bo_create(rdev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,
171 AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, &(*mem)->bo);
172 if (r) {
173 dev_err(rdev->dev,
174 "failed to allocate BO for amdkfd (%d)\n", r);
175 return r;
176 }
177
178 /* map the buffer */
179 r = amdgpu_bo_reserve((*mem)->bo, true);
180 if (r) {
181 dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
182 goto allocate_mem_reserve_bo_failed;
183 }
184
185 r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT,
186 &(*mem)->gpu_addr);
187 if (r) {
188 dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
189 goto allocate_mem_pin_bo_failed;
190 }
191 *gpu_addr = (*mem)->gpu_addr;
192
193 r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
194 if (r) {
195 dev_err(rdev->dev,
196 "(%d) failed to map bo to kernel for amdkfd\n", r);
197 goto allocate_mem_kmap_bo_failed;
198 }
199 *cpu_ptr = (*mem)->cpu_ptr;
200
201 amdgpu_bo_unreserve((*mem)->bo);
202
203 return 0;
204
205allocate_mem_kmap_bo_failed:
206 amdgpu_bo_unpin((*mem)->bo);
207allocate_mem_pin_bo_failed:
208 amdgpu_bo_unreserve((*mem)->bo);
209allocate_mem_reserve_bo_failed:
210 amdgpu_bo_unref(&(*mem)->bo);
211
212 return r;
213}
214
215void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
216{
217 struct kgd_mem *mem = (struct kgd_mem *) mem_obj;
218
219 BUG_ON(mem == NULL);
220
221 amdgpu_bo_reserve(mem->bo, true);
222 amdgpu_bo_kunmap(mem->bo);
223 amdgpu_bo_unpin(mem->bo);
224 amdgpu_bo_unreserve(mem->bo);
225 amdgpu_bo_unref(&(mem->bo));
226 kfree(mem);
227}
228
229uint64_t get_vmem_size(struct kgd_dev *kgd)
230{
231 struct amdgpu_device *rdev =
232 (struct amdgpu_device *)kgd;
233
234 BUG_ON(kgd == NULL);
235
236 return rdev->mc.real_vram_size;
237}
238
239uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
240{
241 struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;
242
243 if (rdev->asic_funcs->get_gpu_clock_counter)
244 return rdev->asic_funcs->get_gpu_clock_counter(rdev);
245 return 0;
246}
247
248uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
249{
250 struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;
251
252 /* The sclk is in quantas of 10kHz */
253 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
254}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu_amdkfd.h"
24#include "amd_shared.h"
25
26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "amdgpu_dma_buf.h"
29#include <linux/module.h>
30#include <linux/dma-buf.h>
31#include "amdgpu_xgmi.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34/* Total memory size in system memory and all GPU VRAM. Used to
35 * estimate worst case amount of memory to reserve for page tables
36 */
37uint64_t amdgpu_amdkfd_total_mem_size;
38
39static bool kfd_initialized;
40
41int amdgpu_amdkfd_init(void)
42{
43 struct sysinfo si;
44 int ret;
45
46 si_meminfo(&si);
47 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
48 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
49
50 ret = kgd2kfd_init();
51 amdgpu_amdkfd_gpuvm_init_mem_limits();
52 kfd_initialized = !ret;
53
54 return ret;
55}
56
57void amdgpu_amdkfd_fini(void)
58{
59 if (kfd_initialized) {
60 kgd2kfd_exit();
61 kfd_initialized = false;
62 }
63}
64
65void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
66{
67 bool vf = amdgpu_sriov_vf(adev);
68
69 if (!kfd_initialized)
70 return;
71
72 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
73 adev->pdev, adev->asic_type, vf);
74
75 if (adev->kfd.dev)
76 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
77}
78
79/**
80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
81 * setup amdkfd
82 *
83 * @adev: amdgpu_device pointer
84 * @aperture_base: output returning doorbell aperture base physical address
85 * @aperture_size: output returning doorbell aperture size in bytes
86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
87 *
88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
89 * takes doorbells required for its own rings and reports the setup to amdkfd.
90 * amdgpu reserved doorbells are at the start of the doorbell aperture.
91 */
92static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
93 phys_addr_t *aperture_base,
94 size_t *aperture_size,
95 size_t *start_offset)
96{
97 /*
98 * The first num_doorbells are used by amdgpu.
99 * amdkfd takes whatever's left in the aperture.
100 */
101 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
102 *aperture_base = adev->doorbell.base;
103 *aperture_size = adev->doorbell.size;
104 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
105 } else {
106 *aperture_base = 0;
107 *aperture_size = 0;
108 *start_offset = 0;
109 }
110}
111
112void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
113{
114 int i;
115 int last_valid_bit;
116
117 if (adev->kfd.dev) {
118 struct kgd2kfd_shared_resources gpu_resources = {
119 .compute_vmid_bitmap =
120 ((1 << AMDGPU_NUM_VMID) - 1) -
121 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
122 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
123 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
124 .gpuvm_size = min(adev->vm_manager.max_pfn
125 << AMDGPU_GPU_PAGE_SHIFT,
126 AMDGPU_GMC_HOLE_START),
127 .drm_render_minor = adev_to_drm(adev)->render->index,
128 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
129
130 };
131
132 /* this is going to have a few of the MSBs set that we need to
133 * clear
134 */
135 bitmap_complement(gpu_resources.cp_queue_bitmap,
136 adev->gfx.mec.queue_bitmap,
137 KGD_MAX_QUEUES);
138
139 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
140 * nbits is not compile time constant
141 */
142 last_valid_bit = 1 /* only first MEC can have compute queues */
143 * adev->gfx.mec.num_pipe_per_mec
144 * adev->gfx.mec.num_queue_per_pipe;
145 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
146 clear_bit(i, gpu_resources.cp_queue_bitmap);
147
148 amdgpu_doorbell_get_kfd_info(adev,
149 &gpu_resources.doorbell_physical_address,
150 &gpu_resources.doorbell_aperture_size,
151 &gpu_resources.doorbell_start_offset);
152
153 /* Since SOC15, BIF starts to statically use the
154 * lower 12 bits of doorbell addresses for routing
155 * based on settings in registers like
156 * SDMA0_DOORBELL_RANGE etc..
157 * In order to route a doorbell to CP engine, the lower
158 * 12 bits of its address has to be outside the range
159 * set for SDMA, VCN, and IH blocks.
160 */
161 if (adev->asic_type >= CHIP_VEGA10) {
162 gpu_resources.non_cp_doorbells_start =
163 adev->doorbell_index.first_non_cp;
164 gpu_resources.non_cp_doorbells_end =
165 adev->doorbell_index.last_non_cp;
166 }
167
168 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
169 adev_to_drm(adev), &gpu_resources);
170 }
171}
172
173void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
174{
175 if (adev->kfd.dev) {
176 kgd2kfd_device_exit(adev->kfd.dev);
177 adev->kfd.dev = NULL;
178 }
179}
180
181void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
182 const void *ih_ring_entry)
183{
184 if (adev->kfd.dev)
185 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
186}
187
188void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
189{
190 if (adev->kfd.dev)
191 kgd2kfd_suspend(adev->kfd.dev, run_pm);
192}
193
194int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
195{
196 int r = 0;
197
198 if (adev->kfd.dev)
199 r = kgd2kfd_resume_iommu(adev->kfd.dev);
200
201 return r;
202}
203
204int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
205{
206 int r = 0;
207
208 if (adev->kfd.dev)
209 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
210
211 return r;
212}
213
214int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
215{
216 int r = 0;
217
218 if (adev->kfd.dev)
219 r = kgd2kfd_pre_reset(adev->kfd.dev);
220
221 return r;
222}
223
224int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
225{
226 int r = 0;
227
228 if (adev->kfd.dev)
229 r = kgd2kfd_post_reset(adev->kfd.dev);
230
231 return r;
232}
233
234void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
235{
236 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
237
238 if (amdgpu_device_should_recover_gpu(adev))
239 amdgpu_device_gpu_recover(adev, NULL);
240}
241
242int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
243 void **mem_obj, uint64_t *gpu_addr,
244 void **cpu_ptr, bool cp_mqd_gfx9)
245{
246 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
247 struct amdgpu_bo *bo = NULL;
248 struct amdgpu_bo_param bp;
249 int r;
250 void *cpu_ptr_tmp = NULL;
251
252 memset(&bp, 0, sizeof(bp));
253 bp.size = size;
254 bp.byte_align = PAGE_SIZE;
255 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
256 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
257 bp.type = ttm_bo_type_kernel;
258 bp.resv = NULL;
259 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
260
261 if (cp_mqd_gfx9)
262 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
263
264 r = amdgpu_bo_create(adev, &bp, &bo);
265 if (r) {
266 dev_err(adev->dev,
267 "failed to allocate BO for amdkfd (%d)\n", r);
268 return r;
269 }
270
271 /* map the buffer */
272 r = amdgpu_bo_reserve(bo, true);
273 if (r) {
274 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
275 goto allocate_mem_reserve_bo_failed;
276 }
277
278 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
279 if (r) {
280 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
281 goto allocate_mem_pin_bo_failed;
282 }
283
284 r = amdgpu_ttm_alloc_gart(&bo->tbo);
285 if (r) {
286 dev_err(adev->dev, "%p bind failed\n", bo);
287 goto allocate_mem_kmap_bo_failed;
288 }
289
290 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
291 if (r) {
292 dev_err(adev->dev,
293 "(%d) failed to map bo to kernel for amdkfd\n", r);
294 goto allocate_mem_kmap_bo_failed;
295 }
296
297 *mem_obj = bo;
298 *gpu_addr = amdgpu_bo_gpu_offset(bo);
299 *cpu_ptr = cpu_ptr_tmp;
300
301 amdgpu_bo_unreserve(bo);
302
303 return 0;
304
305allocate_mem_kmap_bo_failed:
306 amdgpu_bo_unpin(bo);
307allocate_mem_pin_bo_failed:
308 amdgpu_bo_unreserve(bo);
309allocate_mem_reserve_bo_failed:
310 amdgpu_bo_unref(&bo);
311
312 return r;
313}
314
315void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
316{
317 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
318
319 amdgpu_bo_reserve(bo, true);
320 amdgpu_bo_kunmap(bo);
321 amdgpu_bo_unpin(bo);
322 amdgpu_bo_unreserve(bo);
323 amdgpu_bo_unref(&(bo));
324}
325
326int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
327 void **mem_obj)
328{
329 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
330 struct amdgpu_bo *bo = NULL;
331 struct amdgpu_bo_user *ubo;
332 struct amdgpu_bo_param bp;
333 int r;
334
335 memset(&bp, 0, sizeof(bp));
336 bp.size = size;
337 bp.byte_align = 1;
338 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
339 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
340 bp.type = ttm_bo_type_device;
341 bp.resv = NULL;
342 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
343
344 r = amdgpu_bo_create_user(adev, &bp, &ubo);
345 if (r) {
346 dev_err(adev->dev,
347 "failed to allocate gws BO for amdkfd (%d)\n", r);
348 return r;
349 }
350
351 bo = &ubo->bo;
352 *mem_obj = bo;
353 return 0;
354}
355
356void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
357{
358 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
359
360 amdgpu_bo_unref(&bo);
361}
362
363uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
364 enum kgd_engine_type type)
365{
366 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
367
368 switch (type) {
369 case KGD_ENGINE_PFP:
370 return adev->gfx.pfp_fw_version;
371
372 case KGD_ENGINE_ME:
373 return adev->gfx.me_fw_version;
374
375 case KGD_ENGINE_CE:
376 return adev->gfx.ce_fw_version;
377
378 case KGD_ENGINE_MEC1:
379 return adev->gfx.mec_fw_version;
380
381 case KGD_ENGINE_MEC2:
382 return adev->gfx.mec2_fw_version;
383
384 case KGD_ENGINE_RLC:
385 return adev->gfx.rlc_fw_version;
386
387 case KGD_ENGINE_SDMA1:
388 return adev->sdma.instance[0].fw_version;
389
390 case KGD_ENGINE_SDMA2:
391 return adev->sdma.instance[1].fw_version;
392
393 default:
394 return 0;
395 }
396
397 return 0;
398}
399
400void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
401 struct kfd_local_mem_info *mem_info)
402{
403 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
404
405 memset(mem_info, 0, sizeof(*mem_info));
406
407 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
408 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
409 adev->gmc.visible_vram_size;
410
411 mem_info->vram_width = adev->gmc.vram_width;
412
413 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
414 &adev->gmc.aper_base,
415 mem_info->local_mem_size_public,
416 mem_info->local_mem_size_private);
417
418 if (amdgpu_sriov_vf(adev))
419 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
420 else if (adev->pm.dpm_enabled) {
421 if (amdgpu_emu_mode == 1)
422 mem_info->mem_clk_max = 0;
423 else
424 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
425 } else
426 mem_info->mem_clk_max = 100;
427}
428
429uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
430{
431 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
432
433 if (adev->gfx.funcs->get_gpu_clock_counter)
434 return adev->gfx.funcs->get_gpu_clock_counter(adev);
435 return 0;
436}
437
438uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
439{
440 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
441
442 /* the sclk is in quantas of 10kHz */
443 if (amdgpu_sriov_vf(adev))
444 return adev->clock.default_sclk / 100;
445 else if (adev->pm.dpm_enabled)
446 return amdgpu_dpm_get_sclk(adev, false) / 100;
447 else
448 return 100;
449}
450
451void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
452{
453 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
454 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
455
456 memset(cu_info, 0, sizeof(*cu_info));
457 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
458 return;
459
460 cu_info->cu_active_number = acu_info.number;
461 cu_info->cu_ao_mask = acu_info.ao_cu_mask;
462 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
463 sizeof(acu_info.bitmap));
464 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
465 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
466 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
467 cu_info->simd_per_cu = acu_info.simd_per_cu;
468 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
469 cu_info->wave_front_size = acu_info.wave_front_size;
470 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
471 cu_info->lds_size = acu_info.lds_size;
472}
473
474int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
475 struct kgd_dev **dma_buf_kgd,
476 uint64_t *bo_size, void *metadata_buffer,
477 size_t buffer_size, uint32_t *metadata_size,
478 uint32_t *flags)
479{
480 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
481 struct dma_buf *dma_buf;
482 struct drm_gem_object *obj;
483 struct amdgpu_bo *bo;
484 uint64_t metadata_flags;
485 int r = -EINVAL;
486
487 dma_buf = dma_buf_get(dma_buf_fd);
488 if (IS_ERR(dma_buf))
489 return PTR_ERR(dma_buf);
490
491 if (dma_buf->ops != &amdgpu_dmabuf_ops)
492 /* Can't handle non-graphics buffers */
493 goto out_put;
494
495 obj = dma_buf->priv;
496 if (obj->dev->driver != adev_to_drm(adev)->driver)
497 /* Can't handle buffers from different drivers */
498 goto out_put;
499
500 adev = drm_to_adev(obj->dev);
501 bo = gem_to_amdgpu_bo(obj);
502 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
503 AMDGPU_GEM_DOMAIN_GTT)))
504 /* Only VRAM and GTT BOs are supported */
505 goto out_put;
506
507 r = 0;
508 if (dma_buf_kgd)
509 *dma_buf_kgd = (struct kgd_dev *)adev;
510 if (bo_size)
511 *bo_size = amdgpu_bo_size(bo);
512 if (metadata_buffer)
513 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
514 metadata_size, &metadata_flags);
515 if (flags) {
516 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
517 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
518 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
519
520 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
521 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
522 }
523
524out_put:
525 dma_buf_put(dma_buf);
526 return r;
527}
528
529uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
530{
531 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
532 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
533
534 return amdgpu_vram_mgr_usage(vram_man);
535}
536
537uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
538{
539 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
540
541 return adev->gmc.xgmi.hive_id;
542}
543
544uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
545{
546 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
547
548 return adev->unique_id;
549}
550
551uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
552{
553 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
554 struct amdgpu_device *adev = (struct amdgpu_device *)dst;
555 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
556
557 if (ret < 0) {
558 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
559 adev->gmc.xgmi.physical_node_id,
560 peer_adev->gmc.xgmi.physical_node_id, ret);
561 ret = 0;
562 }
563 return (uint8_t)ret;
564}
565
566uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
567{
568 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
569
570 return adev->rmmio_remap.bus_addr;
571}
572
573uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
574{
575 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
576
577 return adev->gds.gws_size;
578}
579
580uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
581{
582 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
583
584 return adev->rev_id;
585}
586
587int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
588{
589 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
590
591 return adev->gmc.noretry;
592}
593
594int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
595 uint32_t vmid, uint64_t gpu_addr,
596 uint32_t *ib_cmd, uint32_t ib_len)
597{
598 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
599 struct amdgpu_job *job;
600 struct amdgpu_ib *ib;
601 struct amdgpu_ring *ring;
602 struct dma_fence *f = NULL;
603 int ret;
604
605 switch (engine) {
606 case KGD_ENGINE_MEC1:
607 ring = &adev->gfx.compute_ring[0];
608 break;
609 case KGD_ENGINE_SDMA1:
610 ring = &adev->sdma.instance[0].ring;
611 break;
612 case KGD_ENGINE_SDMA2:
613 ring = &adev->sdma.instance[1].ring;
614 break;
615 default:
616 pr_err("Invalid engine in IB submission: %d\n", engine);
617 ret = -EINVAL;
618 goto err;
619 }
620
621 ret = amdgpu_job_alloc(adev, 1, &job, NULL);
622 if (ret)
623 goto err;
624
625 ib = &job->ibs[0];
626 memset(ib, 0, sizeof(struct amdgpu_ib));
627
628 ib->gpu_addr = gpu_addr;
629 ib->ptr = ib_cmd;
630 ib->length_dw = ib_len;
631 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
632 job->vmid = vmid;
633
634 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
635
636 if (ret) {
637 DRM_ERROR("amdgpu: failed to schedule IB.\n");
638 goto err_ib_sched;
639 }
640
641 ret = dma_fence_wait(f, false);
642
643err_ib_sched:
644 dma_fence_put(f);
645 amdgpu_job_free(job);
646err:
647 return ret;
648}
649
650void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
651{
652 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
653
654 amdgpu_dpm_switch_power_profile(adev,
655 PP_SMC_POWER_PROFILE_COMPUTE,
656 !idle);
657}
658
659bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
660{
661 if (adev->kfd.dev)
662 return vmid >= adev->vm_manager.first_kfd_vmid;
663
664 return false;
665}
666
667int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
668{
669 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
670
671 if (adev->family == AMDGPU_FAMILY_AI) {
672 int i;
673
674 for (i = 0; i < adev->num_vmhubs; i++)
675 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
676 } else {
677 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
678 }
679
680 return 0;
681}
682
683int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
684 enum TLB_FLUSH_TYPE flush_type)
685{
686 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
687 bool all_hub = false;
688
689 if (adev->family == AMDGPU_FAMILY_AI)
690 all_hub = true;
691
692 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
693}
694
695bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
696{
697 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
698
699 return adev->have_atomics_support;
700}