1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Amlogic Meson-G12A Clock Controller Driver
   4 *
   5 * Copyright (c) 2016 Baylibre SAS.
   6 * Author: Michael Turquette <mturquette@baylibre.com>
   7 *
   8 * Copyright (c) 2018 Amlogic, inc.
   9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10 * Author: Jian Hu <jian.hu@amlogic.com>
  11 */
  12
  13#include <linux/clk-provider.h>
  14#include <linux/init.h>
  15#include <linux/of_device.h>
  16#include <linux/platform_device.h>
  17#include <linux/clk.h>
  18#include <linux/module.h>
  19
  20#include "clk-mpll.h"
  21#include "clk-pll.h"
  22#include "clk-regmap.h"
  23#include "clk-cpu-dyndiv.h"
  24#include "vid-pll-div.h"
  25#include "meson-eeclk.h"
  26#include "g12a.h"
  27
  28static DEFINE_SPINLOCK(meson_clk_lock);
  29
  30static struct clk_regmap g12a_fixed_pll_dco = {
  31	.data = &(struct meson_clk_pll_data){
  32		.en = {
  33			.reg_off = HHI_FIX_PLL_CNTL0,
  34			.shift   = 28,
  35			.width   = 1,
  36		},
  37		.m = {
  38			.reg_off = HHI_FIX_PLL_CNTL0,
  39			.shift   = 0,
  40			.width   = 8,
  41		},
  42		.n = {
  43			.reg_off = HHI_FIX_PLL_CNTL0,
  44			.shift   = 10,
  45			.width   = 5,
  46		},
  47		.frac = {
  48			.reg_off = HHI_FIX_PLL_CNTL1,
  49			.shift   = 0,
  50			.width   = 17,
  51		},
  52		.l = {
  53			.reg_off = HHI_FIX_PLL_CNTL0,
  54			.shift   = 31,
  55			.width   = 1,
  56		},
  57		.rst = {
  58			.reg_off = HHI_FIX_PLL_CNTL0,
  59			.shift   = 29,
  60			.width   = 1,
  61		},
  62	},
  63	.hw.init = &(struct clk_init_data){
  64		.name = "fixed_pll_dco",
  65		.ops = &meson_clk_pll_ro_ops,
  66		.parent_data = &(const struct clk_parent_data) {
  67			.fw_name = "xtal",
  68		},
  69		.num_parents = 1,
  70	},
  71};
  72
  73static struct clk_regmap g12a_fixed_pll = {
  74	.data = &(struct clk_regmap_div_data){
  75		.offset = HHI_FIX_PLL_CNTL0,
  76		.shift = 16,
  77		.width = 2,
  78		.flags = CLK_DIVIDER_POWER_OF_TWO,
  79	},
  80	.hw.init = &(struct clk_init_data){
  81		.name = "fixed_pll",
  82		.ops = &clk_regmap_divider_ro_ops,
  83		.parent_hws = (const struct clk_hw *[]) {
  84			&g12a_fixed_pll_dco.hw
  85		},
  86		.num_parents = 1,
  87		/*
  88		 * This clock won't ever change at runtime so
  89		 * CLK_SET_RATE_PARENT is not required
  90		 */
  91	},
  92};
  93
  94static const struct pll_mult_range g12a_sys_pll_mult_range = {
  95	.min = 128,
  96	.max = 250,
  97};
  98
  99static struct clk_regmap g12a_sys_pll_dco = {
 100	.data = &(struct meson_clk_pll_data){
 101		.en = {
 102			.reg_off = HHI_SYS_PLL_CNTL0,
 103			.shift   = 28,
 104			.width   = 1,
 105		},
 106		.m = {
 107			.reg_off = HHI_SYS_PLL_CNTL0,
 108			.shift   = 0,
 109			.width   = 8,
 110		},
 111		.n = {
 112			.reg_off = HHI_SYS_PLL_CNTL0,
 113			.shift   = 10,
 114			.width   = 5,
 115		},
 116		.l = {
 117			.reg_off = HHI_SYS_PLL_CNTL0,
 118			.shift   = 31,
 119			.width   = 1,
 120		},
 121		.rst = {
 122			.reg_off = HHI_SYS_PLL_CNTL0,
 123			.shift   = 29,
 124			.width   = 1,
 125		},
 126		.range = &g12a_sys_pll_mult_range,
 127	},
 128	.hw.init = &(struct clk_init_data){
 129		.name = "sys_pll_dco",
 130		.ops = &meson_clk_pll_ops,
 131		.parent_data = &(const struct clk_parent_data) {
 132			.fw_name = "xtal",
 133		},
 134		.num_parents = 1,
 135		/* This clock feeds the CPU, avoid disabling it */
 136		.flags = CLK_IS_CRITICAL,
 137	},
 138};
 139
 140static struct clk_regmap g12a_sys_pll = {
 141	.data = &(struct clk_regmap_div_data){
 142		.offset = HHI_SYS_PLL_CNTL0,
 143		.shift = 16,
 144		.width = 3,
 145		.flags = CLK_DIVIDER_POWER_OF_TWO,
 146	},
 147	.hw.init = &(struct clk_init_data){
 148		.name = "sys_pll",
 149		.ops = &clk_regmap_divider_ops,
 150		.parent_hws = (const struct clk_hw *[]) {
 151			&g12a_sys_pll_dco.hw
 152		},
 153		.num_parents = 1,
 154		.flags = CLK_SET_RATE_PARENT,
 155	},
 156};
 157
 158static struct clk_regmap g12b_sys1_pll_dco = {
 159	.data = &(struct meson_clk_pll_data){
 160		.en = {
 161			.reg_off = HHI_SYS1_PLL_CNTL0,
 162			.shift   = 28,
 163			.width   = 1,
 164		},
 165		.m = {
 166			.reg_off = HHI_SYS1_PLL_CNTL0,
 167			.shift   = 0,
 168			.width   = 8,
 169		},
 170		.n = {
 171			.reg_off = HHI_SYS1_PLL_CNTL0,
 172			.shift   = 10,
 173			.width   = 5,
 174		},
 175		.l = {
 176			.reg_off = HHI_SYS1_PLL_CNTL0,
 177			.shift   = 31,
 178			.width   = 1,
 179		},
 180		.rst = {
 181			.reg_off = HHI_SYS1_PLL_CNTL0,
 182			.shift   = 29,
 183			.width   = 1,
 184		},
 185		.range = &g12a_sys_pll_mult_range,
 186	},
 187	.hw.init = &(struct clk_init_data){
 188		.name = "sys1_pll_dco",
 189		.ops = &meson_clk_pll_ops,
 190		.parent_data = &(const struct clk_parent_data) {
 191			.fw_name = "xtal",
 192		},
 193		.num_parents = 1,
 194		/* This clock feeds the CPU, avoid disabling it */
 195		.flags = CLK_IS_CRITICAL,
 196	},
 197};
 198
 199static struct clk_regmap g12b_sys1_pll = {
 200	.data = &(struct clk_regmap_div_data){
 201		.offset = HHI_SYS1_PLL_CNTL0,
 202		.shift = 16,
 203		.width = 3,
 204		.flags = CLK_DIVIDER_POWER_OF_TWO,
 205	},
 206	.hw.init = &(struct clk_init_data){
 207		.name = "sys1_pll",
 208		.ops = &clk_regmap_divider_ops,
 209		.parent_hws = (const struct clk_hw *[]) {
 210			&g12b_sys1_pll_dco.hw
 211		},
 212		.num_parents = 1,
 213		.flags = CLK_SET_RATE_PARENT,
 214	},
 215};
 216
 217static struct clk_regmap g12a_sys_pll_div16_en = {
 218	.data = &(struct clk_regmap_gate_data){
 219		.offset = HHI_SYS_CPU_CLK_CNTL1,
 220		.bit_idx = 24,
 221	},
 222	.hw.init = &(struct clk_init_data) {
 223		.name = "sys_pll_div16_en",
 224		.ops = &clk_regmap_gate_ro_ops,
 225		.parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
 226		.num_parents = 1,
 227		/*
 228		 * This clock is used to debug the sys_pll range
 229		 * Linux should not change it at runtime
 230		 */
 231	},
 232};
 233
 234static struct clk_regmap g12b_sys1_pll_div16_en = {
 235	.data = &(struct clk_regmap_gate_data){
 236		.offset = HHI_SYS_CPUB_CLK_CNTL1,
 237		.bit_idx = 24,
 238	},
 239	.hw.init = &(struct clk_init_data) {
 240		.name = "sys1_pll_div16_en",
 241		.ops = &clk_regmap_gate_ro_ops,
 242		.parent_hws = (const struct clk_hw *[]) {
 243			&g12b_sys1_pll.hw
 244		},
 245		.num_parents = 1,
 246		/*
 247		 * This clock is used to debug the sys_pll range
 248		 * Linux should not change it at runtime
 249		 */
 250	},
 251};
 252
 253static struct clk_fixed_factor g12a_sys_pll_div16 = {
 254	.mult = 1,
 255	.div = 16,
 256	.hw.init = &(struct clk_init_data){
 257		.name = "sys_pll_div16",
 258		.ops = &clk_fixed_factor_ops,
 259		.parent_hws = (const struct clk_hw *[]) {
 260			&g12a_sys_pll_div16_en.hw
 261		},
 262		.num_parents = 1,
 263	},
 264};
 265
 266static struct clk_fixed_factor g12b_sys1_pll_div16 = {
 267	.mult = 1,
 268	.div = 16,
 269	.hw.init = &(struct clk_init_data){
 270		.name = "sys1_pll_div16",
 271		.ops = &clk_fixed_factor_ops,
 272		.parent_hws = (const struct clk_hw *[]) {
 273			&g12b_sys1_pll_div16_en.hw
 274		},
 275		.num_parents = 1,
 276	},
 277};
 278
 279static struct clk_fixed_factor g12a_fclk_div2_div = {
 280	.mult = 1,
 281	.div = 2,
 282	.hw.init = &(struct clk_init_data){
 283		.name = "fclk_div2_div",
 284		.ops = &clk_fixed_factor_ops,
 285		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 286		.num_parents = 1,
 287	},
 288};
 289
 290static struct clk_regmap g12a_fclk_div2 = {
 291	.data = &(struct clk_regmap_gate_data){
 292		.offset = HHI_FIX_PLL_CNTL1,
 293		.bit_idx = 24,
 294	},
 295	.hw.init = &(struct clk_init_data){
 296		.name = "fclk_div2",
 297		.ops = &clk_regmap_gate_ops,
 298		.parent_hws = (const struct clk_hw *[]) {
 299			&g12a_fclk_div2_div.hw
 300		},
 301		.num_parents = 1,
 302		/*
 303		 * Similar to fclk_div3, it seems that this clock is used by
 304		 * the resident firmware and is required by the platform to
 305		 * operate correctly.
 306		 * Until the following condition are met, we need this clock to
 307		 * be marked as critical:
 308		 * a) Mark the clock used by a firmware resource, if possible
 309		 * b) CCF has a clock hand-off mechanism to make the sure the
 310		 *    clock stays on until the proper driver comes along
 311		 */
 312		.flags = CLK_IS_CRITICAL,
 313	},
 314};
 315
 316static struct clk_fixed_factor g12a_fclk_div3_div = {
 317	.mult = 1,
 318	.div = 3,
 319	.hw.init = &(struct clk_init_data){
 320		.name = "fclk_div3_div",
 321		.ops = &clk_fixed_factor_ops,
 322		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 323		.num_parents = 1,
 324	},
 325};
 326
 327static struct clk_regmap g12a_fclk_div3 = {
 328	.data = &(struct clk_regmap_gate_data){
 329		.offset = HHI_FIX_PLL_CNTL1,
 330		.bit_idx = 20,
 331	},
 332	.hw.init = &(struct clk_init_data){
 333		.name = "fclk_div3",
 334		.ops = &clk_regmap_gate_ops,
 335		.parent_hws = (const struct clk_hw *[]) {
 336			&g12a_fclk_div3_div.hw
 337		},
 338		.num_parents = 1,
 339		/*
 340		 * This clock is used by the resident firmware and is required
 341		 * by the platform to operate correctly.
 342		 * Until the following condition are met, we need this clock to
 343		 * be marked as critical:
 344		 * a) Mark the clock used by a firmware resource, if possible
 345		 * b) CCF has a clock hand-off mechanism to make the sure the
 346		 *    clock stays on until the proper driver comes along
 347		 */
 348		.flags = CLK_IS_CRITICAL,
 349	},
 350};
 351
 352/* Datasheet names this field as "premux0" */
 353static struct clk_regmap g12a_cpu_clk_premux0 = {
 354	.data = &(struct clk_regmap_mux_data){
 355		.offset = HHI_SYS_CPU_CLK_CNTL0,
 356		.mask = 0x3,
 357		.shift = 0,
 358		.flags = CLK_MUX_ROUND_CLOSEST,
 359	},
 360	.hw.init = &(struct clk_init_data){
 361		.name = "cpu_clk_dyn0_sel",
 362		.ops = &clk_regmap_mux_ops,
 363		.parent_data = (const struct clk_parent_data []) {
 364			{ .fw_name = "xtal", },
 365			{ .hw = &g12a_fclk_div2.hw },
 366			{ .hw = &g12a_fclk_div3.hw },
 367		},
 368		.num_parents = 3,
 369		.flags = CLK_SET_RATE_PARENT,
 370	},
 371};
 372
 373/* Datasheet names this field as "premux1" */
 374static struct clk_regmap g12a_cpu_clk_premux1 = {
 375	.data = &(struct clk_regmap_mux_data){
 376		.offset = HHI_SYS_CPU_CLK_CNTL0,
 377		.mask = 0x3,
 378		.shift = 16,
 379	},
 380	.hw.init = &(struct clk_init_data){
 381		.name = "cpu_clk_dyn1_sel",
 382		.ops = &clk_regmap_mux_ops,
 383		.parent_data = (const struct clk_parent_data []) {
 384			{ .fw_name = "xtal", },
 385			{ .hw = &g12a_fclk_div2.hw },
 386			{ .hw = &g12a_fclk_div3.hw },
 387		},
 388		.num_parents = 3,
 389		/* This sub-tree is used a parking clock */
 390		.flags = CLK_SET_RATE_NO_REPARENT
 391	},
 392};
 393
 394/* Datasheet names this field as "mux0_divn_tcnt" */
 395static struct clk_regmap g12a_cpu_clk_mux0_div = {
 396	.data = &(struct meson_clk_cpu_dyndiv_data){
 397		.div = {
 398			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
 399			.shift = 4,
 400			.width = 6,
 401		},
 402		.dyn = {
 403			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
 404			.shift = 26,
 405			.width = 1,
 406		},
 407	},
 408	.hw.init = &(struct clk_init_data){
 409		.name = "cpu_clk_dyn0_div",
 410		.ops = &meson_clk_cpu_dyndiv_ops,
 411		.parent_hws = (const struct clk_hw *[]) {
 412			&g12a_cpu_clk_premux0.hw
 413		},
 414		.num_parents = 1,
 415		.flags = CLK_SET_RATE_PARENT,
 416	},
 417};
 418
 419/* Datasheet names this field as "postmux0" */
 420static struct clk_regmap g12a_cpu_clk_postmux0 = {
 421	.data = &(struct clk_regmap_mux_data){
 422		.offset = HHI_SYS_CPU_CLK_CNTL0,
 423		.mask = 0x1,
 424		.shift = 2,
 425		.flags = CLK_MUX_ROUND_CLOSEST,
 426	},
 427	.hw.init = &(struct clk_init_data){
 428		.name = "cpu_clk_dyn0",
 429		.ops = &clk_regmap_mux_ops,
 430		.parent_hws = (const struct clk_hw *[]) {
 431			&g12a_cpu_clk_premux0.hw,
 432			&g12a_cpu_clk_mux0_div.hw,
 433		},
 434		.num_parents = 2,
 435		.flags = CLK_SET_RATE_PARENT,
 436	},
 437};
 438
 439/* Datasheet names this field as "Mux1_divn_tcnt" */
 440static struct clk_regmap g12a_cpu_clk_mux1_div = {
 441	.data = &(struct clk_regmap_div_data){
 442		.offset = HHI_SYS_CPU_CLK_CNTL0,
 443		.shift = 20,
 444		.width = 6,
 445	},
 446	.hw.init = &(struct clk_init_data){
 447		.name = "cpu_clk_dyn1_div",
 448		.ops = &clk_regmap_divider_ro_ops,
 449		.parent_hws = (const struct clk_hw *[]) {
 450			&g12a_cpu_clk_premux1.hw
 451		},
 452		.num_parents = 1,
 453	},
 454};
 455
 456/* Datasheet names this field as "postmux1" */
 457static struct clk_regmap g12a_cpu_clk_postmux1 = {
 458	.data = &(struct clk_regmap_mux_data){
 459		.offset = HHI_SYS_CPU_CLK_CNTL0,
 460		.mask = 0x1,
 461		.shift = 18,
 462	},
 463	.hw.init = &(struct clk_init_data){
 464		.name = "cpu_clk_dyn1",
 465		.ops = &clk_regmap_mux_ops,
 466		.parent_hws = (const struct clk_hw *[]) {
 467			&g12a_cpu_clk_premux1.hw,
 468			&g12a_cpu_clk_mux1_div.hw,
 469		},
 470		.num_parents = 2,
 471		/* This sub-tree is used a parking clock */
 472		.flags = CLK_SET_RATE_NO_REPARENT,
 473	},
 474};
 475
 476/* Datasheet names this field as "Final_dyn_mux_sel" */
 477static struct clk_regmap g12a_cpu_clk_dyn = {
 478	.data = &(struct clk_regmap_mux_data){
 479		.offset = HHI_SYS_CPU_CLK_CNTL0,
 480		.mask = 0x1,
 481		.shift = 10,
 482		.flags = CLK_MUX_ROUND_CLOSEST,
 483	},
 484	.hw.init = &(struct clk_init_data){
 485		.name = "cpu_clk_dyn",
 486		.ops = &clk_regmap_mux_ops,
 487		.parent_hws = (const struct clk_hw *[]) {
 488			&g12a_cpu_clk_postmux0.hw,
 489			&g12a_cpu_clk_postmux1.hw,
 490		},
 491		.num_parents = 2,
 492		.flags = CLK_SET_RATE_PARENT,
 493	},
 494};
 495
 496/* Datasheet names this field as "Final_mux_sel" */
 497static struct clk_regmap g12a_cpu_clk = {
 498	.data = &(struct clk_regmap_mux_data){
 499		.offset = HHI_SYS_CPU_CLK_CNTL0,
 500		.mask = 0x1,
 501		.shift = 11,
 502		.flags = CLK_MUX_ROUND_CLOSEST,
 503	},
 504	.hw.init = &(struct clk_init_data){
 505		.name = "cpu_clk",
 506		.ops = &clk_regmap_mux_ops,
 507		.parent_hws = (const struct clk_hw *[]) {
 508			&g12a_cpu_clk_dyn.hw,
 509			&g12a_sys_pll.hw,
 510		},
 511		.num_parents = 2,
 512		.flags = CLK_SET_RATE_PARENT,
 513	},
 514};
 515
 516/* Datasheet names this field as "Final_mux_sel" */
 517static struct clk_regmap g12b_cpu_clk = {
 518	.data = &(struct clk_regmap_mux_data){
 519		.offset = HHI_SYS_CPU_CLK_CNTL0,
 520		.mask = 0x1,
 521		.shift = 11,
 522		.flags = CLK_MUX_ROUND_CLOSEST,
 523	},
 524	.hw.init = &(struct clk_init_data){
 525		.name = "cpu_clk",
 526		.ops = &clk_regmap_mux_ops,
 527		.parent_hws = (const struct clk_hw *[]) {
 528			&g12a_cpu_clk_dyn.hw,
 529			&g12b_sys1_pll.hw
 530		},
 531		.num_parents = 2,
 532		.flags = CLK_SET_RATE_PARENT,
 533	},
 534};
 535
 536/* Datasheet names this field as "premux0" */
 537static struct clk_regmap g12b_cpub_clk_premux0 = {
 538	.data = &(struct clk_regmap_mux_data){
 539		.offset = HHI_SYS_CPUB_CLK_CNTL,
 540		.mask = 0x3,
 541		.shift = 0,
 542		.flags = CLK_MUX_ROUND_CLOSEST,
 543	},
 544	.hw.init = &(struct clk_init_data){
 545		.name = "cpub_clk_dyn0_sel",
 546		.ops = &clk_regmap_mux_ops,
 547		.parent_data = (const struct clk_parent_data []) {
 548			{ .fw_name = "xtal", },
 549			{ .hw = &g12a_fclk_div2.hw },
 550			{ .hw = &g12a_fclk_div3.hw },
 551		},
 552		.num_parents = 3,
 553		.flags = CLK_SET_RATE_PARENT,
 554	},
 555};
 556
 557/* Datasheet names this field as "mux0_divn_tcnt" */
 558static struct clk_regmap g12b_cpub_clk_mux0_div = {
 559	.data = &(struct meson_clk_cpu_dyndiv_data){
 560		.div = {
 561			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
 562			.shift = 4,
 563			.width = 6,
 564		},
 565		.dyn = {
 566			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
 567			.shift = 26,
 568			.width = 1,
 569		},
 570	},
 571	.hw.init = &(struct clk_init_data){
 572		.name = "cpub_clk_dyn0_div",
 573		.ops = &meson_clk_cpu_dyndiv_ops,
 574		.parent_hws = (const struct clk_hw *[]) {
 575			&g12b_cpub_clk_premux0.hw
 576		},
 577		.num_parents = 1,
 578		.flags = CLK_SET_RATE_PARENT,
 579	},
 580};
 581
 582/* Datasheet names this field as "postmux0" */
 583static struct clk_regmap g12b_cpub_clk_postmux0 = {
 584	.data = &(struct clk_regmap_mux_data){
 585		.offset = HHI_SYS_CPUB_CLK_CNTL,
 586		.mask = 0x1,
 587		.shift = 2,
 588		.flags = CLK_MUX_ROUND_CLOSEST,
 589	},
 590	.hw.init = &(struct clk_init_data){
 591		.name = "cpub_clk_dyn0",
 592		.ops = &clk_regmap_mux_ops,
 593		.parent_hws = (const struct clk_hw *[]) {
 594			&g12b_cpub_clk_premux0.hw,
 595			&g12b_cpub_clk_mux0_div.hw
 596		},
 597		.num_parents = 2,
 598		.flags = CLK_SET_RATE_PARENT,
 599	},
 600};
 601
 602/* Datasheet names this field as "premux1" */
 603static struct clk_regmap g12b_cpub_clk_premux1 = {
 604	.data = &(struct clk_regmap_mux_data){
 605		.offset = HHI_SYS_CPUB_CLK_CNTL,
 606		.mask = 0x3,
 607		.shift = 16,
 608	},
 609	.hw.init = &(struct clk_init_data){
 610		.name = "cpub_clk_dyn1_sel",
 611		.ops = &clk_regmap_mux_ops,
 612		.parent_data = (const struct clk_parent_data []) {
 613			{ .fw_name = "xtal", },
 614			{ .hw = &g12a_fclk_div2.hw },
 615			{ .hw = &g12a_fclk_div3.hw },
 616		},
 617		.num_parents = 3,
 618		/* This sub-tree is used a parking clock */
 619		.flags = CLK_SET_RATE_NO_REPARENT,
 620	},
 621};
 622
 623/* Datasheet names this field as "Mux1_divn_tcnt" */
 624static struct clk_regmap g12b_cpub_clk_mux1_div = {
 625	.data = &(struct clk_regmap_div_data){
 626		.offset = HHI_SYS_CPUB_CLK_CNTL,
 627		.shift = 20,
 628		.width = 6,
 629	},
 630	.hw.init = &(struct clk_init_data){
 631		.name = "cpub_clk_dyn1_div",
 632		.ops = &clk_regmap_divider_ro_ops,
 633		.parent_hws = (const struct clk_hw *[]) {
 634			&g12b_cpub_clk_premux1.hw
 635		},
 636		.num_parents = 1,
 637	},
 638};
 639
 640/* Datasheet names this field as "postmux1" */
 641static struct clk_regmap g12b_cpub_clk_postmux1 = {
 642	.data = &(struct clk_regmap_mux_data){
 643		.offset = HHI_SYS_CPUB_CLK_CNTL,
 644		.mask = 0x1,
 645		.shift = 18,
 646	},
 647	.hw.init = &(struct clk_init_data){
 648		.name = "cpub_clk_dyn1",
 649		.ops = &clk_regmap_mux_ops,
 650		.parent_hws = (const struct clk_hw *[]) {
 651			&g12b_cpub_clk_premux1.hw,
 652			&g12b_cpub_clk_mux1_div.hw
 653		},
 654		.num_parents = 2,
 655		/* This sub-tree is used a parking clock */
 656		.flags = CLK_SET_RATE_NO_REPARENT,
 657	},
 658};
 659
 660/* Datasheet names this field as "Final_dyn_mux_sel" */
 661static struct clk_regmap g12b_cpub_clk_dyn = {
 662	.data = &(struct clk_regmap_mux_data){
 663		.offset = HHI_SYS_CPUB_CLK_CNTL,
 664		.mask = 0x1,
 665		.shift = 10,
 666		.flags = CLK_MUX_ROUND_CLOSEST,
 667	},
 668	.hw.init = &(struct clk_init_data){
 669		.name = "cpub_clk_dyn",
 670		.ops = &clk_regmap_mux_ops,
 671		.parent_hws = (const struct clk_hw *[]) {
 672			&g12b_cpub_clk_postmux0.hw,
 673			&g12b_cpub_clk_postmux1.hw
 674		},
 675		.num_parents = 2,
 676		.flags = CLK_SET_RATE_PARENT,
 677	},
 678};
 679
 680/* Datasheet names this field as "Final_mux_sel" */
 681static struct clk_regmap g12b_cpub_clk = {
 682	.data = &(struct clk_regmap_mux_data){
 683		.offset = HHI_SYS_CPUB_CLK_CNTL,
 684		.mask = 0x1,
 685		.shift = 11,
 686		.flags = CLK_MUX_ROUND_CLOSEST,
 687	},
 688	.hw.init = &(struct clk_init_data){
 689		.name = "cpub_clk",
 690		.ops = &clk_regmap_mux_ops,
 691		.parent_hws = (const struct clk_hw *[]) {
 692			&g12b_cpub_clk_dyn.hw,
 693			&g12a_sys_pll.hw
 694		},
 695		.num_parents = 2,
 696		.flags = CLK_SET_RATE_PARENT,
 697	},
 698};
 699
 700static struct clk_regmap sm1_gp1_pll;
 701
 702/* Datasheet names this field as "premux0" */
 703static struct clk_regmap sm1_dsu_clk_premux0 = {
 704	.data = &(struct clk_regmap_mux_data){
 705		.offset = HHI_SYS_CPU_CLK_CNTL5,
 706		.mask = 0x3,
 707		.shift = 0,
 708	},
 709	.hw.init = &(struct clk_init_data){
 710		.name = "dsu_clk_dyn0_sel",
 711		.ops = &clk_regmap_mux_ro_ops,
 712		.parent_data = (const struct clk_parent_data []) {
 713			{ .fw_name = "xtal", },
 714			{ .hw = &g12a_fclk_div2.hw },
 715			{ .hw = &g12a_fclk_div3.hw },
 716			{ .hw = &sm1_gp1_pll.hw },
 717		},
 718		.num_parents = 4,
 719	},
 720};
 721
 722/* Datasheet names this field as "premux1" */
 723static struct clk_regmap sm1_dsu_clk_premux1 = {
 724	.data = &(struct clk_regmap_mux_data){
 725		.offset = HHI_SYS_CPU_CLK_CNTL5,
 726		.mask = 0x3,
 727		.shift = 16,
 728	},
 729	.hw.init = &(struct clk_init_data){
 730		.name = "dsu_clk_dyn1_sel",
 731		.ops = &clk_regmap_mux_ro_ops,
 732		.parent_data = (const struct clk_parent_data []) {
 733			{ .fw_name = "xtal", },
 734			{ .hw = &g12a_fclk_div2.hw },
 735			{ .hw = &g12a_fclk_div3.hw },
 736			{ .hw = &sm1_gp1_pll.hw },
 737		},
 738		.num_parents = 4,
 739	},
 740};
 741
 742/* Datasheet names this field as "Mux0_divn_tcnt" */
 743static struct clk_regmap sm1_dsu_clk_mux0_div = {
 744	.data = &(struct clk_regmap_div_data){
 745		.offset = HHI_SYS_CPU_CLK_CNTL5,
 746		.shift = 4,
 747		.width = 6,
 748	},
 749	.hw.init = &(struct clk_init_data){
 750		.name = "dsu_clk_dyn0_div",
 751		.ops = &clk_regmap_divider_ro_ops,
 752		.parent_hws = (const struct clk_hw *[]) {
 753			&sm1_dsu_clk_premux0.hw
 754		},
 755		.num_parents = 1,
 756	},
 757};
 758
 759/* Datasheet names this field as "postmux0" */
 760static struct clk_regmap sm1_dsu_clk_postmux0 = {
 761	.data = &(struct clk_regmap_mux_data){
 762		.offset = HHI_SYS_CPU_CLK_CNTL5,
 763		.mask = 0x1,
 764		.shift = 2,
 765	},
 766	.hw.init = &(struct clk_init_data){
 767		.name = "dsu_clk_dyn0",
 768		.ops = &clk_regmap_mux_ro_ops,
 769		.parent_hws = (const struct clk_hw *[]) {
 770			&sm1_dsu_clk_premux0.hw,
 771			&sm1_dsu_clk_mux0_div.hw,
 772		},
 773		.num_parents = 2,
 774	},
 775};
 776
 777/* Datasheet names this field as "Mux1_divn_tcnt" */
 778static struct clk_regmap sm1_dsu_clk_mux1_div = {
 779	.data = &(struct clk_regmap_div_data){
 780		.offset = HHI_SYS_CPU_CLK_CNTL5,
 781		.shift = 20,
 782		.width = 6,
 783	},
 784	.hw.init = &(struct clk_init_data){
 785		.name = "dsu_clk_dyn1_div",
 786		.ops = &clk_regmap_divider_ro_ops,
 787		.parent_hws = (const struct clk_hw *[]) {
 788			&sm1_dsu_clk_premux1.hw
 789		},
 790		.num_parents = 1,
 791	},
 792};
 793
 794/* Datasheet names this field as "postmux1" */
 795static struct clk_regmap sm1_dsu_clk_postmux1 = {
 796	.data = &(struct clk_regmap_mux_data){
 797		.offset = HHI_SYS_CPU_CLK_CNTL5,
 798		.mask = 0x1,
 799		.shift = 18,
 800	},
 801	.hw.init = &(struct clk_init_data){
 802		.name = "dsu_clk_dyn1",
 803		.ops = &clk_regmap_mux_ro_ops,
 804		.parent_hws = (const struct clk_hw *[]) {
 805			&sm1_dsu_clk_premux1.hw,
 806			&sm1_dsu_clk_mux1_div.hw,
 807		},
 808		.num_parents = 2,
 809	},
 810};
 811
 812/* Datasheet names this field as "Final_dyn_mux_sel" */
 813static struct clk_regmap sm1_dsu_clk_dyn = {
 814	.data = &(struct clk_regmap_mux_data){
 815		.offset = HHI_SYS_CPU_CLK_CNTL5,
 816		.mask = 0x1,
 817		.shift = 10,
 818	},
 819	.hw.init = &(struct clk_init_data){
 820		.name = "dsu_clk_dyn",
 821		.ops = &clk_regmap_mux_ro_ops,
 822		.parent_hws = (const struct clk_hw *[]) {
 823			&sm1_dsu_clk_postmux0.hw,
 824			&sm1_dsu_clk_postmux1.hw,
 825		},
 826		.num_parents = 2,
 827	},
 828};
 829
 830/* Datasheet names this field as "Final_mux_sel" */
 831static struct clk_regmap sm1_dsu_final_clk = {
 832	.data = &(struct clk_regmap_mux_data){
 833		.offset = HHI_SYS_CPU_CLK_CNTL5,
 834		.mask = 0x1,
 835		.shift = 11,
 836	},
 837	.hw.init = &(struct clk_init_data){
 838		.name = "dsu_clk_final",
 839		.ops = &clk_regmap_mux_ro_ops,
 840		.parent_hws = (const struct clk_hw *[]) {
 841			&sm1_dsu_clk_dyn.hw,
 842			&g12a_sys_pll.hw,
 843		},
 844		.num_parents = 2,
 845	},
 846};
 847
 848/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
 849static struct clk_regmap sm1_cpu1_clk = {
 850	.data = &(struct clk_regmap_mux_data){
 851		.offset = HHI_SYS_CPU_CLK_CNTL6,
 852		.mask = 0x1,
 853		.shift = 24,
 854	},
 855	.hw.init = &(struct clk_init_data){
 856		.name = "cpu1_clk",
 857		.ops = &clk_regmap_mux_ro_ops,
 858		.parent_hws = (const struct clk_hw *[]) {
 859			&g12a_cpu_clk.hw,
 860			/* This CPU also have a dedicated clock tree */
 861		},
 862		.num_parents = 1,
 863	},
 864};
 865
 866/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
 867static struct clk_regmap sm1_cpu2_clk = {
 868	.data = &(struct clk_regmap_mux_data){
 869		.offset = HHI_SYS_CPU_CLK_CNTL6,
 870		.mask = 0x1,
 871		.shift = 25,
 872	},
 873	.hw.init = &(struct clk_init_data){
 874		.name = "cpu2_clk",
 875		.ops = &clk_regmap_mux_ro_ops,
 876		.parent_hws = (const struct clk_hw *[]) {
 877			&g12a_cpu_clk.hw,
 878			/* This CPU also have a dedicated clock tree */
 879		},
 880		.num_parents = 1,
 881	},
 882};
 883
 884/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
 885static struct clk_regmap sm1_cpu3_clk = {
 886	.data = &(struct clk_regmap_mux_data){
 887		.offset = HHI_SYS_CPU_CLK_CNTL6,
 888		.mask = 0x1,
 889		.shift = 26,
 890	},
 891	.hw.init = &(struct clk_init_data){
 892		.name = "cpu3_clk",
 893		.ops = &clk_regmap_mux_ro_ops,
 894		.parent_hws = (const struct clk_hw *[]) {
 895			&g12a_cpu_clk.hw,
 896			/* This CPU also have a dedicated clock tree */
 897		},
 898		.num_parents = 1,
 899	},
 900};
 901
 902/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
 903static struct clk_regmap sm1_dsu_clk = {
 904	.data = &(struct clk_regmap_mux_data){
 905		.offset = HHI_SYS_CPU_CLK_CNTL6,
 906		.mask = 0x1,
 907		.shift = 27,
 908	},
 909	.hw.init = &(struct clk_init_data){
 910		.name = "dsu_clk",
 911		.ops = &clk_regmap_mux_ro_ops,
 912		.parent_hws = (const struct clk_hw *[]) {
 913			&g12a_cpu_clk.hw,
 914			&sm1_dsu_final_clk.hw,
 915		},
 916		.num_parents = 2,
 917	},
 918};
 919
 920static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
 921					unsigned long event, void *data)
 922{
 923	if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
 924		/* Wait for clock propagation before/after changing the mux */
 925		udelay(100);
 926		return NOTIFY_OK;
 927	}
 928
 929	return NOTIFY_DONE;
 930}
 931
 932static struct notifier_block g12a_cpu_clk_mux_nb = {
 933	.notifier_call = g12a_cpu_clk_mux_notifier_cb,
 934};
 935
 936struct g12a_cpu_clk_postmux_nb_data {
 937	struct notifier_block nb;
 938	struct clk_hw *xtal;
 939	struct clk_hw *cpu_clk_dyn;
 940	struct clk_hw *cpu_clk_postmux0;
 941	struct clk_hw *cpu_clk_postmux1;
 942	struct clk_hw *cpu_clk_premux1;
 943};
 944
 945static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
 946					    unsigned long event, void *data)
 947{
 948	struct g12a_cpu_clk_postmux_nb_data *nb_data =
 949		container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
 950
 951	switch (event) {
 952	case PRE_RATE_CHANGE:
 953		/*
 954		 * This notifier means cpu_clk_postmux0 clock will be changed
 955		 * to feed cpu_clk, this is the current path :
 956		 * cpu_clk
 957		 *    \- cpu_clk_dyn
 958		 *          \- cpu_clk_postmux0
 959		 *                \- cpu_clk_muxX_div
 960		 *                      \- cpu_clk_premux0
 961		 *				\- fclk_div3 or fclk_div2
 962		 *		OR
 963		 *                \- cpu_clk_premux0
 964		 *			\- fclk_div3 or fclk_div2
 965		 */
 966
 967		/* Setup cpu_clk_premux1 to xtal */
 968		clk_hw_set_parent(nb_data->cpu_clk_premux1,
 969				  nb_data->xtal);
 970
 971		/* Setup cpu_clk_postmux1 to bypass divider */
 972		clk_hw_set_parent(nb_data->cpu_clk_postmux1,
 973				  nb_data->cpu_clk_premux1);
 974
 975		/* Switch to parking clk on cpu_clk_postmux1 */
 976		clk_hw_set_parent(nb_data->cpu_clk_dyn,
 977				  nb_data->cpu_clk_postmux1);
 978
 979		/*
 980		 * Now, cpu_clk is 24MHz in the current path :
 981		 * cpu_clk
 982		 *    \- cpu_clk_dyn
 983		 *          \- cpu_clk_postmux1
 984		 *                \- cpu_clk_premux1
 985		 *                      \- xtal
 986		 */
 987
 988		udelay(100);
 989
 990		return NOTIFY_OK;
 991
 992	case POST_RATE_CHANGE:
 993		/*
 994		 * The cpu_clk_postmux0 has ben updated, now switch back
 995		 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
 996		 * in account.
 997		 */
 998
 999		/* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
1000		clk_hw_set_parent(nb_data->cpu_clk_dyn,
1001				  nb_data->cpu_clk_postmux0);
1002
1003		/*
1004		 * new path :
1005		 * cpu_clk
1006		 *    \- cpu_clk_dyn
1007		 *          \- cpu_clk_postmux0
1008		 *                \- cpu_clk_muxX_div
1009		 *                      \- cpu_clk_premux0
1010		 *				\- fclk_div3 or fclk_div2
1011		 *		OR
1012		 *                \- cpu_clk_premux0
1013		 *			\- fclk_div3 or fclk_div2
1014		 */
1015
1016		udelay(100);
1017
1018		return NOTIFY_OK;
1019
1020	default:
1021		return NOTIFY_DONE;
1022	}
1023}
1024
1025static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1026	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1027	.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1028	.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1029	.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1030	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1031};
1032
1033static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1034	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1035	.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1036	.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1037	.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1038	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1039};
1040
1041struct g12a_sys_pll_nb_data {
1042	struct notifier_block nb;
1043	struct clk_hw *sys_pll;
1044	struct clk_hw *cpu_clk;
1045	struct clk_hw *cpu_clk_dyn;
1046};
1047
1048static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1049				    unsigned long event, void *data)
1050{
1051	struct g12a_sys_pll_nb_data *nb_data =
1052		container_of(nb, struct g12a_sys_pll_nb_data, nb);
1053
1054	switch (event) {
1055	case PRE_RATE_CHANGE:
1056		/*
1057		 * This notifier means sys_pll clock will be changed
1058		 * to feed cpu_clk, this the current path :
1059		 * cpu_clk
1060		 *    \- sys_pll
1061		 *          \- sys_pll_dco
1062		 */
1063
1064		/* Configure cpu_clk to use cpu_clk_dyn */
1065		clk_hw_set_parent(nb_data->cpu_clk,
1066				  nb_data->cpu_clk_dyn);
1067
1068		/*
1069		 * Now, cpu_clk uses the dyn path
1070		 * cpu_clk
1071		 *    \- cpu_clk_dyn
1072		 *          \- cpu_clk_dynX
1073		 *                \- cpu_clk_dynX_sel
1074		 *		     \- cpu_clk_dynX_div
1075		 *                      \- xtal/fclk_div2/fclk_div3
1076		 *                   \- xtal/fclk_div2/fclk_div3
1077		 */
1078
1079		udelay(100);
1080
1081		return NOTIFY_OK;
1082
1083	case POST_RATE_CHANGE:
1084		/*
1085		 * The sys_pll has ben updated, now switch back cpu_clk to
1086		 * sys_pll
1087		 */
1088
1089		/* Configure cpu_clk to use sys_pll */
1090		clk_hw_set_parent(nb_data->cpu_clk,
1091				  nb_data->sys_pll);
1092
1093		udelay(100);
1094
1095		/* new path :
1096		 * cpu_clk
1097		 *    \- sys_pll
1098		 *          \- sys_pll_dco
1099		 */
1100
1101		return NOTIFY_OK;
1102
1103	default:
1104		return NOTIFY_DONE;
1105	}
1106}
1107
1108static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1109	.sys_pll = &g12a_sys_pll.hw,
1110	.cpu_clk = &g12a_cpu_clk.hw,
1111	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1112	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1113};
1114
1115/* G12B first CPU cluster uses sys1_pll */
1116static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1117	.sys_pll = &g12b_sys1_pll.hw,
1118	.cpu_clk = &g12b_cpu_clk.hw,
1119	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1120	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1121};
1122
1123/* G12B second CPU cluster uses sys_pll */
1124static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1125	.sys_pll = &g12a_sys_pll.hw,
1126	.cpu_clk = &g12b_cpub_clk.hw,
1127	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1128	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1129};
1130
1131static struct clk_regmap g12a_cpu_clk_div16_en = {
1132	.data = &(struct clk_regmap_gate_data){
1133		.offset = HHI_SYS_CPU_CLK_CNTL1,
1134		.bit_idx = 1,
1135	},
1136	.hw.init = &(struct clk_init_data) {
1137		.name = "cpu_clk_div16_en",
1138		.ops = &clk_regmap_gate_ro_ops,
1139		.parent_hws = (const struct clk_hw *[]) {
1140			&g12a_cpu_clk.hw
1141		},
1142		.num_parents = 1,
1143		/*
1144		 * This clock is used to debug the cpu_clk range
1145		 * Linux should not change it at runtime
1146		 */
1147	},
1148};
1149
1150static struct clk_regmap g12b_cpub_clk_div16_en = {
1151	.data = &(struct clk_regmap_gate_data){
1152		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1153		.bit_idx = 1,
1154	},
1155	.hw.init = &(struct clk_init_data) {
1156		.name = "cpub_clk_div16_en",
1157		.ops = &clk_regmap_gate_ro_ops,
1158		.parent_hws = (const struct clk_hw *[]) {
1159			&g12b_cpub_clk.hw
1160		},
1161		.num_parents = 1,
1162		/*
1163		 * This clock is used to debug the cpu_clk range
1164		 * Linux should not change it at runtime
1165		 */
1166	},
1167};
1168
1169static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1170	.mult = 1,
1171	.div = 16,
1172	.hw.init = &(struct clk_init_data){
1173		.name = "cpu_clk_div16",
1174		.ops = &clk_fixed_factor_ops,
1175		.parent_hws = (const struct clk_hw *[]) {
1176			&g12a_cpu_clk_div16_en.hw
1177		},
1178		.num_parents = 1,
1179	},
1180};
1181
1182static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1183	.mult = 1,
1184	.div = 16,
1185	.hw.init = &(struct clk_init_data){
1186		.name = "cpub_clk_div16",
1187		.ops = &clk_fixed_factor_ops,
1188		.parent_hws = (const struct clk_hw *[]) {
1189			&g12b_cpub_clk_div16_en.hw
1190		},
1191		.num_parents = 1,
1192	},
1193};
1194
1195static struct clk_regmap g12a_cpu_clk_apb_div = {
1196	.data = &(struct clk_regmap_div_data){
1197		.offset = HHI_SYS_CPU_CLK_CNTL1,
1198		.shift = 3,
1199		.width = 3,
1200		.flags = CLK_DIVIDER_POWER_OF_TWO,
1201	},
1202	.hw.init = &(struct clk_init_data){
1203		.name = "cpu_clk_apb_div",
1204		.ops = &clk_regmap_divider_ro_ops,
1205		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1206		.num_parents = 1,
1207	},
1208};
1209
1210static struct clk_regmap g12a_cpu_clk_apb = {
1211	.data = &(struct clk_regmap_gate_data){
1212		.offset = HHI_SYS_CPU_CLK_CNTL1,
1213		.bit_idx = 1,
1214	},
1215	.hw.init = &(struct clk_init_data) {
1216		.name = "cpu_clk_apb",
1217		.ops = &clk_regmap_gate_ro_ops,
1218		.parent_hws = (const struct clk_hw *[]) {
1219			&g12a_cpu_clk_apb_div.hw
1220		},
1221		.num_parents = 1,
1222		/*
1223		 * This clock is set by the ROM monitor code,
1224		 * Linux should not change it at runtime
1225		 */
1226	},
1227};
1228
1229static struct clk_regmap g12a_cpu_clk_atb_div = {
1230	.data = &(struct clk_regmap_div_data){
1231		.offset = HHI_SYS_CPU_CLK_CNTL1,
1232		.shift = 6,
1233		.width = 3,
1234		.flags = CLK_DIVIDER_POWER_OF_TWO,
1235	},
1236	.hw.init = &(struct clk_init_data){
1237		.name = "cpu_clk_atb_div",
1238		.ops = &clk_regmap_divider_ro_ops,
1239		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1240		.num_parents = 1,
1241	},
1242};
1243
1244static struct clk_regmap g12a_cpu_clk_atb = {
1245	.data = &(struct clk_regmap_gate_data){
1246		.offset = HHI_SYS_CPU_CLK_CNTL1,
1247		.bit_idx = 17,
1248	},
1249	.hw.init = &(struct clk_init_data) {
1250		.name = "cpu_clk_atb",
1251		.ops = &clk_regmap_gate_ro_ops,
1252		.parent_hws = (const struct clk_hw *[]) {
1253			&g12a_cpu_clk_atb_div.hw
1254		},
1255		.num_parents = 1,
1256		/*
1257		 * This clock is set by the ROM monitor code,
1258		 * Linux should not change it at runtime
1259		 */
1260	},
1261};
1262
1263static struct clk_regmap g12a_cpu_clk_axi_div = {
1264	.data = &(struct clk_regmap_div_data){
1265		.offset = HHI_SYS_CPU_CLK_CNTL1,
1266		.shift = 9,
1267		.width = 3,
1268		.flags = CLK_DIVIDER_POWER_OF_TWO,
1269	},
1270	.hw.init = &(struct clk_init_data){
1271		.name = "cpu_clk_axi_div",
1272		.ops = &clk_regmap_divider_ro_ops,
1273		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1274		.num_parents = 1,
1275	},
1276};
1277
1278static struct clk_regmap g12a_cpu_clk_axi = {
1279	.data = &(struct clk_regmap_gate_data){
1280		.offset = HHI_SYS_CPU_CLK_CNTL1,
1281		.bit_idx = 18,
1282	},
1283	.hw.init = &(struct clk_init_data) {
1284		.name = "cpu_clk_axi",
1285		.ops = &clk_regmap_gate_ro_ops,
1286		.parent_hws = (const struct clk_hw *[]) {
1287			&g12a_cpu_clk_axi_div.hw
1288		},
1289		.num_parents = 1,
1290		/*
1291		 * This clock is set by the ROM monitor code,
1292		 * Linux should not change it at runtime
1293		 */
1294	},
1295};
1296
1297static struct clk_regmap g12a_cpu_clk_trace_div = {
1298	.data = &(struct clk_regmap_div_data){
1299		.offset = HHI_SYS_CPU_CLK_CNTL1,
1300		.shift = 20,
1301		.width = 3,
1302		.flags = CLK_DIVIDER_POWER_OF_TWO,
1303	},
1304	.hw.init = &(struct clk_init_data){
1305		.name = "cpu_clk_trace_div",
1306		.ops = &clk_regmap_divider_ro_ops,
1307		.parent_data = &(const struct clk_parent_data) {
1308			/*
1309			 * Note:
1310			 * G12A and G12B have different cpu_clks (with
1311			 * different struct clk_hw). We fallback to the global
1312			 * naming string mechanism so cpu_clk_trace_div picks
1313			 * up the appropriate one.
1314			 */
1315			.name = "cpu_clk",
1316			.index = -1,
1317		},
1318		.num_parents = 1,
1319	},
1320};
1321
1322static struct clk_regmap g12a_cpu_clk_trace = {
1323	.data = &(struct clk_regmap_gate_data){
1324		.offset = HHI_SYS_CPU_CLK_CNTL1,
1325		.bit_idx = 23,
1326	},
1327	.hw.init = &(struct clk_init_data) {
1328		.name = "cpu_clk_trace",
1329		.ops = &clk_regmap_gate_ro_ops,
1330		.parent_hws = (const struct clk_hw *[]) {
1331			&g12a_cpu_clk_trace_div.hw
1332		},
1333		.num_parents = 1,
1334		/*
1335		 * This clock is set by the ROM monitor code,
1336		 * Linux should not change it at runtime
1337		 */
1338	},
1339};
1340
1341static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1342	.mult = 1,
1343	.div = 2,
1344	.hw.init = &(struct clk_init_data){
1345		.name = "cpub_clk_div2",
1346		.ops = &clk_fixed_factor_ops,
1347		.parent_hws = (const struct clk_hw *[]) {
1348			&g12b_cpub_clk.hw
1349		},
1350		.num_parents = 1,
1351	},
1352};
1353
1354static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1355	.mult = 1,
1356	.div = 3,
1357	.hw.init = &(struct clk_init_data){
1358		.name = "cpub_clk_div3",
1359		.ops = &clk_fixed_factor_ops,
1360		.parent_hws = (const struct clk_hw *[]) {
1361			&g12b_cpub_clk.hw
1362		},
1363		.num_parents = 1,
1364	},
1365};
1366
1367static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1368	.mult = 1,
1369	.div = 4,
1370	.hw.init = &(struct clk_init_data){
1371		.name = "cpub_clk_div4",
1372		.ops = &clk_fixed_factor_ops,
1373		.parent_hws = (const struct clk_hw *[]) {
1374			&g12b_cpub_clk.hw
1375		},
1376		.num_parents = 1,
1377	},
1378};
1379
1380static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1381	.mult = 1,
1382	.div = 5,
1383	.hw.init = &(struct clk_init_data){
1384		.name = "cpub_clk_div5",
1385		.ops = &clk_fixed_factor_ops,
1386		.parent_hws = (const struct clk_hw *[]) {
1387			&g12b_cpub_clk.hw
1388		},
1389		.num_parents = 1,
1390	},
1391};
1392
1393static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1394	.mult = 1,
1395	.div = 6,
1396	.hw.init = &(struct clk_init_data){
1397		.name = "cpub_clk_div6",
1398		.ops = &clk_fixed_factor_ops,
1399		.parent_hws = (const struct clk_hw *[]) {
1400			&g12b_cpub_clk.hw
1401		},
1402		.num_parents = 1,
1403	},
1404};
1405
1406static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1407	.mult = 1,
1408	.div = 7,
1409	.hw.init = &(struct clk_init_data){
1410		.name = "cpub_clk_div7",
1411		.ops = &clk_fixed_factor_ops,
1412		.parent_hws = (const struct clk_hw *[]) {
1413			&g12b_cpub_clk.hw
1414		},
1415		.num_parents = 1,
1416	},
1417};
1418
1419static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1420	.mult = 1,
1421	.div = 8,
1422	.hw.init = &(struct clk_init_data){
1423		.name = "cpub_clk_div8",
1424		.ops = &clk_fixed_factor_ops,
1425		.parent_hws = (const struct clk_hw *[]) {
1426			&g12b_cpub_clk.hw
1427		},
1428		.num_parents = 1,
1429	},
1430};
1431
1432static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1433static struct clk_regmap g12b_cpub_clk_apb_sel = {
1434	.data = &(struct clk_regmap_mux_data){
1435		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1436		.mask = 7,
1437		.shift = 3,
1438		.table = mux_table_cpub,
1439	},
1440	.hw.init = &(struct clk_init_data){
1441		.name = "cpub_clk_apb_sel",
1442		.ops = &clk_regmap_mux_ro_ops,
1443		.parent_hws = (const struct clk_hw *[]) {
1444			&g12b_cpub_clk_div2.hw,
1445			&g12b_cpub_clk_div3.hw,
1446			&g12b_cpub_clk_div4.hw,
1447			&g12b_cpub_clk_div5.hw,
1448			&g12b_cpub_clk_div6.hw,
1449			&g12b_cpub_clk_div7.hw,
1450			&g12b_cpub_clk_div8.hw
1451		},
1452		.num_parents = 7,
1453	},
1454};
1455
1456static struct clk_regmap g12b_cpub_clk_apb = {
1457	.data = &(struct clk_regmap_gate_data){
1458		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1459		.bit_idx = 16,
1460		.flags = CLK_GATE_SET_TO_DISABLE,
1461	},
1462	.hw.init = &(struct clk_init_data) {
1463		.name = "cpub_clk_apb",
1464		.ops = &clk_regmap_gate_ro_ops,
1465		.parent_hws = (const struct clk_hw *[]) {
1466			&g12b_cpub_clk_apb_sel.hw
1467		},
1468		.num_parents = 1,
1469		/*
1470		 * This clock is set by the ROM monitor code,
1471		 * Linux should not change it at runtime
1472		 */
1473	},
1474};
1475
1476static struct clk_regmap g12b_cpub_clk_atb_sel = {
1477	.data = &(struct clk_regmap_mux_data){
1478		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1479		.mask = 7,
1480		.shift = 6,
1481		.table = mux_table_cpub,
1482	},
1483	.hw.init = &(struct clk_init_data){
1484		.name = "cpub_clk_atb_sel",
1485		.ops = &clk_regmap_mux_ro_ops,
1486		.parent_hws = (const struct clk_hw *[]) {
1487			&g12b_cpub_clk_div2.hw,
1488			&g12b_cpub_clk_div3.hw,
1489			&g12b_cpub_clk_div4.hw,
1490			&g12b_cpub_clk_div5.hw,
1491			&g12b_cpub_clk_div6.hw,
1492			&g12b_cpub_clk_div7.hw,
1493			&g12b_cpub_clk_div8.hw
1494		},
1495		.num_parents = 7,
1496	},
1497};
1498
1499static struct clk_regmap g12b_cpub_clk_atb = {
1500	.data = &(struct clk_regmap_gate_data){
1501		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1502		.bit_idx = 17,
1503		.flags = CLK_GATE_SET_TO_DISABLE,
1504	},
1505	.hw.init = &(struct clk_init_data) {
1506		.name = "cpub_clk_atb",
1507		.ops = &clk_regmap_gate_ro_ops,
1508		.parent_hws = (const struct clk_hw *[]) {
1509			&g12b_cpub_clk_atb_sel.hw
1510		},
1511		.num_parents = 1,
1512		/*
1513		 * This clock is set by the ROM monitor code,
1514		 * Linux should not change it at runtime
1515		 */
1516	},
1517};
1518
1519static struct clk_regmap g12b_cpub_clk_axi_sel = {
1520	.data = &(struct clk_regmap_mux_data){
1521		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1522		.mask = 7,
1523		.shift = 9,
1524		.table = mux_table_cpub,
1525	},
1526	.hw.init = &(struct clk_init_data){
1527		.name = "cpub_clk_axi_sel",
1528		.ops = &clk_regmap_mux_ro_ops,
1529		.parent_hws = (const struct clk_hw *[]) {
1530			&g12b_cpub_clk_div2.hw,
1531			&g12b_cpub_clk_div3.hw,
1532			&g12b_cpub_clk_div4.hw,
1533			&g12b_cpub_clk_div5.hw,
1534			&g12b_cpub_clk_div6.hw,
1535			&g12b_cpub_clk_div7.hw,
1536			&g12b_cpub_clk_div8.hw
1537		},
1538		.num_parents = 7,
1539	},
1540};
1541
1542static struct clk_regmap g12b_cpub_clk_axi = {
1543	.data = &(struct clk_regmap_gate_data){
1544		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1545		.bit_idx = 18,
1546		.flags = CLK_GATE_SET_TO_DISABLE,
1547	},
1548	.hw.init = &(struct clk_init_data) {
1549		.name = "cpub_clk_axi",
1550		.ops = &clk_regmap_gate_ro_ops,
1551		.parent_hws = (const struct clk_hw *[]) {
1552			&g12b_cpub_clk_axi_sel.hw
1553		},
1554		.num_parents = 1,
1555		/*
1556		 * This clock is set by the ROM monitor code,
1557		 * Linux should not change it at runtime
1558		 */
1559	},
1560};
1561
1562static struct clk_regmap g12b_cpub_clk_trace_sel = {
1563	.data = &(struct clk_regmap_mux_data){
1564		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1565		.mask = 7,
1566		.shift = 20,
1567		.table = mux_table_cpub,
1568	},
1569	.hw.init = &(struct clk_init_data){
1570		.name = "cpub_clk_trace_sel",
1571		.ops = &clk_regmap_mux_ro_ops,
1572		.parent_hws = (const struct clk_hw *[]) {
1573			&g12b_cpub_clk_div2.hw,
1574			&g12b_cpub_clk_div3.hw,
1575			&g12b_cpub_clk_div4.hw,
1576			&g12b_cpub_clk_div5.hw,
1577			&g12b_cpub_clk_div6.hw,
1578			&g12b_cpub_clk_div7.hw,
1579			&g12b_cpub_clk_div8.hw
1580		},
1581		.num_parents = 7,
1582	},
1583};
1584
1585static struct clk_regmap g12b_cpub_clk_trace = {
1586	.data = &(struct clk_regmap_gate_data){
1587		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1588		.bit_idx = 23,
1589		.flags = CLK_GATE_SET_TO_DISABLE,
1590	},
1591	.hw.init = &(struct clk_init_data) {
1592		.name = "cpub_clk_trace",
1593		.ops = &clk_regmap_gate_ro_ops,
1594		.parent_hws = (const struct clk_hw *[]) {
1595			&g12b_cpub_clk_trace_sel.hw
1596		},
1597		.num_parents = 1,
1598		/*
1599		 * This clock is set by the ROM monitor code,
1600		 * Linux should not change it at runtime
1601		 */
1602	},
1603};
1604
1605static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1606	.min = 125,
1607	.max = 255,
1608};
1609
1610/*
1611 * Internal gp0 pll emulation configuration parameters
1612 */
1613static const struct reg_sequence g12a_gp0_init_regs[] = {
1614	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0x00000000 },
1615	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0x00000000 },
1616	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x48681c00 },
1617	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0x33771290 },
1618	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x39272000 },
1619	{ .reg = HHI_GP0_PLL_CNTL6,	.def = 0x56540000 },
1620};
1621
1622static struct clk_regmap g12a_gp0_pll_dco = {
1623	.data = &(struct meson_clk_pll_data){
1624		.en = {
1625			.reg_off = HHI_GP0_PLL_CNTL0,
1626			.shift   = 28,
1627			.width   = 1,
1628		},
1629		.m = {
1630			.reg_off = HHI_GP0_PLL_CNTL0,
1631			.shift   = 0,
1632			.width   = 8,
1633		},
1634		.n = {
1635			.reg_off = HHI_GP0_PLL_CNTL0,
1636			.shift   = 10,
1637			.width   = 5,
1638		},
1639		.frac = {
1640			.reg_off = HHI_GP0_PLL_CNTL1,
1641			.shift   = 0,
1642			.width   = 17,
1643		},
1644		.l = {
1645			.reg_off = HHI_GP0_PLL_CNTL0,
1646			.shift   = 31,
1647			.width   = 1,
1648		},
1649		.rst = {
1650			.reg_off = HHI_GP0_PLL_CNTL0,
1651			.shift   = 29,
1652			.width   = 1,
1653		},
1654		.range = &g12a_gp0_pll_mult_range,
1655		.init_regs = g12a_gp0_init_regs,
1656		.init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1657	},
1658	.hw.init = &(struct clk_init_data){
1659		.name = "gp0_pll_dco",
1660		.ops = &meson_clk_pll_ops,
1661		.parent_data = &(const struct clk_parent_data) {
1662			.fw_name = "xtal",
1663		},
1664		.num_parents = 1,
1665	},
1666};
1667
1668static struct clk_regmap g12a_gp0_pll = {
1669	.data = &(struct clk_regmap_div_data){
1670		.offset = HHI_GP0_PLL_CNTL0,
1671		.shift = 16,
1672		.width = 3,
1673		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1674			  CLK_DIVIDER_ROUND_CLOSEST),
1675	},
1676	.hw.init = &(struct clk_init_data){
1677		.name = "gp0_pll",
1678		.ops = &clk_regmap_divider_ops,
1679		.parent_hws = (const struct clk_hw *[]) {
1680			&g12a_gp0_pll_dco.hw
1681		},
1682		.num_parents = 1,
1683		.flags = CLK_SET_RATE_PARENT,
1684	},
1685};
1686
1687static struct clk_regmap sm1_gp1_pll_dco = {
1688	.data = &(struct meson_clk_pll_data){
1689		.en = {
1690			.reg_off = HHI_GP1_PLL_CNTL0,
1691			.shift   = 28,
1692			.width   = 1,
1693		},
1694		.m = {
1695			.reg_off = HHI_GP1_PLL_CNTL0,
1696			.shift   = 0,
1697			.width   = 8,
1698		},
1699		.n = {
1700			.reg_off = HHI_GP1_PLL_CNTL0,
1701			.shift   = 10,
1702			.width   = 5,
1703		},
1704		.frac = {
1705			.reg_off = HHI_GP1_PLL_CNTL1,
1706			.shift   = 0,
1707			.width   = 17,
1708		},
1709		.l = {
1710			.reg_off = HHI_GP1_PLL_CNTL0,
1711			.shift   = 31,
1712			.width   = 1,
1713		},
1714		.rst = {
1715			.reg_off = HHI_GP1_PLL_CNTL0,
1716			.shift   = 29,
1717			.width   = 1,
1718		},
1719	},
1720	.hw.init = &(struct clk_init_data){
1721		.name = "gp1_pll_dco",
1722		.ops = &meson_clk_pll_ro_ops,
1723		.parent_data = &(const struct clk_parent_data) {
1724			.fw_name = "xtal",
1725		},
1726		.num_parents = 1,
1727		/* This clock feeds the DSU, avoid disabling it */
1728		.flags = CLK_IS_CRITICAL,
1729	},
1730};
1731
1732static struct clk_regmap sm1_gp1_pll = {
1733	.data = &(struct clk_regmap_div_data){
1734		.offset = HHI_GP1_PLL_CNTL0,
1735		.shift = 16,
1736		.width = 3,
1737		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1738			  CLK_DIVIDER_ROUND_CLOSEST),
1739	},
1740	.hw.init = &(struct clk_init_data){
1741		.name = "gp1_pll",
1742		.ops = &clk_regmap_divider_ro_ops,
1743		.parent_hws = (const struct clk_hw *[]) {
1744			&sm1_gp1_pll_dco.hw
1745		},
1746		.num_parents = 1,
1747	},
1748};
1749
1750/*
1751 * Internal hifi pll emulation configuration parameters
1752 */
1753static const struct reg_sequence g12a_hifi_init_regs[] = {
1754	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0x00000000 },
1755	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0x00000000 },
1756	{ .reg = HHI_HIFI_PLL_CNTL3,	.def = 0x6a285c00 },
1757	{ .reg = HHI_HIFI_PLL_CNTL4,	.def = 0x65771290 },
1758	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x39272000 },
1759	{ .reg = HHI_HIFI_PLL_CNTL6,	.def = 0x56540000 },
1760};
1761
1762static struct clk_regmap g12a_hifi_pll_dco = {
1763	.data = &(struct meson_clk_pll_data){
1764		.en = {
1765			.reg_off = HHI_HIFI_PLL_CNTL0,
1766			.shift   = 28,
1767			.width   = 1,
1768		},
1769		.m = {
1770			.reg_off = HHI_HIFI_PLL_CNTL0,
1771			.shift   = 0,
1772			.width   = 8,
1773		},
1774		.n = {
1775			.reg_off = HHI_HIFI_PLL_CNTL0,
1776			.shift   = 10,
1777			.width   = 5,
1778		},
1779		.frac = {
1780			.reg_off = HHI_HIFI_PLL_CNTL1,
1781			.shift   = 0,
1782			.width   = 17,
1783		},
1784		.l = {
1785			.reg_off = HHI_HIFI_PLL_CNTL0,
1786			.shift   = 31,
1787			.width   = 1,
1788		},
1789		.rst = {
1790			.reg_off = HHI_HIFI_PLL_CNTL0,
1791			.shift   = 29,
1792			.width   = 1,
1793		},
1794		.range = &g12a_gp0_pll_mult_range,
1795		.init_regs = g12a_hifi_init_regs,
1796		.init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1797		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
1798	},
1799	.hw.init = &(struct clk_init_data){
1800		.name = "hifi_pll_dco",
1801		.ops = &meson_clk_pll_ops,
1802		.parent_data = &(const struct clk_parent_data) {
1803			.fw_name = "xtal",
1804		},
1805		.num_parents = 1,
1806	},
1807};
1808
1809static struct clk_regmap g12a_hifi_pll = {
1810	.data = &(struct clk_regmap_div_data){
1811		.offset = HHI_HIFI_PLL_CNTL0,
1812		.shift = 16,
1813		.width = 2,
1814		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1815			  CLK_DIVIDER_ROUND_CLOSEST),
1816	},
1817	.hw.init = &(struct clk_init_data){
1818		.name = "hifi_pll",
1819		.ops = &clk_regmap_divider_ops,
1820		.parent_hws = (const struct clk_hw *[]) {
1821			&g12a_hifi_pll_dco.hw
1822		},
1823		.num_parents = 1,
1824		.flags = CLK_SET_RATE_PARENT,
1825	},
1826};
1827
1828/*
1829 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1830 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1831 * a strict register sequence to enable the PLL.
1832 */
1833static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1834	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x20090496 },
1835	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x30090496 },
1836	{ .reg = HHI_PCIE_PLL_CNTL1,	.def = 0x00000000 },
1837	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001100 },
1838	{ .reg = HHI_PCIE_PLL_CNTL3,	.def = 0x10058e00 },
1839	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x000100c0 },
1840	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000048 },
1841	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000068, .delay_us = 20 },
1842	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x008100c0, .delay_us = 10 },
1843	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x34090496 },
1844	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x14090496, .delay_us = 10 },
1845	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001000 },
1846};
1847
1848/* Keep a single entry table for recalc/round_rate() ops */
1849static const struct pll_params_table g12a_pcie_pll_table[] = {
1850	PLL_PARAMS(150, 1),
1851	{0, 0},
1852};
1853
1854static struct clk_regmap g12a_pcie_pll_dco = {
1855	.data = &(struct meson_clk_pll_data){
1856		.en = {
1857			.reg_off = HHI_PCIE_PLL_CNTL0,
1858			.shift   = 28,
1859			.width   = 1,
1860		},
1861		.m = {
1862			.reg_off = HHI_PCIE_PLL_CNTL0,
1863			.shift   = 0,
1864			.width   = 8,
1865		},
1866		.n = {
1867			.reg_off = HHI_PCIE_PLL_CNTL0,
1868			.shift   = 10,
1869			.width   = 5,
1870		},
1871		.frac = {
1872			.reg_off = HHI_PCIE_PLL_CNTL1,
1873			.shift   = 0,
1874			.width   = 12,
1875		},
1876		.l = {
1877			.reg_off = HHI_PCIE_PLL_CNTL0,
1878			.shift   = 31,
1879			.width   = 1,
1880		},
1881		.rst = {
1882			.reg_off = HHI_PCIE_PLL_CNTL0,
1883			.shift   = 29,
1884			.width   = 1,
1885		},
1886		.table = g12a_pcie_pll_table,
1887		.init_regs = g12a_pcie_pll_init_regs,
1888		.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1889	},
1890	.hw.init = &(struct clk_init_data){
1891		.name = "pcie_pll_dco",
1892		.ops = &meson_clk_pcie_pll_ops,
1893		.parent_data = &(const struct clk_parent_data) {
1894			.fw_name = "xtal",
1895		},
1896		.num_parents = 1,
1897	},
1898};
1899
1900static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1901	.mult = 1,
1902	.div = 2,
1903	.hw.init = &(struct clk_init_data){
1904		.name = "pcie_pll_dco_div2",
1905		.ops = &clk_fixed_factor_ops,
1906		.parent_hws = (const struct clk_hw *[]) {
1907			&g12a_pcie_pll_dco.hw
1908		},
1909		.num_parents = 1,
1910		.flags = CLK_SET_RATE_PARENT,
1911	},
1912};
1913
1914static struct clk_regmap g12a_pcie_pll_od = {
1915	.data = &(struct clk_regmap_div_data){
1916		.offset = HHI_PCIE_PLL_CNTL0,
1917		.shift = 16,
1918		.width = 5,
1919		.flags = CLK_DIVIDER_ROUND_CLOSEST |
1920			 CLK_DIVIDER_ONE_BASED |
1921			 CLK_DIVIDER_ALLOW_ZERO,
1922	},
1923	.hw.init = &(struct clk_init_data){
1924		.name = "pcie_pll_od",
1925		.ops = &clk_regmap_divider_ops,
1926		.parent_hws = (const struct clk_hw *[]) {
1927			&g12a_pcie_pll_dco_div2.hw
1928		},
1929		.num_parents = 1,
1930		.flags = CLK_SET_RATE_PARENT,
1931	},
1932};
1933
1934static struct clk_fixed_factor g12a_pcie_pll = {
1935	.mult = 1,
1936	.div = 2,
1937	.hw.init = &(struct clk_init_data){
1938		.name = "pcie_pll_pll",
1939		.ops = &clk_fixed_factor_ops,
1940		.parent_hws = (const struct clk_hw *[]) {
1941			&g12a_pcie_pll_od.hw
1942		},
1943		.num_parents = 1,
1944		.flags = CLK_SET_RATE_PARENT,
1945	},
1946};
1947
1948static struct clk_regmap g12a_hdmi_pll_dco = {
1949	.data = &(struct meson_clk_pll_data){
1950		.en = {
1951			.reg_off = HHI_HDMI_PLL_CNTL0,
1952			.shift   = 28,
1953			.width   = 1,
1954		},
1955		.m = {
1956			.reg_off = HHI_HDMI_PLL_CNTL0,
1957			.shift   = 0,
1958			.width   = 8,
1959		},
1960		.n = {
1961			.reg_off = HHI_HDMI_PLL_CNTL0,
1962			.shift   = 10,
1963			.width   = 5,
1964		},
1965		.frac = {
1966			.reg_off = HHI_HDMI_PLL_CNTL1,
1967			.shift   = 0,
1968			.width   = 16,
1969		},
1970		.l = {
1971			.reg_off = HHI_HDMI_PLL_CNTL0,
1972			.shift   = 30,
1973			.width   = 1,
1974		},
1975		.rst = {
1976			.reg_off = HHI_HDMI_PLL_CNTL0,
1977			.shift   = 29,
1978			.width   = 1,
1979		},
1980	},
1981	.hw.init = &(struct clk_init_data){
1982		.name = "hdmi_pll_dco",
1983		.ops = &meson_clk_pll_ro_ops,
1984		.parent_data = &(const struct clk_parent_data) {
1985			.fw_name = "xtal",
1986		},
1987		.num_parents = 1,
1988		/*
1989		 * Display directly handle hdmi pll registers ATM, we need
1990		 * NOCACHE to keep our view of the clock as accurate as possible
1991		 */
1992		.flags = CLK_GET_RATE_NOCACHE,
1993	},
1994};
1995
1996static struct clk_regmap g12a_hdmi_pll_od = {
1997	.data = &(struct clk_regmap_div_data){
1998		.offset = HHI_HDMI_PLL_CNTL0,
1999		.shift = 16,
2000		.width = 2,
2001		.flags = CLK_DIVIDER_POWER_OF_TWO,
2002	},
2003	.hw.init = &(struct clk_init_data){
2004		.name = "hdmi_pll_od",
2005		.ops = &clk_regmap_divider_ro_ops,
2006		.parent_hws = (const struct clk_hw *[]) {
2007			&g12a_hdmi_pll_dco.hw
2008		},
2009		.num_parents = 1,
2010		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2011	},
2012};
2013
2014static struct clk_regmap g12a_hdmi_pll_od2 = {
2015	.data = &(struct clk_regmap_div_data){
2016		.offset = HHI_HDMI_PLL_CNTL0,
2017		.shift = 18,
2018		.width = 2,
2019		.flags = CLK_DIVIDER_POWER_OF_TWO,
2020	},
2021	.hw.init = &(struct clk_init_data){
2022		.name = "hdmi_pll_od2",
2023		.ops = &clk_regmap_divider_ro_ops,
2024		.parent_hws = (const struct clk_hw *[]) {
2025			&g12a_hdmi_pll_od.hw
2026		},
2027		.num_parents = 1,
2028		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2029	},
2030};
2031
2032static struct clk_regmap g12a_hdmi_pll = {
2033	.data = &(struct clk_regmap_div_data){
2034		.offset = HHI_HDMI_PLL_CNTL0,
2035		.shift = 20,
2036		.width = 2,
2037		.flags = CLK_DIVIDER_POWER_OF_TWO,
2038	},
2039	.hw.init = &(struct clk_init_data){
2040		.name = "hdmi_pll",
2041		.ops = &clk_regmap_divider_ro_ops,
2042		.parent_hws = (const struct clk_hw *[]) {
2043			&g12a_hdmi_pll_od2.hw
2044		},
2045		.num_parents = 1,
2046		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2047	},
2048};
2049
2050static struct clk_fixed_factor g12a_fclk_div4_div = {
2051	.mult = 1,
2052	.div = 4,
2053	.hw.init = &(struct clk_init_data){
2054		.name = "fclk_div4_div",
2055		.ops = &clk_fixed_factor_ops,
2056		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2057		.num_parents = 1,
2058	},
2059};
2060
2061static struct clk_regmap g12a_fclk_div4 = {
2062	.data = &(struct clk_regmap_gate_data){
2063		.offset = HHI_FIX_PLL_CNTL1,
2064		.bit_idx = 21,
2065	},
2066	.hw.init = &(struct clk_init_data){
2067		.name = "fclk_div4",
2068		.ops = &clk_regmap_gate_ops,
2069		.parent_hws = (const struct clk_hw *[]) {
2070			&g12a_fclk_div4_div.hw
2071		},
2072		.num_parents = 1,
2073	},
2074};
2075
2076static struct clk_fixed_factor g12a_fclk_div5_div = {
2077	.mult = 1,
2078	.div = 5,
2079	.hw.init = &(struct clk_init_data){
2080		.name = "fclk_div5_div",
2081		.ops = &clk_fixed_factor_ops,
2082		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2083		.num_parents = 1,
2084	},
2085};
2086
2087static struct clk_regmap g12a_fclk_div5 = {
2088	.data = &(struct clk_regmap_gate_data){
2089		.offset = HHI_FIX_PLL_CNTL1,
2090		.bit_idx = 22,
2091	},
2092	.hw.init = &(struct clk_init_data){
2093		.name = "fclk_div5",
2094		.ops = &clk_regmap_gate_ops,
2095		.parent_hws = (const struct clk_hw *[]) {
2096			&g12a_fclk_div5_div.hw
2097		},
2098		.num_parents = 1,
2099	},
2100};
2101
2102static struct clk_fixed_factor g12a_fclk_div7_div = {
2103	.mult = 1,
2104	.div = 7,
2105	.hw.init = &(struct clk_init_data){
2106		.name = "fclk_div7_div",
2107		.ops = &clk_fixed_factor_ops,
2108		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2109		.num_parents = 1,
2110	},
2111};
2112
2113static struct clk_regmap g12a_fclk_div7 = {
2114	.data = &(struct clk_regmap_gate_data){
2115		.offset = HHI_FIX_PLL_CNTL1,
2116		.bit_idx = 23,
2117	},
2118	.hw.init = &(struct clk_init_data){
2119		.name = "fclk_div7",
2120		.ops = &clk_regmap_gate_ops,
2121		.parent_hws = (const struct clk_hw *[]) {
2122			&g12a_fclk_div7_div.hw
2123		},
2124		.num_parents = 1,
2125	},
2126};
2127
2128static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2129	.mult = 1,
2130	.div = 5,
2131	.hw.init = &(struct clk_init_data){
2132		.name = "fclk_div2p5_div",
2133		.ops = &clk_fixed_factor_ops,
2134		.parent_hws = (const struct clk_hw *[]) {
2135			&g12a_fixed_pll_dco.hw
2136		},
2137		.num_parents = 1,
2138	},
2139};
2140
2141static struct clk_regmap g12a_fclk_div2p5 = {
2142	.data = &(struct clk_regmap_gate_data){
2143		.offset = HHI_FIX_PLL_CNTL1,
2144		.bit_idx = 25,
2145	},
2146	.hw.init = &(struct clk_init_data){
2147		.name = "fclk_div2p5",
2148		.ops = &clk_regmap_gate_ops,
2149		.parent_hws = (const struct clk_hw *[]) {
2150			&g12a_fclk_div2p5_div.hw
2151		},
2152		.num_parents = 1,
2153	},
2154};
2155
2156static struct clk_fixed_factor g12a_mpll_50m_div = {
2157	.mult = 1,
2158	.div = 80,
2159	.hw.init = &(struct clk_init_data){
2160		.name = "mpll_50m_div",
2161		.ops = &clk_fixed_factor_ops,
2162		.parent_hws = (const struct clk_hw *[]) {
2163			&g12a_fixed_pll_dco.hw
2164		},
2165		.num_parents = 1,
2166	},
2167};
2168
2169static struct clk_regmap g12a_mpll_50m = {
2170	.data = &(struct clk_regmap_mux_data){
2171		.offset = HHI_FIX_PLL_CNTL3,
2172		.mask = 0x1,
2173		.shift = 5,
2174	},
2175	.hw.init = &(struct clk_init_data){
2176		.name = "mpll_50m",
2177		.ops = &clk_regmap_mux_ro_ops,
2178		.parent_data = (const struct clk_parent_data []) {
2179			{ .fw_name = "xtal", },
2180			{ .hw = &g12a_mpll_50m_div.hw },
2181		},
2182		.num_parents = 2,
2183	},
2184};
2185
2186static struct clk_fixed_factor g12a_mpll_prediv = {
2187	.mult = 1,
2188	.div = 2,
2189	.hw.init = &(struct clk_init_data){
2190		.name = "mpll_prediv",
2191		.ops = &clk_fixed_factor_ops,
2192		.parent_hws = (const struct clk_hw *[]) {
2193			&g12a_fixed_pll_dco.hw
2194		},
2195		.num_parents = 1,
2196	},
2197};
2198
2199static const struct reg_sequence g12a_mpll0_init_regs[] = {
2200	{ .reg = HHI_MPLL_CNTL2,	.def = 0x40000033 },
2201};
2202
2203static struct clk_regmap g12a_mpll0_div = {
2204	.data = &(struct meson_clk_mpll_data){
2205		.sdm = {
2206			.reg_off = HHI_MPLL_CNTL1,
2207			.shift   = 0,
2208			.width   = 14,
2209		},
2210		.sdm_en = {
2211			.reg_off = HHI_MPLL_CNTL1,
2212			.shift   = 30,
2213			.width	 = 1,
2214		},
2215		.n2 = {
2216			.reg_off = HHI_MPLL_CNTL1,
2217			.shift   = 20,
2218			.width   = 9,
2219		},
2220		.ssen = {
2221			.reg_off = HHI_MPLL_CNTL1,
2222			.shift   = 29,
2223			.width	 = 1,
2224		},
2225		.lock = &meson_clk_lock,
2226		.init_regs = g12a_mpll0_init_regs,
2227		.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2228	},
2229	.hw.init = &(struct clk_init_data){
2230		.name = "mpll0_div",
2231		.ops = &meson_clk_mpll_ops,
2232		.parent_hws = (const struct clk_hw *[]) {
2233			&g12a_mpll_prediv.hw
2234		},
2235		.num_parents = 1,
2236	},
2237};
2238
2239static struct clk_regmap g12a_mpll0 = {
2240	.data = &(struct clk_regmap_gate_data){
2241		.offset = HHI_MPLL_CNTL1,
2242		.bit_idx = 31,
2243	},
2244	.hw.init = &(struct clk_init_data){
2245		.name = "mpll0",
2246		.ops = &clk_regmap_gate_ops,
2247		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2248		.num_parents = 1,
2249		.flags = CLK_SET_RATE_PARENT,
2250	},
2251};
2252
2253static const struct reg_sequence g12a_mpll1_init_regs[] = {
2254	{ .reg = HHI_MPLL_CNTL4,	.def = 0x40000033 },
2255};
2256
2257static struct clk_regmap g12a_mpll1_div = {
2258	.data = &(struct meson_clk_mpll_data){
2259		.sdm = {
2260			.reg_off = HHI_MPLL_CNTL3,
2261			.shift   = 0,
2262			.width   = 14,
2263		},
2264		.sdm_en = {
2265			.reg_off = HHI_MPLL_CNTL3,
2266			.shift   = 30,
2267			.width	 = 1,
2268		},
2269		.n2 = {
2270			.reg_off = HHI_MPLL_CNTL3,
2271			.shift   = 20,
2272			.width   = 9,
2273		},
2274		.ssen = {
2275			.reg_off = HHI_MPLL_CNTL3,
2276			.shift   = 29,
2277			.width	 = 1,
2278		},
2279		.lock = &meson_clk_lock,
2280		.init_regs = g12a_mpll1_init_regs,
2281		.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2282	},
2283	.hw.init = &(struct clk_init_data){
2284		.name = "mpll1_div",
2285		.ops = &meson_clk_mpll_ops,
2286		.parent_hws = (const struct clk_hw *[]) {
2287			&g12a_mpll_prediv.hw
2288		},
2289		.num_parents = 1,
2290	},
2291};
2292
2293static struct clk_regmap g12a_mpll1 = {
2294	.data = &(struct clk_regmap_gate_data){
2295		.offset = HHI_MPLL_CNTL3,
2296		.bit_idx = 31,
2297	},
2298	.hw.init = &(struct clk_init_data){
2299		.name = "mpll1",
2300		.ops = &clk_regmap_gate_ops,
2301		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2302		.num_parents = 1,
2303		.flags = CLK_SET_RATE_PARENT,
2304	},
2305};
2306
2307static const struct reg_sequence g12a_mpll2_init_regs[] = {
2308	{ .reg = HHI_MPLL_CNTL6,	.def = 0x40000033 },
2309};
2310
2311static struct clk_regmap g12a_mpll2_div = {
2312	.data = &(struct meson_clk_mpll_data){
2313		.sdm = {
2314			.reg_off = HHI_MPLL_CNTL5,
2315			.shift   = 0,
2316			.width   = 14,
2317		},
2318		.sdm_en = {
2319			.reg_off = HHI_MPLL_CNTL5,
2320			.shift   = 30,
2321			.width	 = 1,
2322		},
2323		.n2 = {
2324			.reg_off = HHI_MPLL_CNTL5,
2325			.shift   = 20,
2326			.width   = 9,
2327		},
2328		.ssen = {
2329			.reg_off = HHI_MPLL_CNTL5,
2330			.shift   = 29,
2331			.width	 = 1,
2332		},
2333		.lock = &meson_clk_lock,
2334		.init_regs = g12a_mpll2_init_regs,
2335		.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2336	},
2337	.hw.init = &(struct clk_init_data){
2338		.name = "mpll2_div",
2339		.ops = &meson_clk_mpll_ops,
2340		.parent_hws = (const struct clk_hw *[]) {
2341			&g12a_mpll_prediv.hw
2342		},
2343		.num_parents = 1,
2344	},
2345};
2346
2347static struct clk_regmap g12a_mpll2 = {
2348	.data = &(struct clk_regmap_gate_data){
2349		.offset = HHI_MPLL_CNTL5,
2350		.bit_idx = 31,
2351	},
2352	.hw.init = &(struct clk_init_data){
2353		.name = "mpll2",
2354		.ops = &clk_regmap_gate_ops,
2355		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2356		.num_parents = 1,
2357		.flags = CLK_SET_RATE_PARENT,
2358	},
2359};
2360
2361static const struct reg_sequence g12a_mpll3_init_regs[] = {
2362	{ .reg = HHI_MPLL_CNTL8,	.def = 0x40000033 },
2363};
2364
2365static struct clk_regmap g12a_mpll3_div = {
2366	.data = &(struct meson_clk_mpll_data){
2367		.sdm = {
2368			.reg_off = HHI_MPLL_CNTL7,
2369			.shift   = 0,
2370			.width   = 14,
2371		},
2372		.sdm_en = {
2373			.reg_off = HHI_MPLL_CNTL7,
2374			.shift   = 30,
2375			.width	 = 1,
2376		},
2377		.n2 = {
2378			.reg_off = HHI_MPLL_CNTL7,
2379			.shift   = 20,
2380			.width   = 9,
2381		},
2382		.ssen = {
2383			.reg_off = HHI_MPLL_CNTL7,
2384			.shift   = 29,
2385			.width	 = 1,
2386		},
2387		.lock = &meson_clk_lock,
2388		.init_regs = g12a_mpll3_init_regs,
2389		.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2390	},
2391	.hw.init = &(struct clk_init_data){
2392		.name = "mpll3_div",
2393		.ops = &meson_clk_mpll_ops,
2394		.parent_hws = (const struct clk_hw *[]) {
2395			&g12a_mpll_prediv.hw
2396		},
2397		.num_parents = 1,
2398	},
2399};
2400
2401static struct clk_regmap g12a_mpll3 = {
2402	.data = &(struct clk_regmap_gate_data){
2403		.offset = HHI_MPLL_CNTL7,
2404		.bit_idx = 31,
2405	},
2406	.hw.init = &(struct clk_init_data){
2407		.name = "mpll3",
2408		.ops = &clk_regmap_gate_ops,
2409		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2410		.num_parents = 1,
2411		.flags = CLK_SET_RATE_PARENT,
2412	},
2413};
2414
2415static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };
2416static const struct clk_parent_data clk81_parent_data[] = {
2417	{ .fw_name = "xtal", },
2418	{ .hw = &g12a_fclk_div7.hw },
2419	{ .hw = &g12a_mpll1.hw },
2420	{ .hw = &g12a_mpll2.hw },
2421	{ .hw = &g12a_fclk_div4.hw },
2422	{ .hw = &g12a_fclk_div3.hw },
2423	{ .hw = &g12a_fclk_div5.hw },
2424};
2425
2426static struct clk_regmap g12a_mpeg_clk_sel = {
2427	.data = &(struct clk_regmap_mux_data){
2428		.offset = HHI_MPEG_CLK_CNTL,
2429		.mask = 0x7,
2430		.shift = 12,
2431		.table = mux_table_clk81,
2432	},
2433	.hw.init = &(struct clk_init_data){
2434		.name = "mpeg_clk_sel",
2435		.ops = &clk_regmap_mux_ro_ops,
2436		.parent_data = clk81_parent_data,
2437		.num_parents = ARRAY_SIZE(clk81_parent_data),
2438	},
2439};
2440
2441static struct clk_regmap g12a_mpeg_clk_div = {
2442	.data = &(struct clk_regmap_div_data){
2443		.offset = HHI_MPEG_CLK_CNTL,
2444		.shift = 0,
2445		.width = 7,
2446	},
2447	.hw.init = &(struct clk_init_data){
2448		.name = "mpeg_clk_div",
2449		.ops = &clk_regmap_divider_ops,
2450		.parent_hws = (const struct clk_hw *[]) {
2451			&g12a_mpeg_clk_sel.hw
2452		},
2453		.num_parents = 1,
2454		.flags = CLK_SET_RATE_PARENT,
2455	},
2456};
2457
2458static struct clk_regmap g12a_clk81 = {
2459	.data = &(struct clk_regmap_gate_data){
2460		.offset = HHI_MPEG_CLK_CNTL,
2461		.bit_idx = 7,
2462	},
2463	.hw.init = &(struct clk_init_data){
2464		.name = "clk81",
2465		.ops = &clk_regmap_gate_ops,
2466		.parent_hws = (const struct clk_hw *[]) {
2467			&g12a_mpeg_clk_div.hw
2468		},
2469		.num_parents = 1,
2470		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2471	},
2472};
2473
2474static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2475	{ .fw_name = "xtal", },
2476	{ .hw = &g12a_fclk_div2.hw },
2477	{ .hw = &g12a_fclk_div3.hw },
2478	{ .hw = &g12a_fclk_div5.hw },
2479	{ .hw = &g12a_fclk_div7.hw },
2480	/*
2481	 * Following these parent clocks, we should also have had mpll2, mpll3
2482	 * and gp0_pll but these clocks are too precious to be used here. All
2483	 * the necessary rates for MMC and NAND operation can be acheived using
2484	 * g12a_ee_core or fclk_div clocks
2485	 */
2486};
2487
2488/* SDIO clock */
2489static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2490	.data = &(struct clk_regmap_mux_data){
2491		.offset = HHI_SD_EMMC_CLK_CNTL,
2492		.mask = 0x7,
2493		.shift = 9,
2494	},
2495	.hw.init = &(struct clk_init_data) {
2496		.name = "sd_emmc_a_clk0_sel",
2497		.ops = &clk_regmap_mux_ops,
2498		.parent_data = g12a_sd_emmc_clk0_parent_data,
2499		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2500		.flags = CLK_SET_RATE_PARENT,
2501	},
2502};
2503
2504static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2505	.data = &(struct clk_regmap_div_data){
2506		.offset = HHI_SD_EMMC_CLK_CNTL,
2507		.shift = 0,
2508		.width = 7,
2509	},
2510	.hw.init = &(struct clk_init_data) {
2511		.name = "sd_emmc_a_clk0_div",
2512		.ops = &clk_regmap_divider_ops,
2513		.parent_hws = (const struct clk_hw *[]) {
2514			&g12a_sd_emmc_a_clk0_sel.hw
2515		},
2516		.num_parents = 1,
2517		.flags = CLK_SET_RATE_PARENT,
2518	},
2519};
2520
2521static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2522	.data = &(struct clk_regmap_gate_data){
2523		.offset = HHI_SD_EMMC_CLK_CNTL,
2524		.bit_idx = 7,
2525	},
2526	.hw.init = &(struct clk_init_data){
2527		.name = "sd_emmc_a_clk0",
2528		.ops = &clk_regmap_gate_ops,
2529		.parent_hws = (const struct clk_hw *[]) {
2530			&g12a_sd_emmc_a_clk0_div.hw
2531		},
2532		.num_parents = 1,
2533		.flags = CLK_SET_RATE_PARENT,
2534	},
2535};
2536
2537/* SDcard clock */
2538static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2539	.data = &(struct clk_regmap_mux_data){
2540		.offset = HHI_SD_EMMC_CLK_CNTL,
2541		.mask = 0x7,
2542		.shift = 25,
2543	},
2544	.hw.init = &(struct clk_init_data) {
2545		.name = "sd_emmc_b_clk0_sel",
2546		.ops = &clk_regmap_mux_ops,
2547		.parent_data = g12a_sd_emmc_clk0_parent_data,
2548		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2549		.flags = CLK_SET_RATE_PARENT,
2550	},
2551};
2552
2553static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2554	.data = &(struct clk_regmap_div_data){
2555		.offset = HHI_SD_EMMC_CLK_CNTL,
2556		.shift = 16,
2557		.width = 7,
2558	},
2559	.hw.init = &(struct clk_init_data) {
2560		.name = "sd_emmc_b_clk0_div",
2561		.ops = &clk_regmap_divider_ops,
2562		.parent_hws = (const struct clk_hw *[]) {
2563			&g12a_sd_emmc_b_clk0_sel.hw
2564		},
2565		.num_parents = 1,
2566		.flags = CLK_SET_RATE_PARENT,
2567	},
2568};
2569
2570static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2571	.data = &(struct clk_regmap_gate_data){
2572		.offset = HHI_SD_EMMC_CLK_CNTL,
2573		.bit_idx = 23,
2574	},
2575	.hw.init = &(struct clk_init_data){
2576		.name = "sd_emmc_b_clk0",
2577		.ops = &clk_regmap_gate_ops,
2578		.parent_hws = (const struct clk_hw *[]) {
2579			&g12a_sd_emmc_b_clk0_div.hw
2580		},
2581		.num_parents = 1,
2582		.flags = CLK_SET_RATE_PARENT,
2583	},
2584};
2585
2586/* EMMC/NAND clock */
2587static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2588	.data = &(struct clk_regmap_mux_data){
2589		.offset = HHI_NAND_CLK_CNTL,
2590		.mask = 0x7,
2591		.shift = 9,
2592	},
2593	.hw.init = &(struct clk_init_data) {
2594		.name = "sd_emmc_c_clk0_sel",
2595		.ops = &clk_regmap_mux_ops,
2596		.parent_data = g12a_sd_emmc_clk0_parent_data,
2597		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2598		.flags = CLK_SET_RATE_PARENT,
2599	},
2600};
2601
2602static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2603	.data = &(struct clk_regmap_div_data){
2604		.offset = HHI_NAND_CLK_CNTL,
2605		.shift = 0,
2606		.width = 7,
2607	},
2608	.hw.init = &(struct clk_init_data) {
2609		.name = "sd_emmc_c_clk0_div",
2610		.ops = &clk_regmap_divider_ops,
2611		.parent_hws = (const struct clk_hw *[]) {
2612			&g12a_sd_emmc_c_clk0_sel.hw
2613		},
2614		.num_parents = 1,
2615		.flags = CLK_SET_RATE_PARENT,
2616	},
2617};
2618
2619static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2620	.data = &(struct clk_regmap_gate_data){
2621		.offset = HHI_NAND_CLK_CNTL,
2622		.bit_idx = 7,
2623	},
2624	.hw.init = &(struct clk_init_data){
2625		.name = "sd_emmc_c_clk0",
2626		.ops = &clk_regmap_gate_ops,
2627		.parent_hws = (const struct clk_hw *[]) {
2628			&g12a_sd_emmc_c_clk0_div.hw
2629		},
2630		.num_parents = 1,
2631		.flags = CLK_SET_RATE_PARENT,
2632	},
2633};
2634
2635/* Video Clocks */
2636
2637static struct clk_regmap g12a_vid_pll_div = {
2638	.data = &(struct meson_vid_pll_div_data){
2639		.val = {
2640			.reg_off = HHI_VID_PLL_CLK_DIV,
2641			.shift   = 0,
2642			.width   = 15,
2643		},
2644		.sel = {
2645			.reg_off = HHI_VID_PLL_CLK_DIV,
2646			.shift   = 16,
2647			.width   = 2,
2648		},
2649	},
2650	.hw.init = &(struct clk_init_data) {
2651		.name = "vid_pll_div",
2652		.ops = &meson_vid_pll_div_ro_ops,
2653		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2654		.num_parents = 1,
2655		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2656	},
2657};
2658
2659static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2660	&g12a_vid_pll_div.hw,
2661	&g12a_hdmi_pll.hw,
2662};
2663
2664static struct clk_regmap g12a_vid_pll_sel = {
2665	.data = &(struct clk_regmap_mux_data){
2666		.offset = HHI_VID_PLL_CLK_DIV,
2667		.mask = 0x1,
2668		.shift = 18,
2669	},
2670	.hw.init = &(struct clk_init_data){
2671		.name = "vid_pll_sel",
2672		.ops = &clk_regmap_mux_ops,
2673		/*
2674		 * bit 18 selects from 2 possible parents:
2675		 * vid_pll_div or hdmi_pll
2676		 */
2677		.parent_hws = g12a_vid_pll_parent_hws,
2678		.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2679		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2680	},
2681};
2682
2683static struct clk_regmap g12a_vid_pll = {
2684	.data = &(struct clk_regmap_gate_data){
2685		.offset = HHI_VID_PLL_CLK_DIV,
2686		.bit_idx = 19,
2687	},
2688	.hw.init = &(struct clk_init_data) {
2689		.name = "vid_pll",
2690		.ops = &clk_regmap_gate_ops,
2691		.parent_hws = (const struct clk_hw *[]) {
2692			&g12a_vid_pll_sel.hw
2693		},
2694		.num_parents = 1,
2695		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2696	},
2697};
2698
2699/* VPU Clock */
2700
2701static const struct clk_hw *g12a_vpu_parent_hws[] = {
2702	&g12a_fclk_div3.hw,
2703	&g12a_fclk_div4.hw,
2704	&g12a_fclk_div5.hw,
2705	&g12a_fclk_div7.hw,
2706	&g12a_mpll1.hw,
2707	&g12a_vid_pll.hw,
2708	&g12a_hifi_pll.hw,
2709	&g12a_gp0_pll.hw,
2710};
2711
2712static struct clk_regmap g12a_vpu_0_sel = {
2713	.data = &(struct clk_regmap_mux_data){
2714		.offset = HHI_VPU_CLK_CNTL,
2715		.mask = 0x7,
2716		.shift = 9,
2717	},
2718	.hw.init = &(struct clk_init_data){
2719		.name = "vpu_0_sel",
2720		.ops = &clk_regmap_mux_ops,
2721		.parent_hws = g12a_vpu_parent_hws,
2722		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2723		.flags = CLK_SET_RATE_NO_REPARENT,
2724	},
2725};
2726
2727static struct clk_regmap g12a_vpu_0_div = {
2728	.data = &(struct clk_regmap_div_data){
2729		.offset = HHI_VPU_CLK_CNTL,
2730		.shift = 0,
2731		.width = 7,
2732	},
2733	.hw.init = &(struct clk_init_data){
2734		.name = "vpu_0_div",
2735		.ops = &clk_regmap_divider_ops,
2736		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2737		.num_parents = 1,
2738		.flags = CLK_SET_RATE_PARENT,
2739	},
2740};
2741
2742static struct clk_regmap g12a_vpu_0 = {
2743	.data = &(struct clk_regmap_gate_data){
2744		.offset = HHI_VPU_CLK_CNTL,
2745		.bit_idx = 8,
2746	},
2747	.hw.init = &(struct clk_init_data) {
2748		.name = "vpu_0",
2749		.ops = &clk_regmap_gate_ops,
2750		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2751		.num_parents = 1,
2752		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2753	},
2754};
2755
2756static struct clk_regmap g12a_vpu_1_sel = {
2757	.data = &(struct clk_regmap_mux_data){
2758		.offset = HHI_VPU_CLK_CNTL,
2759		.mask = 0x7,
2760		.shift = 25,
2761	},
2762	.hw.init = &(struct clk_init_data){
2763		.name = "vpu_1_sel",
2764		.ops = &clk_regmap_mux_ops,
2765		.parent_hws = g12a_vpu_parent_hws,
2766		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2767		.flags = CLK_SET_RATE_NO_REPARENT,
2768	},
2769};
2770
2771static struct clk_regmap g12a_vpu_1_div = {
2772	.data = &(struct clk_regmap_div_data){
2773		.offset = HHI_VPU_CLK_CNTL,
2774		.shift = 16,
2775		.width = 7,
2776	},
2777	.hw.init = &(struct clk_init_data){
2778		.name = "vpu_1_div",
2779		.ops = &clk_regmap_divider_ops,
2780		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2781		.num_parents = 1,
2782		.flags = CLK_SET_RATE_PARENT,
2783	},
2784};
2785
2786static struct clk_regmap g12a_vpu_1 = {
2787	.data = &(struct clk_regmap_gate_data){
2788		.offset = HHI_VPU_CLK_CNTL,
2789		.bit_idx = 24,
2790	},
2791	.hw.init = &(struct clk_init_data) {
2792		.name = "vpu_1",
2793		.ops = &clk_regmap_gate_ops,
2794		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2795		.num_parents = 1,
2796		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2797	},
2798};
2799
2800static struct clk_regmap g12a_vpu = {
2801	.data = &(struct clk_regmap_mux_data){
2802		.offset = HHI_VPU_CLK_CNTL,
2803		.mask = 1,
2804		.shift = 31,
2805	},
2806	.hw.init = &(struct clk_init_data){
2807		.name = "vpu",
2808		.ops = &clk_regmap_mux_ops,
2809		/*
2810		 * bit 31 selects from 2 possible parents:
2811		 * vpu_0 or vpu_1
2812		 */
2813		.parent_hws = (const struct clk_hw *[]) {
2814			&g12a_vpu_0.hw,
2815			&g12a_vpu_1.hw,
2816		},
2817		.num_parents = 2,
2818		.flags = CLK_SET_RATE_NO_REPARENT,
2819	},
2820};
2821
2822/* VDEC clocks */
2823
2824static const struct clk_hw *g12a_vdec_parent_hws[] = {
2825	&g12a_fclk_div2p5.hw,
2826	&g12a_fclk_div3.hw,
2827	&g12a_fclk_div4.hw,
2828	&g12a_fclk_div5.hw,
2829	&g12a_fclk_div7.hw,
2830	&g12a_hifi_pll.hw,
2831	&g12a_gp0_pll.hw,
2832};
2833
2834static struct clk_regmap g12a_vdec_1_sel = {
2835	.data = &(struct clk_regmap_mux_data){
2836		.offset = HHI_VDEC_CLK_CNTL,
2837		.mask = 0x7,
2838		.shift = 9,
2839		.flags = CLK_MUX_ROUND_CLOSEST,
2840	},
2841	.hw.init = &(struct clk_init_data){
2842		.name = "vdec_1_sel",
2843		.ops = &clk_regmap_mux_ops,
2844		.parent_hws = g12a_vdec_parent_hws,
2845		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2846		.flags = CLK_SET_RATE_PARENT,
2847	},
2848};
2849
2850static struct clk_regmap g12a_vdec_1_div = {
2851	.data = &(struct clk_regmap_div_data){
2852		.offset = HHI_VDEC_CLK_CNTL,
2853		.shift = 0,
2854		.width = 7,
2855		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2856	},
2857	.hw.init = &(struct clk_init_data){
2858		.name = "vdec_1_div",
2859		.ops = &clk_regmap_divider_ops,
2860		.parent_hws = (const struct clk_hw *[]) {
2861			&g12a_vdec_1_sel.hw
2862		},
2863		.num_parents = 1,
2864		.flags = CLK_SET_RATE_PARENT,
2865	},
2866};
2867
2868static struct clk_regmap g12a_vdec_1 = {
2869	.data = &(struct clk_regmap_gate_data){
2870		.offset = HHI_VDEC_CLK_CNTL,
2871		.bit_idx = 8,
2872	},
2873	.hw.init = &(struct clk_init_data) {
2874		.name = "vdec_1",
2875		.ops = &clk_regmap_gate_ops,
2876		.parent_hws = (const struct clk_hw *[]) {
2877			&g12a_vdec_1_div.hw
2878		},
2879		.num_parents = 1,
2880		.flags = CLK_SET_RATE_PARENT,
2881	},
2882};
2883
2884static struct clk_regmap g12a_vdec_hevcf_sel = {
2885	.data = &(struct clk_regmap_mux_data){
2886		.offset = HHI_VDEC2_CLK_CNTL,
2887		.mask = 0x7,
2888		.shift = 9,
2889		.flags = CLK_MUX_ROUND_CLOSEST,
2890	},
2891	.hw.init = &(struct clk_init_data){
2892		.name = "vdec_hevcf_sel",
2893		.ops = &clk_regmap_mux_ops,
2894		.parent_hws = g12a_vdec_parent_hws,
2895		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2896		.flags = CLK_SET_RATE_PARENT,
2897	},
2898};
2899
2900static struct clk_regmap g12a_vdec_hevcf_div = {
2901	.data = &(struct clk_regmap_div_data){
2902		.offset = HHI_VDEC2_CLK_CNTL,
2903		.shift = 0,
2904		.width = 7,
2905		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2906	},
2907	.hw.init = &(struct clk_init_data){
2908		.name = "vdec_hevcf_div",
2909		.ops = &clk_regmap_divider_ops,
2910		.parent_hws = (const struct clk_hw *[]) {
2911			&g12a_vdec_hevcf_sel.hw
2912		},
2913		.num_parents = 1,
2914		.flags = CLK_SET_RATE_PARENT,
2915	},
2916};
2917
2918static struct clk_regmap g12a_vdec_hevcf = {
2919	.data = &(struct clk_regmap_gate_data){
2920		.offset = HHI_VDEC2_CLK_CNTL,
2921		.bit_idx = 8,
2922	},
2923	.hw.init = &(struct clk_init_data) {
2924		.name = "vdec_hevcf",
2925		.ops = &clk_regmap_gate_ops,
2926		.parent_hws = (const struct clk_hw *[]) {
2927			&g12a_vdec_hevcf_div.hw
2928		},
2929		.num_parents = 1,
2930		.flags = CLK_SET_RATE_PARENT,
2931	},
2932};
2933
2934static struct clk_regmap g12a_vdec_hevc_sel = {
2935	.data = &(struct clk_regmap_mux_data){
2936		.offset = HHI_VDEC2_CLK_CNTL,
2937		.mask = 0x7,
2938		.shift = 25,
2939		.flags = CLK_MUX_ROUND_CLOSEST,
2940	},
2941	.hw.init = &(struct clk_init_data){
2942		.name = "vdec_hevc_sel",
2943		.ops = &clk_regmap_mux_ops,
2944		.parent_hws = g12a_vdec_parent_hws,
2945		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2946		.flags = CLK_SET_RATE_PARENT,
2947	},
2948};
2949
2950static struct clk_regmap g12a_vdec_hevc_div = {
2951	.data = &(struct clk_regmap_div_data){
2952		.offset = HHI_VDEC2_CLK_CNTL,
2953		.shift = 16,
2954		.width = 7,
2955		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2956	},
2957	.hw.init = &(struct clk_init_data){
2958		.name = "vdec_hevc_div",
2959		.ops = &clk_regmap_divider_ops,
2960		.parent_hws = (const struct clk_hw *[]) {
2961			&g12a_vdec_hevc_sel.hw
2962		},
2963		.num_parents = 1,
2964		.flags = CLK_SET_RATE_PARENT,
2965	},
2966};
2967
2968static struct clk_regmap g12a_vdec_hevc = {
2969	.data = &(struct clk_regmap_gate_data){
2970		.offset = HHI_VDEC2_CLK_CNTL,
2971		.bit_idx = 24,
2972	},
2973	.hw.init = &(struct clk_init_data) {
2974		.name = "vdec_hevc",
2975		.ops = &clk_regmap_gate_ops,
2976		.parent_hws = (const struct clk_hw *[]) {
2977			&g12a_vdec_hevc_div.hw
2978		},
2979		.num_parents = 1,
2980		.flags = CLK_SET_RATE_PARENT,
2981	},
2982};
2983
2984/* VAPB Clock */
2985
2986static const struct clk_hw *g12a_vapb_parent_hws[] = {
2987	&g12a_fclk_div4.hw,
2988	&g12a_fclk_div3.hw,
2989	&g12a_fclk_div5.hw,
2990	&g12a_fclk_div7.hw,
2991	&g12a_mpll1.hw,
2992	&g12a_vid_pll.hw,
2993	&g12a_mpll2.hw,
2994	&g12a_fclk_div2p5.hw,
2995};
2996
2997static struct clk_regmap g12a_vapb_0_sel = {
2998	.data = &(struct clk_regmap_mux_data){
2999		.offset = HHI_VAPBCLK_CNTL,
3000		.mask = 0x3,
3001		.shift = 9,
3002	},
3003	.hw.init = &(struct clk_init_data){
3004		.name = "vapb_0_sel",
3005		.ops = &clk_regmap_mux_ops,
3006		.parent_hws = g12a_vapb_parent_hws,
3007		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3008		.flags = CLK_SET_RATE_NO_REPARENT,
3009	},
3010};
3011
3012static struct clk_regmap g12a_vapb_0_div = {
3013	.data = &(struct clk_regmap_div_data){
3014		.offset = HHI_VAPBCLK_CNTL,
3015		.shift = 0,
3016		.width = 7,
3017	},
3018	.hw.init = &(struct clk_init_data){
3019		.name = "vapb_0_div",
3020		.ops = &clk_regmap_divider_ops,
3021		.parent_hws = (const struct clk_hw *[]) {
3022			&g12a_vapb_0_sel.hw
3023		},
3024		.num_parents = 1,
3025		.flags = CLK_SET_RATE_PARENT,
3026	},
3027};
3028
3029static struct clk_regmap g12a_vapb_0 = {
3030	.data = &(struct clk_regmap_gate_data){
3031		.offset = HHI_VAPBCLK_CNTL,
3032		.bit_idx = 8,
3033	},
3034	.hw.init = &(struct clk_init_data) {
3035		.name = "vapb_0",
3036		.ops = &clk_regmap_gate_ops,
3037		.parent_hws = (const struct clk_hw *[]) {
3038			&g12a_vapb_0_div.hw
3039		},
3040		.num_parents = 1,
3041		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3042	},
3043};
3044
3045static struct clk_regmap g12a_vapb_1_sel = {
3046	.data = &(struct clk_regmap_mux_data){
3047		.offset = HHI_VAPBCLK_CNTL,
3048		.mask = 0x3,
3049		.shift = 25,
3050	},
3051	.hw.init = &(struct clk_init_data){
3052		.name = "vapb_1_sel",
3053		.ops = &clk_regmap_mux_ops,
3054		.parent_hws = g12a_vapb_parent_hws,
3055		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3056		.flags = CLK_SET_RATE_NO_REPARENT,
3057	},
3058};
3059
3060static struct clk_regmap g12a_vapb_1_div = {
3061	.data = &(struct clk_regmap_div_data){
3062		.offset = HHI_VAPBCLK_CNTL,
3063		.shift = 16,
3064		.width = 7,
3065	},
3066	.hw.init = &(struct clk_init_data){
3067		.name = "vapb_1_div",
3068		.ops = &clk_regmap_divider_ops,
3069		.parent_hws = (const struct clk_hw *[]) {
3070			&g12a_vapb_1_sel.hw
3071		},
3072		.num_parents = 1,
3073		.flags = CLK_SET_RATE_PARENT,
3074	},
3075};
3076
3077static struct clk_regmap g12a_vapb_1 = {
3078	.data = &(struct clk_regmap_gate_data){
3079		.offset = HHI_VAPBCLK_CNTL,
3080		.bit_idx = 24,
3081	},
3082	.hw.init = &(struct clk_init_data) {
3083		.name = "vapb_1",
3084		.ops = &clk_regmap_gate_ops,
3085		.parent_hws = (const struct clk_hw *[]) {
3086			&g12a_vapb_1_div.hw
3087		},
3088		.num_parents = 1,
3089		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3090	},
3091};
3092
3093static struct clk_regmap g12a_vapb_sel = {
3094	.data = &(struct clk_regmap_mux_data){
3095		.offset = HHI_VAPBCLK_CNTL,
3096		.mask = 1,
3097		.shift = 31,
3098	},
3099	.hw.init = &(struct clk_init_data){
3100		.name = "vapb_sel",
3101		.ops = &clk_regmap_mux_ops,
3102		/*
3103		 * bit 31 selects from 2 possible parents:
3104		 * vapb_0 or vapb_1
3105		 */
3106		.parent_hws = (const struct clk_hw *[]) {
3107			&g12a_vapb_0.hw,
3108			&g12a_vapb_1.hw,
3109		},
3110		.num_parents = 2,
3111		.flags = CLK_SET_RATE_NO_REPARENT,
3112	},
3113};
3114
3115static struct clk_regmap g12a_vapb = {
3116	.data = &(struct clk_regmap_gate_data){
3117		.offset = HHI_VAPBCLK_CNTL,
3118		.bit_idx = 30,
3119	},
3120	.hw.init = &(struct clk_init_data) {
3121		.name = "vapb",
3122		.ops = &clk_regmap_gate_ops,
3123		.parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3124		.num_parents = 1,
3125		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3126	},
3127};
3128
3129static const struct clk_hw *g12a_vclk_parent_hws[] = {
3130	&g12a_vid_pll.hw,
3131	&g12a_gp0_pll.hw,
3132	&g12a_hifi_pll.hw,
3133	&g12a_mpll1.hw,
3134	&g12a_fclk_div3.hw,
3135	&g12a_fclk_div4.hw,
3136	&g12a_fclk_div5.hw,
3137	&g12a_fclk_div7.hw,
3138};
3139
3140static struct clk_regmap g12a_vclk_sel = {
3141	.data = &(struct clk_regmap_mux_data){
3142		.offset = HHI_VID_CLK_CNTL,
3143		.mask = 0x7,
3144		.shift = 16,
3145	},
3146	.hw.init = &(struct clk_init_data){
3147		.name = "vclk_sel",
3148		.ops = &clk_regmap_mux_ops,
3149		.parent_hws = g12a_vclk_parent_hws,
3150		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3151		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3152	},
3153};
3154
3155static struct clk_regmap g12a_vclk2_sel = {
3156	.data = &(struct clk_regmap_mux_data){
3157		.offset = HHI_VIID_CLK_CNTL,
3158		.mask = 0x7,
3159		.shift = 16,
3160	},
3161	.hw.init = &(struct clk_init_data){
3162		.name = "vclk2_sel",
3163		.ops = &clk_regmap_mux_ops,
3164		.parent_hws = g12a_vclk_parent_hws,
3165		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3166		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3167	},
3168};
3169
3170static struct clk_regmap g12a_vclk_input = {
3171	.data = &(struct clk_regmap_gate_data){
3172		.offset = HHI_VID_CLK_DIV,
3173		.bit_idx = 16,
3174	},
3175	.hw.init = &(struct clk_init_data) {
3176		.name = "vclk_input",
3177		.ops = &clk_regmap_gate_ops,
3178		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3179		.num_parents = 1,
3180		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3181	},
3182};
3183
3184static struct clk_regmap g12a_vclk2_input = {
3185	.data = &(struct clk_regmap_gate_data){
3186		.offset = HHI_VIID_CLK_DIV,
3187		.bit_idx = 16,
3188	},
3189	.hw.init = &(struct clk_init_data) {
3190		.name = "vclk2_input",
3191		.ops = &clk_regmap_gate_ops,
3192		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3193		.num_parents = 1,
3194		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3195	},
3196};
3197
3198static struct clk_regmap g12a_vclk_div = {
3199	.data = &(struct clk_regmap_div_data){
3200		.offset = HHI_VID_CLK_DIV,
3201		.shift = 0,
3202		.width = 8,
3203	},
3204	.hw.init = &(struct clk_init_data){
3205		.name = "vclk_div",
3206		.ops = &clk_regmap_divider_ops,
3207		.parent_hws = (const struct clk_hw *[]) {
3208			&g12a_vclk_input.hw
3209		},
3210		.num_parents = 1,
3211		.flags = CLK_GET_RATE_NOCACHE,
3212	},
3213};
3214
3215static struct clk_regmap g12a_vclk2_div = {
3216	.data = &(struct clk_regmap_div_data){
3217		.offset = HHI_VIID_CLK_DIV,
3218		.shift = 0,
3219		.width = 8,
3220	},
3221	.hw.init = &(struct clk_init_data){
3222		.name = "vclk2_div",
3223		.ops = &clk_regmap_divider_ops,
3224		.parent_hws = (const struct clk_hw *[]) {
3225			&g12a_vclk2_input.hw
3226		},
3227		.num_parents = 1,
3228		.flags = CLK_GET_RATE_NOCACHE,
3229	},
3230};
3231
3232static struct clk_regmap g12a_vclk = {
3233	.data = &(struct clk_regmap_gate_data){
3234		.offset = HHI_VID_CLK_CNTL,
3235		.bit_idx = 19,
3236	},
3237	.hw.init = &(struct clk_init_data) {
3238		.name = "vclk",
3239		.ops = &clk_regmap_gate_ops,
3240		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3241		.num_parents = 1,
3242		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3243	},
3244};
3245
3246static struct clk_regmap g12a_vclk2 = {
3247	.data = &(struct clk_regmap_gate_data){
3248		.offset = HHI_VIID_CLK_CNTL,
3249		.bit_idx = 19,
3250	},
3251	.hw.init = &(struct clk_init_data) {
3252		.name = "vclk2",
3253		.ops = &clk_regmap_gate_ops,
3254		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3255		.num_parents = 1,
3256		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3257	},
3258};
3259
3260static struct clk_regmap g12a_vclk_div1 = {
3261	.data = &(struct clk_regmap_gate_data){
3262		.offset = HHI_VID_CLK_CNTL,
3263		.bit_idx = 0,
3264	},
3265	.hw.init = &(struct clk_init_data) {
3266		.name = "vclk_div1",
3267		.ops = &clk_regmap_gate_ops,
3268		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3269		.num_parents = 1,
3270		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3271	},
3272};
3273
3274static struct clk_regmap g12a_vclk_div2_en = {
3275	.data = &(struct clk_regmap_gate_data){
3276		.offset = HHI_VID_CLK_CNTL,
3277		.bit_idx = 1,
3278	},
3279	.hw.init = &(struct clk_init_data) {
3280		.name = "vclk_div2_en",
3281		.ops = &clk_regmap_gate_ops,
3282		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3283		.num_parents = 1,
3284		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3285	},
3286};
3287
3288static struct clk_regmap g12a_vclk_div4_en = {
3289	.data = &(struct clk_regmap_gate_data){
3290		.offset = HHI_VID_CLK_CNTL,
3291		.bit_idx = 2,
3292	},
3293	.hw.init = &(struct clk_init_data) {
3294		.name = "vclk_div4_en",
3295		.ops = &clk_regmap_gate_ops,
3296		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3297		.num_parents = 1,
3298		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3299	},
3300};
3301
3302static struct clk_regmap g12a_vclk_div6_en = {
3303	.data = &(struct clk_regmap_gate_data){
3304		.offset = HHI_VID_CLK_CNTL,
3305		.bit_idx = 3,
3306	},
3307	.hw.init = &(struct clk_init_data) {
3308		.name = "vclk_div6_en",
3309		.ops = &clk_regmap_gate_ops,
3310		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3311		.num_parents = 1,
3312		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3313	},
3314};
3315
3316static struct clk_regmap g12a_vclk_div12_en = {
3317	.data = &(struct clk_regmap_gate_data){
3318		.offset = HHI_VID_CLK_CNTL,
3319		.bit_idx = 4,
3320	},
3321	.hw.init = &(struct clk_init_data) {
3322		.name = "vclk_div12_en",
3323		.ops = &clk_regmap_gate_ops,
3324		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3325		.num_parents = 1,
3326		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3327	},
3328};
3329
3330static struct clk_regmap g12a_vclk2_div1 = {
3331	.data = &(struct clk_regmap_gate_data){
3332		.offset = HHI_VIID_CLK_CNTL,
3333		.bit_idx = 0,
3334	},
3335	.hw.init = &(struct clk_init_data) {
3336		.name = "vclk2_div1",
3337		.ops = &clk_regmap_gate_ops,
3338		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3339		.num_parents = 1,
3340		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3341	},
3342};
3343
3344static struct clk_regmap g12a_vclk2_div2_en = {
3345	.data = &(struct clk_regmap_gate_data){
3346		.offset = HHI_VIID_CLK_CNTL,
3347		.bit_idx = 1,
3348	},
3349	.hw.init = &(struct clk_init_data) {
3350		.name = "vclk2_div2_en",
3351		.ops = &clk_regmap_gate_ops,
3352		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3353		.num_parents = 1,
3354		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3355	},
3356};
3357
3358static struct clk_regmap g12a_vclk2_div4_en = {
3359	.data = &(struct clk_regmap_gate_data){
3360		.offset = HHI_VIID_CLK_CNTL,
3361		.bit_idx = 2,
3362	},
3363	.hw.init = &(struct clk_init_data) {
3364		.name = "vclk2_div4_en",
3365		.ops = &clk_regmap_gate_ops,
3366		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3367		.num_parents = 1,
3368		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3369	},
3370};
3371
3372static struct clk_regmap g12a_vclk2_div6_en = {
3373	.data = &(struct clk_regmap_gate_data){
3374		.offset = HHI_VIID_CLK_CNTL,
3375		.bit_idx = 3,
3376	},
3377	.hw.init = &(struct clk_init_data) {
3378		.name = "vclk2_div6_en",
3379		.ops = &clk_regmap_gate_ops,
3380		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3381		.num_parents = 1,
3382		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3383	},
3384};
3385
3386static struct clk_regmap g12a_vclk2_div12_en = {
3387	.data = &(struct clk_regmap_gate_data){
3388		.offset = HHI_VIID_CLK_CNTL,
3389		.bit_idx = 4,
3390	},
3391	.hw.init = &(struct clk_init_data) {
3392		.name = "vclk2_div12_en",
3393		.ops = &clk_regmap_gate_ops,
3394		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3395		.num_parents = 1,
3396		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3397	},
3398};
3399
3400static struct clk_fixed_factor g12a_vclk_div2 = {
3401	.mult = 1,
3402	.div = 2,
3403	.hw.init = &(struct clk_init_data){
3404		.name = "vclk_div2",
3405		.ops = &clk_fixed_factor_ops,
3406		.parent_hws = (const struct clk_hw *[]) {
3407			&g12a_vclk_div2_en.hw
3408		},
3409		.num_parents = 1,
3410	},
3411};
3412
3413static struct clk_fixed_factor g12a_vclk_div4 = {
3414	.mult = 1,
3415	.div = 4,
3416	.hw.init = &(struct clk_init_data){
3417		.name = "vclk_div4",
3418		.ops = &clk_fixed_factor_ops,
3419		.parent_hws = (const struct clk_hw *[]) {
3420			&g12a_vclk_div4_en.hw
3421		},
3422		.num_parents = 1,
3423	},
3424};
3425
3426static struct clk_fixed_factor g12a_vclk_div6 = {
3427	.mult = 1,
3428	.div = 6,
3429	.hw.init = &(struct clk_init_data){
3430		.name = "vclk_div6",
3431		.ops = &clk_fixed_factor_ops,
3432		.parent_hws = (const struct clk_hw *[]) {
3433			&g12a_vclk_div6_en.hw
3434		},
3435		.num_parents = 1,
3436	},
3437};
3438
3439static struct clk_fixed_factor g12a_vclk_div12 = {
3440	.mult = 1,
3441	.div = 12,
3442	.hw.init = &(struct clk_init_data){
3443		.name = "vclk_div12",
3444		.ops = &clk_fixed_factor_ops,
3445		.parent_hws = (const struct clk_hw *[]) {
3446			&g12a_vclk_div12_en.hw
3447		},
3448		.num_parents = 1,
3449	},
3450};
3451
3452static struct clk_fixed_factor g12a_vclk2_div2 = {
3453	.mult = 1,
3454	.div = 2,
3455	.hw.init = &(struct clk_init_data){
3456		.name = "vclk2_div2",
3457		.ops = &clk_fixed_factor_ops,
3458		.parent_hws = (const struct clk_hw *[]) {
3459			&g12a_vclk2_div2_en.hw
3460		},
3461		.num_parents = 1,
3462	},
3463};
3464
3465static struct clk_fixed_factor g12a_vclk2_div4 = {
3466	.mult = 1,
3467	.div = 4,
3468	.hw.init = &(struct clk_init_data){
3469		.name = "vclk2_div4",
3470		.ops = &clk_fixed_factor_ops,
3471		.parent_hws = (const struct clk_hw *[]) {
3472			&g12a_vclk2_div4_en.hw
3473		},
3474		.num_parents = 1,
3475	},
3476};
3477
3478static struct clk_fixed_factor g12a_vclk2_div6 = {
3479	.mult = 1,
3480	.div = 6,
3481	.hw.init = &(struct clk_init_data){
3482		.name = "vclk2_div6",
3483		.ops = &clk_fixed_factor_ops,
3484		.parent_hws = (const struct clk_hw *[]) {
3485			&g12a_vclk2_div6_en.hw
3486		},
3487		.num_parents = 1,
3488	},
3489};
3490
3491static struct clk_fixed_factor g12a_vclk2_div12 = {
3492	.mult = 1,
3493	.div = 12,
3494	.hw.init = &(struct clk_init_data){
3495		.name = "vclk2_div12",
3496		.ops = &clk_fixed_factor_ops,
3497		.parent_hws = (const struct clk_hw *[]) {
3498			&g12a_vclk2_div12_en.hw
3499		},
3500		.num_parents = 1,
3501	},
3502};
3503
3504static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3505static const struct clk_hw *g12a_cts_parent_hws[] = {
3506	&g12a_vclk_div1.hw,
3507	&g12a_vclk_div2.hw,
3508	&g12a_vclk_div4.hw,
3509	&g12a_vclk_div6.hw,
3510	&g12a_vclk_div12.hw,
3511	&g12a_vclk2_div1.hw,
3512	&g12a_vclk2_div2.hw,
3513	&g12a_vclk2_div4.hw,
3514	&g12a_vclk2_div6.hw,
3515	&g12a_vclk2_div12.hw,
3516};
3517
3518static struct clk_regmap g12a_cts_enci_sel = {
3519	.data = &(struct clk_regmap_mux_data){
3520		.offset = HHI_VID_CLK_DIV,
3521		.mask = 0xf,
3522		.shift = 28,
3523		.table = mux_table_cts_sel,
3524	},
3525	.hw.init = &(struct clk_init_data){
3526		.name = "cts_enci_sel",
3527		.ops = &clk_regmap_mux_ops,
3528		.parent_hws = g12a_cts_parent_hws,
3529		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3530		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3531	},
3532};
3533
3534static struct clk_regmap g12a_cts_encp_sel = {
3535	.data = &(struct clk_regmap_mux_data){
3536		.offset = HHI_VID_CLK_DIV,
3537		.mask = 0xf,
3538		.shift = 20,
3539		.table = mux_table_cts_sel,
3540	},
3541	.hw.init = &(struct clk_init_data){
3542		.name = "cts_encp_sel",
3543		.ops = &clk_regmap_mux_ops,
3544		.parent_hws = g12a_cts_parent_hws,
3545		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3546		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3547	},
3548};
3549
3550static struct clk_regmap g12a_cts_vdac_sel = {
3551	.data = &(struct clk_regmap_mux_data){
3552		.offset = HHI_VIID_CLK_DIV,
3553		.mask = 0xf,
3554		.shift = 28,
3555		.table = mux_table_cts_sel,
3556	},
3557	.hw.init = &(struct clk_init_data){
3558		.name = "cts_vdac_sel",
3559		.ops = &clk_regmap_mux_ops,
3560		.parent_hws = g12a_cts_parent_hws,
3561		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3562		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3563	},
3564};
3565
3566/* TOFIX: add support for cts_tcon */
3567static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3568static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3569	&g12a_vclk_div1.hw,
3570	&g12a_vclk_div2.hw,
3571	&g12a_vclk_div4.hw,
3572	&g12a_vclk_div6.hw,
3573	&g12a_vclk_div12.hw,
3574	&g12a_vclk2_div1.hw,
3575	&g12a_vclk2_div2.hw,
3576	&g12a_vclk2_div4.hw,
3577	&g12a_vclk2_div6.hw,
3578	&g12a_vclk2_div12.hw,
3579};
3580
3581static struct clk_regmap g12a_hdmi_tx_sel = {
3582	.data = &(struct clk_regmap_mux_data){
3583		.offset = HHI_HDMI_CLK_CNTL,
3584		.mask = 0xf,
3585		.shift = 16,
3586		.table = mux_table_hdmi_tx_sel,
3587	},
3588	.hw.init = &(struct clk_init_data){
3589		.name = "hdmi_tx_sel",
3590		.ops = &clk_regmap_mux_ops,
3591		.parent_hws = g12a_cts_hdmi_tx_parent_hws,
3592		.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3593		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3594	},
3595};
3596
3597static struct clk_regmap g12a_cts_enci = {
3598	.data = &(struct clk_regmap_gate_data){
3599		.offset = HHI_VID_CLK_CNTL2,
3600		.bit_idx = 0,
3601	},
3602	.hw.init = &(struct clk_init_data) {
3603		.name = "cts_enci",
3604		.ops = &clk_regmap_gate_ops,
3605		.parent_hws = (const struct clk_hw *[]) {
3606			&g12a_cts_enci_sel.hw
3607		},
3608		.num_parents = 1,
3609		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3610	},
3611};
3612
3613static struct clk_regmap g12a_cts_encp = {
3614	.data = &(struct clk_regmap_gate_data){
3615		.offset = HHI_VID_CLK_CNTL2,
3616		.bit_idx = 2,
3617	},
3618	.hw.init = &(struct clk_init_data) {
3619		.name = "cts_encp",
3620		.ops = &clk_regmap_gate_ops,
3621		.parent_hws = (const struct clk_hw *[]) {
3622			&g12a_cts_encp_sel.hw
3623		},
3624		.num_parents = 1,
3625		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3626	},
3627};
3628
3629static struct clk_regmap g12a_cts_vdac = {
3630	.data = &(struct clk_regmap_gate_data){
3631		.offset = HHI_VID_CLK_CNTL2,
3632		.bit_idx = 4,
3633	},
3634	.hw.init = &(struct clk_init_data) {
3635		.name = "cts_vdac",
3636		.ops = &clk_regmap_gate_ops,
3637		.parent_hws = (const struct clk_hw *[]) {
3638			&g12a_cts_vdac_sel.hw
3639		},
3640		.num_parents = 1,
3641		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3642	},
3643};
3644
3645static struct clk_regmap g12a_hdmi_tx = {
3646	.data = &(struct clk_regmap_gate_data){
3647		.offset = HHI_VID_CLK_CNTL2,
3648		.bit_idx = 5,
3649	},
3650	.hw.init = &(struct clk_init_data) {
3651		.name = "hdmi_tx",
3652		.ops = &clk_regmap_gate_ops,
3653		.parent_hws = (const struct clk_hw *[]) {
3654			&g12a_hdmi_tx_sel.hw
3655		},
3656		.num_parents = 1,
3657		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3658	},
3659};
3660
3661/* MIPI DSI Host Clocks */
3662
3663static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
3664	&g12a_vid_pll.hw,
3665	&g12a_gp0_pll.hw,
3666	&g12a_hifi_pll.hw,
3667	&g12a_mpll1.hw,
3668	&g12a_fclk_div2.hw,
3669	&g12a_fclk_div2p5.hw,
3670	&g12a_fclk_div3.hw,
3671	&g12a_fclk_div7.hw,
3672};
3673
3674static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
3675	.data = &(struct clk_regmap_mux_data){
3676		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3677		.mask = 0x7,
3678		.shift = 12,
3679		.flags = CLK_MUX_ROUND_CLOSEST,
3680	},
3681	.hw.init = &(struct clk_init_data){
3682		.name = "mipi_dsi_pxclk_sel",
3683		.ops = &clk_regmap_mux_ops,
3684		.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3685		.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3686		.flags = CLK_SET_RATE_NO_REPARENT,
3687	},
3688};
3689
3690static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
3691	.data = &(struct clk_regmap_div_data){
3692		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3693		.shift = 0,
3694		.width = 7,
3695	},
3696	.hw.init = &(struct clk_init_data){
3697		.name = "mipi_dsi_pxclk_div",
3698		.ops = &clk_regmap_divider_ops,
3699		.parent_hws = (const struct clk_hw *[]) {
3700			&g12a_mipi_dsi_pxclk_sel.hw
3701		},
3702		.num_parents = 1,
3703		.flags = CLK_SET_RATE_PARENT,
3704	},
3705};
3706
3707static struct clk_regmap g12a_mipi_dsi_pxclk = {
3708	.data = &(struct clk_regmap_gate_data){
3709		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3710		.bit_idx = 8,
3711	},
3712	.hw.init = &(struct clk_init_data) {
3713		.name = "mipi_dsi_pxclk",
3714		.ops = &clk_regmap_gate_ops,
3715		.parent_hws = (const struct clk_hw *[]) {
3716			&g12a_mipi_dsi_pxclk_div.hw
3717		},
3718		.num_parents = 1,
3719		.flags = CLK_SET_RATE_PARENT,
3720	},
3721};
3722
3723/* HDMI Clocks */
3724
3725static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3726	{ .fw_name = "xtal", },
3727	{ .hw = &g12a_fclk_div4.hw },
3728	{ .hw = &g12a_fclk_div3.hw },
3729	{ .hw = &g12a_fclk_div5.hw },
3730};
3731
3732static struct clk_regmap g12a_hdmi_sel = {
3733	.data = &(struct clk_regmap_mux_data){
3734		.offset = HHI_HDMI_CLK_CNTL,
3735		.mask = 0x3,
3736		.shift = 9,
3737		.flags = CLK_MUX_ROUND_CLOSEST,
3738	},
3739	.hw.init = &(struct clk_init_data){
3740		.name = "hdmi_sel",
3741		.ops = &clk_regmap_mux_ops,
3742		.parent_data = g12a_hdmi_parent_data,
3743		.num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3744		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3745	},
3746};
3747
3748static struct clk_regmap g12a_hdmi_div = {
3749	.data = &(struct clk_regmap_div_data){
3750		.offset = HHI_HDMI_CLK_CNTL,
3751		.shift = 0,
3752		.width = 7,
3753	},
3754	.hw.init = &(struct clk_init_data){
3755		.name = "hdmi_div",
3756		.ops = &clk_regmap_divider_ops,
3757		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3758		.num_parents = 1,
3759		.flags = CLK_GET_RATE_NOCACHE,
3760	},
3761};
3762
3763static struct clk_regmap g12a_hdmi = {
3764	.data = &(struct clk_regmap_gate_data){
3765		.offset = HHI_HDMI_CLK_CNTL,
3766		.bit_idx = 8,
3767	},
3768	.hw.init = &(struct clk_init_data) {
3769		.name = "hdmi",
3770		.ops = &clk_regmap_gate_ops,
3771		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3772		.num_parents = 1,
3773		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3774	},
3775};
3776
3777/*
3778 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3779 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3780 * mux because it does top-to-bottom updates the each clock tree and
3781 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
3782 */
3783static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3784	{ .fw_name = "xtal", },
3785	{ .hw = &g12a_gp0_pll.hw },
3786	{ .hw = &g12a_hifi_pll.hw },
3787	{ .hw = &g12a_fclk_div2p5.hw },
3788	{ .hw = &g12a_fclk_div3.hw },
3789	{ .hw = &g12a_fclk_div4.hw },
3790	{ .hw = &g12a_fclk_div5.hw },
3791	{ .hw = &g12a_fclk_div7.hw },
3792};
3793
3794static struct clk_regmap g12a_mali_0_sel = {
3795	.data = &(struct clk_regmap_mux_data){
3796		.offset = HHI_MALI_CLK_CNTL,
3797		.mask = 0x7,
3798		.shift = 9,
3799	},
3800	.hw.init = &(struct clk_init_data){
3801		.name = "mali_0_sel",
3802		.ops = &clk_regmap_mux_ops,
3803		.parent_data = g12a_mali_0_1_parent_data,
3804		.num_parents = 8,
3805		/*
3806		 * Don't request the parent to change the rate because
3807		 * all GPU frequencies can be derived from the fclk_*
3808		 * clocks and one special GP0_PLL setting. This is
3809		 * important because we need the MPLL clocks for audio.
3810		 */
3811		.flags = 0,
3812	},
3813};
3814
3815static struct clk_regmap g12a_mali_0_div = {
3816	.data = &(struct clk_regmap_div_data){
3817		.offset = HHI_MALI_CLK_CNTL,
3818		.shift = 0,
3819		.width = 7,
3820	},
3821	.hw.init = &(struct clk_init_data){
3822		.name = "mali_0_div",
3823		.ops = &clk_regmap_divider_ops,
3824		.parent_hws = (const struct clk_hw *[]) {
3825			&g12a_mali_0_sel.hw
3826		},
3827		.num_parents = 1,
3828		.flags = CLK_SET_RATE_PARENT,
3829	},
3830};
3831
3832static struct clk_regmap g12a_mali_0 = {
3833	.data = &(struct clk_regmap_gate_data){
3834		.offset = HHI_MALI_CLK_CNTL,
3835		.bit_idx = 8,
3836	},
3837	.hw.init = &(struct clk_init_data){
3838		.name = "mali_0",
3839		.ops = &clk_regmap_gate_ops,
3840		.parent_hws = (const struct clk_hw *[]) {
3841			&g12a_mali_0_div.hw
3842		},
3843		.num_parents = 1,
3844		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3845	},
3846};
3847
3848static struct clk_regmap g12a_mali_1_sel = {
3849	.data = &(struct clk_regmap_mux_data){
3850		.offset = HHI_MALI_CLK_CNTL,
3851		.mask = 0x7,
3852		.shift = 25,
3853	},
3854	.hw.init = &(struct clk_init_data){
3855		.name = "mali_1_sel",
3856		.ops = &clk_regmap_mux_ops,
3857		.parent_data = g12a_mali_0_1_parent_data,
3858		.num_parents = 8,
3859		/*
3860		 * Don't request the parent to change the rate because
3861		 * all GPU frequencies can be derived from the fclk_*
3862		 * clocks and one special GP0_PLL setting. This is
3863		 * important because we need the MPLL clocks for audio.
3864		 */
3865		.flags = 0,
3866	},
3867};
3868
3869static struct clk_regmap g12a_mali_1_div = {
3870	.data = &(struct clk_regmap_div_data){
3871		.offset = HHI_MALI_CLK_CNTL,
3872		.shift = 16,
3873		.width = 7,
3874	},
3875	.hw.init = &(struct clk_init_data){
3876		.name = "mali_1_div",
3877		.ops = &clk_regmap_divider_ops,
3878		.parent_hws = (const struct clk_hw *[]) {
3879			&g12a_mali_1_sel.hw
3880		},
3881		.num_parents = 1,
3882		.flags = CLK_SET_RATE_PARENT,
3883	},
3884};
3885
3886static struct clk_regmap g12a_mali_1 = {
3887	.data = &(struct clk_regmap_gate_data){
3888		.offset = HHI_MALI_CLK_CNTL,
3889		.bit_idx = 24,
3890	},
3891	.hw.init = &(struct clk_init_data){
3892		.name = "mali_1",
3893		.ops = &clk_regmap_gate_ops,
3894		.parent_hws = (const struct clk_hw *[]) {
3895			&g12a_mali_1_div.hw
3896		},
3897		.num_parents = 1,
3898		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3899	},
3900};
3901
3902static const struct clk_hw *g12a_mali_parent_hws[] = {
3903	&g12a_mali_0.hw,
3904	&g12a_mali_1.hw,
3905};
3906
3907static struct clk_regmap g12a_mali = {
3908	.data = &(struct clk_regmap_mux_data){
3909		.offset = HHI_MALI_CLK_CNTL,
3910		.mask = 1,
3911		.shift = 31,
3912	},
3913	.hw.init = &(struct clk_init_data){
3914		.name = "mali",
3915		.ops = &clk_regmap_mux_ops,
3916		.parent_hws = g12a_mali_parent_hws,
3917		.num_parents = 2,
3918		.flags = CLK_SET_RATE_PARENT,
3919	},
3920};
3921
3922static struct clk_regmap g12a_ts_div = {
3923	.data = &(struct clk_regmap_div_data){
3924		.offset = HHI_TS_CLK_CNTL,
3925		.shift = 0,
3926		.width = 8,
3927	},
3928	.hw.init = &(struct clk_init_data){
3929		.name = "ts_div",
3930		.ops = &clk_regmap_divider_ro_ops,
3931		.parent_data = &(const struct clk_parent_data) {
3932			.fw_name = "xtal",
3933		},
3934		.num_parents = 1,
3935	},
3936};
3937
3938static struct clk_regmap g12a_ts = {
3939	.data = &(struct clk_regmap_gate_data){
3940		.offset = HHI_TS_CLK_CNTL,
3941		.bit_idx = 8,
3942	},
3943	.hw.init = &(struct clk_init_data){
3944		.name = "ts",
3945		.ops = &clk_regmap_gate_ops,
3946		.parent_hws = (const struct clk_hw *[]) {
3947			&g12a_ts_div.hw
3948		},
3949		.num_parents = 1,
3950	},
3951};
3952
3953/* SPICC SCLK source clock */
3954
3955static const struct clk_parent_data spicc_sclk_parent_data[] = {
3956	{ .fw_name = "xtal", },
3957	{ .hw = &g12a_clk81.hw },
3958	{ .hw = &g12a_fclk_div4.hw },
3959	{ .hw = &g12a_fclk_div3.hw },
3960	{ .hw = &g12a_fclk_div5.hw },
3961	{ .hw = &g12a_fclk_div7.hw },
3962};
3963
3964static struct clk_regmap g12a_spicc0_sclk_sel = {
3965	.data = &(struct clk_regmap_mux_data){
3966		.offset = HHI_SPICC_CLK_CNTL,
3967		.mask = 7,
3968		.shift = 7,
3969	},
3970	.hw.init = &(struct clk_init_data){
3971		.name = "spicc0_sclk_sel",
3972		.ops = &clk_regmap_mux_ops,
3973		.parent_data = spicc_sclk_parent_data,
3974		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3975	},
3976};
3977
3978static struct clk_regmap g12a_spicc0_sclk_div = {
3979	.data = &(struct clk_regmap_div_data){
3980		.offset = HHI_SPICC_CLK_CNTL,
3981		.shift = 0,
3982		.width = 6,
3983	},
3984	.hw.init = &(struct clk_init_data){
3985		.name = "spicc0_sclk_div",
3986		.ops = &clk_regmap_divider_ops,
3987		.parent_hws = (const struct clk_hw *[]) {
3988			&g12a_spicc0_sclk_sel.hw
3989		},
3990		.num_parents = 1,
3991		.flags = CLK_SET_RATE_PARENT,
3992	},
3993};
3994
3995static struct clk_regmap g12a_spicc0_sclk = {
3996	.data = &(struct clk_regmap_gate_data){
3997		.offset = HHI_SPICC_CLK_CNTL,
3998		.bit_idx = 6,
3999	},
4000	.hw.init = &(struct clk_init_data){
4001		.name = "spicc0_sclk",
4002		.ops = &clk_regmap_gate_ops,
4003		.parent_hws = (const struct clk_hw *[]) {
4004			&g12a_spicc0_sclk_div.hw
4005		},
4006		.num_parents = 1,
4007		.flags = CLK_SET_RATE_PARENT,
4008	},
4009};
4010
4011static struct clk_regmap g12a_spicc1_sclk_sel = {
4012	.data = &(struct clk_regmap_mux_data){
4013		.offset = HHI_SPICC_CLK_CNTL,
4014		.mask = 7,
4015		.shift = 23,
4016	},
4017	.hw.init = &(struct clk_init_data){
4018		.name = "spicc1_sclk_sel",
4019		.ops = &clk_regmap_mux_ops,
4020		.parent_data = spicc_sclk_parent_data,
4021		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4022	},
4023};
4024
4025static struct clk_regmap g12a_spicc1_sclk_div = {
4026	.data = &(struct clk_regmap_div_data){
4027		.offset = HHI_SPICC_CLK_CNTL,
4028		.shift = 16,
4029		.width = 6,
4030	},
4031	.hw.init = &(struct clk_init_data){
4032		.name = "spicc1_sclk_div",
4033		.ops = &clk_regmap_divider_ops,
4034		.parent_hws = (const struct clk_hw *[]) {
4035			&g12a_spicc1_sclk_sel.hw
4036		},
4037		.num_parents = 1,
4038		.flags = CLK_SET_RATE_PARENT,
4039	},
4040};
4041
4042static struct clk_regmap g12a_spicc1_sclk = {
4043	.data = &(struct clk_regmap_gate_data){
4044		.offset = HHI_SPICC_CLK_CNTL,
4045		.bit_idx = 22,
4046	},
4047	.hw.init = &(struct clk_init_data){
4048		.name = "spicc1_sclk",
4049		.ops = &clk_regmap_gate_ops,
4050		.parent_hws = (const struct clk_hw *[]) {
4051			&g12a_spicc1_sclk_div.hw
4052		},
4053		.num_parents = 1,
4054		.flags = CLK_SET_RATE_PARENT,
4055	},
4056};
4057
4058/* Neural Network Accelerator source clock */
4059
4060static const struct clk_parent_data nna_clk_parent_data[] = {
4061	{ .fw_name = "xtal", },
4062	{ .hw = &g12a_gp0_pll.hw, },
4063	{ .hw = &g12a_hifi_pll.hw, },
4064	{ .hw = &g12a_fclk_div2p5.hw, },
4065	{ .hw = &g12a_fclk_div3.hw, },
4066	{ .hw = &g12a_fclk_div4.hw, },
4067	{ .hw = &g12a_fclk_div5.hw, },
4068	{ .hw = &g12a_fclk_div7.hw },
4069};
4070
4071static struct clk_regmap sm1_nna_axi_clk_sel = {
4072	.data = &(struct clk_regmap_mux_data){
4073		.offset = HHI_NNA_CLK_CNTL,
4074		.mask = 7,
4075		.shift = 9,
4076	},
4077	.hw.init = &(struct clk_init_data){
4078		.name = "nna_axi_clk_sel",
4079		.ops = &clk_regmap_mux_ops,
4080		.parent_data = nna_clk_parent_data,
4081		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4082	},
4083};
4084
4085static struct clk_regmap sm1_nna_axi_clk_div = {
4086	.data = &(struct clk_regmap_div_data){
4087		.offset = HHI_NNA_CLK_CNTL,
4088		.shift = 0,
4089		.width = 7,
4090	},
4091	.hw.init = &(struct clk_init_data){
4092		.name = "nna_axi_clk_div",
4093		.ops = &clk_regmap_divider_ops,
4094		.parent_hws = (const struct clk_hw *[]) {
4095			&sm1_nna_axi_clk_sel.hw
4096		},
4097		.num_parents = 1,
4098		.flags = CLK_SET_RATE_PARENT,
4099	},
4100};
4101
4102static struct clk_regmap sm1_nna_axi_clk = {
4103	.data = &(struct clk_regmap_gate_data){
4104		.offset = HHI_NNA_CLK_CNTL,
4105		.bit_idx = 8,
4106	},
4107	.hw.init = &(struct clk_init_data){
4108		.name = "nna_axi_clk",
4109		.ops = &clk_regmap_gate_ops,
4110		.parent_hws = (const struct clk_hw *[]) {
4111			&sm1_nna_axi_clk_div.hw
4112		},
4113		.num_parents = 1,
4114		.flags = CLK_SET_RATE_PARENT,
4115	},
4116};
4117
4118static struct clk_regmap sm1_nna_core_clk_sel = {
4119	.data = &(struct clk_regmap_mux_data){
4120		.offset = HHI_NNA_CLK_CNTL,
4121		.mask = 7,
4122		.shift = 25,
4123	},
4124	.hw.init = &(struct clk_init_data){
4125		.name = "nna_core_clk_sel",
4126		.ops = &clk_regmap_mux_ops,
4127		.parent_data = nna_clk_parent_data,
4128		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4129	},
4130};
4131
4132static struct clk_regmap sm1_nna_core_clk_div = {
4133	.data = &(struct clk_regmap_div_data){
4134		.offset = HHI_NNA_CLK_CNTL,
4135		.shift = 16,
4136		.width = 7,
4137	},
4138	.hw.init = &(struct clk_init_data){
4139		.name = "nna_core_clk_div",
4140		.ops = &clk_regmap_divider_ops,
4141		.parent_hws = (const struct clk_hw *[]) {
4142			&sm1_nna_core_clk_sel.hw
4143		},
4144		.num_parents = 1,
4145		.flags = CLK_SET_RATE_PARENT,
4146	},
4147};
4148
4149static struct clk_regmap sm1_nna_core_clk = {
4150	.data = &(struct clk_regmap_gate_data){
4151		.offset = HHI_NNA_CLK_CNTL,
4152		.bit_idx = 24,
4153	},
4154	.hw.init = &(struct clk_init_data){
4155		.name = "nna_core_clk",
4156		.ops = &clk_regmap_gate_ops,
4157		.parent_hws = (const struct clk_hw *[]) {
4158			&sm1_nna_core_clk_div.hw
4159		},
4160		.num_parents = 1,
4161		.flags = CLK_SET_RATE_PARENT,
4162	},
4163};
4164
4165#define MESON_GATE(_name, _reg, _bit) \
4166	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4167
4168#define MESON_GATE_RO(_name, _reg, _bit) \
4169	MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4170
4171/* Everything Else (EE) domain gates */
4172static MESON_GATE(g12a_ddr,			HHI_GCLK_MPEG0,	0);
4173static MESON_GATE(g12a_dos,			HHI_GCLK_MPEG0,	1);
4174static MESON_GATE(g12a_audio_locker,		HHI_GCLK_MPEG0,	2);
4175static MESON_GATE(g12a_mipi_dsi_host,		HHI_GCLK_MPEG0,	3);
4176static MESON_GATE(g12a_eth_phy,			HHI_GCLK_MPEG0,	4);
4177static MESON_GATE(g12a_isa,			HHI_GCLK_MPEG0,	5);
4178static MESON_GATE(g12a_pl301,			HHI_GCLK_MPEG0,	6);
4179static MESON_GATE(g12a_periphs,			HHI_GCLK_MPEG0,	7);
4180static MESON_GATE(g12a_spicc_0,			HHI_GCLK_MPEG0,	8);
4181static MESON_GATE(g12a_i2c,			HHI_GCLK_MPEG0,	9);
4182static MESON_GATE(g12a_sana,			HHI_GCLK_MPEG0,	10);
4183static MESON_GATE(g12a_sd,			HHI_GCLK_MPEG0,	11);
4184static MESON_GATE(g12a_rng0,			HHI_GCLK_MPEG0,	12);
4185static MESON_GATE(g12a_uart0,			HHI_GCLK_MPEG0,	13);
4186static MESON_GATE(g12a_spicc_1,			HHI_GCLK_MPEG0,	14);
4187static MESON_GATE(g12a_hiu_reg,			HHI_GCLK_MPEG0,	19);
4188static MESON_GATE(g12a_mipi_dsi_phy,		HHI_GCLK_MPEG0,	20);
4189static MESON_GATE(g12a_assist_misc,		HHI_GCLK_MPEG0,	23);
4190static MESON_GATE(g12a_emmc_a,			HHI_GCLK_MPEG0,	4);
4191static MESON_GATE(g12a_emmc_b,			HHI_GCLK_MPEG0,	25);
4192static MESON_GATE(g12a_emmc_c,			HHI_GCLK_MPEG0,	26);
4193static MESON_GATE(g12a_audio_codec,		HHI_GCLK_MPEG0,	28);
4194
4195static MESON_GATE(g12a_audio,			HHI_GCLK_MPEG1,	0);
4196static MESON_GATE(g12a_eth_core,		HHI_GCLK_MPEG1,	3);
4197static MESON_GATE(g12a_demux,			HHI_GCLK_MPEG1,	4);
4198static MESON_GATE(g12a_audio_ififo,		HHI_GCLK_MPEG1,	11);
4199static MESON_GATE(g12a_adc,			HHI_GCLK_MPEG1,	13);
4200static MESON_GATE(g12a_uart1,			HHI_GCLK_MPEG1,	16);
4201static MESON_GATE(g12a_g2d,			HHI_GCLK_MPEG1,	20);
4202static MESON_GATE(g12a_reset,			HHI_GCLK_MPEG1,	23);
4203static MESON_GATE(g12a_pcie_comb,		HHI_GCLK_MPEG1,	24);
4204static MESON_GATE(g12a_parser,			HHI_GCLK_MPEG1,	25);
4205static MESON_GATE(g12a_usb_general,		HHI_GCLK_MPEG1,	26);
4206static MESON_GATE(g12a_pcie_phy,		HHI_GCLK_MPEG1,	27);
4207static MESON_GATE(g12a_ahb_arb0,		HHI_GCLK_MPEG1,	29);
4208
4209static MESON_GATE(g12a_ahb_data_bus,		HHI_GCLK_MPEG2,	1);
4210static MESON_GATE(g12a_ahb_ctrl_bus,		HHI_GCLK_MPEG2,	2);
4211static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);
4212static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);
4213static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);
4214static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);
4215static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);
4216static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);
4217static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);
4218static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);
4219
4220static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
4221static MESON_GATE(g12a_vclk2_venci1,		HHI_GCLK_OTHER,	2);
4222static MESON_GATE(g12a_vclk2_vencp0,		HHI_GCLK_OTHER,	3);
4223static MESON_GATE(g12a_vclk2_vencp1,		HHI_GCLK_OTHER,	4);
4224static MESON_GATE(g12a_vclk2_venct0,		HHI_GCLK_OTHER,	5);
4225static MESON_GATE(g12a_vclk2_venct1,		HHI_GCLK_OTHER,	6);
4226static MESON_GATE(g12a_vclk2_other,		HHI_GCLK_OTHER,	7);
4227static MESON_GATE(g12a_vclk2_enci,		HHI_GCLK_OTHER,	8);
4228static MESON_GATE(g12a_vclk2_encp,		HHI_GCLK_OTHER,	9);
4229static MESON_GATE(g12a_dac_clk,			HHI_GCLK_OTHER,	10);
4230static MESON_GATE(g12a_aoclk_gate,		HHI_GCLK_OTHER,	14);
4231static MESON_GATE(g12a_iec958_gate,		HHI_GCLK_OTHER,	16);
4232static MESON_GATE(g12a_enc480p,			HHI_GCLK_OTHER,	20);
4233static MESON_GATE(g12a_rng1,			HHI_GCLK_OTHER,	21);
4234static MESON_GATE(g12a_vclk2_enct,		HHI_GCLK_OTHER,	22);
4235static MESON_GATE(g12a_vclk2_encl,		HHI_GCLK_OTHER,	23);
4236static MESON_GATE(g12a_vclk2_venclmmc,		HHI_GCLK_OTHER,	24);
4237static MESON_GATE(g12a_vclk2_vencl,		HHI_GCLK_OTHER,	25);
4238static MESON_GATE(g12a_vclk2_other1,		HHI_GCLK_OTHER,	26);
4239
4240static MESON_GATE_RO(g12a_dma,			HHI_GCLK_OTHER2, 0);
4241static MESON_GATE_RO(g12a_efuse,		HHI_GCLK_OTHER2, 1);
4242static MESON_GATE_RO(g12a_rom_boot,		HHI_GCLK_OTHER2, 2);
4243static MESON_GATE_RO(g12a_reset_sec,		HHI_GCLK_OTHER2, 3);
4244static MESON_GATE_RO(g12a_sec_ahb_apb3,		HHI_GCLK_OTHER2, 4);
4245
4246/* Array of all clocks provided by this provider */
4247static struct clk_hw_onecell_data g12a_hw_onecell_data = {
4248	.hws = {
4249		[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4250		[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4251		[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4252		[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4253		[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4254		[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4255		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4256		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4257		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4258		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4259		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4260		[CLKID_CLK81]			= &g12a_clk81.hw,
4261		[CLKID_MPLL0]			= &g12a_mpll0.hw,
4262		[CLKID_MPLL1]			= &g12a_mpll1.hw,
4263		[CLKID_MPLL2]			= &g12a_mpll2.hw,
4264		[CLKID_MPLL3]			= &g12a_mpll3.hw,
4265		[CLKID_DDR]			= &g12a_ddr.hw,
4266		[CLKID_DOS]			= &g12a_dos.hw,
4267		[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4268		[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4269		[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4270		[CLKID_ISA]			= &g12a_isa.hw,
4271		[CLKID_PL301]			= &g12a_pl301.hw,
4272		[CLKID_PERIPHS]			= &g12a_periphs.hw,
4273		[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4274		[CLKID_I2C]			= &g12a_i2c.hw,
4275		[CLKID_SANA]			= &g12a_sana.hw,
4276		[CLKID_SD]			= &g12a_sd.hw,
4277		[CLKID_RNG0]			= &g12a_rng0.hw,
4278		[CLKID_UART0]			= &g12a_uart0.hw,
4279		[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4280		[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4281		[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4282		[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4283		[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4284		[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4285		[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4286		[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4287		[CLKID_AUDIO]			= &g12a_audio.hw,
4288		[CLKID_ETH]			= &g12a_eth_core.hw,
4289		[CLKID_DEMUX]			= &g12a_demux.hw,
4290		[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4291		[CLKID_ADC]			= &g12a_adc.hw,
4292		[CLKID_UART1]			= &g12a_uart1.hw,
4293		[CLKID_G2D]			= &g12a_g2d.hw,
4294		[CLKID_RESET]			= &g12a_reset.hw,
4295		[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4296		[CLKID_PARSER]			= &g12a_parser.hw,
4297		[CLKID_USB]			= &g12a_usb_general.hw,
4298		[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4299		[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4300		[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4301		[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4302		[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4303		[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4304		[CLKID_BT656]			= &g12a_bt656.hw,
4305		[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4306		[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4307		[CLKID_UART2]			= &g12a_uart2.hw,
4308		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4309		[CLKID_GIC]			= &g12a_gic.hw,
4310		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4311		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4312		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4313		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4314		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4315		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4316		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4317		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4318		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4319		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4320		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4321		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4322		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4323		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4324		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4325		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4326		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4327		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4328		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4329		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4330		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4331		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4332		[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4333		[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4334		[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4335		[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4336		[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4337		[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4338		[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4339		[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4340		[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4341		[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4342		[CLKID_ENC480P]			= &g12a_enc480p.hw,
4343		[CLKID_RNG1]			= &g12a_rng1.hw,
4344		[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4345		[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4346		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4347		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4348		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4349		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4350		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4351		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4352		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4353		[CLKID_DMA]			= &g12a_dma.hw,
4354		[CLKID_EFUSE]			= &g12a_efuse.hw,
4355		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4356		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4357		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4358		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4359		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4360		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4361		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4362		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4363		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4364		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4365		[CLKID_VPU]			= &g12a_vpu.hw,
4366		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4367		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4368		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4369		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4370		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4371		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4372		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4373		[CLKID_VAPB]			= &g12a_vapb.hw,
4374		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4375		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4376		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4377		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4378		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4379		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4380		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4381		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4382		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4383		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4384		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4385		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4386		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4387		[CLKID_VCLK]			= &g12a_vclk.hw,
4388		[CLKID_VCLK2]			= &g12a_vclk2.hw,
4389		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4390		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4391		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4392		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4393		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4394		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4395		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4396		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4397		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4398		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4399		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4400		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4401		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4402		[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4403		[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4404		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4405		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4406		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4407		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4408		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4409		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4410		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4411		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4412		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4413		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4414		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4415		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4416		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4417		[CLKID_HDMI]			= &g12a_hdmi.hw,
4418		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4419		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4420		[CLKID_MALI_0]			= &g12a_mali_0.hw,
4421		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4422		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4423		[CLKID_MALI_1]			= &g12a_mali_1.hw,
4424		[CLKID_MALI]			= &g12a_mali.hw,
4425		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4426		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4427		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4428		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4429		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4430		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4431		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4432		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4433		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4434		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4435		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4436		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
4437		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4438		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4439		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4440		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4441		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4442		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4443		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4444		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4445		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4446		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4447		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4448		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4449		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4450		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4451		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4452		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4453		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4454		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4455		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4456		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4457		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4458		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4459		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4460		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4461		[CLKID_TS]			= &g12a_ts.hw,
4462		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4463		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4464		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4465		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4466		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4467		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4468		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4469		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4470		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4471		[NR_CLKS]			= NULL,
4472	},
4473	.num = NR_CLKS,
4474};
4475
4476static struct clk_hw_onecell_data g12b_hw_onecell_data = {
4477	.hws = {
4478		[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4479		[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4480		[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4481		[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4482		[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4483		[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4484		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4485		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4486		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4487		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4488		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4489		[CLKID_CLK81]			= &g12a_clk81.hw,
4490		[CLKID_MPLL0]			= &g12a_mpll0.hw,
4491		[CLKID_MPLL1]			= &g12a_mpll1.hw,
4492		[CLKID_MPLL2]			= &g12a_mpll2.hw,
4493		[CLKID_MPLL3]			= &g12a_mpll3.hw,
4494		[CLKID_DDR]			= &g12a_ddr.hw,
4495		[CLKID_DOS]			= &g12a_dos.hw,
4496		[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4497		[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4498		[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4499		[CLKID_ISA]			= &g12a_isa.hw,
4500		[CLKID_PL301]			= &g12a_pl301.hw,
4501		[CLKID_PERIPHS]			= &g12a_periphs.hw,
4502		[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4503		[CLKID_I2C]			= &g12a_i2c.hw,
4504		[CLKID_SANA]			= &g12a_sana.hw,
4505		[CLKID_SD]			= &g12a_sd.hw,
4506		[CLKID_RNG0]			= &g12a_rng0.hw,
4507		[CLKID_UART0]			= &g12a_uart0.hw,
4508		[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4509		[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4510		[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4511		[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4512		[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4513		[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4514		[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4515		[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4516		[CLKID_AUDIO]			= &g12a_audio.hw,
4517		[CLKID_ETH]			= &g12a_eth_core.hw,
4518		[CLKID_DEMUX]			= &g12a_demux.hw,
4519		[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4520		[CLKID_ADC]			= &g12a_adc.hw,
4521		[CLKID_UART1]			= &g12a_uart1.hw,
4522		[CLKID_G2D]			= &g12a_g2d.hw,
4523		[CLKID_RESET]			= &g12a_reset.hw,
4524		[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4525		[CLKID_PARSER]			= &g12a_parser.hw,
4526		[CLKID_USB]			= &g12a_usb_general.hw,
4527		[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4528		[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4529		[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4530		[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4531		[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4532		[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4533		[CLKID_BT656]			= &g12a_bt656.hw,
4534		[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4535		[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4536		[CLKID_UART2]			= &g12a_uart2.hw,
4537		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4538		[CLKID_GIC]			= &g12a_gic.hw,
4539		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4540		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4541		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4542		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4543		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4544		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4545		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4546		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4547		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4548		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4549		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4550		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4551		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4552		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4553		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4554		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4555		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4556		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4557		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4558		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4559		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4560		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4561		[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4562		[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4563		[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4564		[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4565		[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4566		[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4567		[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4568		[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4569		[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4570		[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4571		[CLKID_ENC480P]			= &g12a_enc480p.hw,
4572		[CLKID_RNG1]			= &g12a_rng1.hw,
4573		[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4574		[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4575		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4576		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4577		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4578		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4579		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4580		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4581		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4582		[CLKID_DMA]			= &g12a_dma.hw,
4583		[CLKID_EFUSE]			= &g12a_efuse.hw,
4584		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4585		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4586		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4587		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4588		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4589		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4590		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4591		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4592		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4593		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4594		[CLKID_VPU]			= &g12a_vpu.hw,
4595		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4596		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4597		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4598		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4599		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4600		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4601		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4602		[CLKID_VAPB]			= &g12a_vapb.hw,
4603		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4604		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4605		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4606		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4607		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4608		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4609		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4610		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4611		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4612		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4613		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4614		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4615		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4616		[CLKID_VCLK]			= &g12a_vclk.hw,
4617		[CLKID_VCLK2]			= &g12a_vclk2.hw,
4618		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4619		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4620		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4621		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4622		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4623		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4624		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4625		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4626		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4627		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4628		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4629		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4630		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4631		[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4632		[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4633		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4634		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4635		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4636		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4637		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4638		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4639		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4640		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4641		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4642		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4643		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4644		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4645		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4646		[CLKID_HDMI]			= &g12a_hdmi.hw,
4647		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4648		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4649		[CLKID_MALI_0]			= &g12a_mali_0.hw,
4650		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4651		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4652		[CLKID_MALI_1]			= &g12a_mali_1.hw,
4653		[CLKID_MALI]			= &g12a_mali.hw,
4654		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4655		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4656		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4657		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4658		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4659		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4660		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4661		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4662		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4663		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4664		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4665		[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
4666		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4667		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4668		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4669		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4670		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4671		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4672		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4673		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4674		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4675		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4676		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4677		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4678		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4679		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4680		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4681		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4682		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4683		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4684		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4685		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4686		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4687		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4688		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4689		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4690		[CLKID_TS]			= &g12a_ts.hw,
4691		[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
4692		[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
4693		[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
4694		[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
4695		[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
4696		[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
4697		[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
4698		[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
4699		[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
4700		[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
4701		[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
4702		[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
4703		[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
4704		[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
4705		[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
4706		[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
4707		[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
4708		[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
4709		[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
4710		[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
4711		[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
4712		[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
4713		[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
4714		[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
4715		[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
4716		[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
4717		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
4718		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
4719		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
4720		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4721		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4722		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4723		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4724		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4725		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4726		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
4727		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
4728		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
4729		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
4730		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
4731		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
4732		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4733		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4734		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4735		[NR_CLKS]			= NULL,
4736	},
4737	.num = NR_CLKS,
4738};
4739
4740static struct clk_hw_onecell_data sm1_hw_onecell_data = {
4741	.hws = {
4742		[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4743		[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4744		[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4745		[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4746		[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4747		[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4748		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4749		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4750		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4751		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4752		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4753		[CLKID_CLK81]			= &g12a_clk81.hw,
4754		[CLKID_MPLL0]			= &g12a_mpll0.hw,
4755		[CLKID_MPLL1]			= &g12a_mpll1.hw,
4756		[CLKID_MPLL2]			= &g12a_mpll2.hw,
4757		[CLKID_MPLL3]			= &g12a_mpll3.hw,
4758		[CLKID_DDR]			= &g12a_ddr.hw,
4759		[CLKID_DOS]			= &g12a_dos.hw,
4760		[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4761		[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4762		[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4763		[CLKID_ISA]			= &g12a_isa.hw,
4764		[CLKID_PL301]			= &g12a_pl301.hw,
4765		[CLKID_PERIPHS]			= &g12a_periphs.hw,
4766		[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4767		[CLKID_I2C]			= &g12a_i2c.hw,
4768		[CLKID_SANA]			= &g12a_sana.hw,
4769		[CLKID_SD]			= &g12a_sd.hw,
4770		[CLKID_RNG0]			= &g12a_rng0.hw,
4771		[CLKID_UART0]			= &g12a_uart0.hw,
4772		[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4773		[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4774		[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4775		[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4776		[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4777		[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4778		[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4779		[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4780		[CLKID_AUDIO]			= &g12a_audio.hw,
4781		[CLKID_ETH]			= &g12a_eth_core.hw,
4782		[CLKID_DEMUX]			= &g12a_demux.hw,
4783		[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4784		[CLKID_ADC]			= &g12a_adc.hw,
4785		[CLKID_UART1]			= &g12a_uart1.hw,
4786		[CLKID_G2D]			= &g12a_g2d.hw,
4787		[CLKID_RESET]			= &g12a_reset.hw,
4788		[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4789		[CLKID_PARSER]			= &g12a_parser.hw,
4790		[CLKID_USB]			= &g12a_usb_general.hw,
4791		[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4792		[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4793		[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4794		[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4795		[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4796		[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4797		[CLKID_BT656]			= &g12a_bt656.hw,
4798		[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4799		[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4800		[CLKID_UART2]			= &g12a_uart2.hw,
4801		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4802		[CLKID_GIC]			= &g12a_gic.hw,
4803		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4804		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4805		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4806		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4807		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4808		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4809		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4810		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4811		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4812		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4813		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4814		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4815		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4816		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4817		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4818		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4819		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4820		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4821		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4822		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4823		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4824		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4825		[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4826		[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4827		[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4828		[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4829		[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4830		[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4831		[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4832		[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4833		[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4834		[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4835		[CLKID_ENC480P]			= &g12a_enc480p.hw,
4836		[CLKID_RNG1]			= &g12a_rng1.hw,
4837		[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4838		[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4839		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4840		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4841		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4842		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4843		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4844		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4845		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4846		[CLKID_DMA]			= &g12a_dma.hw,
4847		[CLKID_EFUSE]			= &g12a_efuse.hw,
4848		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4849		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4850		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4851		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4852		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4853		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4854		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4855		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4856		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4857		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4858		[CLKID_VPU]			= &g12a_vpu.hw,
4859		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4860		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4861		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4862		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4863		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4864		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4865		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4866		[CLKID_VAPB]			= &g12a_vapb.hw,
4867		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4868		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4869		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4870		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4871		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4872		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4873		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4874		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4875		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4876		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4877		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4878		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4879		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4880		[CLKID_VCLK]			= &g12a_vclk.hw,
4881		[CLKID_VCLK2]			= &g12a_vclk2.hw,
4882		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4883		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4884		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4885		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4886		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4887		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4888		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4889		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4890		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4891		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4892		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4893		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4894		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4895		[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4896		[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4897		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4898		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4899		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4900		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4901		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4902		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4903		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4904		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4905		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4906		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4907		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4908		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4909		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4910		[CLKID_HDMI]			= &g12a_hdmi.hw,
4911		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4912		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4913		[CLKID_MALI_0]			= &g12a_mali_0.hw,
4914		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4915		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4916		[CLKID_MALI_1]			= &g12a_mali_1.hw,
4917		[CLKID_MALI]			= &g12a_mali.hw,
4918		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4919		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4920		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4921		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4922		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4923		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4924		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4925		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4926		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4927		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4928		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4929		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
4930		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4931		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4932		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4933		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4934		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4935		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4936		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4937		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4938		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4939		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4940		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4941		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4942		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4943		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4944		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4945		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4946		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4947		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4948		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4949		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4950		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4951		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4952		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4953		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4954		[CLKID_TS]			= &g12a_ts.hw,
4955		[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
4956		[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
4957		[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
4958		[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
4959		[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
4960		[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
4961		[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
4962		[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
4963		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
4964		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
4965		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
4966		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
4967		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
4968		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
4969		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4970		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4971		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4972		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4973		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4974		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4975		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
4976		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
4977		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
4978		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
4979		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
4980		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
4981		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4982		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4983		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4984		[NR_CLKS]			= NULL,
4985	},
4986	.num = NR_CLKS,
4987};
4988
4989/* Convenience table to populate regmap in .probe */
4990static struct clk_regmap *const g12a_clk_regmaps[] = {
4991	&g12a_clk81,
4992	&g12a_dos,
4993	&g12a_ddr,
4994	&g12a_audio_locker,
4995	&g12a_mipi_dsi_host,
4996	&g12a_eth_phy,
4997	&g12a_isa,
4998	&g12a_pl301,
4999	&g12a_periphs,
5000	&g12a_spicc_0,
5001	&g12a_i2c,
5002	&g12a_sana,
5003	&g12a_sd,
5004	&g12a_rng0,
5005	&g12a_uart0,
5006	&g12a_spicc_1,
5007	&g12a_hiu_reg,
5008	&g12a_mipi_dsi_phy,
5009	&g12a_assist_misc,
5010	&g12a_emmc_a,
5011	&g12a_emmc_b,
5012	&g12a_emmc_c,
5013	&g12a_audio_codec,
5014	&g12a_audio,
5015	&g12a_eth_core,
5016	&g12a_demux,
5017	&g12a_audio_ififo,
5018	&g12a_adc,
5019	&g12a_uart1,
5020	&g12a_g2d,
5021	&g12a_reset,
5022	&g12a_pcie_comb,
5023	&g12a_parser,
5024	&g12a_usb_general,
5025	&g12a_pcie_phy,
5026	&g12a_ahb_arb0,
5027	&g12a_ahb_data_bus,
5028	&g12a_ahb_ctrl_bus,
5029	&g12a_htx_hdcp22,
5030	&g12a_htx_pclk,
5031	&g12a_bt656,
5032	&g12a_usb1_to_ddr,
5033	&g12a_mmc_pclk,
5034	&g12a_uart2,
5035	&g12a_vpu_intr,
5036	&g12a_gic,
5037	&g12a_sd_emmc_a_clk0,
5038	&g12a_sd_emmc_b_clk0,
5039	&g12a_sd_emmc_c_clk0,
5040	&g12a_mpeg_clk_div,
5041	&g12a_sd_emmc_a_clk0_div,
5042	&g12a_sd_emmc_b_clk0_div,
5043	&g12a_sd_emmc_c_clk0_div,
5044	&g12a_mpeg_clk_sel,
5045	&g12a_sd_emmc_a_clk0_sel,
5046	&g12a_sd_emmc_b_clk0_sel,
5047	&g12a_sd_emmc_c_clk0_sel,
5048	&g12a_mpll0,
5049	&g12a_mpll1,
5050	&g12a_mpll2,
5051	&g12a_mpll3,
5052	&g12a_mpll0_div,
5053	&g12a_mpll1_div,
5054	&g12a_mpll2_div,
5055	&g12a_mpll3_div,
5056	&g12a_fixed_pll,
5057	&g12a_sys_pll,
5058	&g12a_gp0_pll,
5059	&g12a_hifi_pll,
5060	&g12a_vclk2_venci0,
5061	&g12a_vclk2_venci1,
5062	&g12a_vclk2_vencp0,
5063	&g12a_vclk2_vencp1,
5064	&g12a_vclk2_venct0,
5065	&g12a_vclk2_venct1,
5066	&g12a_vclk2_other,
5067	&g12a_vclk2_enci,
5068	&g12a_vclk2_encp,
5069	&g12a_dac_clk,
5070	&g12a_aoclk_gate,
5071	&g12a_iec958_gate,
5072	&g12a_enc480p,
5073	&g12a_rng1,
5074	&g12a_vclk2_enct,
5075	&g12a_vclk2_encl,
5076	&g12a_vclk2_venclmmc,
5077	&g12a_vclk2_vencl,
5078	&g12a_vclk2_other1,
5079	&g12a_fixed_pll_dco,
5080	&g12a_sys_pll_dco,
5081	&g12a_gp0_pll_dco,
5082	&g12a_hifi_pll_dco,
5083	&g12a_fclk_div2,
5084	&g12a_fclk_div3,
5085	&g12a_fclk_div4,
5086	&g12a_fclk_div5,
5087	&g12a_fclk_div7,
5088	&g12a_fclk_div2p5,
5089	&g12a_dma,
5090	&g12a_efuse,
5091	&g12a_rom_boot,
5092	&g12a_reset_sec,
5093	&g12a_sec_ahb_apb3,
5094	&g12a_vpu_0_sel,
5095	&g12a_vpu_0_div,
5096	&g12a_vpu_0,
5097	&g12a_vpu_1_sel,
5098	&g12a_vpu_1_div,
5099	&g12a_vpu_1,
5100	&g12a_vpu,
5101	&g12a_vapb_0_sel,
5102	&g12a_vapb_0_div,
5103	&g12a_vapb_0,
5104	&g12a_vapb_1_sel,
5105	&g12a_vapb_1_div,
5106	&g12a_vapb_1,
5107	&g12a_vapb_sel,
5108	&g12a_vapb,
5109	&g12a_hdmi_pll_dco,
5110	&g12a_hdmi_pll_od,
5111	&g12a_hdmi_pll_od2,
5112	&g12a_hdmi_pll,
5113	&g12a_vid_pll_div,
5114	&g12a_vid_pll_sel,
5115	&g12a_vid_pll,
5116	&g12a_vclk_sel,
5117	&g12a_vclk2_sel,
5118	&g12a_vclk_input,
5119	&g12a_vclk2_input,
5120	&g12a_vclk_div,
5121	&g12a_vclk2_div,
5122	&g12a_vclk,
5123	&g12a_vclk2,
5124	&g12a_vclk_div1,
5125	&g12a_vclk_div2_en,
5126	&g12a_vclk_div4_en,
5127	&g12a_vclk_div6_en,
5128	&g12a_vclk_div12_en,
5129	&g12a_vclk2_div1,
5130	&g12a_vclk2_div2_en,
5131	&g12a_vclk2_div4_en,
5132	&g12a_vclk2_div6_en,
5133	&g12a_vclk2_div12_en,
5134	&g12a_cts_enci_sel,
5135	&g12a_cts_encp_sel,
5136	&g12a_cts_vdac_sel,
5137	&g12a_hdmi_tx_sel,
5138	&g12a_cts_enci,
5139	&g12a_cts_encp,
5140	&g12a_cts_vdac,
5141	&g12a_hdmi_tx,
5142	&g12a_hdmi_sel,
5143	&g12a_hdmi_div,
5144	&g12a_hdmi,
5145	&g12a_mali_0_sel,
5146	&g12a_mali_0_div,
5147	&g12a_mali_0,
5148	&g12a_mali_1_sel,
5149	&g12a_mali_1_div,
5150	&g12a_mali_1,
5151	&g12a_mali,
5152	&g12a_mpll_50m,
5153	&g12a_sys_pll_div16_en,
5154	&g12a_cpu_clk_premux0,
5155	&g12a_cpu_clk_mux0_div,
5156	&g12a_cpu_clk_postmux0,
5157	&g12a_cpu_clk_premux1,
5158	&g12a_cpu_clk_mux1_div,
5159	&g12a_cpu_clk_postmux1,
5160	&g12a_cpu_clk_dyn,
5161	&g12a_cpu_clk,
5162	&g12a_cpu_clk_div16_en,
5163	&g12a_cpu_clk_apb_div,
5164	&g12a_cpu_clk_apb,
5165	&g12a_cpu_clk_atb_div,
5166	&g12a_cpu_clk_atb,
5167	&g12a_cpu_clk_axi_div,
5168	&g12a_cpu_clk_axi,
5169	&g12a_cpu_clk_trace_div,
5170	&g12a_cpu_clk_trace,
5171	&g12a_pcie_pll_od,
5172	&g12a_pcie_pll_dco,
5173	&g12a_vdec_1_sel,
5174	&g12a_vdec_1_div,
5175	&g12a_vdec_1,
5176	&g12a_vdec_hevc_sel,
5177	&g12a_vdec_hevc_div,
5178	&g12a_vdec_hevc,
5179	&g12a_vdec_hevcf_sel,
5180	&g12a_vdec_hevcf_div,
5181	&g12a_vdec_hevcf,
5182	&g12a_ts_div,
5183	&g12a_ts,
5184	&g12b_cpu_clk,
5185	&g12b_sys1_pll_dco,
5186	&g12b_sys1_pll,
5187	&g12b_sys1_pll_div16_en,
5188	&g12b_cpub_clk_premux0,
5189	&g12b_cpub_clk_mux0_div,
5190	&g12b_cpub_clk_postmux0,
5191	&g12b_cpub_clk_premux1,
5192	&g12b_cpub_clk_mux1_div,
5193	&g12b_cpub_clk_postmux1,
5194	&g12b_cpub_clk_dyn,
5195	&g12b_cpub_clk,
5196	&g12b_cpub_clk_div16_en,
5197	&g12b_cpub_clk_apb_sel,
5198	&g12b_cpub_clk_apb,
5199	&g12b_cpub_clk_atb_sel,
5200	&g12b_cpub_clk_atb,
5201	&g12b_cpub_clk_axi_sel,
5202	&g12b_cpub_clk_axi,
5203	&g12b_cpub_clk_trace_sel,
5204	&g12b_cpub_clk_trace,
5205	&sm1_gp1_pll_dco,
5206	&sm1_gp1_pll,
5207	&sm1_dsu_clk_premux0,
5208	&sm1_dsu_clk_premux1,
5209	&sm1_dsu_clk_mux0_div,
5210	&sm1_dsu_clk_postmux0,
5211	&sm1_dsu_clk_mux1_div,
5212	&sm1_dsu_clk_postmux1,
5213	&sm1_dsu_clk_dyn,
5214	&sm1_dsu_final_clk,
5215	&sm1_dsu_clk,
5216	&sm1_cpu1_clk,
5217	&sm1_cpu2_clk,
5218	&sm1_cpu3_clk,
5219	&g12a_spicc0_sclk_sel,
5220	&g12a_spicc0_sclk_div,
5221	&g12a_spicc0_sclk,
5222	&g12a_spicc1_sclk_sel,
5223	&g12a_spicc1_sclk_div,
5224	&g12a_spicc1_sclk,
5225	&sm1_nna_axi_clk_sel,
5226	&sm1_nna_axi_clk_div,
5227	&sm1_nna_axi_clk,
5228	&sm1_nna_core_clk_sel,
5229	&sm1_nna_core_clk_div,
5230	&sm1_nna_core_clk,
5231	&g12a_mipi_dsi_pxclk_sel,
5232	&g12a_mipi_dsi_pxclk_div,
5233	&g12a_mipi_dsi_pxclk,
5234};
5235
5236static const struct reg_sequence g12a_init_regs[] = {
5237	{ .reg = HHI_MPLL_CNTL0,	.def = 0x00000543 },
5238};
5239
5240#define DVFS_CON_ID "dvfs"
5241
5242static int meson_g12a_dvfs_setup_common(struct device *dev,
5243					struct clk_hw **hws)
5244{
5245	struct clk *notifier_clk;
5246	struct clk_hw *xtal;
5247	int ret;
5248
5249	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5250
5251	/* Setup clock notifier for cpu_clk_postmux0 */
5252	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5253	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5254					   DVFS_CON_ID);
5255	ret = devm_clk_notifier_register(dev, notifier_clk,
5256					 &g12a_cpu_clk_postmux0_nb_data.nb);
5257	if (ret) {
5258		dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
5259		return ret;
5260	}
5261
5262	/* Setup clock notifier for cpu_clk_dyn mux */
5263	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5264					   DVFS_CON_ID);
5265	ret = devm_clk_notifier_register(dev, notifier_clk,
5266					 &g12a_cpu_clk_mux_nb);
5267	if (ret) {
5268		dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
5269		return ret;
5270	}
5271
5272	return 0;
5273}
5274
5275static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5276{
5277	struct clk_hw **hws = g12b_hw_onecell_data.hws;
5278	struct device *dev = &pdev->dev;
5279	struct clk *notifier_clk;
5280	struct clk_hw *xtal;
5281	int ret;
5282
5283	ret = meson_g12a_dvfs_setup_common(dev, hws);
5284	if (ret)
5285		return ret;
5286
5287	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5288
5289	/* Setup clock notifier for cpu_clk mux */
5290	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5291					   DVFS_CON_ID);
5292	ret = devm_clk_notifier_register(dev, notifier_clk,
5293					 &g12a_cpu_clk_mux_nb);
5294	if (ret) {
5295		dev_err(dev, "failed to register the cpu_clk notifier\n");
5296		return ret;
5297	}
5298
5299	/* Setup clock notifier for sys1_pll */
5300	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5301					   DVFS_CON_ID);
5302	ret = devm_clk_notifier_register(dev, notifier_clk,
5303					 &g12b_cpu_clk_sys1_pll_nb_data.nb);
5304	if (ret) {
5305		dev_err(dev, "failed to register the sys1_pll notifier\n");
5306		return ret;
5307	}
5308
5309	/* Add notifiers for the second CPU cluster */
5310
5311	/* Setup clock notifier for cpub_clk_postmux0 */
5312	g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5313	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5314					   DVFS_CON_ID);
5315	ret = devm_clk_notifier_register(dev, notifier_clk,
5316					 &g12b_cpub_clk_postmux0_nb_data.nb);
5317	if (ret) {
5318		dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
5319		return ret;
5320	}
5321
5322	/* Setup clock notifier for cpub_clk_dyn mux */
5323	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5324	ret = devm_clk_notifier_register(dev, notifier_clk,
5325					 &g12a_cpu_clk_mux_nb);
5326	if (ret) {
5327		dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
5328		return ret;
5329	}
5330
5331	/* Setup clock notifier for cpub_clk mux */
5332	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5333	ret = devm_clk_notifier_register(dev, notifier_clk,
5334					 &g12a_cpu_clk_mux_nb);
5335	if (ret) {
5336		dev_err(dev, "failed to register the cpub_clk notifier\n");
5337		return ret;
5338	}
5339
5340	/* Setup clock notifier for sys_pll */
5341	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5342	ret = devm_clk_notifier_register(dev, notifier_clk,
5343					 &g12b_cpub_clk_sys_pll_nb_data.nb);
5344	if (ret) {
5345		dev_err(dev, "failed to register the sys_pll notifier\n");
5346		return ret;
5347	}
5348
5349	return 0;
5350}
5351
5352static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5353{
5354	struct clk_hw **hws = g12a_hw_onecell_data.hws;
5355	struct device *dev = &pdev->dev;
5356	struct clk *notifier_clk;
5357	int ret;
5358
5359	ret = meson_g12a_dvfs_setup_common(dev, hws);
5360	if (ret)
5361		return ret;
5362
5363	/* Setup clock notifier for cpu_clk mux */
5364	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5365	ret = devm_clk_notifier_register(dev, notifier_clk,
5366				    &g12a_cpu_clk_mux_nb);
5367	if (ret) {
5368		dev_err(dev, "failed to register the cpu_clk notifier\n");
5369		return ret;
5370	}
5371
5372	/* Setup clock notifier for sys_pll */
5373	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5374	ret = devm_clk_notifier_register(dev, notifier_clk,
5375					 &g12a_sys_pll_nb_data.nb);
5376	if (ret) {
5377		dev_err(dev, "failed to register the sys_pll notifier\n");
5378		return ret;
5379	}
5380
5381	return 0;
5382}
5383
5384struct meson_g12a_data {
5385	const struct meson_eeclkc_data eeclkc_data;
5386	int (*dvfs_setup)(struct platform_device *pdev);
5387};
5388
5389static int meson_g12a_probe(struct platform_device *pdev)
5390{
5391	const struct meson_eeclkc_data *eeclkc_data;
5392	const struct meson_g12a_data *g12a_data;
5393	int ret;
5394
5395	eeclkc_data = of_device_get_match_data(&pdev->dev);
5396	if (!eeclkc_data)
5397		return -EINVAL;
5398
5399	ret = meson_eeclkc_probe(pdev);
5400	if (ret)
5401		return ret;
5402
5403	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5404				 eeclkc_data);
5405
5406	if (g12a_data->dvfs_setup)
5407		return g12a_data->dvfs_setup(pdev);
5408
5409	return 0;
5410}
5411
5412static const struct meson_g12a_data g12a_clkc_data = {
5413	.eeclkc_data = {
5414		.regmap_clks = g12a_clk_regmaps,
5415		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5416		.hw_onecell_data = &g12a_hw_onecell_data,
5417		.init_regs = g12a_init_regs,
5418		.init_count = ARRAY_SIZE(g12a_init_regs),
5419	},
5420	.dvfs_setup = meson_g12a_dvfs_setup,
5421};
5422
5423static const struct meson_g12a_data g12b_clkc_data = {
5424	.eeclkc_data = {
5425		.regmap_clks = g12a_clk_regmaps,
5426		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5427		.hw_onecell_data = &g12b_hw_onecell_data,
5428	},
5429	.dvfs_setup = meson_g12b_dvfs_setup,
5430};
5431
5432static const struct meson_g12a_data sm1_clkc_data = {
5433	.eeclkc_data = {
5434		.regmap_clks = g12a_clk_regmaps,
5435		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5436		.hw_onecell_data = &sm1_hw_onecell_data,
5437	},
5438	.dvfs_setup = meson_g12a_dvfs_setup,
5439};
5440
5441static const struct of_device_id clkc_match_table[] = {
5442	{
5443		.compatible = "amlogic,g12a-clkc",
5444		.data = &g12a_clkc_data.eeclkc_data
5445	},
5446	{
5447		.compatible = "amlogic,g12b-clkc",
5448		.data = &g12b_clkc_data.eeclkc_data
5449	},
5450	{
5451		.compatible = "amlogic,sm1-clkc",
5452		.data = &sm1_clkc_data.eeclkc_data
5453	},
5454	{}
5455};
5456MODULE_DEVICE_TABLE(of, clkc_match_table);
5457
5458static struct platform_driver g12a_driver = {
5459	.probe		= meson_g12a_probe,
5460	.driver		= {
5461		.name	= "g12a-clkc",
5462		.of_match_table = clkc_match_table,
5463	},
5464};
5465
5466module_platform_driver(g12a_driver);
5467MODULE_LICENSE("GPL v2");