Loading...
1/*
2 * drivers/pwm/pwm-tegra.c
3 *
4 * Tegra pulse-width-modulation controller driver
5 *
6 * Copyright (c) 2010, NVIDIA Corporation.
7 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 */
23
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/of.h>
29#include <linux/pwm.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32
33#define PWM_ENABLE (1 << 31)
34#define PWM_DUTY_WIDTH 8
35#define PWM_DUTY_SHIFT 16
36#define PWM_SCALE_WIDTH 13
37#define PWM_SCALE_SHIFT 0
38
39#define NUM_PWM 4
40
41struct tegra_pwm_chip {
42 struct pwm_chip chip;
43 struct device *dev;
44
45 struct clk *clk;
46
47 void __iomem *mmio_base;
48};
49
50static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
51{
52 return container_of(chip, struct tegra_pwm_chip, chip);
53}
54
55static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
56{
57 return readl(chip->mmio_base + (num << 4));
58}
59
60static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
61 unsigned long val)
62{
63 writel(val, chip->mmio_base + (num << 4));
64}
65
66static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
67 int duty_ns, int period_ns)
68{
69 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
70 unsigned long long c;
71 unsigned long rate, hz;
72 u32 val = 0;
73 int err;
74
75 /*
76 * Convert from duty_ns / period_ns to a fixed number of duty ticks
77 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
78 * nearest integer during division.
79 */
80 c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
81 do_div(c, period_ns);
82
83 val = (u32)c << PWM_DUTY_SHIFT;
84
85 /*
86 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
87 * cycles at the PWM clock rate will take period_ns nanoseconds.
88 */
89 rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
90 hz = NSEC_PER_SEC / period_ns;
91
92 rate = (rate + (hz / 2)) / hz;
93
94 /*
95 * Since the actual PWM divider is the register's frequency divider
96 * field minus 1, we need to decrement to get the correct value to
97 * write to the register.
98 */
99 if (rate > 0)
100 rate--;
101
102 /*
103 * Make sure that the rate will fit in the register's frequency
104 * divider field.
105 */
106 if (rate >> PWM_SCALE_WIDTH)
107 return -EINVAL;
108
109 val |= rate << PWM_SCALE_SHIFT;
110
111 /*
112 * If the PWM channel is disabled, make sure to turn on the clock
113 * before writing the register. Otherwise, keep it enabled.
114 */
115 if (!pwm_is_enabled(pwm)) {
116 err = clk_prepare_enable(pc->clk);
117 if (err < 0)
118 return err;
119 } else
120 val |= PWM_ENABLE;
121
122 pwm_writel(pc, pwm->hwpwm, val);
123
124 /*
125 * If the PWM is not enabled, turn the clock off again to save power.
126 */
127 if (!pwm_is_enabled(pwm))
128 clk_disable_unprepare(pc->clk);
129
130 return 0;
131}
132
133static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
134{
135 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
136 int rc = 0;
137 u32 val;
138
139 rc = clk_prepare_enable(pc->clk);
140 if (rc < 0)
141 return rc;
142
143 val = pwm_readl(pc, pwm->hwpwm);
144 val |= PWM_ENABLE;
145 pwm_writel(pc, pwm->hwpwm, val);
146
147 return 0;
148}
149
150static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
151{
152 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
153 u32 val;
154
155 val = pwm_readl(pc, pwm->hwpwm);
156 val &= ~PWM_ENABLE;
157 pwm_writel(pc, pwm->hwpwm, val);
158
159 clk_disable_unprepare(pc->clk);
160}
161
162static const struct pwm_ops tegra_pwm_ops = {
163 .config = tegra_pwm_config,
164 .enable = tegra_pwm_enable,
165 .disable = tegra_pwm_disable,
166 .owner = THIS_MODULE,
167};
168
169static int tegra_pwm_probe(struct platform_device *pdev)
170{
171 struct tegra_pwm_chip *pwm;
172 struct resource *r;
173 int ret;
174
175 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
176 if (!pwm)
177 return -ENOMEM;
178
179 pwm->dev = &pdev->dev;
180
181 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
182 pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
183 if (IS_ERR(pwm->mmio_base))
184 return PTR_ERR(pwm->mmio_base);
185
186 platform_set_drvdata(pdev, pwm);
187
188 pwm->clk = devm_clk_get(&pdev->dev, NULL);
189 if (IS_ERR(pwm->clk))
190 return PTR_ERR(pwm->clk);
191
192 pwm->chip.dev = &pdev->dev;
193 pwm->chip.ops = &tegra_pwm_ops;
194 pwm->chip.base = -1;
195 pwm->chip.npwm = NUM_PWM;
196
197 ret = pwmchip_add(&pwm->chip);
198 if (ret < 0) {
199 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
200 return ret;
201 }
202
203 return 0;
204}
205
206static int tegra_pwm_remove(struct platform_device *pdev)
207{
208 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
209 int i;
210
211 if (WARN_ON(!pc))
212 return -ENODEV;
213
214 for (i = 0; i < NUM_PWM; i++) {
215 struct pwm_device *pwm = &pc->chip.pwms[i];
216
217 if (!pwm_is_enabled(pwm))
218 if (clk_prepare_enable(pc->clk) < 0)
219 continue;
220
221 pwm_writel(pc, i, 0);
222
223 clk_disable_unprepare(pc->clk);
224 }
225
226 return pwmchip_remove(&pc->chip);
227}
228
229static const struct of_device_id tegra_pwm_of_match[] = {
230 { .compatible = "nvidia,tegra20-pwm" },
231 { .compatible = "nvidia,tegra30-pwm" },
232 { }
233};
234
235MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
236
237static struct platform_driver tegra_pwm_driver = {
238 .driver = {
239 .name = "tegra-pwm",
240 .of_match_table = tegra_pwm_of_match,
241 },
242 .probe = tegra_pwm_probe,
243 .remove = tegra_pwm_remove,
244};
245
246module_platform_driver(tegra_pwm_driver);
247
248MODULE_LICENSE("GPL");
249MODULE_AUTHOR("NVIDIA Corporation");
250MODULE_ALIAS("platform:tegra-pwm");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/pwm/pwm-tegra.c
4 *
5 * Tegra pulse-width-modulation controller driver
6 *
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
9 *
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
14 *
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
17 * frequency for PWM output. The maximum output frequency that can be
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
20 * 408 MHz/256 = 1.6 MHz.
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
22 *
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
24 * To achieve 100% duty cycle, program Bit [24] of this register to
25 * 1’b1. In which case the other bits [23:16] are set to don't care.
26 *
27 * Limitations:
28 * - When PWM is disabled, the output is driven to inactive.
29 * - It does not allow the current PWM period to complete and
30 * stops abruptly.
31 *
32 * - If the register is reconfigured while PWM is running,
33 * it does not complete the currently running period.
34 *
35 * - If the user input duty is beyond acceptible limits,
36 * -EINVAL is returned.
37 */
38
39#include <linux/clk.h>
40#include <linux/err.h>
41#include <linux/io.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/of_device.h>
45#include <linux/pwm.h>
46#include <linux/platform_device.h>
47#include <linux/pinctrl/consumer.h>
48#include <linux/slab.h>
49#include <linux/reset.h>
50
51#define PWM_ENABLE (1 << 31)
52#define PWM_DUTY_WIDTH 8
53#define PWM_DUTY_SHIFT 16
54#define PWM_SCALE_WIDTH 13
55#define PWM_SCALE_SHIFT 0
56
57struct tegra_pwm_soc {
58 unsigned int num_channels;
59
60 /* Maximum IP frequency for given SoCs */
61 unsigned long max_frequency;
62};
63
64struct tegra_pwm_chip {
65 struct pwm_chip chip;
66 struct device *dev;
67
68 struct clk *clk;
69 struct reset_control*rst;
70
71 unsigned long clk_rate;
72 unsigned long min_period_ns;
73
74 void __iomem *regs;
75
76 const struct tegra_pwm_soc *soc;
77};
78
79static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
80{
81 return container_of(chip, struct tegra_pwm_chip, chip);
82}
83
84static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
85{
86 return readl(chip->regs + (num << 4));
87}
88
89static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
90 unsigned long val)
91{
92 writel(val, chip->regs + (num << 4));
93}
94
95static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96 int duty_ns, int period_ns)
97{
98 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
99 unsigned long long c = duty_ns, hz;
100 unsigned long rate, required_clk_rate;
101 u32 val = 0;
102 int err;
103
104 /*
105 * Convert from duty_ns / period_ns to a fixed number of duty ticks
106 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
107 * nearest integer during division.
108 */
109 c *= (1 << PWM_DUTY_WIDTH);
110 c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
111
112 val = (u32)c << PWM_DUTY_SHIFT;
113
114 /*
115 * min period = max clock limit >> PWM_DUTY_WIDTH
116 */
117 if (period_ns < pc->min_period_ns)
118 return -EINVAL;
119
120 /*
121 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
122 * cycles at the PWM clock rate will take period_ns nanoseconds.
123 *
124 * num_channels: If single instance of PWM controller has multiple
125 * channels (e.g. Tegra210 or older) then it is not possible to
126 * configure separate clock rates to each of the channels, in such
127 * case the value stored during probe will be referred.
128 *
129 * If every PWM controller instance has one channel respectively, i.e.
130 * nums_channels == 1 then only the clock rate can be modified
131 * dynamically (e.g. Tegra186 or Tegra194).
132 */
133 if (pc->soc->num_channels == 1) {
134 /*
135 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
136 * with the maximum possible rate that the controller can
137 * provide. Any further lower value can be derived by setting
138 * PFM bits[0:12].
139 *
140 * required_clk_rate is a reference rate for source clock and
141 * it is derived based on user requested period. By setting the
142 * source clock rate as required_clk_rate, PWM controller will
143 * be able to configure the requested period.
144 */
145 required_clk_rate =
146 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
147
148 err = clk_set_rate(pc->clk, required_clk_rate);
149 if (err < 0)
150 return -EINVAL;
151
152 /* Store the new rate for further references */
153 pc->clk_rate = clk_get_rate(pc->clk);
154 }
155
156 rate = pc->clk_rate >> PWM_DUTY_WIDTH;
157
158 /* Consider precision in PWM_SCALE_WIDTH rate calculation */
159 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
160 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
161
162 /*
163 * Since the actual PWM divider is the register's frequency divider
164 * field plus 1, we need to decrement to get the correct value to
165 * write to the register.
166 */
167 if (rate > 0)
168 rate--;
169
170 /*
171 * Make sure that the rate will fit in the register's frequency
172 * divider field.
173 */
174 if (rate >> PWM_SCALE_WIDTH)
175 return -EINVAL;
176
177 val |= rate << PWM_SCALE_SHIFT;
178
179 /*
180 * If the PWM channel is disabled, make sure to turn on the clock
181 * before writing the register. Otherwise, keep it enabled.
182 */
183 if (!pwm_is_enabled(pwm)) {
184 err = clk_prepare_enable(pc->clk);
185 if (err < 0)
186 return err;
187 } else
188 val |= PWM_ENABLE;
189
190 pwm_writel(pc, pwm->hwpwm, val);
191
192 /*
193 * If the PWM is not enabled, turn the clock off again to save power.
194 */
195 if (!pwm_is_enabled(pwm))
196 clk_disable_unprepare(pc->clk);
197
198 return 0;
199}
200
201static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
202{
203 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
204 int rc = 0;
205 u32 val;
206
207 rc = clk_prepare_enable(pc->clk);
208 if (rc < 0)
209 return rc;
210
211 val = pwm_readl(pc, pwm->hwpwm);
212 val |= PWM_ENABLE;
213 pwm_writel(pc, pwm->hwpwm, val);
214
215 return 0;
216}
217
218static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
219{
220 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
221 u32 val;
222
223 val = pwm_readl(pc, pwm->hwpwm);
224 val &= ~PWM_ENABLE;
225 pwm_writel(pc, pwm->hwpwm, val);
226
227 clk_disable_unprepare(pc->clk);
228}
229
230static const struct pwm_ops tegra_pwm_ops = {
231 .config = tegra_pwm_config,
232 .enable = tegra_pwm_enable,
233 .disable = tegra_pwm_disable,
234 .owner = THIS_MODULE,
235};
236
237static int tegra_pwm_probe(struct platform_device *pdev)
238{
239 struct tegra_pwm_chip *pwm;
240 int ret;
241
242 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
243 if (!pwm)
244 return -ENOMEM;
245
246 pwm->soc = of_device_get_match_data(&pdev->dev);
247 pwm->dev = &pdev->dev;
248
249 pwm->regs = devm_platform_ioremap_resource(pdev, 0);
250 if (IS_ERR(pwm->regs))
251 return PTR_ERR(pwm->regs);
252
253 platform_set_drvdata(pdev, pwm);
254
255 pwm->clk = devm_clk_get(&pdev->dev, NULL);
256 if (IS_ERR(pwm->clk))
257 return PTR_ERR(pwm->clk);
258
259 /* Set maximum frequency of the IP */
260 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
261 if (ret < 0) {
262 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
263 return ret;
264 }
265
266 /*
267 * The requested and configured frequency may differ due to
268 * clock register resolutions. Get the configured frequency
269 * so that PWM period can be calculated more accurately.
270 */
271 pwm->clk_rate = clk_get_rate(pwm->clk);
272
273 /* Set minimum limit of PWM period for the IP */
274 pwm->min_period_ns =
275 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
276
277 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
278 if (IS_ERR(pwm->rst)) {
279 ret = PTR_ERR(pwm->rst);
280 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
281 return ret;
282 }
283
284 reset_control_deassert(pwm->rst);
285
286 pwm->chip.dev = &pdev->dev;
287 pwm->chip.ops = &tegra_pwm_ops;
288 pwm->chip.npwm = pwm->soc->num_channels;
289
290 ret = pwmchip_add(&pwm->chip);
291 if (ret < 0) {
292 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
293 reset_control_assert(pwm->rst);
294 return ret;
295 }
296
297 return 0;
298}
299
300static int tegra_pwm_remove(struct platform_device *pdev)
301{
302 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
303
304 pwmchip_remove(&pc->chip);
305
306 reset_control_assert(pc->rst);
307
308 return 0;
309}
310
311#ifdef CONFIG_PM_SLEEP
312static int tegra_pwm_suspend(struct device *dev)
313{
314 return pinctrl_pm_select_sleep_state(dev);
315}
316
317static int tegra_pwm_resume(struct device *dev)
318{
319 return pinctrl_pm_select_default_state(dev);
320}
321#endif
322
323static const struct tegra_pwm_soc tegra20_pwm_soc = {
324 .num_channels = 4,
325 .max_frequency = 48000000UL,
326};
327
328static const struct tegra_pwm_soc tegra186_pwm_soc = {
329 .num_channels = 1,
330 .max_frequency = 102000000UL,
331};
332
333static const struct tegra_pwm_soc tegra194_pwm_soc = {
334 .num_channels = 1,
335 .max_frequency = 408000000UL,
336};
337
338static const struct of_device_id tegra_pwm_of_match[] = {
339 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
340 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
341 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
342 { }
343};
344MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
345
346static const struct dev_pm_ops tegra_pwm_pm_ops = {
347 SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
348};
349
350static struct platform_driver tegra_pwm_driver = {
351 .driver = {
352 .name = "tegra-pwm",
353 .of_match_table = tegra_pwm_of_match,
354 .pm = &tegra_pwm_pm_ops,
355 },
356 .probe = tegra_pwm_probe,
357 .remove = tegra_pwm_remove,
358};
359
360module_platform_driver(tegra_pwm_driver);
361
362MODULE_LICENSE("GPL");
363MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
364MODULE_DESCRIPTION("Tegra PWM controller driver");
365MODULE_ALIAS("platform:tegra-pwm");