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1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform PWM support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/pwm.h>
23
24#include <asm/mach-jz4740/gpio.h>
25#include <asm/mach-jz4740/timer.h>
26
27#define NUM_PWM 8
28
29static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = {
30 JZ_GPIO_PWM0,
31 JZ_GPIO_PWM1,
32 JZ_GPIO_PWM2,
33 JZ_GPIO_PWM3,
34 JZ_GPIO_PWM4,
35 JZ_GPIO_PWM5,
36 JZ_GPIO_PWM6,
37 JZ_GPIO_PWM7,
38};
39
40struct jz4740_pwm_chip {
41 struct pwm_chip chip;
42 struct clk *clk;
43};
44
45static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
46{
47 return container_of(chip, struct jz4740_pwm_chip, chip);
48}
49
50static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
51{
52 unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
53 int ret;
54
55 /*
56 * Timers 0 and 1 are used for system tasks, so they are unavailable
57 * for use as PWMs.
58 */
59 if (pwm->hwpwm < 2)
60 return -EBUSY;
61
62 ret = gpio_request(gpio, pwm->label);
63 if (ret) {
64 dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n",
65 gpio, ret);
66 return ret;
67 }
68
69 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM);
70
71 jz4740_timer_start(pwm->hwpwm);
72
73 return 0;
74}
75
76static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
77{
78 unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
79
80 jz4740_timer_set_ctrl(pwm->hwpwm, 0);
81
82 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
83 gpio_free(gpio);
84
85 jz4740_timer_stop(pwm->hwpwm);
86}
87
88static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
89{
90 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
91
92 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
93 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
94 jz4740_timer_enable(pwm->hwpwm);
95
96 return 0;
97}
98
99static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
100{
101 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
102
103 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
104 jz4740_timer_disable(pwm->hwpwm);
105 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
106}
107
108static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
109 int duty_ns, int period_ns)
110{
111 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
112 unsigned long long tmp;
113 unsigned long period, duty;
114 unsigned int prescaler = 0;
115 uint16_t ctrl;
116 bool is_enabled;
117
118 tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns;
119 do_div(tmp, 1000000000);
120 period = tmp;
121
122 while (period > 0xffff && prescaler < 6) {
123 period >>= 2;
124 ++prescaler;
125 }
126
127 if (prescaler == 6)
128 return -EINVAL;
129
130 tmp = (unsigned long long)period * duty_ns;
131 do_div(tmp, period_ns);
132 duty = period - tmp;
133
134 if (duty >= period)
135 duty = period - 1;
136
137 is_enabled = jz4740_timer_is_enabled(pwm->hwpwm);
138 if (is_enabled)
139 jz4740_pwm_disable(chip, pwm);
140
141 jz4740_timer_set_count(pwm->hwpwm, 0);
142 jz4740_timer_set_duty(pwm->hwpwm, duty);
143 jz4740_timer_set_period(pwm->hwpwm, period);
144
145 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
146 JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
147
148 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
149
150 if (is_enabled)
151 jz4740_pwm_enable(chip, pwm);
152
153 return 0;
154}
155
156static const struct pwm_ops jz4740_pwm_ops = {
157 .request = jz4740_pwm_request,
158 .free = jz4740_pwm_free,
159 .config = jz4740_pwm_config,
160 .enable = jz4740_pwm_enable,
161 .disable = jz4740_pwm_disable,
162 .owner = THIS_MODULE,
163};
164
165static int jz4740_pwm_probe(struct platform_device *pdev)
166{
167 struct jz4740_pwm_chip *jz4740;
168
169 jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL);
170 if (!jz4740)
171 return -ENOMEM;
172
173 jz4740->clk = devm_clk_get(&pdev->dev, "ext");
174 if (IS_ERR(jz4740->clk))
175 return PTR_ERR(jz4740->clk);
176
177 jz4740->chip.dev = &pdev->dev;
178 jz4740->chip.ops = &jz4740_pwm_ops;
179 jz4740->chip.npwm = NUM_PWM;
180 jz4740->chip.base = -1;
181
182 platform_set_drvdata(pdev, jz4740);
183
184 return pwmchip_add(&jz4740->chip);
185}
186
187static int jz4740_pwm_remove(struct platform_device *pdev)
188{
189 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
190
191 return pwmchip_remove(&jz4740->chip);
192}
193
194static struct platform_driver jz4740_pwm_driver = {
195 .driver = {
196 .name = "jz4740-pwm",
197 },
198 .probe = jz4740_pwm_probe,
199 .remove = jz4740_pwm_remove,
200};
201module_platform_driver(jz4740_pwm_driver);
202
203MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
204MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
205MODULE_ALIAS("platform:jz4740-pwm");
206MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
5 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/mfd/ingenic-tcu.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
22
23struct soc_info {
24 unsigned int num_pwms;
25};
26
27struct jz4740_pwm_chip {
28 struct pwm_chip chip;
29 struct regmap *map;
30};
31
32static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
33{
34 return container_of(chip, struct jz4740_pwm_chip, chip);
35}
36
37static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
38 unsigned int channel)
39{
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
42
43 device_property_read_u32(jz->chip.dev->parent,
44 "ingenic,pwm-channels-mask",
45 &pwm_channels_mask);
46
47 return !!(pwm_channels_mask & BIT(channel));
48}
49
50static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
51{
52 struct jz4740_pwm_chip *jz = to_jz4740(chip);
53 struct clk *clk;
54 char name[16];
55 int err;
56
57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
58 return -EBUSY;
59
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
61
62 clk = clk_get(chip->dev, name);
63 if (IS_ERR(clk))
64 return dev_err_probe(chip->dev, PTR_ERR(clk),
65 "Failed to get clock\n");
66
67 err = clk_prepare_enable(clk);
68 if (err < 0) {
69 clk_put(clk);
70 return err;
71 }
72
73 pwm_set_chip_data(pwm, clk);
74
75 return 0;
76}
77
78static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
79{
80 struct clk *clk = pwm_get_chip_data(pwm);
81
82 clk_disable_unprepare(clk);
83 clk_put(clk);
84}
85
86static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
87{
88 struct jz4740_pwm_chip *jz = to_jz4740(chip);
89
90 /* Enable PWM output */
91 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
92 TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
93
94 /* Start counter */
95 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
96
97 return 0;
98}
99
100static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
101{
102 struct jz4740_pwm_chip *jz = to_jz4740(chip);
103
104 /*
105 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
106 * properly return to their init level.
107 */
108 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
109 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
110
111 /*
112 * Disable PWM output.
113 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
114 * counter is stopped, while in TCU1 mode the order does not matter.
115 */
116 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
117 TCU_TCSR_PWM_EN, 0);
118
119 /* Stop counter */
120 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
121}
122
123static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
124 const struct pwm_state *state)
125{
126 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
127 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
128 struct clk *clk = pwm_get_chip_data(pwm);
129 unsigned long period, duty;
130 long rate;
131 int err;
132
133 /*
134 * Limit the clock to a maximum rate that still gives us a period value
135 * which fits in 16 bits.
136 */
137 do_div(tmp, state->period);
138
139 /*
140 * /!\ IMPORTANT NOTE:
141 * -------------------
142 * This code relies on the fact that clk_round_rate() will always round
143 * down, which is not a valid assumption given by the clk API, but only
144 * happens to be true with the clk drivers used for Ingenic SoCs.
145 *
146 * Right now, there is no alternative as the clk API does not have a
147 * round-down function (and won't have one for a while), but if it ever
148 * comes to light, a round-down function should be used instead.
149 */
150 rate = clk_round_rate(clk, tmp);
151 if (rate < 0) {
152 dev_err(chip->dev, "Unable to round rate: %ld", rate);
153 return rate;
154 }
155
156 /* Calculate period value */
157 tmp = (unsigned long long)rate * state->period;
158 do_div(tmp, NSEC_PER_SEC);
159 period = tmp;
160
161 /* Calculate duty value */
162 tmp = (unsigned long long)rate * state->duty_cycle;
163 do_div(tmp, NSEC_PER_SEC);
164 duty = tmp;
165
166 if (duty >= period)
167 duty = period - 1;
168
169 jz4740_pwm_disable(chip, pwm);
170
171 err = clk_set_rate(clk, rate);
172 if (err) {
173 dev_err(chip->dev, "Unable to set rate: %d", err);
174 return err;
175 }
176
177 /* Reset counter to 0 */
178 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
179
180 /* Set duty */
181 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
182
183 /* Set period */
184 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
185
186 /* Set abrupt shutdown */
187 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
188 TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
189
190 /*
191 * Set polarity.
192 *
193 * The PWM starts in inactive state until the internal timer reaches the
194 * duty value, then becomes active until the timer reaches the period
195 * value. In theory, we should then use (period - duty) as the real duty
196 * value, as a high duty value would otherwise result in the PWM pin
197 * being inactive most of the time.
198 *
199 * Here, we don't do that, and instead invert the polarity of the PWM
200 * when it is active. This trick makes the PWM start with its active
201 * state instead of its inactive state.
202 */
203 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
204 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
205 TCU_TCSR_PWM_INITL_HIGH, 0);
206 else
207 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
208 TCU_TCSR_PWM_INITL_HIGH,
209 TCU_TCSR_PWM_INITL_HIGH);
210
211 if (state->enabled)
212 jz4740_pwm_enable(chip, pwm);
213
214 return 0;
215}
216
217static const struct pwm_ops jz4740_pwm_ops = {
218 .request = jz4740_pwm_request,
219 .free = jz4740_pwm_free,
220 .apply = jz4740_pwm_apply,
221 .owner = THIS_MODULE,
222};
223
224static int jz4740_pwm_probe(struct platform_device *pdev)
225{
226 struct device *dev = &pdev->dev;
227 struct jz4740_pwm_chip *jz4740;
228 const struct soc_info *info;
229
230 info = device_get_match_data(dev);
231 if (!info)
232 return -EINVAL;
233
234 jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
235 if (!jz4740)
236 return -ENOMEM;
237
238 jz4740->map = device_node_to_regmap(dev->parent->of_node);
239 if (IS_ERR(jz4740->map)) {
240 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
241 return PTR_ERR(jz4740->map);
242 }
243
244 jz4740->chip.dev = dev;
245 jz4740->chip.ops = &jz4740_pwm_ops;
246 jz4740->chip.npwm = info->num_pwms;
247
248 platform_set_drvdata(pdev, jz4740);
249
250 return pwmchip_add(&jz4740->chip);
251}
252
253static int jz4740_pwm_remove(struct platform_device *pdev)
254{
255 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
256
257 return pwmchip_remove(&jz4740->chip);
258}
259
260static const struct soc_info __maybe_unused jz4740_soc_info = {
261 .num_pwms = 8,
262};
263
264static const struct soc_info __maybe_unused jz4725b_soc_info = {
265 .num_pwms = 6,
266};
267
268#ifdef CONFIG_OF
269static const struct of_device_id jz4740_pwm_dt_ids[] = {
270 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
271 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
272 {},
273};
274MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
275#endif
276
277static struct platform_driver jz4740_pwm_driver = {
278 .driver = {
279 .name = "jz4740-pwm",
280 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
281 },
282 .probe = jz4740_pwm_probe,
283 .remove = jz4740_pwm_remove,
284};
285module_platform_driver(jz4740_pwm_driver);
286
287MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
288MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
289MODULE_ALIAS("platform:jz4740-pwm");
290MODULE_LICENSE("GPL");