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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
65 default:
66 hw->mac.type = I40E_MAC_GENERIC;
67 break;
68 }
69 } else {
70 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
71 }
72
73 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw->mac.type, status);
75 return status;
76}
77
78/**
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
82 **/
83const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
84{
85 switch (aq_err) {
86 case I40E_AQ_RC_OK:
87 return "OK";
88 case I40E_AQ_RC_EPERM:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR:
95 return "I40E_AQ_RC_EINTR";
96 case I40E_AQ_RC_EIO:
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG:
131 return "I40E_AQ_RC_EFBIG";
132 }
133
134 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
135 return hw->err_str;
136}
137
138/**
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
142 **/
143const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
144{
145 switch (stat_err) {
146 case 0:
147 return "OK";
148 case I40E_ERR_NVM:
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM:
151 return "I40E_ERR_NVM_CHECKSUM";
152 case I40E_ERR_PHY:
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG:
155 return "I40E_ERR_CONFIG";
156 case I40E_ERR_PARAM:
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
278 }
279
280 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
281 return hw->err_str;
282}
283
284/**
285 * i40e_debug_aq
286 * @hw: debug mask related to admin queue
287 * @mask: debug mask
288 * @desc: pointer to admin queue descriptor
289 * @buffer: pointer to command buffer
290 * @buf_len: max length of buffer
291 *
292 * Dumps debug log about adminq command with descriptor contents.
293 **/
294void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
295 void *buffer, u16 buf_len)
296{
297 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
298 u16 len = le16_to_cpu(aq_desc->datalen);
299 u8 *buf = (u8 *)buffer;
300 u16 i = 0;
301
302 if ((!(mask & hw->debug_mask)) || (desc == NULL))
303 return;
304
305 i40e_debug(hw, mask,
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc->opcode),
308 le16_to_cpu(aq_desc->flags),
309 le16_to_cpu(aq_desc->datalen),
310 le16_to_cpu(aq_desc->retval));
311 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc->cookie_high),
313 le32_to_cpu(aq_desc->cookie_low));
314 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc->params.internal.param0),
316 le32_to_cpu(aq_desc->params.internal.param1));
317 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc->params.external.addr_high),
319 le32_to_cpu(aq_desc->params.external.addr_low));
320
321 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
322 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
323 if (buf_len < len)
324 len = buf_len;
325 /* write the full 16-byte chunks */
326 for (i = 0; i < (len - 16); i += 16)
327 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
328 /* write whatever's left over without overrunning the buffer */
329 if (i < len)
330 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
331 i, len - i, buf + i);
332 }
333}
334
335/**
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
338 *
339 * Returns true if Queue is enabled else false.
340 **/
341bool i40e_check_asq_alive(struct i40e_hw *hw)
342{
343 if (hw->aq.asq.len)
344 return !!(rd32(hw, hw->aq.asq.len) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK);
346 else
347 return false;
348}
349
350/**
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
354 *
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
357 **/
358i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
359 bool unloading)
360{
361 struct i40e_aq_desc desc;
362 struct i40e_aqc_queue_shutdown *cmd =
363 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
364 i40e_status status;
365
366 i40e_fill_default_direct_cmd_desc(&desc,
367 i40e_aqc_opc_queue_shutdown);
368
369 if (unloading)
370 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
371 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
372
373 return status;
374}
375
376/**
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
384 *
385 * Internal function to get or set RSS look up table
386 **/
387static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
388 u16 vsi_id, bool pf_lut,
389 u8 *lut, u16 lut_size,
390 bool set)
391{
392 i40e_status status;
393 struct i40e_aq_desc desc;
394 struct i40e_aqc_get_set_rss_lut *cmd_resp =
395 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
396
397 if (set)
398 i40e_fill_default_direct_cmd_desc(&desc,
399 i40e_aqc_opc_set_rss_lut);
400 else
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_get_rss_lut);
403
404 /* Indirect command */
405 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
407
408 cmd_resp->vsi_id =
409 cpu_to_le16((u16)((vsi_id <<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
412 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
413
414 if (pf_lut)
415 cmd_resp->flags |= cpu_to_le16((u16)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
419 else
420 cmd_resp->flags |= cpu_to_le16((u16)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
424
425 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
426
427 return status;
428}
429
430/**
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
437 *
438 * get the RSS lookup table, PF or VSI type
439 **/
440i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
441 bool pf_lut, u8 *lut, u16 lut_size)
442{
443 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
444 false);
445}
446
447/**
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
454 *
455 * set the RSS lookup table, PF or VSI type
456 **/
457i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
458 bool pf_lut, u8 *lut, u16 lut_size)
459{
460 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
461}
462
463/**
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
469 *
470 * get the RSS key per VSI
471 **/
472static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
473 u16 vsi_id,
474 struct i40e_aqc_get_set_rss_key_data *key,
475 bool set)
476{
477 i40e_status status;
478 struct i40e_aq_desc desc;
479 struct i40e_aqc_get_set_rss_key *cmd_resp =
480 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
481 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
482
483 if (set)
484 i40e_fill_default_direct_cmd_desc(&desc,
485 i40e_aqc_opc_set_rss_key);
486 else
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_get_rss_key);
489
490 /* Indirect command */
491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
493
494 cmd_resp->vsi_id =
495 cpu_to_le16((u16)((vsi_id <<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
498 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
499
500 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
501
502 return status;
503}
504
505/**
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
510 *
511 **/
512i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
513 u16 vsi_id,
514 struct i40e_aqc_get_set_rss_key_data *key)
515{
516 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
517}
518
519/**
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
524 *
525 * set the RSS key per VSI
526 **/
527i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
528 u16 vsi_id,
529 struct i40e_aqc_get_set_rss_key_data *key)
530{
531 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
532}
533
534/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
536 * packet type.
537 *
538 * Macros are used to shorten the table lines and make this table human
539 * readable.
540 *
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
544 *
545 * Typical work flow:
546 *
547 * IF NOT i40e_ptype_lookup[ptype].known
548 * THEN
549 * Packet is unknown
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
552 * ELSE
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
554 * ENDIF
555 */
556
557/* macro to make the table lines short */
558#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
559 { PTYPE, \
560 1, \
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
569
570#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
572
573/* shorter macros makes the table fit but are terse */
574#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
577
578/* Lookup table mapping the HW PTYPE to the bit field for decoding */
579struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
584 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
593 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
610 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
611 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
612
613 /* IPv4 --> IPv4 */
614 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
621
622 /* IPv4 --> IPv6 */
623 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
630
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
633
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
693
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
696 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
700 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
701 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
702
703 /* IPv6 --> IPv4 */
704 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
711
712 /* IPv6 --> IPv6 */
713 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
720
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
723
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
783
784 /* unused entries */
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
791
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
802
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
813
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
824
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
835
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
846
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
857
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
868
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
879
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
890
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
897};
898
899/**
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
902 *
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
910 **/
911i40e_status i40e_init_shared_code(struct i40e_hw *hw)
912{
913 i40e_status status = 0;
914 u32 port, ari, func_rid;
915
916 i40e_set_mac_type(hw);
917
918 switch (hw->mac.type) {
919 case I40E_MAC_XL710:
920 case I40E_MAC_X722:
921 break;
922 default:
923 return I40E_ERR_DEVICE_NOT_SUPPORTED;
924 }
925
926 hw->phy.get_link_info = true;
927
928 /* Determine port number and PF number*/
929 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
931 hw->port = (u8)port;
932 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
934 func_rid = rd32(hw, I40E_PF_FUNC_RID);
935 if (ari)
936 hw->pf_id = (u8)(func_rid & 0xff);
937 else
938 hw->pf_id = (u8)(func_rid & 0x7);
939
940 if (hw->mac.type == I40E_MAC_X722)
941 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
942
943 status = i40e_init_nvm(hw);
944 return status;
945}
946
947/**
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
953 **/
954static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
955 u16 *flags,
956 struct i40e_aqc_mac_address_read_data *addrs,
957 struct i40e_asq_cmd_details *cmd_details)
958{
959 struct i40e_aq_desc desc;
960 struct i40e_aqc_mac_address_read *cmd_data =
961 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
962 i40e_status status;
963
964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
965 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
966
967 status = i40e_asq_send_command(hw, &desc, addrs,
968 sizeof(*addrs), cmd_details);
969 *flags = le16_to_cpu(cmd_data->command_flags);
970
971 return status;
972}
973
974/**
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
980 **/
981i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
982 u16 flags, u8 *mac_addr,
983 struct i40e_asq_cmd_details *cmd_details)
984{
985 struct i40e_aq_desc desc;
986 struct i40e_aqc_mac_address_write *cmd_data =
987 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
988 i40e_status status;
989
990 i40e_fill_default_direct_cmd_desc(&desc,
991 i40e_aqc_opc_mac_address_write);
992 cmd_data->command_flags = cpu_to_le16(flags);
993 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
994 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
995 ((u32)mac_addr[3] << 16) |
996 ((u32)mac_addr[4] << 8) |
997 mac_addr[5]);
998
999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1000
1001 return status;
1002}
1003
1004/**
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1008 *
1009 * Reads the adapter's MAC address from register
1010 **/
1011i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1012{
1013 struct i40e_aqc_mac_address_read_data addrs;
1014 i40e_status status;
1015 u16 flags = 0;
1016
1017 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1018
1019 if (flags & I40E_AQC_LAN_ADDR_VALID)
1020 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1021
1022 return status;
1023}
1024
1025/**
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1029 *
1030 * Reads the adapter's Port MAC address
1031 **/
1032i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033{
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039 if (status)
1040 return status;
1041
1042 if (flags & I40E_AQC_PORT_ADDR_VALID)
1043 ether_addr_copy(mac_addr, addrs.port_mac);
1044 else
1045 status = I40E_ERR_INVALID_MAC_ADDR;
1046
1047 return status;
1048}
1049
1050/**
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
1053 * @queue: target PF queue index
1054 * @enable: state change request
1055 *
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1058 **/
1059void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1060{
1061 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1062 u32 reg_block = 0;
1063 u32 reg_val;
1064
1065 if (abs_queue_idx >= 128) {
1066 reg_block = abs_queue_idx / 128;
1067 abs_queue_idx %= 128;
1068 }
1069
1070 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1071 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1072 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1073
1074 if (enable)
1075 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1076 else
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1078
1079 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1080}
1081#ifdef I40E_FCOE
1082
1083/**
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1087 *
1088 * Reads the adapter's SAN MAC address from NVM
1089 **/
1090i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1091{
1092 struct i40e_aqc_mac_address_read_data addrs;
1093 i40e_status status;
1094 u16 flags = 0;
1095
1096 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1097 if (status)
1098 return status;
1099
1100 if (flags & I40E_AQC_SAN_ADDR_VALID)
1101 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1102 else
1103 status = I40E_ERR_INVALID_MAC_ADDR;
1104
1105 return status;
1106}
1107#endif
1108
1109/**
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1114 *
1115 * Reads the part number string from the EEPROM.
1116 **/
1117i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1118 u32 pba_num_size)
1119{
1120 i40e_status status = 0;
1121 u16 pba_word = 0;
1122 u16 pba_size = 0;
1123 u16 pba_ptr = 0;
1124 u16 i = 0;
1125
1126 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1127 if (status || (pba_word != 0xFAFA)) {
1128 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1129 return status;
1130 }
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1133 if (status) {
1134 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block size.\n");
1141 return status;
1142 }
1143
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1145 * total size)
1146 */
1147 pba_size--;
1148 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1149 hw_dbg(hw, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM;
1151 }
1152
1153 for (i = 0; i < pba_size; i++) {
1154 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1155 if (status) {
1156 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1157 return status;
1158 }
1159
1160 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1161 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1162 }
1163 pba_num[(pba_size * 2)] = '\0';
1164
1165 return status;
1166}
1167
1168/**
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1171 **/
1172static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1173{
1174 enum i40e_media_type media;
1175
1176 switch (hw->phy.link_info.phy_type) {
1177 case I40E_PHY_TYPE_10GBASE_SR:
1178 case I40E_PHY_TYPE_10GBASE_LR:
1179 case I40E_PHY_TYPE_1000BASE_SX:
1180 case I40E_PHY_TYPE_1000BASE_LX:
1181 case I40E_PHY_TYPE_40GBASE_SR4:
1182 case I40E_PHY_TYPE_40GBASE_LR4:
1183 media = I40E_MEDIA_TYPE_FIBER;
1184 break;
1185 case I40E_PHY_TYPE_100BASE_TX:
1186 case I40E_PHY_TYPE_1000BASE_T:
1187 case I40E_PHY_TYPE_10GBASE_T:
1188 media = I40E_MEDIA_TYPE_BASET;
1189 break;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1192 case I40E_PHY_TYPE_10GBASE_CR1:
1193 case I40E_PHY_TYPE_40GBASE_CR4:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1195 case I40E_PHY_TYPE_40GBASE_AOC:
1196 case I40E_PHY_TYPE_10GBASE_AOC:
1197 media = I40E_MEDIA_TYPE_DA;
1198 break;
1199 case I40E_PHY_TYPE_1000BASE_KX:
1200 case I40E_PHY_TYPE_10GBASE_KX4:
1201 case I40E_PHY_TYPE_10GBASE_KR:
1202 case I40E_PHY_TYPE_40GBASE_KR4:
1203 case I40E_PHY_TYPE_20GBASE_KR2:
1204 media = I40E_MEDIA_TYPE_BACKPLANE;
1205 break;
1206 case I40E_PHY_TYPE_SGMII:
1207 case I40E_PHY_TYPE_XAUI:
1208 case I40E_PHY_TYPE_XFI:
1209 case I40E_PHY_TYPE_XLAUI:
1210 case I40E_PHY_TYPE_XLPPI:
1211 default:
1212 media = I40E_MEDIA_TYPE_UNKNOWN;
1213 break;
1214 }
1215
1216 return media;
1217}
1218
1219#define I40E_PF_RESET_WAIT_COUNT_A0 200
1220#define I40E_PF_RESET_WAIT_COUNT 200
1221/**
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1224 *
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1227 **/
1228i40e_status i40e_pf_reset(struct i40e_hw *hw)
1229{
1230 u32 cnt = 0;
1231 u32 cnt1 = 0;
1232 u32 reg = 0;
1233 u32 grst_del;
1234
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1238 */
1239 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1242
1243 /* It can take upto 15 secs for GRST steady state.
1244 * Bump it to 16 secs max to be safe.
1245 */
1246 grst_del = grst_del * 20;
1247
1248 for (cnt = 0; cnt < grst_del; cnt++) {
1249 reg = rd32(hw, I40E_GLGEN_RSTAT);
1250 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1251 break;
1252 msleep(100);
1253 }
1254 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1255 hw_dbg(hw, "Global reset polling failed to complete.\n");
1256 return I40E_ERR_RESET_FAILED;
1257 }
1258
1259 /* Now Wait for the FW to be ready */
1260 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1261 reg = rd32(hw, I40E_GLNVM_ULD);
1262 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1264 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1266 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1267 break;
1268 }
1269 usleep_range(10000, 20000);
1270 }
1271 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1273 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1274 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1275 return I40E_ERR_RESET_FAILED;
1276 }
1277
1278 /* If there was a Global Reset in progress when we got here,
1279 * we don't need to do the PF Reset
1280 */
1281 if (!cnt) {
1282 if (hw->revision_id == 0)
1283 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284 else
1285 cnt = I40E_PF_RESET_WAIT_COUNT;
1286 reg = rd32(hw, I40E_PFGEN_CTRL);
1287 wr32(hw, I40E_PFGEN_CTRL,
1288 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289 for (; cnt; cnt--) {
1290 reg = rd32(hw, I40E_PFGEN_CTRL);
1291 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292 break;
1293 usleep_range(1000, 2000);
1294 }
1295 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1296 hw_dbg(hw, "PF reset polling failed to complete.\n");
1297 return I40E_ERR_RESET_FAILED;
1298 }
1299 }
1300
1301 i40e_clear_pxe_mode(hw);
1302
1303 return 0;
1304}
1305
1306/**
1307 * i40e_clear_hw - clear out any left over hw state
1308 * @hw: pointer to the hw struct
1309 *
1310 * Clear queues and interrupts, typically called at init time,
1311 * but after the capabilities have been found so we know how many
1312 * queues and msix vectors have been allocated.
1313 **/
1314void i40e_clear_hw(struct i40e_hw *hw)
1315{
1316 u32 num_queues, base_queue;
1317 u32 num_pf_int;
1318 u32 num_vf_int;
1319 u32 num_vfs;
1320 u32 i, j;
1321 u32 val;
1322 u32 eol = 0x7ff;
1323
1324 /* get number of interrupts, queues, and VFs */
1325 val = rd32(hw, I40E_GLPCI_CNF2);
1326 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1327 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1328 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1330
1331 val = rd32(hw, I40E_PFLAN_QALLOC);
1332 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1333 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1334 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1336 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1337 num_queues = (j - base_queue) + 1;
1338 else
1339 num_queues = 0;
1340
1341 val = rd32(hw, I40E_PF_VT_PFALLOC);
1342 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1343 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1344 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1346 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1347 num_vfs = (j - i) + 1;
1348 else
1349 num_vfs = 0;
1350
1351 /* stop all the interrupts */
1352 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1353 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1356
1357 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1358 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1359 wr32(hw, I40E_PFINT_LNKLST0, val);
1360 for (i = 0; i < num_pf_int - 2; i++)
1361 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1362 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1363 for (i = 0; i < num_vfs; i++)
1364 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1365 for (i = 0; i < num_vf_int - 2; i++)
1366 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1367
1368 /* warn the HW of the coming Tx disables */
1369 for (i = 0; i < num_queues; i++) {
1370 u32 abs_queue_idx = base_queue + i;
1371 u32 reg_block = 0;
1372
1373 if (abs_queue_idx >= 128) {
1374 reg_block = abs_queue_idx / 128;
1375 abs_queue_idx %= 128;
1376 }
1377
1378 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1379 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1380 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1381 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1382
1383 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1384 }
1385 udelay(400);
1386
1387 /* stop all the queues */
1388 for (i = 0; i < num_queues; i++) {
1389 wr32(hw, I40E_QINT_TQCTL(i), 0);
1390 wr32(hw, I40E_QTX_ENA(i), 0);
1391 wr32(hw, I40E_QINT_RQCTL(i), 0);
1392 wr32(hw, I40E_QRX_ENA(i), 0);
1393 }
1394
1395 /* short wait for all queue disables to settle */
1396 udelay(50);
1397}
1398
1399/**
1400 * i40e_clear_pxe_mode - clear pxe operations mode
1401 * @hw: pointer to the hw struct
1402 *
1403 * Make sure all PXE mode settings are cleared, including things
1404 * like descriptor fetch/write-back mode.
1405 **/
1406void i40e_clear_pxe_mode(struct i40e_hw *hw)
1407{
1408 u32 reg;
1409
1410 if (i40e_check_asq_alive(hw))
1411 i40e_aq_clear_pxe_mode(hw, NULL);
1412
1413 /* Clear single descriptor fetch/write-back mode */
1414 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1415
1416 if (hw->revision_id == 0) {
1417 /* As a work around clear PXE_MODE instead of setting it */
1418 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1419 } else {
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1421 }
1422}
1423
1424/**
1425 * i40e_led_is_mine - helper to find matching led
1426 * @hw: pointer to the hw struct
1427 * @idx: index into GPIO registers
1428 *
1429 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1430 */
1431static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1432{
1433 u32 gpio_val = 0;
1434 u32 port;
1435
1436 if (!hw->func_caps.led[idx])
1437 return 0;
1438
1439 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1440 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1441 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1442
1443 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1444 * if it is not our port then ignore
1445 */
1446 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1447 (port != hw->port))
1448 return 0;
1449
1450 return gpio_val;
1451}
1452
1453#define I40E_COMBINED_ACTIVITY 0xA
1454#define I40E_FILTER_ACTIVITY 0xE
1455#define I40E_LINK_ACTIVITY 0xC
1456#define I40E_MAC_ACTIVITY 0xD
1457#define I40E_LED0 22
1458
1459/**
1460 * i40e_led_get - return current on/off mode
1461 * @hw: pointer to the hw struct
1462 *
1463 * The value returned is the 'mode' field as defined in the
1464 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1465 * values are variations of possible behaviors relating to
1466 * blink, link, and wire.
1467 **/
1468u32 i40e_led_get(struct i40e_hw *hw)
1469{
1470 u32 current_mode = 0;
1471 u32 mode = 0;
1472 int i;
1473
1474 /* as per the documentation GPIO 22-29 are the LED
1475 * GPIO pins named LED0..LED7
1476 */
1477 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1478 u32 gpio_val = i40e_led_is_mine(hw, i);
1479
1480 if (!gpio_val)
1481 continue;
1482
1483 /* ignore gpio LED src mode entries related to the activity
1484 * LEDs
1485 */
1486 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1487 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1488 switch (current_mode) {
1489 case I40E_COMBINED_ACTIVITY:
1490 case I40E_FILTER_ACTIVITY:
1491 case I40E_MAC_ACTIVITY:
1492 continue;
1493 default:
1494 break;
1495 }
1496
1497 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499 break;
1500 }
1501
1502 return mode;
1503}
1504
1505/**
1506 * i40e_led_set - set new on/off mode
1507 * @hw: pointer to the hw struct
1508 * @mode: 0=off, 0xf=on (else see manual for mode details)
1509 * @blink: true if the LED should blink when on, false if steady
1510 *
1511 * if this function is used to turn on the blink it should
1512 * be used to disable the blink when restoring the original state.
1513 **/
1514void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515{
1516 u32 current_mode = 0;
1517 int i;
1518
1519 if (mode & 0xfffffff0)
1520 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522 /* as per the documentation GPIO 22-29 are the LED
1523 * GPIO pins named LED0..LED7
1524 */
1525 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528 if (!gpio_val)
1529 continue;
1530
1531 /* ignore gpio LED src mode entries related to the activity
1532 * LEDs
1533 */
1534 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536 switch (current_mode) {
1537 case I40E_COMBINED_ACTIVITY:
1538 case I40E_FILTER_ACTIVITY:
1539 case I40E_MAC_ACTIVITY:
1540 continue;
1541 default:
1542 break;
1543 }
1544
1545 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1546 /* this & is a bit of paranoia, but serves as a range check */
1547 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1549
1550 if (mode == I40E_LINK_ACTIVITY)
1551 blink = false;
1552
1553 if (blink)
1554 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555 else
1556 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557
1558 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1559 break;
1560 }
1561}
1562
1563/* Admin command wrappers */
1564
1565/**
1566 * i40e_aq_get_phy_capabilities
1567 * @hw: pointer to the hw struct
1568 * @abilities: structure for PHY capabilities to be filled
1569 * @qualified_modules: report Qualified Modules
1570 * @report_init: report init capabilities (active are default)
1571 * @cmd_details: pointer to command details structure or NULL
1572 *
1573 * Returns the various PHY abilities supported on the Port.
1574 **/
1575i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1576 bool qualified_modules, bool report_init,
1577 struct i40e_aq_get_phy_abilities_resp *abilities,
1578 struct i40e_asq_cmd_details *cmd_details)
1579{
1580 struct i40e_aq_desc desc;
1581 i40e_status status;
1582 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1583
1584 if (!abilities)
1585 return I40E_ERR_PARAM;
1586
1587 i40e_fill_default_direct_cmd_desc(&desc,
1588 i40e_aqc_opc_get_phy_abilities);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (abilities_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 if (qualified_modules)
1595 desc.params.external.param0 |=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598 if (report_init)
1599 desc.params.external.param0 |=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1603 cmd_details);
1604
1605 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1606 status = I40E_ERR_UNKNOWN_PHY;
1607
1608 if (report_init)
1609 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1610
1611 return status;
1612}
1613
1614/**
1615 * i40e_aq_set_phy_config
1616 * @hw: pointer to the hw struct
1617 * @config: structure with PHY configuration to be set
1618 * @cmd_details: pointer to command details structure or NULL
1619 *
1620 * Set the various PHY configuration parameters
1621 * supported on the Port.One or more of the Set PHY config parameters may be
1622 * ignored in an MFP mode as the PF may not have the privilege to set some
1623 * of the PHY Config parameters. This status will be indicated by the
1624 * command response.
1625 **/
1626enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1627 struct i40e_aq_set_phy_config *config,
1628 struct i40e_asq_cmd_details *cmd_details)
1629{
1630 struct i40e_aq_desc desc;
1631 struct i40e_aq_set_phy_config *cmd =
1632 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1633 enum i40e_status_code status;
1634
1635 if (!config)
1636 return I40E_ERR_PARAM;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_set_phy_config);
1640
1641 *cmd = *config;
1642
1643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644
1645 return status;
1646}
1647
1648/**
1649 * i40e_set_fc
1650 * @hw: pointer to the hw struct
1651 *
1652 * Set the requested flow control mode using set_phy_config.
1653 **/
1654enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1655 bool atomic_restart)
1656{
1657 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1658 struct i40e_aq_get_phy_abilities_resp abilities;
1659 struct i40e_aq_set_phy_config config;
1660 enum i40e_status_code status;
1661 u8 pause_mask = 0x0;
1662
1663 *aq_failures = 0x0;
1664
1665 switch (fc_mode) {
1666 case I40E_FC_FULL:
1667 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1669 break;
1670 case I40E_FC_RX_PAUSE:
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672 break;
1673 case I40E_FC_TX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1675 break;
1676 default:
1677 break;
1678 }
1679
1680 /* Get the current phy config */
1681 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1682 NULL);
1683 if (status) {
1684 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1685 return status;
1686 }
1687
1688 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1689 /* clear the old pause settings */
1690 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1691 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1692 /* set the new abilities */
1693 config.abilities |= pause_mask;
1694 /* If the abilities have changed, then set the new config */
1695 if (config.abilities != abilities.abilities) {
1696 /* Auto restart link so settings take effect */
1697 if (atomic_restart)
1698 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1699 /* Copy over all the old settings */
1700 config.phy_type = abilities.phy_type;
1701 config.link_speed = abilities.link_speed;
1702 config.eee_capability = abilities.eee_capability;
1703 config.eeer = abilities.eeer_val;
1704 config.low_power_ctrl = abilities.d3_lpan;
1705 status = i40e_aq_set_phy_config(hw, &config, NULL);
1706
1707 if (status)
1708 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1709 }
1710 /* Update the link info */
1711 status = i40e_update_link_info(hw);
1712 if (status) {
1713 /* Wait a little bit (on 40G cards it sometimes takes a really
1714 * long time for link to come back from the atomic reset)
1715 * and try once more
1716 */
1717 msleep(1000);
1718 status = i40e_update_link_info(hw);
1719 }
1720 if (status)
1721 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1722
1723 return status;
1724}
1725
1726/**
1727 * i40e_aq_clear_pxe_mode
1728 * @hw: pointer to the hw struct
1729 * @cmd_details: pointer to command details structure or NULL
1730 *
1731 * Tell the firmware that the driver is taking over from PXE
1732 **/
1733i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1734 struct i40e_asq_cmd_details *cmd_details)
1735{
1736 i40e_status status;
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_clear_pxe *cmd =
1739 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1740
1741 i40e_fill_default_direct_cmd_desc(&desc,
1742 i40e_aqc_opc_clear_pxe_mode);
1743
1744 cmd->rx_cnt = 0x2;
1745
1746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747
1748 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1749
1750 return status;
1751}
1752
1753/**
1754 * i40e_aq_set_link_restart_an
1755 * @hw: pointer to the hw struct
1756 * @enable_link: if true: enable link, if false: disable link
1757 * @cmd_details: pointer to command details structure or NULL
1758 *
1759 * Sets up the link and restarts the Auto-Negotiation over the link.
1760 **/
1761i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1762 bool enable_link,
1763 struct i40e_asq_cmd_details *cmd_details)
1764{
1765 struct i40e_aq_desc desc;
1766 struct i40e_aqc_set_link_restart_an *cmd =
1767 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1768 i40e_status status;
1769
1770 i40e_fill_default_direct_cmd_desc(&desc,
1771 i40e_aqc_opc_set_link_restart_an);
1772
1773 cmd->command = I40E_AQ_PHY_RESTART_AN;
1774 if (enable_link)
1775 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1776 else
1777 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1778
1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780
1781 return status;
1782}
1783
1784/**
1785 * i40e_aq_get_link_info
1786 * @hw: pointer to the hw struct
1787 * @enable_lse: enable/disable LinkStatusEvent reporting
1788 * @link: pointer to link status structure - optional
1789 * @cmd_details: pointer to command details structure or NULL
1790 *
1791 * Returns the link status of the adapter.
1792 **/
1793i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1794 bool enable_lse, struct i40e_link_status *link,
1795 struct i40e_asq_cmd_details *cmd_details)
1796{
1797 struct i40e_aq_desc desc;
1798 struct i40e_aqc_get_link_status *resp =
1799 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1800 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1801 i40e_status status;
1802 bool tx_pause, rx_pause;
1803 u16 command_flags;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1806
1807 if (enable_lse)
1808 command_flags = I40E_AQ_LSE_ENABLE;
1809 else
1810 command_flags = I40E_AQ_LSE_DISABLE;
1811 resp->command_flags = cpu_to_le16(command_flags);
1812
1813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1814
1815 if (status)
1816 goto aq_get_link_info_exit;
1817
1818 /* save off old link status information */
1819 hw->phy.link_info_old = *hw_link_info;
1820
1821 /* update link status */
1822 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1823 hw->phy.media_type = i40e_get_media_type(hw);
1824 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1825 hw_link_info->link_info = resp->link_info;
1826 hw_link_info->an_info = resp->an_info;
1827 hw_link_info->ext_info = resp->ext_info;
1828 hw_link_info->loopback = resp->loopback;
1829 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1830 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1831
1832 /* update fc info */
1833 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1834 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1835 if (tx_pause & rx_pause)
1836 hw->fc.current_mode = I40E_FC_FULL;
1837 else if (tx_pause)
1838 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1839 else if (rx_pause)
1840 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1841 else
1842 hw->fc.current_mode = I40E_FC_NONE;
1843
1844 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1845 hw_link_info->crc_enable = true;
1846 else
1847 hw_link_info->crc_enable = false;
1848
1849 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1850 hw_link_info->lse_enable = true;
1851 else
1852 hw_link_info->lse_enable = false;
1853
1854 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1855 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1856 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1857
1858 /* save link status information */
1859 if (link)
1860 *link = *hw_link_info;
1861
1862 /* flag cleared so helper functions don't call AQ again */
1863 hw->phy.get_link_info = false;
1864
1865aq_get_link_info_exit:
1866 return status;
1867}
1868
1869/**
1870 * i40e_aq_set_phy_int_mask
1871 * @hw: pointer to the hw struct
1872 * @mask: interrupt mask to be set
1873 * @cmd_details: pointer to command details structure or NULL
1874 *
1875 * Set link interrupt mask.
1876 **/
1877i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1878 u16 mask,
1879 struct i40e_asq_cmd_details *cmd_details)
1880{
1881 struct i40e_aq_desc desc;
1882 struct i40e_aqc_set_phy_int_mask *cmd =
1883 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1884 i40e_status status;
1885
1886 i40e_fill_default_direct_cmd_desc(&desc,
1887 i40e_aqc_opc_set_phy_int_mask);
1888
1889 cmd->event_mask = cpu_to_le16(mask);
1890
1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1892
1893 return status;
1894}
1895
1896/**
1897 * i40e_aq_set_phy_debug
1898 * @hw: pointer to the hw struct
1899 * @cmd_flags: debug command flags
1900 * @cmd_details: pointer to command details structure or NULL
1901 *
1902 * Reset the external PHY.
1903 **/
1904enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1905 struct i40e_asq_cmd_details *cmd_details)
1906{
1907 struct i40e_aq_desc desc;
1908 struct i40e_aqc_set_phy_debug *cmd =
1909 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1910 enum i40e_status_code status;
1911
1912 i40e_fill_default_direct_cmd_desc(&desc,
1913 i40e_aqc_opc_set_phy_debug);
1914
1915 cmd->command_flags = cmd_flags;
1916
1917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918
1919 return status;
1920}
1921
1922/**
1923 * i40e_aq_add_vsi
1924 * @hw: pointer to the hw struct
1925 * @vsi_ctx: pointer to a vsi context struct
1926 * @cmd_details: pointer to command details structure or NULL
1927 *
1928 * Add a VSI context to the hardware.
1929**/
1930i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1931 struct i40e_vsi_context *vsi_ctx,
1932 struct i40e_asq_cmd_details *cmd_details)
1933{
1934 struct i40e_aq_desc desc;
1935 struct i40e_aqc_add_get_update_vsi *cmd =
1936 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1937 struct i40e_aqc_add_get_update_vsi_completion *resp =
1938 (struct i40e_aqc_add_get_update_vsi_completion *)
1939 &desc.params.raw;
1940 i40e_status status;
1941
1942 i40e_fill_default_direct_cmd_desc(&desc,
1943 i40e_aqc_opc_add_vsi);
1944
1945 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1946 cmd->connection_type = vsi_ctx->connection_type;
1947 cmd->vf_id = vsi_ctx->vf_num;
1948 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1949
1950 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1951
1952 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1953 sizeof(vsi_ctx->info), cmd_details);
1954
1955 if (status)
1956 goto aq_add_vsi_exit;
1957
1958 vsi_ctx->seid = le16_to_cpu(resp->seid);
1959 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1960 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1961 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1962
1963aq_add_vsi_exit:
1964 return status;
1965}
1966
1967/**
1968 * i40e_aq_set_vsi_unicast_promiscuous
1969 * @hw: pointer to the hw struct
1970 * @seid: vsi number
1971 * @set: set unicast promiscuous enable/disable
1972 * @cmd_details: pointer to command details structure or NULL
1973 **/
1974i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1975 u16 seid, bool set,
1976 struct i40e_asq_cmd_details *cmd_details)
1977{
1978 struct i40e_aq_desc desc;
1979 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1980 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1981 i40e_status status;
1982 u16 flags = 0;
1983
1984 i40e_fill_default_direct_cmd_desc(&desc,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes);
1986
1987 if (set) {
1988 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1989 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1990 (hw->aq.api_maj_ver > 1))
1991 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1992 }
1993
1994 cmd->promiscuous_flags = cpu_to_le16(flags);
1995
1996 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1997 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
1998 (hw->aq.api_maj_ver > 1))
1999 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2000
2001 cmd->seid = cpu_to_le16(seid);
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003
2004 return status;
2005}
2006
2007/**
2008 * i40e_aq_set_vsi_multicast_promiscuous
2009 * @hw: pointer to the hw struct
2010 * @seid: vsi number
2011 * @set: set multicast promiscuous enable/disable
2012 * @cmd_details: pointer to command details structure or NULL
2013 **/
2014i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2015 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2016{
2017 struct i40e_aq_desc desc;
2018 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2019 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2020 i40e_status status;
2021 u16 flags = 0;
2022
2023 i40e_fill_default_direct_cmd_desc(&desc,
2024 i40e_aqc_opc_set_vsi_promiscuous_modes);
2025
2026 if (set)
2027 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2028
2029 cmd->promiscuous_flags = cpu_to_le16(flags);
2030
2031 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2032
2033 cmd->seid = cpu_to_le16(seid);
2034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2035
2036 return status;
2037}
2038
2039/**
2040 * i40e_aq_set_vsi_broadcast
2041 * @hw: pointer to the hw struct
2042 * @seid: vsi number
2043 * @set_filter: true to set filter, false to clear filter
2044 * @cmd_details: pointer to command details structure or NULL
2045 *
2046 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2047 **/
2048i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2049 u16 seid, bool set_filter,
2050 struct i40e_asq_cmd_details *cmd_details)
2051{
2052 struct i40e_aq_desc desc;
2053 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2054 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2055 i40e_status status;
2056
2057 i40e_fill_default_direct_cmd_desc(&desc,
2058 i40e_aqc_opc_set_vsi_promiscuous_modes);
2059
2060 if (set_filter)
2061 cmd->promiscuous_flags
2062 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2063 else
2064 cmd->promiscuous_flags
2065 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2066
2067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2068 cmd->seid = cpu_to_le16(seid);
2069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2070
2071 return status;
2072}
2073
2074/**
2075 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2076 * @hw: pointer to the hw struct
2077 * @seid: vsi number
2078 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2079 * @cmd_details: pointer to command details structure or NULL
2080 **/
2081i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2082 u16 seid, bool enable,
2083 struct i40e_asq_cmd_details *cmd_details)
2084{
2085 struct i40e_aq_desc desc;
2086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2088 i40e_status status;
2089 u16 flags = 0;
2090
2091 i40e_fill_default_direct_cmd_desc(&desc,
2092 i40e_aqc_opc_set_vsi_promiscuous_modes);
2093 if (enable)
2094 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2095
2096 cmd->promiscuous_flags = cpu_to_le16(flags);
2097 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2098 cmd->seid = cpu_to_le16(seid);
2099
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101
2102 return status;
2103}
2104
2105/**
2106 * i40e_get_vsi_params - get VSI configuration info
2107 * @hw: pointer to the hw struct
2108 * @vsi_ctx: pointer to a vsi context struct
2109 * @cmd_details: pointer to command details structure or NULL
2110 **/
2111i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2112 struct i40e_vsi_context *vsi_ctx,
2113 struct i40e_asq_cmd_details *cmd_details)
2114{
2115 struct i40e_aq_desc desc;
2116 struct i40e_aqc_add_get_update_vsi *cmd =
2117 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2118 struct i40e_aqc_add_get_update_vsi_completion *resp =
2119 (struct i40e_aqc_add_get_update_vsi_completion *)
2120 &desc.params.raw;
2121 i40e_status status;
2122
2123 i40e_fill_default_direct_cmd_desc(&desc,
2124 i40e_aqc_opc_get_vsi_parameters);
2125
2126 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2127
2128 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2129
2130 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2131 sizeof(vsi_ctx->info), NULL);
2132
2133 if (status)
2134 goto aq_get_vsi_params_exit;
2135
2136 vsi_ctx->seid = le16_to_cpu(resp->seid);
2137 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2138 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2139 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2140
2141aq_get_vsi_params_exit:
2142 return status;
2143}
2144
2145/**
2146 * i40e_aq_update_vsi_params
2147 * @hw: pointer to the hw struct
2148 * @vsi_ctx: pointer to a vsi context struct
2149 * @cmd_details: pointer to command details structure or NULL
2150 *
2151 * Update a VSI context.
2152 **/
2153i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2154 struct i40e_vsi_context *vsi_ctx,
2155 struct i40e_asq_cmd_details *cmd_details)
2156{
2157 struct i40e_aq_desc desc;
2158 struct i40e_aqc_add_get_update_vsi *cmd =
2159 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2160 i40e_status status;
2161
2162 i40e_fill_default_direct_cmd_desc(&desc,
2163 i40e_aqc_opc_update_vsi_parameters);
2164 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2165
2166 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2167
2168 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2169 sizeof(vsi_ctx->info), cmd_details);
2170
2171 return status;
2172}
2173
2174/**
2175 * i40e_aq_get_switch_config
2176 * @hw: pointer to the hardware structure
2177 * @buf: pointer to the result buffer
2178 * @buf_size: length of input buffer
2179 * @start_seid: seid to start for the report, 0 == beginning
2180 * @cmd_details: pointer to command details structure or NULL
2181 *
2182 * Fill the buf with switch configuration returned from AdminQ command
2183 **/
2184i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2185 struct i40e_aqc_get_switch_config_resp *buf,
2186 u16 buf_size, u16 *start_seid,
2187 struct i40e_asq_cmd_details *cmd_details)
2188{
2189 struct i40e_aq_desc desc;
2190 struct i40e_aqc_switch_seid *scfg =
2191 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2192 i40e_status status;
2193
2194 i40e_fill_default_direct_cmd_desc(&desc,
2195 i40e_aqc_opc_get_switch_config);
2196 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2197 if (buf_size > I40E_AQ_LARGE_BUF)
2198 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2199 scfg->seid = cpu_to_le16(*start_seid);
2200
2201 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2202 *start_seid = le16_to_cpu(scfg->seid);
2203
2204 return status;
2205}
2206
2207/**
2208 * i40e_aq_get_firmware_version
2209 * @hw: pointer to the hw struct
2210 * @fw_major_version: firmware major version
2211 * @fw_minor_version: firmware minor version
2212 * @fw_build: firmware build number
2213 * @api_major_version: major queue version
2214 * @api_minor_version: minor queue version
2215 * @cmd_details: pointer to command details structure or NULL
2216 *
2217 * Get the firmware version from the admin queue commands
2218 **/
2219i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2220 u16 *fw_major_version, u16 *fw_minor_version,
2221 u32 *fw_build,
2222 u16 *api_major_version, u16 *api_minor_version,
2223 struct i40e_asq_cmd_details *cmd_details)
2224{
2225 struct i40e_aq_desc desc;
2226 struct i40e_aqc_get_version *resp =
2227 (struct i40e_aqc_get_version *)&desc.params.raw;
2228 i40e_status status;
2229
2230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2231
2232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2233
2234 if (!status) {
2235 if (fw_major_version)
2236 *fw_major_version = le16_to_cpu(resp->fw_major);
2237 if (fw_minor_version)
2238 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2239 if (fw_build)
2240 *fw_build = le32_to_cpu(resp->fw_build);
2241 if (api_major_version)
2242 *api_major_version = le16_to_cpu(resp->api_major);
2243 if (api_minor_version)
2244 *api_minor_version = le16_to_cpu(resp->api_minor);
2245 }
2246
2247 return status;
2248}
2249
2250/**
2251 * i40e_aq_send_driver_version
2252 * @hw: pointer to the hw struct
2253 * @dv: driver's major, minor version
2254 * @cmd_details: pointer to command details structure or NULL
2255 *
2256 * Send the driver version to the firmware
2257 **/
2258i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2259 struct i40e_driver_version *dv,
2260 struct i40e_asq_cmd_details *cmd_details)
2261{
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_driver_version *cmd =
2264 (struct i40e_aqc_driver_version *)&desc.params.raw;
2265 i40e_status status;
2266 u16 len;
2267
2268 if (dv == NULL)
2269 return I40E_ERR_PARAM;
2270
2271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2272
2273 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2274 cmd->driver_major_ver = dv->major_version;
2275 cmd->driver_minor_ver = dv->minor_version;
2276 cmd->driver_build_ver = dv->build_version;
2277 cmd->driver_subbuild_ver = dv->subbuild_version;
2278
2279 len = 0;
2280 while (len < sizeof(dv->driver_string) &&
2281 (dv->driver_string[len] < 0x80) &&
2282 dv->driver_string[len])
2283 len++;
2284 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2285 len, cmd_details);
2286
2287 return status;
2288}
2289
2290/**
2291 * i40e_get_link_status - get status of the HW network link
2292 * @hw: pointer to the hw struct
2293 * @link_up: pointer to bool (true/false = linkup/linkdown)
2294 *
2295 * Variable link_up true if link is up, false if link is down.
2296 * The variable link_up is invalid if returned value of status != 0
2297 *
2298 * Side effect: LinkStatusEvent reporting becomes enabled
2299 **/
2300i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2301{
2302 i40e_status status = 0;
2303
2304 if (hw->phy.get_link_info) {
2305 status = i40e_update_link_info(hw);
2306
2307 if (status)
2308 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2309 status);
2310 }
2311
2312 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2313
2314 return status;
2315}
2316
2317/**
2318 * i40e_updatelink_status - update status of the HW network link
2319 * @hw: pointer to the hw struct
2320 **/
2321i40e_status i40e_update_link_info(struct i40e_hw *hw)
2322{
2323 struct i40e_aq_get_phy_abilities_resp abilities;
2324 i40e_status status = 0;
2325
2326 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2327 if (status)
2328 return status;
2329
2330 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2331 status = i40e_aq_get_phy_capabilities(hw, false, false,
2332 &abilities, NULL);
2333 if (status)
2334 return status;
2335
2336 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2337 sizeof(hw->phy.link_info.module_type));
2338 }
2339
2340 return status;
2341}
2342
2343/**
2344 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2345 * @hw: pointer to the hw struct
2346 * @uplink_seid: the MAC or other gizmo SEID
2347 * @downlink_seid: the VSI SEID
2348 * @enabled_tc: bitmap of TCs to be enabled
2349 * @default_port: true for default port VSI, false for control port
2350 * @veb_seid: pointer to where to put the resulting VEB SEID
2351 * @enable_stats: true to turn on VEB stats
2352 * @cmd_details: pointer to command details structure or NULL
2353 *
2354 * This asks the FW to add a VEB between the uplink and downlink
2355 * elements. If the uplink SEID is 0, this will be a floating VEB.
2356 **/
2357i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2358 u16 downlink_seid, u8 enabled_tc,
2359 bool default_port, u16 *veb_seid,
2360 bool enable_stats,
2361 struct i40e_asq_cmd_details *cmd_details)
2362{
2363 struct i40e_aq_desc desc;
2364 struct i40e_aqc_add_veb *cmd =
2365 (struct i40e_aqc_add_veb *)&desc.params.raw;
2366 struct i40e_aqc_add_veb_completion *resp =
2367 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2368 i40e_status status;
2369 u16 veb_flags = 0;
2370
2371 /* SEIDs need to either both be set or both be 0 for floating VEB */
2372 if (!!uplink_seid != !!downlink_seid)
2373 return I40E_ERR_PARAM;
2374
2375 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2376
2377 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2378 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2379 cmd->enable_tcs = enabled_tc;
2380 if (!uplink_seid)
2381 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2382 if (default_port)
2383 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2384 else
2385 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2386
2387 /* reverse logic here: set the bitflag to disable the stats */
2388 if (!enable_stats)
2389 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2390
2391 cmd->veb_flags = cpu_to_le16(veb_flags);
2392
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394
2395 if (!status && veb_seid)
2396 *veb_seid = le16_to_cpu(resp->veb_seid);
2397
2398 return status;
2399}
2400
2401/**
2402 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2403 * @hw: pointer to the hw struct
2404 * @veb_seid: the SEID of the VEB to query
2405 * @switch_id: the uplink switch id
2406 * @floating: set to true if the VEB is floating
2407 * @statistic_index: index of the stats counter block for this VEB
2408 * @vebs_used: number of VEB's used by function
2409 * @vebs_free: total VEB's not reserved by any function
2410 * @cmd_details: pointer to command details structure or NULL
2411 *
2412 * This retrieves the parameters for a particular VEB, specified by
2413 * uplink_seid, and returns them to the caller.
2414 **/
2415i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2416 u16 veb_seid, u16 *switch_id,
2417 bool *floating, u16 *statistic_index,
2418 u16 *vebs_used, u16 *vebs_free,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2423 (struct i40e_aqc_get_veb_parameters_completion *)
2424 &desc.params.raw;
2425 i40e_status status;
2426
2427 if (veb_seid == 0)
2428 return I40E_ERR_PARAM;
2429
2430 i40e_fill_default_direct_cmd_desc(&desc,
2431 i40e_aqc_opc_get_veb_parameters);
2432 cmd_resp->seid = cpu_to_le16(veb_seid);
2433
2434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435 if (status)
2436 goto get_veb_exit;
2437
2438 if (switch_id)
2439 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2440 if (statistic_index)
2441 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2442 if (vebs_used)
2443 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2444 if (vebs_free)
2445 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2446 if (floating) {
2447 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2448
2449 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2450 *floating = true;
2451 else
2452 *floating = false;
2453 }
2454
2455get_veb_exit:
2456 return status;
2457}
2458
2459/**
2460 * i40e_aq_add_macvlan
2461 * @hw: pointer to the hw struct
2462 * @seid: VSI for the mac address
2463 * @mv_list: list of macvlans to be added
2464 * @count: length of the list
2465 * @cmd_details: pointer to command details structure or NULL
2466 *
2467 * Add MAC/VLAN addresses to the HW filtering
2468 **/
2469i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2470 struct i40e_aqc_add_macvlan_element_data *mv_list,
2471 u16 count, struct i40e_asq_cmd_details *cmd_details)
2472{
2473 struct i40e_aq_desc desc;
2474 struct i40e_aqc_macvlan *cmd =
2475 (struct i40e_aqc_macvlan *)&desc.params.raw;
2476 i40e_status status;
2477 u16 buf_size;
2478 int i;
2479
2480 if (count == 0 || !mv_list || !hw)
2481 return I40E_ERR_PARAM;
2482
2483 buf_size = count * sizeof(*mv_list);
2484
2485 /* prep the rest of the request */
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2487 cmd->num_addresses = cpu_to_le16(count);
2488 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2489 cmd->seid[1] = 0;
2490 cmd->seid[2] = 0;
2491
2492 for (i = 0; i < count; i++)
2493 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2494 mv_list[i].flags |=
2495 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2496
2497 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2498 if (buf_size > I40E_AQ_LARGE_BUF)
2499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2500
2501 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2502 cmd_details);
2503
2504 return status;
2505}
2506
2507/**
2508 * i40e_aq_remove_macvlan
2509 * @hw: pointer to the hw struct
2510 * @seid: VSI for the mac address
2511 * @mv_list: list of macvlans to be removed
2512 * @count: length of the list
2513 * @cmd_details: pointer to command details structure or NULL
2514 *
2515 * Remove MAC/VLAN addresses from the HW filtering
2516 **/
2517i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2518 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2519 u16 count, struct i40e_asq_cmd_details *cmd_details)
2520{
2521 struct i40e_aq_desc desc;
2522 struct i40e_aqc_macvlan *cmd =
2523 (struct i40e_aqc_macvlan *)&desc.params.raw;
2524 i40e_status status;
2525 u16 buf_size;
2526
2527 if (count == 0 || !mv_list || !hw)
2528 return I40E_ERR_PARAM;
2529
2530 buf_size = count * sizeof(*mv_list);
2531
2532 /* prep the rest of the request */
2533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2534 cmd->num_addresses = cpu_to_le16(count);
2535 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2536 cmd->seid[1] = 0;
2537 cmd->seid[2] = 0;
2538
2539 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2540 if (buf_size > I40E_AQ_LARGE_BUF)
2541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2542
2543 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2544 cmd_details);
2545
2546 return status;
2547}
2548
2549/**
2550 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2551 * @hw: pointer to the hw struct
2552 * @opcode: AQ opcode for add or delete mirror rule
2553 * @sw_seid: Switch SEID (to which rule refers)
2554 * @rule_type: Rule Type (ingress/egress/VLAN)
2555 * @id: Destination VSI SEID or Rule ID
2556 * @count: length of the list
2557 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2558 * @cmd_details: pointer to command details structure or NULL
2559 * @rule_id: Rule ID returned from FW
2560 * @rule_used: Number of rules used in internal switch
2561 * @rule_free: Number of rules free in internal switch
2562 *
2563 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2564 * VEBs/VEPA elements only
2565 **/
2566static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2567 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2568 u16 count, __le16 *mr_list,
2569 struct i40e_asq_cmd_details *cmd_details,
2570 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2571{
2572 struct i40e_aq_desc desc;
2573 struct i40e_aqc_add_delete_mirror_rule *cmd =
2574 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2575 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2576 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2577 i40e_status status;
2578 u16 buf_size;
2579
2580 buf_size = count * sizeof(*mr_list);
2581
2582 /* prep the rest of the request */
2583 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2584 cmd->seid = cpu_to_le16(sw_seid);
2585 cmd->rule_type = cpu_to_le16(rule_type &
2586 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2587 cmd->num_entries = cpu_to_le16(count);
2588 /* Dest VSI for add, rule_id for delete */
2589 cmd->destination = cpu_to_le16(id);
2590 if (mr_list) {
2591 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2592 I40E_AQ_FLAG_RD));
2593 if (buf_size > I40E_AQ_LARGE_BUF)
2594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2595 }
2596
2597 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2598 cmd_details);
2599 if (!status ||
2600 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2601 if (rule_id)
2602 *rule_id = le16_to_cpu(resp->rule_id);
2603 if (rules_used)
2604 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2605 if (rules_free)
2606 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2607 }
2608 return status;
2609}
2610
2611/**
2612 * i40e_aq_add_mirrorrule - add a mirror rule
2613 * @hw: pointer to the hw struct
2614 * @sw_seid: Switch SEID (to which rule refers)
2615 * @rule_type: Rule Type (ingress/egress/VLAN)
2616 * @dest_vsi: SEID of VSI to which packets will be mirrored
2617 * @count: length of the list
2618 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2619 * @cmd_details: pointer to command details structure or NULL
2620 * @rule_id: Rule ID returned from FW
2621 * @rule_used: Number of rules used in internal switch
2622 * @rule_free: Number of rules free in internal switch
2623 *
2624 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2625 **/
2626i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2627 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2628 struct i40e_asq_cmd_details *cmd_details,
2629 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2630{
2631 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2632 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2633 if (count == 0 || !mr_list)
2634 return I40E_ERR_PARAM;
2635 }
2636
2637 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2638 rule_type, dest_vsi, count, mr_list,
2639 cmd_details, rule_id, rules_used, rules_free);
2640}
2641
2642/**
2643 * i40e_aq_delete_mirrorrule - delete a mirror rule
2644 * @hw: pointer to the hw struct
2645 * @sw_seid: Switch SEID (to which rule refers)
2646 * @rule_type: Rule Type (ingress/egress/VLAN)
2647 * @count: length of the list
2648 * @rule_id: Rule ID that is returned in the receive desc as part of
2649 * add_mirrorrule.
2650 * @mr_list: list of mirrored VLAN IDs to be removed
2651 * @cmd_details: pointer to command details structure or NULL
2652 * @rule_used: Number of rules used in internal switch
2653 * @rule_free: Number of rules free in internal switch
2654 *
2655 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2656 **/
2657i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2658 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2659 struct i40e_asq_cmd_details *cmd_details,
2660 u16 *rules_used, u16 *rules_free)
2661{
2662 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2663 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2664 if (!rule_id)
2665 return I40E_ERR_PARAM;
2666 } else {
2667 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2668 * mirroring. For other rule_type, count and rule_type should
2669 * not matter.
2670 */
2671 if (count == 0 || !mr_list)
2672 return I40E_ERR_PARAM;
2673 }
2674
2675 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2676 rule_type, rule_id, count, mr_list,
2677 cmd_details, NULL, rules_used, rules_free);
2678}
2679
2680/**
2681 * i40e_aq_send_msg_to_vf
2682 * @hw: pointer to the hardware structure
2683 * @vfid: VF id to send msg
2684 * @v_opcode: opcodes for VF-PF communication
2685 * @v_retval: return error code
2686 * @msg: pointer to the msg buffer
2687 * @msglen: msg length
2688 * @cmd_details: pointer to command details
2689 *
2690 * send msg to vf
2691 **/
2692i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2693 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2694 struct i40e_asq_cmd_details *cmd_details)
2695{
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_pf_vf_message *cmd =
2698 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2699 i40e_status status;
2700
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2702 cmd->id = cpu_to_le32(vfid);
2703 desc.cookie_high = cpu_to_le32(v_opcode);
2704 desc.cookie_low = cpu_to_le32(v_retval);
2705 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2706 if (msglen) {
2707 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2708 I40E_AQ_FLAG_RD));
2709 if (msglen > I40E_AQ_LARGE_BUF)
2710 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2711 desc.datalen = cpu_to_le16(msglen);
2712 }
2713 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2714
2715 return status;
2716}
2717
2718/**
2719 * i40e_aq_debug_read_register
2720 * @hw: pointer to the hw struct
2721 * @reg_addr: register address
2722 * @reg_val: register value
2723 * @cmd_details: pointer to command details structure or NULL
2724 *
2725 * Read the register using the admin queue commands
2726 **/
2727i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2728 u32 reg_addr, u64 *reg_val,
2729 struct i40e_asq_cmd_details *cmd_details)
2730{
2731 struct i40e_aq_desc desc;
2732 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2733 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2734 i40e_status status;
2735
2736 if (reg_val == NULL)
2737 return I40E_ERR_PARAM;
2738
2739 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2740
2741 cmd_resp->address = cpu_to_le32(reg_addr);
2742
2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2744
2745 if (!status) {
2746 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2747 (u64)le32_to_cpu(cmd_resp->value_low);
2748 }
2749
2750 return status;
2751}
2752
2753/**
2754 * i40e_aq_debug_write_register
2755 * @hw: pointer to the hw struct
2756 * @reg_addr: register address
2757 * @reg_val: register value
2758 * @cmd_details: pointer to command details structure or NULL
2759 *
2760 * Write to a register using the admin queue commands
2761 **/
2762i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2763 u32 reg_addr, u64 reg_val,
2764 struct i40e_asq_cmd_details *cmd_details)
2765{
2766 struct i40e_aq_desc desc;
2767 struct i40e_aqc_debug_reg_read_write *cmd =
2768 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2769 i40e_status status;
2770
2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2772
2773 cmd->address = cpu_to_le32(reg_addr);
2774 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2775 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2776
2777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2778
2779 return status;
2780}
2781
2782/**
2783 * i40e_aq_set_hmc_resource_profile
2784 * @hw: pointer to the hw struct
2785 * @profile: type of profile the HMC is to be set as
2786 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2787 * @cmd_details: pointer to command details structure or NULL
2788 *
2789 * set the HMC profile of the device.
2790 **/
2791i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2792 enum i40e_aq_hmc_profile profile,
2793 u8 pe_vf_enabled_count,
2794 struct i40e_asq_cmd_details *cmd_details)
2795{
2796 struct i40e_aq_desc desc;
2797 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2798 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2799 i40e_status status;
2800
2801 i40e_fill_default_direct_cmd_desc(&desc,
2802 i40e_aqc_opc_set_hmc_resource_profile);
2803
2804 cmd->pm_profile = (u8)profile;
2805 cmd->pe_vf_enabled = pe_vf_enabled_count;
2806
2807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2808
2809 return status;
2810}
2811
2812/**
2813 * i40e_aq_request_resource
2814 * @hw: pointer to the hw struct
2815 * @resource: resource id
2816 * @access: access type
2817 * @sdp_number: resource number
2818 * @timeout: the maximum time in ms that the driver may hold the resource
2819 * @cmd_details: pointer to command details structure or NULL
2820 *
2821 * requests common resource using the admin queue commands
2822 **/
2823i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2824 enum i40e_aq_resources_ids resource,
2825 enum i40e_aq_resource_access_type access,
2826 u8 sdp_number, u64 *timeout,
2827 struct i40e_asq_cmd_details *cmd_details)
2828{
2829 struct i40e_aq_desc desc;
2830 struct i40e_aqc_request_resource *cmd_resp =
2831 (struct i40e_aqc_request_resource *)&desc.params.raw;
2832 i40e_status status;
2833
2834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2835
2836 cmd_resp->resource_id = cpu_to_le16(resource);
2837 cmd_resp->access_type = cpu_to_le16(access);
2838 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2839
2840 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2841 /* The completion specifies the maximum time in ms that the driver
2842 * may hold the resource in the Timeout field.
2843 * If the resource is held by someone else, the command completes with
2844 * busy return value and the timeout field indicates the maximum time
2845 * the current owner of the resource has to free it.
2846 */
2847 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2848 *timeout = le32_to_cpu(cmd_resp->timeout);
2849
2850 return status;
2851}
2852
2853/**
2854 * i40e_aq_release_resource
2855 * @hw: pointer to the hw struct
2856 * @resource: resource id
2857 * @sdp_number: resource number
2858 * @cmd_details: pointer to command details structure or NULL
2859 *
2860 * release common resource using the admin queue commands
2861 **/
2862i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2863 enum i40e_aq_resources_ids resource,
2864 u8 sdp_number,
2865 struct i40e_asq_cmd_details *cmd_details)
2866{
2867 struct i40e_aq_desc desc;
2868 struct i40e_aqc_request_resource *cmd =
2869 (struct i40e_aqc_request_resource *)&desc.params.raw;
2870 i40e_status status;
2871
2872 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2873
2874 cmd->resource_id = cpu_to_le16(resource);
2875 cmd->resource_number = cpu_to_le32(sdp_number);
2876
2877 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2878
2879 return status;
2880}
2881
2882/**
2883 * i40e_aq_read_nvm
2884 * @hw: pointer to the hw struct
2885 * @module_pointer: module pointer location in words from the NVM beginning
2886 * @offset: byte offset from the module beginning
2887 * @length: length of the section to be read (in bytes from the offset)
2888 * @data: command buffer (size [bytes] = length)
2889 * @last_command: tells if this is the last command in a series
2890 * @cmd_details: pointer to command details structure or NULL
2891 *
2892 * Read the NVM using the admin queue commands
2893 **/
2894i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2895 u32 offset, u16 length, void *data,
2896 bool last_command,
2897 struct i40e_asq_cmd_details *cmd_details)
2898{
2899 struct i40e_aq_desc desc;
2900 struct i40e_aqc_nvm_update *cmd =
2901 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2902 i40e_status status;
2903
2904 /* In offset the highest byte must be zeroed. */
2905 if (offset & 0xFF000000) {
2906 status = I40E_ERR_PARAM;
2907 goto i40e_aq_read_nvm_exit;
2908 }
2909
2910 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2911
2912 /* If this is the last command in a series, set the proper flag. */
2913 if (last_command)
2914 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2915 cmd->module_pointer = module_pointer;
2916 cmd->offset = cpu_to_le32(offset);
2917 cmd->length = cpu_to_le16(length);
2918
2919 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2920 if (length > I40E_AQ_LARGE_BUF)
2921 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2922
2923 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2924
2925i40e_aq_read_nvm_exit:
2926 return status;
2927}
2928
2929/**
2930 * i40e_aq_erase_nvm
2931 * @hw: pointer to the hw struct
2932 * @module_pointer: module pointer location in words from the NVM beginning
2933 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2934 * @length: length of the section to be erased (expressed in 4 KB)
2935 * @last_command: tells if this is the last command in a series
2936 * @cmd_details: pointer to command details structure or NULL
2937 *
2938 * Erase the NVM sector using the admin queue commands
2939 **/
2940i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2941 u32 offset, u16 length, bool last_command,
2942 struct i40e_asq_cmd_details *cmd_details)
2943{
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_nvm_update *cmd =
2946 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2947 i40e_status status;
2948
2949 /* In offset the highest byte must be zeroed. */
2950 if (offset & 0xFF000000) {
2951 status = I40E_ERR_PARAM;
2952 goto i40e_aq_erase_nvm_exit;
2953 }
2954
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2956
2957 /* If this is the last command in a series, set the proper flag. */
2958 if (last_command)
2959 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2960 cmd->module_pointer = module_pointer;
2961 cmd->offset = cpu_to_le32(offset);
2962 cmd->length = cpu_to_le16(length);
2963
2964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2965
2966i40e_aq_erase_nvm_exit:
2967 return status;
2968}
2969
2970/**
2971 * i40e_parse_discover_capabilities
2972 * @hw: pointer to the hw struct
2973 * @buff: pointer to a buffer containing device/function capability records
2974 * @cap_count: number of capability records in the list
2975 * @list_type_opc: type of capabilities list to parse
2976 *
2977 * Parse the device/function capabilities list.
2978 **/
2979static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2980 u32 cap_count,
2981 enum i40e_admin_queue_opc list_type_opc)
2982{
2983 struct i40e_aqc_list_capabilities_element_resp *cap;
2984 u32 valid_functions, num_functions;
2985 u32 number, logical_id, phys_id;
2986 struct i40e_hw_capabilities *p;
2987 u8 major_rev;
2988 u32 i = 0;
2989 u16 id;
2990
2991 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2992
2993 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2994 p = &hw->dev_caps;
2995 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2996 p = &hw->func_caps;
2997 else
2998 return;
2999
3000 for (i = 0; i < cap_count; i++, cap++) {
3001 id = le16_to_cpu(cap->id);
3002 number = le32_to_cpu(cap->number);
3003 logical_id = le32_to_cpu(cap->logical_id);
3004 phys_id = le32_to_cpu(cap->phys_id);
3005 major_rev = cap->major_rev;
3006
3007 switch (id) {
3008 case I40E_AQ_CAP_ID_SWITCH_MODE:
3009 p->switch_mode = number;
3010 break;
3011 case I40E_AQ_CAP_ID_MNG_MODE:
3012 p->management_mode = number;
3013 break;
3014 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3015 p->npar_enable = number;
3016 break;
3017 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3018 p->os2bmc = number;
3019 break;
3020 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3021 p->valid_functions = number;
3022 break;
3023 case I40E_AQ_CAP_ID_SRIOV:
3024 if (number == 1)
3025 p->sr_iov_1_1 = true;
3026 break;
3027 case I40E_AQ_CAP_ID_VF:
3028 p->num_vfs = number;
3029 p->vf_base_id = logical_id;
3030 break;
3031 case I40E_AQ_CAP_ID_VMDQ:
3032 if (number == 1)
3033 p->vmdq = true;
3034 break;
3035 case I40E_AQ_CAP_ID_8021QBG:
3036 if (number == 1)
3037 p->evb_802_1_qbg = true;
3038 break;
3039 case I40E_AQ_CAP_ID_8021QBR:
3040 if (number == 1)
3041 p->evb_802_1_qbh = true;
3042 break;
3043 case I40E_AQ_CAP_ID_VSI:
3044 p->num_vsis = number;
3045 break;
3046 case I40E_AQ_CAP_ID_DCB:
3047 if (number == 1) {
3048 p->dcb = true;
3049 p->enabled_tcmap = logical_id;
3050 p->maxtc = phys_id;
3051 }
3052 break;
3053 case I40E_AQ_CAP_ID_FCOE:
3054 if (number == 1)
3055 p->fcoe = true;
3056 break;
3057 case I40E_AQ_CAP_ID_ISCSI:
3058 if (number == 1)
3059 p->iscsi = true;
3060 break;
3061 case I40E_AQ_CAP_ID_RSS:
3062 p->rss = true;
3063 p->rss_table_size = number;
3064 p->rss_table_entry_width = logical_id;
3065 break;
3066 case I40E_AQ_CAP_ID_RXQ:
3067 p->num_rx_qp = number;
3068 p->base_queue = phys_id;
3069 break;
3070 case I40E_AQ_CAP_ID_TXQ:
3071 p->num_tx_qp = number;
3072 p->base_queue = phys_id;
3073 break;
3074 case I40E_AQ_CAP_ID_MSIX:
3075 p->num_msix_vectors = number;
3076 break;
3077 case I40E_AQ_CAP_ID_VF_MSIX:
3078 p->num_msix_vectors_vf = number;
3079 break;
3080 case I40E_AQ_CAP_ID_FLEX10:
3081 if (major_rev == 1) {
3082 if (number == 1) {
3083 p->flex10_enable = true;
3084 p->flex10_capable = true;
3085 }
3086 } else {
3087 /* Capability revision >= 2 */
3088 if (number & 1)
3089 p->flex10_enable = true;
3090 if (number & 2)
3091 p->flex10_capable = true;
3092 }
3093 p->flex10_mode = logical_id;
3094 p->flex10_status = phys_id;
3095 break;
3096 case I40E_AQ_CAP_ID_CEM:
3097 if (number == 1)
3098 p->mgmt_cem = true;
3099 break;
3100 case I40E_AQ_CAP_ID_IWARP:
3101 if (number == 1)
3102 p->iwarp = true;
3103 break;
3104 case I40E_AQ_CAP_ID_LED:
3105 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3106 p->led[phys_id] = true;
3107 break;
3108 case I40E_AQ_CAP_ID_SDP:
3109 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3110 p->sdp[phys_id] = true;
3111 break;
3112 case I40E_AQ_CAP_ID_MDIO:
3113 if (number == 1) {
3114 p->mdio_port_num = phys_id;
3115 p->mdio_port_mode = logical_id;
3116 }
3117 break;
3118 case I40E_AQ_CAP_ID_1588:
3119 if (number == 1)
3120 p->ieee_1588 = true;
3121 break;
3122 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3123 p->fd = true;
3124 p->fd_filters_guaranteed = number;
3125 p->fd_filters_best_effort = logical_id;
3126 break;
3127 case I40E_AQ_CAP_ID_WSR_PROT:
3128 p->wr_csr_prot = (u64)number;
3129 p->wr_csr_prot |= (u64)logical_id << 32;
3130 break;
3131 default:
3132 break;
3133 }
3134 }
3135
3136 if (p->fcoe)
3137 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3138
3139 /* Software override ensuring FCoE is disabled if npar or mfp
3140 * mode because it is not supported in these modes.
3141 */
3142 if (p->npar_enable || p->flex10_enable)
3143 p->fcoe = false;
3144
3145 /* count the enabled ports (aka the "not disabled" ports) */
3146 hw->num_ports = 0;
3147 for (i = 0; i < 4; i++) {
3148 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3149 u64 port_cfg = 0;
3150
3151 /* use AQ read to get the physical register offset instead
3152 * of the port relative offset
3153 */
3154 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3155 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3156 hw->num_ports++;
3157 }
3158
3159 valid_functions = p->valid_functions;
3160 num_functions = 0;
3161 while (valid_functions) {
3162 if (valid_functions & 1)
3163 num_functions++;
3164 valid_functions >>= 1;
3165 }
3166
3167 /* partition id is 1-based, and functions are evenly spread
3168 * across the ports as partitions
3169 */
3170 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3171 hw->num_partitions = num_functions / hw->num_ports;
3172
3173 /* additional HW specific goodies that might
3174 * someday be HW version specific
3175 */
3176 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3177}
3178
3179/**
3180 * i40e_aq_discover_capabilities
3181 * @hw: pointer to the hw struct
3182 * @buff: a virtual buffer to hold the capabilities
3183 * @buff_size: Size of the virtual buffer
3184 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3185 * @list_type_opc: capabilities type to discover - pass in the command opcode
3186 * @cmd_details: pointer to command details structure or NULL
3187 *
3188 * Get the device capabilities descriptions from the firmware
3189 **/
3190i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3191 void *buff, u16 buff_size, u16 *data_size,
3192 enum i40e_admin_queue_opc list_type_opc,
3193 struct i40e_asq_cmd_details *cmd_details)
3194{
3195 struct i40e_aqc_list_capabilites *cmd;
3196 struct i40e_aq_desc desc;
3197 i40e_status status = 0;
3198
3199 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3200
3201 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3202 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3203 status = I40E_ERR_PARAM;
3204 goto exit;
3205 }
3206
3207 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3208
3209 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3210 if (buff_size > I40E_AQ_LARGE_BUF)
3211 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3212
3213 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3214 *data_size = le16_to_cpu(desc.datalen);
3215
3216 if (status)
3217 goto exit;
3218
3219 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3220 list_type_opc);
3221
3222exit:
3223 return status;
3224}
3225
3226/**
3227 * i40e_aq_update_nvm
3228 * @hw: pointer to the hw struct
3229 * @module_pointer: module pointer location in words from the NVM beginning
3230 * @offset: byte offset from the module beginning
3231 * @length: length of the section to be written (in bytes from the offset)
3232 * @data: command buffer (size [bytes] = length)
3233 * @last_command: tells if this is the last command in a series
3234 * @cmd_details: pointer to command details structure or NULL
3235 *
3236 * Update the NVM using the admin queue commands
3237 **/
3238i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3239 u32 offset, u16 length, void *data,
3240 bool last_command,
3241 struct i40e_asq_cmd_details *cmd_details)
3242{
3243 struct i40e_aq_desc desc;
3244 struct i40e_aqc_nvm_update *cmd =
3245 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3246 i40e_status status;
3247
3248 /* In offset the highest byte must be zeroed. */
3249 if (offset & 0xFF000000) {
3250 status = I40E_ERR_PARAM;
3251 goto i40e_aq_update_nvm_exit;
3252 }
3253
3254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3255
3256 /* If this is the last command in a series, set the proper flag. */
3257 if (last_command)
3258 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3259 cmd->module_pointer = module_pointer;
3260 cmd->offset = cpu_to_le32(offset);
3261 cmd->length = cpu_to_le16(length);
3262
3263 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3264 if (length > I40E_AQ_LARGE_BUF)
3265 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3266
3267 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3268
3269i40e_aq_update_nvm_exit:
3270 return status;
3271}
3272
3273/**
3274 * i40e_aq_get_lldp_mib
3275 * @hw: pointer to the hw struct
3276 * @bridge_type: type of bridge requested
3277 * @mib_type: Local, Remote or both Local and Remote MIBs
3278 * @buff: pointer to a user supplied buffer to store the MIB block
3279 * @buff_size: size of the buffer (in bytes)
3280 * @local_len : length of the returned Local LLDP MIB
3281 * @remote_len: length of the returned Remote LLDP MIB
3282 * @cmd_details: pointer to command details structure or NULL
3283 *
3284 * Requests the complete LLDP MIB (entire packet).
3285 **/
3286i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3287 u8 mib_type, void *buff, u16 buff_size,
3288 u16 *local_len, u16 *remote_len,
3289 struct i40e_asq_cmd_details *cmd_details)
3290{
3291 struct i40e_aq_desc desc;
3292 struct i40e_aqc_lldp_get_mib *cmd =
3293 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3294 struct i40e_aqc_lldp_get_mib *resp =
3295 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3296 i40e_status status;
3297
3298 if (buff_size == 0 || !buff)
3299 return I40E_ERR_PARAM;
3300
3301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3302 /* Indirect Command */
3303 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3304
3305 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3306 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3307 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3308
3309 desc.datalen = cpu_to_le16(buff_size);
3310
3311 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3312 if (buff_size > I40E_AQ_LARGE_BUF)
3313 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3314
3315 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3316 if (!status) {
3317 if (local_len != NULL)
3318 *local_len = le16_to_cpu(resp->local_len);
3319 if (remote_len != NULL)
3320 *remote_len = le16_to_cpu(resp->remote_len);
3321 }
3322
3323 return status;
3324}
3325
3326/**
3327 * i40e_aq_cfg_lldp_mib_change_event
3328 * @hw: pointer to the hw struct
3329 * @enable_update: Enable or Disable event posting
3330 * @cmd_details: pointer to command details structure or NULL
3331 *
3332 * Enable or Disable posting of an event on ARQ when LLDP MIB
3333 * associated with the interface changes
3334 **/
3335i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3336 bool enable_update,
3337 struct i40e_asq_cmd_details *cmd_details)
3338{
3339 struct i40e_aq_desc desc;
3340 struct i40e_aqc_lldp_update_mib *cmd =
3341 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3342 i40e_status status;
3343
3344 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3345
3346 if (!enable_update)
3347 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3348
3349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350
3351 return status;
3352}
3353
3354/**
3355 * i40e_aq_stop_lldp
3356 * @hw: pointer to the hw struct
3357 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3358 * @cmd_details: pointer to command details structure or NULL
3359 *
3360 * Stop or Shutdown the embedded LLDP Agent
3361 **/
3362i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3363 struct i40e_asq_cmd_details *cmd_details)
3364{
3365 struct i40e_aq_desc desc;
3366 struct i40e_aqc_lldp_stop *cmd =
3367 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3368 i40e_status status;
3369
3370 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3371
3372 if (shutdown_agent)
3373 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3374
3375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3376
3377 return status;
3378}
3379
3380/**
3381 * i40e_aq_start_lldp
3382 * @hw: pointer to the hw struct
3383 * @cmd_details: pointer to command details structure or NULL
3384 *
3385 * Start the embedded LLDP Agent on all ports.
3386 **/
3387i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3388 struct i40e_asq_cmd_details *cmd_details)
3389{
3390 struct i40e_aq_desc desc;
3391 struct i40e_aqc_lldp_start *cmd =
3392 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3393 i40e_status status;
3394
3395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3396
3397 cmd->command = I40E_AQ_LLDP_AGENT_START;
3398
3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400
3401 return status;
3402}
3403
3404/**
3405 * i40e_aq_get_cee_dcb_config
3406 * @hw: pointer to the hw struct
3407 * @buff: response buffer that stores CEE operational configuration
3408 * @buff_size: size of the buffer passed
3409 * @cmd_details: pointer to command details structure or NULL
3410 *
3411 * Get CEE DCBX mode operational configuration from firmware
3412 **/
3413i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3414 void *buff, u16 buff_size,
3415 struct i40e_asq_cmd_details *cmd_details)
3416{
3417 struct i40e_aq_desc desc;
3418 i40e_status status;
3419
3420 if (buff_size == 0 || !buff)
3421 return I40E_ERR_PARAM;
3422
3423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3424
3425 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3426 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3427 cmd_details);
3428
3429 return status;
3430}
3431
3432/**
3433 * i40e_aq_add_udp_tunnel
3434 * @hw: pointer to the hw struct
3435 * @udp_port: the UDP port to add
3436 * @header_len: length of the tunneling header length in DWords
3437 * @protocol_index: protocol index type
3438 * @filter_index: pointer to filter index
3439 * @cmd_details: pointer to command details structure or NULL
3440 **/
3441i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3442 u16 udp_port, u8 protocol_index,
3443 u8 *filter_index,
3444 struct i40e_asq_cmd_details *cmd_details)
3445{
3446 struct i40e_aq_desc desc;
3447 struct i40e_aqc_add_udp_tunnel *cmd =
3448 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3449 struct i40e_aqc_del_udp_tunnel_completion *resp =
3450 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3451 i40e_status status;
3452
3453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3454
3455 cmd->udp_port = cpu_to_le16(udp_port);
3456 cmd->protocol_type = protocol_index;
3457
3458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459
3460 if (!status && filter_index)
3461 *filter_index = resp->index;
3462
3463 return status;
3464}
3465
3466/**
3467 * i40e_aq_del_udp_tunnel
3468 * @hw: pointer to the hw struct
3469 * @index: filter index
3470 * @cmd_details: pointer to command details structure or NULL
3471 **/
3472i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3473 struct i40e_asq_cmd_details *cmd_details)
3474{
3475 struct i40e_aq_desc desc;
3476 struct i40e_aqc_remove_udp_tunnel *cmd =
3477 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3478 i40e_status status;
3479
3480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3481
3482 cmd->index = index;
3483
3484 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3485
3486 return status;
3487}
3488
3489/**
3490 * i40e_aq_delete_element - Delete switch element
3491 * @hw: pointer to the hw struct
3492 * @seid: the SEID to delete from the switch
3493 * @cmd_details: pointer to command details structure or NULL
3494 *
3495 * This deletes a switch element from the switch.
3496 **/
3497i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3498 struct i40e_asq_cmd_details *cmd_details)
3499{
3500 struct i40e_aq_desc desc;
3501 struct i40e_aqc_switch_seid *cmd =
3502 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3503 i40e_status status;
3504
3505 if (seid == 0)
3506 return I40E_ERR_PARAM;
3507
3508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3509
3510 cmd->seid = cpu_to_le16(seid);
3511
3512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513
3514 return status;
3515}
3516
3517/**
3518 * i40e_aq_dcb_updated - DCB Updated Command
3519 * @hw: pointer to the hw struct
3520 * @cmd_details: pointer to command details structure or NULL
3521 *
3522 * EMP will return when the shared RPB settings have been
3523 * recomputed and modified. The retval field in the descriptor
3524 * will be set to 0 when RPB is modified.
3525 **/
3526i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3527 struct i40e_asq_cmd_details *cmd_details)
3528{
3529 struct i40e_aq_desc desc;
3530 i40e_status status;
3531
3532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3533
3534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3535
3536 return status;
3537}
3538
3539/**
3540 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3541 * @hw: pointer to the hw struct
3542 * @seid: seid for the physical port/switching component/vsi
3543 * @buff: Indirect buffer to hold data parameters and response
3544 * @buff_size: Indirect buffer size
3545 * @opcode: Tx scheduler AQ command opcode
3546 * @cmd_details: pointer to command details structure or NULL
3547 *
3548 * Generic command handler for Tx scheduler AQ commands
3549 **/
3550static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3551 void *buff, u16 buff_size,
3552 enum i40e_admin_queue_opc opcode,
3553 struct i40e_asq_cmd_details *cmd_details)
3554{
3555 struct i40e_aq_desc desc;
3556 struct i40e_aqc_tx_sched_ind *cmd =
3557 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3558 i40e_status status;
3559 bool cmd_param_flag = false;
3560
3561 switch (opcode) {
3562 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3563 case i40e_aqc_opc_configure_vsi_tc_bw:
3564 case i40e_aqc_opc_enable_switching_comp_ets:
3565 case i40e_aqc_opc_modify_switching_comp_ets:
3566 case i40e_aqc_opc_disable_switching_comp_ets:
3567 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3568 case i40e_aqc_opc_configure_switching_comp_bw_config:
3569 cmd_param_flag = true;
3570 break;
3571 case i40e_aqc_opc_query_vsi_bw_config:
3572 case i40e_aqc_opc_query_vsi_ets_sla_config:
3573 case i40e_aqc_opc_query_switching_comp_ets_config:
3574 case i40e_aqc_opc_query_port_ets_config:
3575 case i40e_aqc_opc_query_switching_comp_bw_config:
3576 cmd_param_flag = false;
3577 break;
3578 default:
3579 return I40E_ERR_PARAM;
3580 }
3581
3582 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3583
3584 /* Indirect command */
3585 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3586 if (cmd_param_flag)
3587 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3588 if (buff_size > I40E_AQ_LARGE_BUF)
3589 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3590
3591 desc.datalen = cpu_to_le16(buff_size);
3592
3593 cmd->vsi_seid = cpu_to_le16(seid);
3594
3595 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3596
3597 return status;
3598}
3599
3600/**
3601 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3602 * @hw: pointer to the hw struct
3603 * @seid: VSI seid
3604 * @credit: BW limit credits (0 = disabled)
3605 * @max_credit: Max BW limit credits
3606 * @cmd_details: pointer to command details structure or NULL
3607 **/
3608i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3609 u16 seid, u16 credit, u8 max_credit,
3610 struct i40e_asq_cmd_details *cmd_details)
3611{
3612 struct i40e_aq_desc desc;
3613 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3614 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3615 i40e_status status;
3616
3617 i40e_fill_default_direct_cmd_desc(&desc,
3618 i40e_aqc_opc_configure_vsi_bw_limit);
3619
3620 cmd->vsi_seid = cpu_to_le16(seid);
3621 cmd->credit = cpu_to_le16(credit);
3622 cmd->max_credit = max_credit;
3623
3624 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3625
3626 return status;
3627}
3628
3629/**
3630 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3631 * @hw: pointer to the hw struct
3632 * @seid: VSI seid
3633 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3634 * @cmd_details: pointer to command details structure or NULL
3635 **/
3636i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3637 u16 seid,
3638 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3639 struct i40e_asq_cmd_details *cmd_details)
3640{
3641 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3642 i40e_aqc_opc_configure_vsi_tc_bw,
3643 cmd_details);
3644}
3645
3646/**
3647 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3648 * @hw: pointer to the hw struct
3649 * @seid: seid of the switching component connected to Physical Port
3650 * @ets_data: Buffer holding ETS parameters
3651 * @cmd_details: pointer to command details structure or NULL
3652 **/
3653i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3654 u16 seid,
3655 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3656 enum i40e_admin_queue_opc opcode,
3657 struct i40e_asq_cmd_details *cmd_details)
3658{
3659 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3660 sizeof(*ets_data), opcode, cmd_details);
3661}
3662
3663/**
3664 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3665 * @hw: pointer to the hw struct
3666 * @seid: seid of the switching component
3667 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3668 * @cmd_details: pointer to command details structure or NULL
3669 **/
3670i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3671 u16 seid,
3672 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3673 struct i40e_asq_cmd_details *cmd_details)
3674{
3675 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3676 i40e_aqc_opc_configure_switching_comp_bw_config,
3677 cmd_details);
3678}
3679
3680/**
3681 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3682 * @hw: pointer to the hw struct
3683 * @seid: seid of the VSI
3684 * @bw_data: Buffer to hold VSI BW configuration
3685 * @cmd_details: pointer to command details structure or NULL
3686 **/
3687i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3688 u16 seid,
3689 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3690 struct i40e_asq_cmd_details *cmd_details)
3691{
3692 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3693 i40e_aqc_opc_query_vsi_bw_config,
3694 cmd_details);
3695}
3696
3697/**
3698 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3699 * @hw: pointer to the hw struct
3700 * @seid: seid of the VSI
3701 * @bw_data: Buffer to hold VSI BW configuration per TC
3702 * @cmd_details: pointer to command details structure or NULL
3703 **/
3704i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3705 u16 seid,
3706 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3707 struct i40e_asq_cmd_details *cmd_details)
3708{
3709 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3710 i40e_aqc_opc_query_vsi_ets_sla_config,
3711 cmd_details);
3712}
3713
3714/**
3715 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3716 * @hw: pointer to the hw struct
3717 * @seid: seid of the switching component
3718 * @bw_data: Buffer to hold switching component's per TC BW config
3719 * @cmd_details: pointer to command details structure or NULL
3720 **/
3721i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3722 u16 seid,
3723 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3724 struct i40e_asq_cmd_details *cmd_details)
3725{
3726 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3727 i40e_aqc_opc_query_switching_comp_ets_config,
3728 cmd_details);
3729}
3730
3731/**
3732 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3733 * @hw: pointer to the hw struct
3734 * @seid: seid of the VSI or switching component connected to Physical Port
3735 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3736 * @cmd_details: pointer to command details structure or NULL
3737 **/
3738i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3739 u16 seid,
3740 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3741 struct i40e_asq_cmd_details *cmd_details)
3742{
3743 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3744 i40e_aqc_opc_query_port_ets_config,
3745 cmd_details);
3746}
3747
3748/**
3749 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3750 * @hw: pointer to the hw struct
3751 * @seid: seid of the switching component
3752 * @bw_data: Buffer to hold switching component's BW configuration
3753 * @cmd_details: pointer to command details structure or NULL
3754 **/
3755i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3756 u16 seid,
3757 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3758 struct i40e_asq_cmd_details *cmd_details)
3759{
3760 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3761 i40e_aqc_opc_query_switching_comp_bw_config,
3762 cmd_details);
3763}
3764
3765/**
3766 * i40e_validate_filter_settings
3767 * @hw: pointer to the hardware structure
3768 * @settings: Filter control settings
3769 *
3770 * Check and validate the filter control settings passed.
3771 * The function checks for the valid filter/context sizes being
3772 * passed for FCoE and PE.
3773 *
3774 * Returns 0 if the values passed are valid and within
3775 * range else returns an error.
3776 **/
3777static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3778 struct i40e_filter_control_settings *settings)
3779{
3780 u32 fcoe_cntx_size, fcoe_filt_size;
3781 u32 pe_cntx_size, pe_filt_size;
3782 u32 fcoe_fmax;
3783 u32 val;
3784
3785 /* Validate FCoE settings passed */
3786 switch (settings->fcoe_filt_num) {
3787 case I40E_HASH_FILTER_SIZE_1K:
3788 case I40E_HASH_FILTER_SIZE_2K:
3789 case I40E_HASH_FILTER_SIZE_4K:
3790 case I40E_HASH_FILTER_SIZE_8K:
3791 case I40E_HASH_FILTER_SIZE_16K:
3792 case I40E_HASH_FILTER_SIZE_32K:
3793 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3794 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3795 break;
3796 default:
3797 return I40E_ERR_PARAM;
3798 }
3799
3800 switch (settings->fcoe_cntx_num) {
3801 case I40E_DMA_CNTX_SIZE_512:
3802 case I40E_DMA_CNTX_SIZE_1K:
3803 case I40E_DMA_CNTX_SIZE_2K:
3804 case I40E_DMA_CNTX_SIZE_4K:
3805 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3806 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3807 break;
3808 default:
3809 return I40E_ERR_PARAM;
3810 }
3811
3812 /* Validate PE settings passed */
3813 switch (settings->pe_filt_num) {
3814 case I40E_HASH_FILTER_SIZE_1K:
3815 case I40E_HASH_FILTER_SIZE_2K:
3816 case I40E_HASH_FILTER_SIZE_4K:
3817 case I40E_HASH_FILTER_SIZE_8K:
3818 case I40E_HASH_FILTER_SIZE_16K:
3819 case I40E_HASH_FILTER_SIZE_32K:
3820 case I40E_HASH_FILTER_SIZE_64K:
3821 case I40E_HASH_FILTER_SIZE_128K:
3822 case I40E_HASH_FILTER_SIZE_256K:
3823 case I40E_HASH_FILTER_SIZE_512K:
3824 case I40E_HASH_FILTER_SIZE_1M:
3825 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3826 pe_filt_size <<= (u32)settings->pe_filt_num;
3827 break;
3828 default:
3829 return I40E_ERR_PARAM;
3830 }
3831
3832 switch (settings->pe_cntx_num) {
3833 case I40E_DMA_CNTX_SIZE_512:
3834 case I40E_DMA_CNTX_SIZE_1K:
3835 case I40E_DMA_CNTX_SIZE_2K:
3836 case I40E_DMA_CNTX_SIZE_4K:
3837 case I40E_DMA_CNTX_SIZE_8K:
3838 case I40E_DMA_CNTX_SIZE_16K:
3839 case I40E_DMA_CNTX_SIZE_32K:
3840 case I40E_DMA_CNTX_SIZE_64K:
3841 case I40E_DMA_CNTX_SIZE_128K:
3842 case I40E_DMA_CNTX_SIZE_256K:
3843 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3844 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3845 break;
3846 default:
3847 return I40E_ERR_PARAM;
3848 }
3849
3850 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3851 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3852 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3853 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3854 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3855 return I40E_ERR_INVALID_SIZE;
3856
3857 return 0;
3858}
3859
3860/**
3861 * i40e_set_filter_control
3862 * @hw: pointer to the hardware structure
3863 * @settings: Filter control settings
3864 *
3865 * Set the Queue Filters for PE/FCoE and enable filters required
3866 * for a single PF. It is expected that these settings are programmed
3867 * at the driver initialization time.
3868 **/
3869i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3870 struct i40e_filter_control_settings *settings)
3871{
3872 i40e_status ret = 0;
3873 u32 hash_lut_size = 0;
3874 u32 val;
3875
3876 if (!settings)
3877 return I40E_ERR_PARAM;
3878
3879 /* Validate the input settings */
3880 ret = i40e_validate_filter_settings(hw, settings);
3881 if (ret)
3882 return ret;
3883
3884 /* Read the PF Queue Filter control register */
3885 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3886
3887 /* Program required PE hash buckets for the PF */
3888 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3889 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3890 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3891 /* Program required PE contexts for the PF */
3892 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3893 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3894 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3895
3896 /* Program required FCoE hash buckets for the PF */
3897 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3898 val |= ((u32)settings->fcoe_filt_num <<
3899 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3900 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3901 /* Program required FCoE DDP contexts for the PF */
3902 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3903 val |= ((u32)settings->fcoe_cntx_num <<
3904 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3905 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3906
3907 /* Program Hash LUT size for the PF */
3908 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3909 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3910 hash_lut_size = 1;
3911 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3912 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3913
3914 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3915 if (settings->enable_fdir)
3916 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3917 if (settings->enable_ethtype)
3918 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3919 if (settings->enable_macvlan)
3920 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3921
3922 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3923
3924 return 0;
3925}
3926
3927/**
3928 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3929 * @hw: pointer to the hw struct
3930 * @mac_addr: MAC address to use in the filter
3931 * @ethtype: Ethertype to use in the filter
3932 * @flags: Flags that needs to be applied to the filter
3933 * @vsi_seid: seid of the control VSI
3934 * @queue: VSI queue number to send the packet to
3935 * @is_add: Add control packet filter if True else remove
3936 * @stats: Structure to hold information on control filter counts
3937 * @cmd_details: pointer to command details structure or NULL
3938 *
3939 * This command will Add or Remove control packet filter for a control VSI.
3940 * In return it will update the total number of perfect filter count in
3941 * the stats member.
3942 **/
3943i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3944 u8 *mac_addr, u16 ethtype, u16 flags,
3945 u16 vsi_seid, u16 queue, bool is_add,
3946 struct i40e_control_filter_stats *stats,
3947 struct i40e_asq_cmd_details *cmd_details)
3948{
3949 struct i40e_aq_desc desc;
3950 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3951 (struct i40e_aqc_add_remove_control_packet_filter *)
3952 &desc.params.raw;
3953 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3954 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3955 &desc.params.raw;
3956 i40e_status status;
3957
3958 if (vsi_seid == 0)
3959 return I40E_ERR_PARAM;
3960
3961 if (is_add) {
3962 i40e_fill_default_direct_cmd_desc(&desc,
3963 i40e_aqc_opc_add_control_packet_filter);
3964 cmd->queue = cpu_to_le16(queue);
3965 } else {
3966 i40e_fill_default_direct_cmd_desc(&desc,
3967 i40e_aqc_opc_remove_control_packet_filter);
3968 }
3969
3970 if (mac_addr)
3971 ether_addr_copy(cmd->mac, mac_addr);
3972
3973 cmd->etype = cpu_to_le16(ethtype);
3974 cmd->flags = cpu_to_le16(flags);
3975 cmd->seid = cpu_to_le16(vsi_seid);
3976
3977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3978
3979 if (!status && stats) {
3980 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3981 stats->etype_used = le16_to_cpu(resp->etype_used);
3982 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3983 stats->etype_free = le16_to_cpu(resp->etype_free);
3984 }
3985
3986 return status;
3987}
3988
3989/**
3990 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3991 * @hw: pointer to the hw struct
3992 * @seid: VSI seid to add ethertype filter from
3993 **/
3994#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3995void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3996 u16 seid)
3997{
3998 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3999 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4000 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4001 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4002 i40e_status status;
4003
4004 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4005 seid, 0, true, NULL,
4006 NULL);
4007 if (status)
4008 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4009}
4010
4011/**
4012 * i40e_aq_alternate_read
4013 * @hw: pointer to the hardware structure
4014 * @reg_addr0: address of first dword to be read
4015 * @reg_val0: pointer for data read from 'reg_addr0'
4016 * @reg_addr1: address of second dword to be read
4017 * @reg_val1: pointer for data read from 'reg_addr1'
4018 *
4019 * Read one or two dwords from alternate structure. Fields are indicated
4020 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4021 * is not passed then only register at 'reg_addr0' is read.
4022 *
4023 **/
4024static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4025 u32 reg_addr0, u32 *reg_val0,
4026 u32 reg_addr1, u32 *reg_val1)
4027{
4028 struct i40e_aq_desc desc;
4029 struct i40e_aqc_alternate_write *cmd_resp =
4030 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4031 i40e_status status;
4032
4033 if (!reg_val0)
4034 return I40E_ERR_PARAM;
4035
4036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4037 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4038 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4039
4040 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4041
4042 if (!status) {
4043 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4044
4045 if (reg_val1)
4046 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4047 }
4048
4049 return status;
4050}
4051
4052/**
4053 * i40e_aq_resume_port_tx
4054 * @hw: pointer to the hardware structure
4055 * @cmd_details: pointer to command details structure or NULL
4056 *
4057 * Resume port's Tx traffic
4058 **/
4059i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4060 struct i40e_asq_cmd_details *cmd_details)
4061{
4062 struct i40e_aq_desc desc;
4063 i40e_status status;
4064
4065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4066
4067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4068
4069 return status;
4070}
4071
4072/**
4073 * i40e_set_pci_config_data - store PCI bus info
4074 * @hw: pointer to hardware structure
4075 * @link_status: the link status word from PCI config space
4076 *
4077 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4078 **/
4079void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4080{
4081 hw->bus.type = i40e_bus_type_pci_express;
4082
4083 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4084 case PCI_EXP_LNKSTA_NLW_X1:
4085 hw->bus.width = i40e_bus_width_pcie_x1;
4086 break;
4087 case PCI_EXP_LNKSTA_NLW_X2:
4088 hw->bus.width = i40e_bus_width_pcie_x2;
4089 break;
4090 case PCI_EXP_LNKSTA_NLW_X4:
4091 hw->bus.width = i40e_bus_width_pcie_x4;
4092 break;
4093 case PCI_EXP_LNKSTA_NLW_X8:
4094 hw->bus.width = i40e_bus_width_pcie_x8;
4095 break;
4096 default:
4097 hw->bus.width = i40e_bus_width_unknown;
4098 break;
4099 }
4100
4101 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4102 case PCI_EXP_LNKSTA_CLS_2_5GB:
4103 hw->bus.speed = i40e_bus_speed_2500;
4104 break;
4105 case PCI_EXP_LNKSTA_CLS_5_0GB:
4106 hw->bus.speed = i40e_bus_speed_5000;
4107 break;
4108 case PCI_EXP_LNKSTA_CLS_8_0GB:
4109 hw->bus.speed = i40e_bus_speed_8000;
4110 break;
4111 default:
4112 hw->bus.speed = i40e_bus_speed_unknown;
4113 break;
4114 }
4115}
4116
4117/**
4118 * i40e_aq_debug_dump
4119 * @hw: pointer to the hardware structure
4120 * @cluster_id: specific cluster to dump
4121 * @table_id: table id within cluster
4122 * @start_index: index of line in the block to read
4123 * @buff_size: dump buffer size
4124 * @buff: dump buffer
4125 * @ret_buff_size: actual buffer size returned
4126 * @ret_next_table: next block to read
4127 * @ret_next_index: next index to read
4128 *
4129 * Dump internal FW/HW data for debug purposes.
4130 *
4131 **/
4132i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4133 u8 table_id, u32 start_index, u16 buff_size,
4134 void *buff, u16 *ret_buff_size,
4135 u8 *ret_next_table, u32 *ret_next_index,
4136 struct i40e_asq_cmd_details *cmd_details)
4137{
4138 struct i40e_aq_desc desc;
4139 struct i40e_aqc_debug_dump_internals *cmd =
4140 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4141 struct i40e_aqc_debug_dump_internals *resp =
4142 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4143 i40e_status status;
4144
4145 if (buff_size == 0 || !buff)
4146 return I40E_ERR_PARAM;
4147
4148 i40e_fill_default_direct_cmd_desc(&desc,
4149 i40e_aqc_opc_debug_dump_internals);
4150 /* Indirect Command */
4151 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4152 if (buff_size > I40E_AQ_LARGE_BUF)
4153 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4154
4155 cmd->cluster_id = cluster_id;
4156 cmd->table_id = table_id;
4157 cmd->idx = cpu_to_le32(start_index);
4158
4159 desc.datalen = cpu_to_le16(buff_size);
4160
4161 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4162 if (!status) {
4163 if (ret_buff_size)
4164 *ret_buff_size = le16_to_cpu(desc.datalen);
4165 if (ret_next_table)
4166 *ret_next_table = resp->table_id;
4167 if (ret_next_index)
4168 *ret_next_index = le32_to_cpu(resp->idx);
4169 }
4170
4171 return status;
4172}
4173
4174/**
4175 * i40e_read_bw_from_alt_ram
4176 * @hw: pointer to the hardware structure
4177 * @max_bw: pointer for max_bw read
4178 * @min_bw: pointer for min_bw read
4179 * @min_valid: pointer for bool that is true if min_bw is a valid value
4180 * @max_valid: pointer for bool that is true if max_bw is a valid value
4181 *
4182 * Read bw from the alternate ram for the given pf
4183 **/
4184i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4185 u32 *max_bw, u32 *min_bw,
4186 bool *min_valid, bool *max_valid)
4187{
4188 i40e_status status;
4189 u32 max_bw_addr, min_bw_addr;
4190
4191 /* Calculate the address of the min/max bw registers */
4192 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4193 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4194 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4195 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4196 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4197 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4198
4199 /* Read the bandwidths from alt ram */
4200 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4201 min_bw_addr, min_bw);
4202
4203 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4204 *min_valid = true;
4205 else
4206 *min_valid = false;
4207
4208 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4209 *max_valid = true;
4210 else
4211 *max_valid = false;
4212
4213 return status;
4214}
4215
4216/**
4217 * i40e_aq_configure_partition_bw
4218 * @hw: pointer to the hardware structure
4219 * @bw_data: Buffer holding valid pfs and bw limits
4220 * @cmd_details: pointer to command details
4221 *
4222 * Configure partitions guaranteed/max bw
4223 **/
4224i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4225 struct i40e_aqc_configure_partition_bw_data *bw_data,
4226 struct i40e_asq_cmd_details *cmd_details)
4227{
4228 i40e_status status;
4229 struct i40e_aq_desc desc;
4230 u16 bwd_size = sizeof(*bw_data);
4231
4232 i40e_fill_default_direct_cmd_desc(&desc,
4233 i40e_aqc_opc_configure_partition_bw);
4234
4235 /* Indirect command */
4236 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4238
4239 if (bwd_size > I40E_AQ_LARGE_BUF)
4240 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4241
4242 desc.datalen = cpu_to_le16(bwd_size);
4243
4244 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4245 cmd_details);
4246
4247 return status;
4248}
4249
4250/**
4251 * i40e_read_phy_register
4252 * @hw: pointer to the HW structure
4253 * @page: registers page number
4254 * @reg: register address in the page
4255 * @phy_adr: PHY address on MDIO interface
4256 * @value: PHY register value
4257 *
4258 * Reads specified PHY register value
4259 **/
4260i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4261 u8 page, u16 reg, u8 phy_addr,
4262 u16 *value)
4263{
4264 i40e_status status = I40E_ERR_TIMEOUT;
4265 u32 command = 0;
4266 u16 retry = 1000;
4267 u8 port_num = hw->func_caps.mdio_port_num;
4268
4269 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4270 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4271 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4272 (I40E_MDIO_OPCODE_ADDRESS) |
4273 (I40E_MDIO_STCODE) |
4274 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4275 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4276 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4277 do {
4278 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4279 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4280 status = 0;
4281 break;
4282 }
4283 usleep_range(10, 20);
4284 retry--;
4285 } while (retry);
4286
4287 if (status) {
4288 i40e_debug(hw, I40E_DEBUG_PHY,
4289 "PHY: Can't write command to external PHY.\n");
4290 goto phy_read_end;
4291 }
4292
4293 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4294 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4295 (I40E_MDIO_OPCODE_READ) |
4296 (I40E_MDIO_STCODE) |
4297 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4298 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4299 status = I40E_ERR_TIMEOUT;
4300 retry = 1000;
4301 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4302 do {
4303 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4304 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4305 status = 0;
4306 break;
4307 }
4308 usleep_range(10, 20);
4309 retry--;
4310 } while (retry);
4311
4312 if (!status) {
4313 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4314 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4315 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4316 } else {
4317 i40e_debug(hw, I40E_DEBUG_PHY,
4318 "PHY: Can't read register value from external PHY.\n");
4319 }
4320
4321phy_read_end:
4322 return status;
4323}
4324
4325/**
4326 * i40e_write_phy_register
4327 * @hw: pointer to the HW structure
4328 * @page: registers page number
4329 * @reg: register address in the page
4330 * @phy_adr: PHY address on MDIO interface
4331 * @value: PHY register value
4332 *
4333 * Writes value to specified PHY register
4334 **/
4335i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4336 u8 page, u16 reg, u8 phy_addr,
4337 u16 value)
4338{
4339 i40e_status status = I40E_ERR_TIMEOUT;
4340 u32 command = 0;
4341 u16 retry = 1000;
4342 u8 port_num = hw->func_caps.mdio_port_num;
4343
4344 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4345 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4346 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4347 (I40E_MDIO_OPCODE_ADDRESS) |
4348 (I40E_MDIO_STCODE) |
4349 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4350 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4351 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4352 do {
4353 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4354 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4355 status = 0;
4356 break;
4357 }
4358 usleep_range(10, 20);
4359 retry--;
4360 } while (retry);
4361 if (status) {
4362 i40e_debug(hw, I40E_DEBUG_PHY,
4363 "PHY: Can't write command to external PHY.\n");
4364 goto phy_write_end;
4365 }
4366
4367 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4368 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4369
4370 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4371 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4372 (I40E_MDIO_OPCODE_WRITE) |
4373 (I40E_MDIO_STCODE) |
4374 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4375 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4376 status = I40E_ERR_TIMEOUT;
4377 retry = 1000;
4378 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4379 do {
4380 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4381 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4382 status = 0;
4383 break;
4384 }
4385 usleep_range(10, 20);
4386 retry--;
4387 } while (retry);
4388
4389phy_write_end:
4390 return status;
4391}
4392
4393/**
4394 * i40e_get_phy_address
4395 * @hw: pointer to the HW structure
4396 * @dev_num: PHY port num that address we want
4397 * @phy_addr: Returned PHY address
4398 *
4399 * Gets PHY address for current port
4400 **/
4401u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4402{
4403 u8 port_num = hw->func_caps.mdio_port_num;
4404 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4405
4406 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4407}
4408
4409/**
4410 * i40e_blink_phy_led
4411 * @hw: pointer to the HW structure
4412 * @time: time how long led will blinks in secs
4413 * @interval: gap between LED on and off in msecs
4414 *
4415 * Blinks PHY link LED
4416 **/
4417i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4418 u32 time, u32 interval)
4419{
4420 i40e_status status = 0;
4421 u32 i;
4422 u16 led_ctl;
4423 u16 gpio_led_port;
4424 u16 led_reg;
4425 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4426 u8 phy_addr = 0;
4427 u8 port_num;
4428
4429 i = rd32(hw, I40E_PFGEN_PORTNUM);
4430 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4431 phy_addr = i40e_get_phy_address(hw, port_num);
4432
4433 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4434 led_addr++) {
4435 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4436 led_addr, phy_addr, &led_reg);
4437 if (status)
4438 goto phy_blinking_end;
4439 led_ctl = led_reg;
4440 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4441 led_reg = 0;
4442 status = i40e_write_phy_register(hw,
4443 I40E_PHY_COM_REG_PAGE,
4444 led_addr, phy_addr,
4445 led_reg);
4446 if (status)
4447 goto phy_blinking_end;
4448 break;
4449 }
4450 }
4451
4452 if (time > 0 && interval > 0) {
4453 for (i = 0; i < time * 1000; i += interval) {
4454 status = i40e_read_phy_register(hw,
4455 I40E_PHY_COM_REG_PAGE,
4456 led_addr, phy_addr,
4457 &led_reg);
4458 if (status)
4459 goto restore_config;
4460 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4461 led_reg = 0;
4462 else
4463 led_reg = I40E_PHY_LED_MANUAL_ON;
4464 status = i40e_write_phy_register(hw,
4465 I40E_PHY_COM_REG_PAGE,
4466 led_addr, phy_addr,
4467 led_reg);
4468 if (status)
4469 goto restore_config;
4470 msleep(interval);
4471 }
4472 }
4473
4474restore_config:
4475 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4476 phy_addr, led_ctl);
4477
4478phy_blinking_end:
4479 return status;
4480}
4481
4482/**
4483 * i40e_led_get_phy - return current on/off mode
4484 * @hw: pointer to the hw struct
4485 * @led_addr: address of led register to use
4486 * @val: original value of register to use
4487 *
4488 **/
4489i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4490 u16 *val)
4491{
4492 i40e_status status = 0;
4493 u16 gpio_led_port;
4494 u8 phy_addr = 0;
4495 u16 reg_val;
4496 u16 temp_addr;
4497 u8 port_num;
4498 u32 i;
4499
4500 temp_addr = I40E_PHY_LED_PROV_REG_1;
4501 i = rd32(hw, I40E_PFGEN_PORTNUM);
4502 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4503 phy_addr = i40e_get_phy_address(hw, port_num);
4504
4505 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4506 temp_addr++) {
4507 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4508 temp_addr, phy_addr, ®_val);
4509 if (status)
4510 return status;
4511 *val = reg_val;
4512 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4513 *led_addr = temp_addr;
4514 break;
4515 }
4516 }
4517 return status;
4518}
4519
4520/**
4521 * i40e_led_set_phy
4522 * @hw: pointer to the HW structure
4523 * @on: true or false
4524 * @mode: original val plus bit for set or ignore
4525 * Set led's on or off when controlled by the PHY
4526 *
4527 **/
4528i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4529 u16 led_addr, u32 mode)
4530{
4531 i40e_status status = 0;
4532 u16 led_ctl = 0;
4533 u16 led_reg = 0;
4534 u8 phy_addr = 0;
4535 u8 port_num;
4536 u32 i;
4537
4538 i = rd32(hw, I40E_PFGEN_PORTNUM);
4539 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4540 phy_addr = i40e_get_phy_address(hw, port_num);
4541
4542 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4543 phy_addr, &led_reg);
4544 if (status)
4545 return status;
4546 led_ctl = led_reg;
4547 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4548 led_reg = 0;
4549 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4550 led_addr, phy_addr, led_reg);
4551 if (status)
4552 return status;
4553 }
4554 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4555 led_addr, phy_addr, &led_reg);
4556 if (status)
4557 goto restore_config;
4558 if (on)
4559 led_reg = I40E_PHY_LED_MANUAL_ON;
4560 else
4561 led_reg = 0;
4562 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4563 led_addr, phy_addr, led_reg);
4564 if (status)
4565 goto restore_config;
4566 if (mode & I40E_PHY_LED_MODE_ORIG) {
4567 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4568 status = i40e_write_phy_register(hw,
4569 I40E_PHY_COM_REG_PAGE,
4570 led_addr, phy_addr, led_ctl);
4571 }
4572 return status;
4573restore_config:
4574 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4575 phy_addr, led_ctl);
4576 return status;
4577}
4578
4579/**
4580 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4581 * @hw: pointer to the hw struct
4582 * @reg_addr: register address
4583 * @reg_val: ptr to register value
4584 * @cmd_details: pointer to command details structure or NULL
4585 *
4586 * Use the firmware to read the Rx control register,
4587 * especially useful if the Rx unit is under heavy pressure
4588 **/
4589i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4590 u32 reg_addr, u32 *reg_val,
4591 struct i40e_asq_cmd_details *cmd_details)
4592{
4593 struct i40e_aq_desc desc;
4594 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4595 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4596 i40e_status status;
4597
4598 if (!reg_val)
4599 return I40E_ERR_PARAM;
4600
4601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4602
4603 cmd_resp->address = cpu_to_le32(reg_addr);
4604
4605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4606
4607 if (status == 0)
4608 *reg_val = le32_to_cpu(cmd_resp->value);
4609
4610 return status;
4611}
4612
4613/**
4614 * i40e_read_rx_ctl - read from an Rx control register
4615 * @hw: pointer to the hw struct
4616 * @reg_addr: register address
4617 **/
4618u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4619{
4620 i40e_status status = 0;
4621 bool use_register;
4622 int retry = 5;
4623 u32 val = 0;
4624
4625 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4626 if (!use_register) {
4627do_retry:
4628 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4629 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4630 usleep_range(1000, 2000);
4631 retry--;
4632 goto do_retry;
4633 }
4634 }
4635
4636 /* if the AQ access failed, try the old-fashioned way */
4637 if (status || use_register)
4638 val = rd32(hw, reg_addr);
4639
4640 return val;
4641}
4642
4643/**
4644 * i40e_aq_rx_ctl_write_register
4645 * @hw: pointer to the hw struct
4646 * @reg_addr: register address
4647 * @reg_val: register value
4648 * @cmd_details: pointer to command details structure or NULL
4649 *
4650 * Use the firmware to write to an Rx control register,
4651 * especially useful if the Rx unit is under heavy pressure
4652 **/
4653i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4654 u32 reg_addr, u32 reg_val,
4655 struct i40e_asq_cmd_details *cmd_details)
4656{
4657 struct i40e_aq_desc desc;
4658 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4659 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4660 i40e_status status;
4661
4662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4663
4664 cmd->address = cpu_to_le32(reg_addr);
4665 cmd->value = cpu_to_le32(reg_val);
4666
4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4668
4669 return status;
4670}
4671
4672/**
4673 * i40e_write_rx_ctl - write to an Rx control register
4674 * @hw: pointer to the hw struct
4675 * @reg_addr: register address
4676 * @reg_val: register value
4677 **/
4678void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4679{
4680 i40e_status status = 0;
4681 bool use_register;
4682 int retry = 5;
4683
4684 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4685 if (!use_register) {
4686do_retry:
4687 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4688 reg_val, NULL);
4689 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4690 usleep_range(1000, 2000);
4691 retry--;
4692 goto do_retry;
4693 }
4694 }
4695
4696 /* if the AQ access failed, try the old-fashioned way */
4697 if (status || use_register)
4698 wr32(hw, reg_addr, reg_val);
4699}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#include "i40e.h"
5#include "i40e_type.h"
6#include "i40e_adminq.h"
7#include "i40e_prototype.h"
8#include <linux/avf/virtchnl.h>
9
10/**
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
13 *
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
16 **/
17i40e_status i40e_set_mac_type(struct i40e_hw *hw)
18{
19 i40e_status status = 0;
20
21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
22 switch (hw->device_id) {
23 case I40E_DEV_ID_SFP_XL710:
24 case I40E_DEV_ID_QEMU:
25 case I40E_DEV_ID_KX_B:
26 case I40E_DEV_ID_KX_C:
27 case I40E_DEV_ID_QSFP_A:
28 case I40E_DEV_ID_QSFP_B:
29 case I40E_DEV_ID_QSFP_C:
30 case I40E_DEV_ID_5G_BASE_T_BC:
31 case I40E_DEV_ID_10G_BASE_T:
32 case I40E_DEV_ID_10G_BASE_T4:
33 case I40E_DEV_ID_10G_BASE_T_BC:
34 case I40E_DEV_ID_10G_B:
35 case I40E_DEV_ID_10G_SFP:
36 case I40E_DEV_ID_20G_KR2:
37 case I40E_DEV_ID_20G_KR2_A:
38 case I40E_DEV_ID_25G_B:
39 case I40E_DEV_ID_25G_SFP28:
40 case I40E_DEV_ID_X710_N3000:
41 case I40E_DEV_ID_XXV710_N3000:
42 hw->mac.type = I40E_MAC_XL710;
43 break;
44 case I40E_DEV_ID_KX_X722:
45 case I40E_DEV_ID_QSFP_X722:
46 case I40E_DEV_ID_SFP_X722:
47 case I40E_DEV_ID_1G_BASE_T_X722:
48 case I40E_DEV_ID_10G_BASE_T_X722:
49 case I40E_DEV_ID_SFP_I_X722:
50 hw->mac.type = I40E_MAC_X722;
51 break;
52 default:
53 hw->mac.type = I40E_MAC_GENERIC;
54 break;
55 }
56 } else {
57 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
58 }
59
60 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
61 hw->mac.type, status);
62 return status;
63}
64
65/**
66 * i40e_aq_str - convert AQ err code to a string
67 * @hw: pointer to the HW structure
68 * @aq_err: the AQ error code to convert
69 **/
70const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
71{
72 switch (aq_err) {
73 case I40E_AQ_RC_OK:
74 return "OK";
75 case I40E_AQ_RC_EPERM:
76 return "I40E_AQ_RC_EPERM";
77 case I40E_AQ_RC_ENOENT:
78 return "I40E_AQ_RC_ENOENT";
79 case I40E_AQ_RC_ESRCH:
80 return "I40E_AQ_RC_ESRCH";
81 case I40E_AQ_RC_EINTR:
82 return "I40E_AQ_RC_EINTR";
83 case I40E_AQ_RC_EIO:
84 return "I40E_AQ_RC_EIO";
85 case I40E_AQ_RC_ENXIO:
86 return "I40E_AQ_RC_ENXIO";
87 case I40E_AQ_RC_E2BIG:
88 return "I40E_AQ_RC_E2BIG";
89 case I40E_AQ_RC_EAGAIN:
90 return "I40E_AQ_RC_EAGAIN";
91 case I40E_AQ_RC_ENOMEM:
92 return "I40E_AQ_RC_ENOMEM";
93 case I40E_AQ_RC_EACCES:
94 return "I40E_AQ_RC_EACCES";
95 case I40E_AQ_RC_EFAULT:
96 return "I40E_AQ_RC_EFAULT";
97 case I40E_AQ_RC_EBUSY:
98 return "I40E_AQ_RC_EBUSY";
99 case I40E_AQ_RC_EEXIST:
100 return "I40E_AQ_RC_EEXIST";
101 case I40E_AQ_RC_EINVAL:
102 return "I40E_AQ_RC_EINVAL";
103 case I40E_AQ_RC_ENOTTY:
104 return "I40E_AQ_RC_ENOTTY";
105 case I40E_AQ_RC_ENOSPC:
106 return "I40E_AQ_RC_ENOSPC";
107 case I40E_AQ_RC_ENOSYS:
108 return "I40E_AQ_RC_ENOSYS";
109 case I40E_AQ_RC_ERANGE:
110 return "I40E_AQ_RC_ERANGE";
111 case I40E_AQ_RC_EFLUSHED:
112 return "I40E_AQ_RC_EFLUSHED";
113 case I40E_AQ_RC_BAD_ADDR:
114 return "I40E_AQ_RC_BAD_ADDR";
115 case I40E_AQ_RC_EMODE:
116 return "I40E_AQ_RC_EMODE";
117 case I40E_AQ_RC_EFBIG:
118 return "I40E_AQ_RC_EFBIG";
119 }
120
121 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
122 return hw->err_str;
123}
124
125/**
126 * i40e_stat_str - convert status err code to a string
127 * @hw: pointer to the HW structure
128 * @stat_err: the status error code to convert
129 **/
130const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
131{
132 switch (stat_err) {
133 case 0:
134 return "OK";
135 case I40E_ERR_NVM:
136 return "I40E_ERR_NVM";
137 case I40E_ERR_NVM_CHECKSUM:
138 return "I40E_ERR_NVM_CHECKSUM";
139 case I40E_ERR_PHY:
140 return "I40E_ERR_PHY";
141 case I40E_ERR_CONFIG:
142 return "I40E_ERR_CONFIG";
143 case I40E_ERR_PARAM:
144 return "I40E_ERR_PARAM";
145 case I40E_ERR_MAC_TYPE:
146 return "I40E_ERR_MAC_TYPE";
147 case I40E_ERR_UNKNOWN_PHY:
148 return "I40E_ERR_UNKNOWN_PHY";
149 case I40E_ERR_LINK_SETUP:
150 return "I40E_ERR_LINK_SETUP";
151 case I40E_ERR_ADAPTER_STOPPED:
152 return "I40E_ERR_ADAPTER_STOPPED";
153 case I40E_ERR_INVALID_MAC_ADDR:
154 return "I40E_ERR_INVALID_MAC_ADDR";
155 case I40E_ERR_DEVICE_NOT_SUPPORTED:
156 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
157 case I40E_ERR_MASTER_REQUESTS_PENDING:
158 return "I40E_ERR_MASTER_REQUESTS_PENDING";
159 case I40E_ERR_INVALID_LINK_SETTINGS:
160 return "I40E_ERR_INVALID_LINK_SETTINGS";
161 case I40E_ERR_AUTONEG_NOT_COMPLETE:
162 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
163 case I40E_ERR_RESET_FAILED:
164 return "I40E_ERR_RESET_FAILED";
165 case I40E_ERR_SWFW_SYNC:
166 return "I40E_ERR_SWFW_SYNC";
167 case I40E_ERR_NO_AVAILABLE_VSI:
168 return "I40E_ERR_NO_AVAILABLE_VSI";
169 case I40E_ERR_NO_MEMORY:
170 return "I40E_ERR_NO_MEMORY";
171 case I40E_ERR_BAD_PTR:
172 return "I40E_ERR_BAD_PTR";
173 case I40E_ERR_RING_FULL:
174 return "I40E_ERR_RING_FULL";
175 case I40E_ERR_INVALID_PD_ID:
176 return "I40E_ERR_INVALID_PD_ID";
177 case I40E_ERR_INVALID_QP_ID:
178 return "I40E_ERR_INVALID_QP_ID";
179 case I40E_ERR_INVALID_CQ_ID:
180 return "I40E_ERR_INVALID_CQ_ID";
181 case I40E_ERR_INVALID_CEQ_ID:
182 return "I40E_ERR_INVALID_CEQ_ID";
183 case I40E_ERR_INVALID_AEQ_ID:
184 return "I40E_ERR_INVALID_AEQ_ID";
185 case I40E_ERR_INVALID_SIZE:
186 return "I40E_ERR_INVALID_SIZE";
187 case I40E_ERR_INVALID_ARP_INDEX:
188 return "I40E_ERR_INVALID_ARP_INDEX";
189 case I40E_ERR_INVALID_FPM_FUNC_ID:
190 return "I40E_ERR_INVALID_FPM_FUNC_ID";
191 case I40E_ERR_QP_INVALID_MSG_SIZE:
192 return "I40E_ERR_QP_INVALID_MSG_SIZE";
193 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
194 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
195 case I40E_ERR_INVALID_FRAG_COUNT:
196 return "I40E_ERR_INVALID_FRAG_COUNT";
197 case I40E_ERR_QUEUE_EMPTY:
198 return "I40E_ERR_QUEUE_EMPTY";
199 case I40E_ERR_INVALID_ALIGNMENT:
200 return "I40E_ERR_INVALID_ALIGNMENT";
201 case I40E_ERR_FLUSHED_QUEUE:
202 return "I40E_ERR_FLUSHED_QUEUE";
203 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
204 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
205 case I40E_ERR_INVALID_IMM_DATA_SIZE:
206 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
207 case I40E_ERR_TIMEOUT:
208 return "I40E_ERR_TIMEOUT";
209 case I40E_ERR_OPCODE_MISMATCH:
210 return "I40E_ERR_OPCODE_MISMATCH";
211 case I40E_ERR_CQP_COMPL_ERROR:
212 return "I40E_ERR_CQP_COMPL_ERROR";
213 case I40E_ERR_INVALID_VF_ID:
214 return "I40E_ERR_INVALID_VF_ID";
215 case I40E_ERR_INVALID_HMCFN_ID:
216 return "I40E_ERR_INVALID_HMCFN_ID";
217 case I40E_ERR_BACKING_PAGE_ERROR:
218 return "I40E_ERR_BACKING_PAGE_ERROR";
219 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
220 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
221 case I40E_ERR_INVALID_PBLE_INDEX:
222 return "I40E_ERR_INVALID_PBLE_INDEX";
223 case I40E_ERR_INVALID_SD_INDEX:
224 return "I40E_ERR_INVALID_SD_INDEX";
225 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
226 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
227 case I40E_ERR_INVALID_SD_TYPE:
228 return "I40E_ERR_INVALID_SD_TYPE";
229 case I40E_ERR_MEMCPY_FAILED:
230 return "I40E_ERR_MEMCPY_FAILED";
231 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
232 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
233 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
234 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
235 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
236 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
237 case I40E_ERR_SRQ_ENABLED:
238 return "I40E_ERR_SRQ_ENABLED";
239 case I40E_ERR_ADMIN_QUEUE_ERROR:
240 return "I40E_ERR_ADMIN_QUEUE_ERROR";
241 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
242 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
243 case I40E_ERR_BUF_TOO_SHORT:
244 return "I40E_ERR_BUF_TOO_SHORT";
245 case I40E_ERR_ADMIN_QUEUE_FULL:
246 return "I40E_ERR_ADMIN_QUEUE_FULL";
247 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
248 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
249 case I40E_ERR_BAD_IWARP_CQE:
250 return "I40E_ERR_BAD_IWARP_CQE";
251 case I40E_ERR_NVM_BLANK_MODE:
252 return "I40E_ERR_NVM_BLANK_MODE";
253 case I40E_ERR_NOT_IMPLEMENTED:
254 return "I40E_ERR_NOT_IMPLEMENTED";
255 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
256 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
257 case I40E_ERR_DIAG_TEST_FAILED:
258 return "I40E_ERR_DIAG_TEST_FAILED";
259 case I40E_ERR_NOT_READY:
260 return "I40E_ERR_NOT_READY";
261 case I40E_NOT_SUPPORTED:
262 return "I40E_NOT_SUPPORTED";
263 case I40E_ERR_FIRMWARE_API_VERSION:
264 return "I40E_ERR_FIRMWARE_API_VERSION";
265 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
267 }
268
269 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
270 return hw->err_str;
271}
272
273/**
274 * i40e_debug_aq
275 * @hw: debug mask related to admin queue
276 * @mask: debug mask
277 * @desc: pointer to admin queue descriptor
278 * @buffer: pointer to command buffer
279 * @buf_len: max length of buffer
280 *
281 * Dumps debug log about adminq command with descriptor contents.
282 **/
283void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
284 void *buffer, u16 buf_len)
285{
286 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
287 u32 effective_mask = hw->debug_mask & mask;
288 char prefix[27];
289 u16 len;
290 u8 *buf = (u8 *)buffer;
291
292 if (!effective_mask || !desc)
293 return;
294
295 len = le16_to_cpu(aq_desc->datalen);
296
297 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
298 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
299 le16_to_cpu(aq_desc->opcode),
300 le16_to_cpu(aq_desc->flags),
301 le16_to_cpu(aq_desc->datalen),
302 le16_to_cpu(aq_desc->retval));
303 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
304 "\tcookie (h,l) 0x%08X 0x%08X\n",
305 le32_to_cpu(aq_desc->cookie_high),
306 le32_to_cpu(aq_desc->cookie_low));
307 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
308 "\tparam (0,1) 0x%08X 0x%08X\n",
309 le32_to_cpu(aq_desc->params.internal.param0),
310 le32_to_cpu(aq_desc->params.internal.param1));
311 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
312 "\taddr (h,l) 0x%08X 0x%08X\n",
313 le32_to_cpu(aq_desc->params.external.addr_high),
314 le32_to_cpu(aq_desc->params.external.addr_low));
315
316 if (buffer && buf_len != 0 && len != 0 &&
317 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
318 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
319 if (buf_len < len)
320 len = buf_len;
321
322 snprintf(prefix, sizeof(prefix),
323 "i40e %02x:%02x.%x: \t0x",
324 hw->bus.bus_id,
325 hw->bus.device,
326 hw->bus.func);
327
328 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
329 16, 1, buf, len, false);
330 }
331}
332
333/**
334 * i40e_check_asq_alive
335 * @hw: pointer to the hw struct
336 *
337 * Returns true if Queue is enabled else false.
338 **/
339bool i40e_check_asq_alive(struct i40e_hw *hw)
340{
341 if (hw->aq.asq.len)
342 return !!(rd32(hw, hw->aq.asq.len) &
343 I40E_PF_ATQLEN_ATQENABLE_MASK);
344 else
345 return false;
346}
347
348/**
349 * i40e_aq_queue_shutdown
350 * @hw: pointer to the hw struct
351 * @unloading: is the driver unloading itself
352 *
353 * Tell the Firmware that we're shutting down the AdminQ and whether
354 * or not the driver is unloading as well.
355 **/
356i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
357 bool unloading)
358{
359 struct i40e_aq_desc desc;
360 struct i40e_aqc_queue_shutdown *cmd =
361 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
362 i40e_status status;
363
364 i40e_fill_default_direct_cmd_desc(&desc,
365 i40e_aqc_opc_queue_shutdown);
366
367 if (unloading)
368 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
369 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
370
371 return status;
372}
373
374/**
375 * i40e_aq_get_set_rss_lut
376 * @hw: pointer to the hardware structure
377 * @vsi_id: vsi fw index
378 * @pf_lut: for PF table set true, for VSI table set false
379 * @lut: pointer to the lut buffer provided by the caller
380 * @lut_size: size of the lut buffer
381 * @set: set true to set the table, false to get the table
382 *
383 * Internal function to get or set RSS look up table
384 **/
385static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
386 u16 vsi_id, bool pf_lut,
387 u8 *lut, u16 lut_size,
388 bool set)
389{
390 i40e_status status;
391 struct i40e_aq_desc desc;
392 struct i40e_aqc_get_set_rss_lut *cmd_resp =
393 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
394
395 if (set)
396 i40e_fill_default_direct_cmd_desc(&desc,
397 i40e_aqc_opc_set_rss_lut);
398 else
399 i40e_fill_default_direct_cmd_desc(&desc,
400 i40e_aqc_opc_get_rss_lut);
401
402 /* Indirect command */
403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
404 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
405
406 cmd_resp->vsi_id =
407 cpu_to_le16((u16)((vsi_id <<
408 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
409 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
410 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
411
412 if (pf_lut)
413 cmd_resp->flags |= cpu_to_le16((u16)
414 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
415 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
416 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
417 else
418 cmd_resp->flags |= cpu_to_le16((u16)
419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
422
423 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
424
425 return status;
426}
427
428/**
429 * i40e_aq_get_rss_lut
430 * @hw: pointer to the hardware structure
431 * @vsi_id: vsi fw index
432 * @pf_lut: for PF table set true, for VSI table set false
433 * @lut: pointer to the lut buffer provided by the caller
434 * @lut_size: size of the lut buffer
435 *
436 * get the RSS lookup table, PF or VSI type
437 **/
438i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
439 bool pf_lut, u8 *lut, u16 lut_size)
440{
441 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
442 false);
443}
444
445/**
446 * i40e_aq_set_rss_lut
447 * @hw: pointer to the hardware structure
448 * @vsi_id: vsi fw index
449 * @pf_lut: for PF table set true, for VSI table set false
450 * @lut: pointer to the lut buffer provided by the caller
451 * @lut_size: size of the lut buffer
452 *
453 * set the RSS lookup table, PF or VSI type
454 **/
455i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
456 bool pf_lut, u8 *lut, u16 lut_size)
457{
458 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
459}
460
461/**
462 * i40e_aq_get_set_rss_key
463 * @hw: pointer to the hw struct
464 * @vsi_id: vsi fw index
465 * @key: pointer to key info struct
466 * @set: set true to set the key, false to get the key
467 *
468 * get the RSS key per VSI
469 **/
470static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
471 u16 vsi_id,
472 struct i40e_aqc_get_set_rss_key_data *key,
473 bool set)
474{
475 i40e_status status;
476 struct i40e_aq_desc desc;
477 struct i40e_aqc_get_set_rss_key *cmd_resp =
478 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
479 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
480
481 if (set)
482 i40e_fill_default_direct_cmd_desc(&desc,
483 i40e_aqc_opc_set_rss_key);
484 else
485 i40e_fill_default_direct_cmd_desc(&desc,
486 i40e_aqc_opc_get_rss_key);
487
488 /* Indirect command */
489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
491
492 cmd_resp->vsi_id =
493 cpu_to_le16((u16)((vsi_id <<
494 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
495 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
496 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
497
498 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
499
500 return status;
501}
502
503/**
504 * i40e_aq_get_rss_key
505 * @hw: pointer to the hw struct
506 * @vsi_id: vsi fw index
507 * @key: pointer to key info struct
508 *
509 **/
510i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
511 u16 vsi_id,
512 struct i40e_aqc_get_set_rss_key_data *key)
513{
514 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
515}
516
517/**
518 * i40e_aq_set_rss_key
519 * @hw: pointer to the hw struct
520 * @vsi_id: vsi fw index
521 * @key: pointer to key info struct
522 *
523 * set the RSS key per VSI
524 **/
525i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
526 u16 vsi_id,
527 struct i40e_aqc_get_set_rss_key_data *key)
528{
529 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
530}
531
532/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
533 * hardware to a bit-field that can be used by SW to more easily determine the
534 * packet type.
535 *
536 * Macros are used to shorten the table lines and make this table human
537 * readable.
538 *
539 * We store the PTYPE in the top byte of the bit field - this is just so that
540 * we can check that the table doesn't have a row missing, as the index into
541 * the table should be the PTYPE.
542 *
543 * Typical work flow:
544 *
545 * IF NOT i40e_ptype_lookup[ptype].known
546 * THEN
547 * Packet is unknown
548 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
549 * Use the rest of the fields to look at the tunnels, inner protocols, etc
550 * ELSE
551 * Use the enum i40e_rx_l2_ptype to decode the packet type
552 * ENDIF
553 */
554
555/* macro to make the table lines short, use explicit indexing with [PTYPE] */
556#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
557 [PTYPE] = { \
558 1, \
559 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
560 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
561 I40E_RX_PTYPE_##OUTER_FRAG, \
562 I40E_RX_PTYPE_TUNNEL_##T, \
563 I40E_RX_PTYPE_TUNNEL_END_##TE, \
564 I40E_RX_PTYPE_##TEF, \
565 I40E_RX_PTYPE_INNER_PROT_##I, \
566 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
567
568#define I40E_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
569
570/* shorter macros makes the table fit but are terse */
571#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
572#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
573#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
574
575/* Lookup table mapping in the 8-bit HW PTYPE to the bit field for decoding */
576struct i40e_rx_ptype_decoded i40e_ptype_lookup[BIT(8)] = {
577 /* L2 Packet types */
578 I40E_PTT_UNUSED_ENTRY(0),
579 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
580 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
581 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
582 I40E_PTT_UNUSED_ENTRY(4),
583 I40E_PTT_UNUSED_ENTRY(5),
584 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
586 I40E_PTT_UNUSED_ENTRY(8),
587 I40E_PTT_UNUSED_ENTRY(9),
588 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
590 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
591 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
593 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600
601 /* Non Tunneled IPv4 */
602 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
605 I40E_PTT_UNUSED_ENTRY(25),
606 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
607 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
608 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
609
610 /* IPv4 --> IPv4 */
611 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
612 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
613 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
614 I40E_PTT_UNUSED_ENTRY(32),
615 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
616 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
617 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
618
619 /* IPv4 --> IPv6 */
620 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
621 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
622 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
623 I40E_PTT_UNUSED_ENTRY(39),
624 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
625 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
626 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
627
628 /* IPv4 --> GRE/NAT */
629 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
630
631 /* IPv4 --> GRE/NAT --> IPv4 */
632 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
633 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
634 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
635 I40E_PTT_UNUSED_ENTRY(47),
636 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
637 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
638 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
639
640 /* IPv4 --> GRE/NAT --> IPv6 */
641 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
642 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
643 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
644 I40E_PTT_UNUSED_ENTRY(54),
645 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
646 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
647 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
648
649 /* IPv4 --> GRE/NAT --> MAC */
650 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
651
652 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
653 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
654 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
655 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(62),
657 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
658 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
659 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
660
661 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
662 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
663 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
664 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
665 I40E_PTT_UNUSED_ENTRY(69),
666 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
667 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
668 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
669
670 /* IPv4 --> GRE/NAT --> MAC/VLAN */
671 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
672
673 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
674 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
675 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
676 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
677 I40E_PTT_UNUSED_ENTRY(77),
678 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
679 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
680 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
681
682 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
683 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
684 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
685 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(84),
687 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
688 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
689 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
690
691 /* Non Tunneled IPv6 */
692 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
693 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
694 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(91),
696 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
697 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
698 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
699
700 /* IPv6 --> IPv4 */
701 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
702 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
703 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
704 I40E_PTT_UNUSED_ENTRY(98),
705 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
706 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
707 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
708
709 /* IPv6 --> IPv6 */
710 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
711 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
712 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
713 I40E_PTT_UNUSED_ENTRY(105),
714 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
715 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
716 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
717
718 /* IPv6 --> GRE/NAT */
719 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
720
721 /* IPv6 --> GRE/NAT -> IPv4 */
722 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
723 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
724 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
725 I40E_PTT_UNUSED_ENTRY(113),
726 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
727 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
728 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
729
730 /* IPv6 --> GRE/NAT -> IPv6 */
731 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
732 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
733 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
734 I40E_PTT_UNUSED_ENTRY(120),
735 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
736 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
737 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
738
739 /* IPv6 --> GRE/NAT -> MAC */
740 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
741
742 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
743 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
744 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
745 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
746 I40E_PTT_UNUSED_ENTRY(128),
747 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
748 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
749 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
750
751 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
752 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
753 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
754 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
755 I40E_PTT_UNUSED_ENTRY(135),
756 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
757 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
758 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
759
760 /* IPv6 --> GRE/NAT -> MAC/VLAN */
761 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
762
763 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
764 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
765 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
766 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
767 I40E_PTT_UNUSED_ENTRY(143),
768 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
769 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
770 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
771
772 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
773 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
774 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
775 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(150),
777 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
778 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
779 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
780
781 /* unused entries */
782 [154 ... 255] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
783};
784
785/**
786 * i40e_init_shared_code - Initialize the shared code
787 * @hw: pointer to hardware structure
788 *
789 * This assigns the MAC type and PHY code and inits the NVM.
790 * Does not touch the hardware. This function must be called prior to any
791 * other function in the shared code. The i40e_hw structure should be
792 * memset to 0 prior to calling this function. The following fields in
793 * hw structure should be filled in prior to calling this function:
794 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
795 * subsystem_vendor_id, and revision_id
796 **/
797i40e_status i40e_init_shared_code(struct i40e_hw *hw)
798{
799 i40e_status status = 0;
800 u32 port, ari, func_rid;
801
802 i40e_set_mac_type(hw);
803
804 switch (hw->mac.type) {
805 case I40E_MAC_XL710:
806 case I40E_MAC_X722:
807 break;
808 default:
809 return I40E_ERR_DEVICE_NOT_SUPPORTED;
810 }
811
812 hw->phy.get_link_info = true;
813
814 /* Determine port number and PF number*/
815 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
816 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
817 hw->port = (u8)port;
818 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
819 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
820 func_rid = rd32(hw, I40E_PF_FUNC_RID);
821 if (ari)
822 hw->pf_id = (u8)(func_rid & 0xff);
823 else
824 hw->pf_id = (u8)(func_rid & 0x7);
825
826 status = i40e_init_nvm(hw);
827 return status;
828}
829
830/**
831 * i40e_aq_mac_address_read - Retrieve the MAC addresses
832 * @hw: pointer to the hw struct
833 * @flags: a return indicator of what addresses were added to the addr store
834 * @addrs: the requestor's mac addr store
835 * @cmd_details: pointer to command details structure or NULL
836 **/
837static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
838 u16 *flags,
839 struct i40e_aqc_mac_address_read_data *addrs,
840 struct i40e_asq_cmd_details *cmd_details)
841{
842 struct i40e_aq_desc desc;
843 struct i40e_aqc_mac_address_read *cmd_data =
844 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
845 i40e_status status;
846
847 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
848 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
849
850 status = i40e_asq_send_command(hw, &desc, addrs,
851 sizeof(*addrs), cmd_details);
852 *flags = le16_to_cpu(cmd_data->command_flags);
853
854 return status;
855}
856
857/**
858 * i40e_aq_mac_address_write - Change the MAC addresses
859 * @hw: pointer to the hw struct
860 * @flags: indicates which MAC to be written
861 * @mac_addr: address to write
862 * @cmd_details: pointer to command details structure or NULL
863 **/
864i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
865 u16 flags, u8 *mac_addr,
866 struct i40e_asq_cmd_details *cmd_details)
867{
868 struct i40e_aq_desc desc;
869 struct i40e_aqc_mac_address_write *cmd_data =
870 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
871 i40e_status status;
872
873 i40e_fill_default_direct_cmd_desc(&desc,
874 i40e_aqc_opc_mac_address_write);
875 cmd_data->command_flags = cpu_to_le16(flags);
876 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
877 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
878 ((u32)mac_addr[3] << 16) |
879 ((u32)mac_addr[4] << 8) |
880 mac_addr[5]);
881
882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
883
884 return status;
885}
886
887/**
888 * i40e_get_mac_addr - get MAC address
889 * @hw: pointer to the HW structure
890 * @mac_addr: pointer to MAC address
891 *
892 * Reads the adapter's MAC address from register
893 **/
894i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
895{
896 struct i40e_aqc_mac_address_read_data addrs;
897 i40e_status status;
898 u16 flags = 0;
899
900 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
901
902 if (flags & I40E_AQC_LAN_ADDR_VALID)
903 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
904
905 return status;
906}
907
908/**
909 * i40e_get_port_mac_addr - get Port MAC address
910 * @hw: pointer to the HW structure
911 * @mac_addr: pointer to Port MAC address
912 *
913 * Reads the adapter's Port MAC address
914 **/
915i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
916{
917 struct i40e_aqc_mac_address_read_data addrs;
918 i40e_status status;
919 u16 flags = 0;
920
921 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
922 if (status)
923 return status;
924
925 if (flags & I40E_AQC_PORT_ADDR_VALID)
926 ether_addr_copy(mac_addr, addrs.port_mac);
927 else
928 status = I40E_ERR_INVALID_MAC_ADDR;
929
930 return status;
931}
932
933/**
934 * i40e_pre_tx_queue_cfg - pre tx queue configure
935 * @hw: pointer to the HW structure
936 * @queue: target PF queue index
937 * @enable: state change request
938 *
939 * Handles hw requirement to indicate intention to enable
940 * or disable target queue.
941 **/
942void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
943{
944 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
945 u32 reg_block = 0;
946 u32 reg_val;
947
948 if (abs_queue_idx >= 128) {
949 reg_block = abs_queue_idx / 128;
950 abs_queue_idx %= 128;
951 }
952
953 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
954 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
955 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
956
957 if (enable)
958 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
959 else
960 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
961
962 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
963}
964
965/**
966 * i40e_read_pba_string - Reads part number string from EEPROM
967 * @hw: pointer to hardware structure
968 * @pba_num: stores the part number string from the EEPROM
969 * @pba_num_size: part number string buffer length
970 *
971 * Reads the part number string from the EEPROM.
972 **/
973i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
974 u32 pba_num_size)
975{
976 i40e_status status = 0;
977 u16 pba_word = 0;
978 u16 pba_size = 0;
979 u16 pba_ptr = 0;
980 u16 i = 0;
981
982 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
983 if (status || (pba_word != 0xFAFA)) {
984 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
985 return status;
986 }
987
988 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
989 if (status) {
990 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
991 return status;
992 }
993
994 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
995 if (status) {
996 hw_dbg(hw, "Failed to read PBA Block size.\n");
997 return status;
998 }
999
1000 /* Subtract one to get PBA word count (PBA Size word is included in
1001 * total size)
1002 */
1003 pba_size--;
1004 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1005 hw_dbg(hw, "Buffer too small for PBA data.\n");
1006 return I40E_ERR_PARAM;
1007 }
1008
1009 for (i = 0; i < pba_size; i++) {
1010 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1011 if (status) {
1012 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1013 return status;
1014 }
1015
1016 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1017 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1018 }
1019 pba_num[(pba_size * 2)] = '\0';
1020
1021 return status;
1022}
1023
1024/**
1025 * i40e_get_media_type - Gets media type
1026 * @hw: pointer to the hardware structure
1027 **/
1028static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1029{
1030 enum i40e_media_type media;
1031
1032 switch (hw->phy.link_info.phy_type) {
1033 case I40E_PHY_TYPE_10GBASE_SR:
1034 case I40E_PHY_TYPE_10GBASE_LR:
1035 case I40E_PHY_TYPE_1000BASE_SX:
1036 case I40E_PHY_TYPE_1000BASE_LX:
1037 case I40E_PHY_TYPE_40GBASE_SR4:
1038 case I40E_PHY_TYPE_40GBASE_LR4:
1039 case I40E_PHY_TYPE_25GBASE_LR:
1040 case I40E_PHY_TYPE_25GBASE_SR:
1041 media = I40E_MEDIA_TYPE_FIBER;
1042 break;
1043 case I40E_PHY_TYPE_100BASE_TX:
1044 case I40E_PHY_TYPE_1000BASE_T:
1045 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
1046 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
1047 case I40E_PHY_TYPE_10GBASE_T:
1048 media = I40E_MEDIA_TYPE_BASET;
1049 break;
1050 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1051 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1052 case I40E_PHY_TYPE_10GBASE_CR1:
1053 case I40E_PHY_TYPE_40GBASE_CR4:
1054 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1055 case I40E_PHY_TYPE_40GBASE_AOC:
1056 case I40E_PHY_TYPE_10GBASE_AOC:
1057 case I40E_PHY_TYPE_25GBASE_CR:
1058 case I40E_PHY_TYPE_25GBASE_AOC:
1059 case I40E_PHY_TYPE_25GBASE_ACC:
1060 media = I40E_MEDIA_TYPE_DA;
1061 break;
1062 case I40E_PHY_TYPE_1000BASE_KX:
1063 case I40E_PHY_TYPE_10GBASE_KX4:
1064 case I40E_PHY_TYPE_10GBASE_KR:
1065 case I40E_PHY_TYPE_40GBASE_KR4:
1066 case I40E_PHY_TYPE_20GBASE_KR2:
1067 case I40E_PHY_TYPE_25GBASE_KR:
1068 media = I40E_MEDIA_TYPE_BACKPLANE;
1069 break;
1070 case I40E_PHY_TYPE_SGMII:
1071 case I40E_PHY_TYPE_XAUI:
1072 case I40E_PHY_TYPE_XFI:
1073 case I40E_PHY_TYPE_XLAUI:
1074 case I40E_PHY_TYPE_XLPPI:
1075 default:
1076 media = I40E_MEDIA_TYPE_UNKNOWN;
1077 break;
1078 }
1079
1080 return media;
1081}
1082
1083/**
1084 * i40e_poll_globr - Poll for Global Reset completion
1085 * @hw: pointer to the hardware structure
1086 * @retry_limit: how many times to retry before failure
1087 **/
1088static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1089 u32 retry_limit)
1090{
1091 u32 cnt, reg = 0;
1092
1093 for (cnt = 0; cnt < retry_limit; cnt++) {
1094 reg = rd32(hw, I40E_GLGEN_RSTAT);
1095 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1096 return 0;
1097 msleep(100);
1098 }
1099
1100 hw_dbg(hw, "Global reset failed.\n");
1101 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1102
1103 return I40E_ERR_RESET_FAILED;
1104}
1105
1106#define I40E_PF_RESET_WAIT_COUNT_A0 200
1107#define I40E_PF_RESET_WAIT_COUNT 200
1108/**
1109 * i40e_pf_reset - Reset the PF
1110 * @hw: pointer to the hardware structure
1111 *
1112 * Assuming someone else has triggered a global reset,
1113 * assure the global reset is complete and then reset the PF
1114 **/
1115i40e_status i40e_pf_reset(struct i40e_hw *hw)
1116{
1117 u32 cnt = 0;
1118 u32 cnt1 = 0;
1119 u32 reg = 0;
1120 u32 grst_del;
1121
1122 /* Poll for Global Reset steady state in case of recent GRST.
1123 * The grst delay value is in 100ms units, and we'll wait a
1124 * couple counts longer to be sure we don't just miss the end.
1125 */
1126 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1127 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1128 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1129
1130 /* It can take upto 15 secs for GRST steady state.
1131 * Bump it to 16 secs max to be safe.
1132 */
1133 grst_del = grst_del * 20;
1134
1135 for (cnt = 0; cnt < grst_del; cnt++) {
1136 reg = rd32(hw, I40E_GLGEN_RSTAT);
1137 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1138 break;
1139 msleep(100);
1140 }
1141 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1142 hw_dbg(hw, "Global reset polling failed to complete.\n");
1143 return I40E_ERR_RESET_FAILED;
1144 }
1145
1146 /* Now Wait for the FW to be ready */
1147 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1148 reg = rd32(hw, I40E_GLNVM_ULD);
1149 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1150 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1151 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1152 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1153 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1154 break;
1155 }
1156 usleep_range(10000, 20000);
1157 }
1158 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1159 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1160 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1161 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1162 return I40E_ERR_RESET_FAILED;
1163 }
1164
1165 /* If there was a Global Reset in progress when we got here,
1166 * we don't need to do the PF Reset
1167 */
1168 if (!cnt) {
1169 u32 reg2 = 0;
1170 if (hw->revision_id == 0)
1171 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1172 else
1173 cnt = I40E_PF_RESET_WAIT_COUNT;
1174 reg = rd32(hw, I40E_PFGEN_CTRL);
1175 wr32(hw, I40E_PFGEN_CTRL,
1176 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1177 for (; cnt; cnt--) {
1178 reg = rd32(hw, I40E_PFGEN_CTRL);
1179 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1180 break;
1181 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1182 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1183 break;
1184 usleep_range(1000, 2000);
1185 }
1186 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1187 if (i40e_poll_globr(hw, grst_del))
1188 return I40E_ERR_RESET_FAILED;
1189 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1190 hw_dbg(hw, "PF reset polling failed to complete.\n");
1191 return I40E_ERR_RESET_FAILED;
1192 }
1193 }
1194
1195 i40e_clear_pxe_mode(hw);
1196
1197 return 0;
1198}
1199
1200/**
1201 * i40e_clear_hw - clear out any left over hw state
1202 * @hw: pointer to the hw struct
1203 *
1204 * Clear queues and interrupts, typically called at init time,
1205 * but after the capabilities have been found so we know how many
1206 * queues and msix vectors have been allocated.
1207 **/
1208void i40e_clear_hw(struct i40e_hw *hw)
1209{
1210 u32 num_queues, base_queue;
1211 u32 num_pf_int;
1212 u32 num_vf_int;
1213 u32 num_vfs;
1214 u32 i, j;
1215 u32 val;
1216 u32 eol = 0x7ff;
1217
1218 /* get number of interrupts, queues, and VFs */
1219 val = rd32(hw, I40E_GLPCI_CNF2);
1220 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1221 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1222 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1223 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1224
1225 val = rd32(hw, I40E_PFLAN_QALLOC);
1226 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1227 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1228 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1229 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1230 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1231 num_queues = (j - base_queue) + 1;
1232 else
1233 num_queues = 0;
1234
1235 val = rd32(hw, I40E_PF_VT_PFALLOC);
1236 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1237 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1238 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1239 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1240 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1241 num_vfs = (j - i) + 1;
1242 else
1243 num_vfs = 0;
1244
1245 /* stop all the interrupts */
1246 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1247 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1248 for (i = 0; i < num_pf_int - 2; i++)
1249 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1250
1251 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1252 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1253 wr32(hw, I40E_PFINT_LNKLST0, val);
1254 for (i = 0; i < num_pf_int - 2; i++)
1255 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1256 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1257 for (i = 0; i < num_vfs; i++)
1258 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1259 for (i = 0; i < num_vf_int - 2; i++)
1260 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1261
1262 /* warn the HW of the coming Tx disables */
1263 for (i = 0; i < num_queues; i++) {
1264 u32 abs_queue_idx = base_queue + i;
1265 u32 reg_block = 0;
1266
1267 if (abs_queue_idx >= 128) {
1268 reg_block = abs_queue_idx / 128;
1269 abs_queue_idx %= 128;
1270 }
1271
1272 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1273 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1274 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1275 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1276
1277 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1278 }
1279 udelay(400);
1280
1281 /* stop all the queues */
1282 for (i = 0; i < num_queues; i++) {
1283 wr32(hw, I40E_QINT_TQCTL(i), 0);
1284 wr32(hw, I40E_QTX_ENA(i), 0);
1285 wr32(hw, I40E_QINT_RQCTL(i), 0);
1286 wr32(hw, I40E_QRX_ENA(i), 0);
1287 }
1288
1289 /* short wait for all queue disables to settle */
1290 udelay(50);
1291}
1292
1293/**
1294 * i40e_clear_pxe_mode - clear pxe operations mode
1295 * @hw: pointer to the hw struct
1296 *
1297 * Make sure all PXE mode settings are cleared, including things
1298 * like descriptor fetch/write-back mode.
1299 **/
1300void i40e_clear_pxe_mode(struct i40e_hw *hw)
1301{
1302 u32 reg;
1303
1304 if (i40e_check_asq_alive(hw))
1305 i40e_aq_clear_pxe_mode(hw, NULL);
1306
1307 /* Clear single descriptor fetch/write-back mode */
1308 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1309
1310 if (hw->revision_id == 0) {
1311 /* As a work around clear PXE_MODE instead of setting it */
1312 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1313 } else {
1314 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1315 }
1316}
1317
1318/**
1319 * i40e_led_is_mine - helper to find matching led
1320 * @hw: pointer to the hw struct
1321 * @idx: index into GPIO registers
1322 *
1323 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1324 */
1325static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1326{
1327 u32 gpio_val = 0;
1328 u32 port;
1329
1330 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1331 !hw->func_caps.led[idx])
1332 return 0;
1333 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1334 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1335 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1336
1337 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1338 * if it is not our port then ignore
1339 */
1340 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1341 (port != hw->port))
1342 return 0;
1343
1344 return gpio_val;
1345}
1346
1347#define I40E_FW_LED BIT(4)
1348#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1349 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1350
1351#define I40E_LED0 22
1352
1353#define I40E_PIN_FUNC_SDP 0x0
1354#define I40E_PIN_FUNC_LED 0x1
1355
1356/**
1357 * i40e_led_get - return current on/off mode
1358 * @hw: pointer to the hw struct
1359 *
1360 * The value returned is the 'mode' field as defined in the
1361 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1362 * values are variations of possible behaviors relating to
1363 * blink, link, and wire.
1364 **/
1365u32 i40e_led_get(struct i40e_hw *hw)
1366{
1367 u32 mode = 0;
1368 int i;
1369
1370 /* as per the documentation GPIO 22-29 are the LED
1371 * GPIO pins named LED0..LED7
1372 */
1373 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1374 u32 gpio_val = i40e_led_is_mine(hw, i);
1375
1376 if (!gpio_val)
1377 continue;
1378
1379 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1380 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1381 break;
1382 }
1383
1384 return mode;
1385}
1386
1387/**
1388 * i40e_led_set - set new on/off mode
1389 * @hw: pointer to the hw struct
1390 * @mode: 0=off, 0xf=on (else see manual for mode details)
1391 * @blink: true if the LED should blink when on, false if steady
1392 *
1393 * if this function is used to turn on the blink it should
1394 * be used to disable the blink when restoring the original state.
1395 **/
1396void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1397{
1398 int i;
1399
1400 if (mode & ~I40E_LED_MODE_VALID) {
1401 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1402 return;
1403 }
1404
1405 /* as per the documentation GPIO 22-29 are the LED
1406 * GPIO pins named LED0..LED7
1407 */
1408 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1409 u32 gpio_val = i40e_led_is_mine(hw, i);
1410
1411 if (!gpio_val)
1412 continue;
1413
1414 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1415 u32 pin_func = 0;
1416
1417 if (mode & I40E_FW_LED)
1418 pin_func = I40E_PIN_FUNC_SDP;
1419 else
1420 pin_func = I40E_PIN_FUNC_LED;
1421
1422 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1423 gpio_val |= ((pin_func <<
1424 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1425 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1426 }
1427 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1428 /* this & is a bit of paranoia, but serves as a range check */
1429 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1430 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1431
1432 if (blink)
1433 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1434 else
1435 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1436
1437 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1438 break;
1439 }
1440}
1441
1442/* Admin command wrappers */
1443
1444/**
1445 * i40e_aq_get_phy_capabilities
1446 * @hw: pointer to the hw struct
1447 * @abilities: structure for PHY capabilities to be filled
1448 * @qualified_modules: report Qualified Modules
1449 * @report_init: report init capabilities (active are default)
1450 * @cmd_details: pointer to command details structure or NULL
1451 *
1452 * Returns the various PHY abilities supported on the Port.
1453 **/
1454i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1455 bool qualified_modules, bool report_init,
1456 struct i40e_aq_get_phy_abilities_resp *abilities,
1457 struct i40e_asq_cmd_details *cmd_details)
1458{
1459 struct i40e_aq_desc desc;
1460 i40e_status status;
1461 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1462 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1463
1464 if (!abilities)
1465 return I40E_ERR_PARAM;
1466
1467 do {
1468 i40e_fill_default_direct_cmd_desc(&desc,
1469 i40e_aqc_opc_get_phy_abilities);
1470
1471 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1472 if (abilities_size > I40E_AQ_LARGE_BUF)
1473 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1474
1475 if (qualified_modules)
1476 desc.params.external.param0 |=
1477 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1478
1479 if (report_init)
1480 desc.params.external.param0 |=
1481 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1482
1483 status = i40e_asq_send_command(hw, &desc, abilities,
1484 abilities_size, cmd_details);
1485
1486 switch (hw->aq.asq_last_status) {
1487 case I40E_AQ_RC_EIO:
1488 status = I40E_ERR_UNKNOWN_PHY;
1489 break;
1490 case I40E_AQ_RC_EAGAIN:
1491 usleep_range(1000, 2000);
1492 total_delay++;
1493 status = I40E_ERR_TIMEOUT;
1494 break;
1495 /* also covers I40E_AQ_RC_OK */
1496 default:
1497 break;
1498 }
1499
1500 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1501 (total_delay < max_delay));
1502
1503 if (status)
1504 return status;
1505
1506 if (report_init) {
1507 if (hw->mac.type == I40E_MAC_XL710 &&
1508 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1509 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1510 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1511 } else {
1512 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1513 hw->phy.phy_types |=
1514 ((u64)abilities->phy_type_ext << 32);
1515 }
1516 }
1517
1518 return status;
1519}
1520
1521/**
1522 * i40e_aq_set_phy_config
1523 * @hw: pointer to the hw struct
1524 * @config: structure with PHY configuration to be set
1525 * @cmd_details: pointer to command details structure or NULL
1526 *
1527 * Set the various PHY configuration parameters
1528 * supported on the Port.One or more of the Set PHY config parameters may be
1529 * ignored in an MFP mode as the PF may not have the privilege to set some
1530 * of the PHY Config parameters. This status will be indicated by the
1531 * command response.
1532 **/
1533enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1534 struct i40e_aq_set_phy_config *config,
1535 struct i40e_asq_cmd_details *cmd_details)
1536{
1537 struct i40e_aq_desc desc;
1538 struct i40e_aq_set_phy_config *cmd =
1539 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1540 enum i40e_status_code status;
1541
1542 if (!config)
1543 return I40E_ERR_PARAM;
1544
1545 i40e_fill_default_direct_cmd_desc(&desc,
1546 i40e_aqc_opc_set_phy_config);
1547
1548 *cmd = *config;
1549
1550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1551
1552 return status;
1553}
1554
1555static noinline_for_stack enum i40e_status_code
1556i40e_set_fc_status(struct i40e_hw *hw,
1557 struct i40e_aq_get_phy_abilities_resp *abilities,
1558 bool atomic_restart)
1559{
1560 struct i40e_aq_set_phy_config config;
1561 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1562 u8 pause_mask = 0x0;
1563
1564 switch (fc_mode) {
1565 case I40E_FC_FULL:
1566 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1567 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1568 break;
1569 case I40E_FC_RX_PAUSE:
1570 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1571 break;
1572 case I40E_FC_TX_PAUSE:
1573 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1574 break;
1575 default:
1576 break;
1577 }
1578
1579 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1580 /* clear the old pause settings */
1581 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1582 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1583 /* set the new abilities */
1584 config.abilities |= pause_mask;
1585 /* If the abilities have changed, then set the new config */
1586 if (config.abilities == abilities->abilities)
1587 return 0;
1588
1589 /* Auto restart link so settings take effect */
1590 if (atomic_restart)
1591 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1592 /* Copy over all the old settings */
1593 config.phy_type = abilities->phy_type;
1594 config.phy_type_ext = abilities->phy_type_ext;
1595 config.link_speed = abilities->link_speed;
1596 config.eee_capability = abilities->eee_capability;
1597 config.eeer = abilities->eeer_val;
1598 config.low_power_ctrl = abilities->d3_lpan;
1599 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1600 I40E_AQ_PHY_FEC_CONFIG_MASK;
1601
1602 return i40e_aq_set_phy_config(hw, &config, NULL);
1603}
1604
1605/**
1606 * i40e_set_fc
1607 * @hw: pointer to the hw struct
1608 * @aq_failures: buffer to return AdminQ failure information
1609 * @atomic_restart: whether to enable atomic link restart
1610 *
1611 * Set the requested flow control mode using set_phy_config.
1612 **/
1613enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1614 bool atomic_restart)
1615{
1616 struct i40e_aq_get_phy_abilities_resp abilities;
1617 enum i40e_status_code status;
1618
1619 *aq_failures = 0x0;
1620
1621 /* Get the current phy config */
1622 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1623 NULL);
1624 if (status) {
1625 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1626 return status;
1627 }
1628
1629 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1630 if (status)
1631 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1632
1633 /* Update the link info */
1634 status = i40e_update_link_info(hw);
1635 if (status) {
1636 /* Wait a little bit (on 40G cards it sometimes takes a really
1637 * long time for link to come back from the atomic reset)
1638 * and try once more
1639 */
1640 msleep(1000);
1641 status = i40e_update_link_info(hw);
1642 }
1643 if (status)
1644 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1645
1646 return status;
1647}
1648
1649/**
1650 * i40e_aq_clear_pxe_mode
1651 * @hw: pointer to the hw struct
1652 * @cmd_details: pointer to command details structure or NULL
1653 *
1654 * Tell the firmware that the driver is taking over from PXE
1655 **/
1656i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1657 struct i40e_asq_cmd_details *cmd_details)
1658{
1659 i40e_status status;
1660 struct i40e_aq_desc desc;
1661 struct i40e_aqc_clear_pxe *cmd =
1662 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1663
1664 i40e_fill_default_direct_cmd_desc(&desc,
1665 i40e_aqc_opc_clear_pxe_mode);
1666
1667 cmd->rx_cnt = 0x2;
1668
1669 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1670
1671 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1672
1673 return status;
1674}
1675
1676/**
1677 * i40e_aq_set_link_restart_an
1678 * @hw: pointer to the hw struct
1679 * @enable_link: if true: enable link, if false: disable link
1680 * @cmd_details: pointer to command details structure or NULL
1681 *
1682 * Sets up the link and restarts the Auto-Negotiation over the link.
1683 **/
1684i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1685 bool enable_link,
1686 struct i40e_asq_cmd_details *cmd_details)
1687{
1688 struct i40e_aq_desc desc;
1689 struct i40e_aqc_set_link_restart_an *cmd =
1690 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1691 i40e_status status;
1692
1693 i40e_fill_default_direct_cmd_desc(&desc,
1694 i40e_aqc_opc_set_link_restart_an);
1695
1696 cmd->command = I40E_AQ_PHY_RESTART_AN;
1697 if (enable_link)
1698 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1699 else
1700 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1701
1702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1703
1704 return status;
1705}
1706
1707/**
1708 * i40e_aq_get_link_info
1709 * @hw: pointer to the hw struct
1710 * @enable_lse: enable/disable LinkStatusEvent reporting
1711 * @link: pointer to link status structure - optional
1712 * @cmd_details: pointer to command details structure or NULL
1713 *
1714 * Returns the link status of the adapter.
1715 **/
1716i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1717 bool enable_lse, struct i40e_link_status *link,
1718 struct i40e_asq_cmd_details *cmd_details)
1719{
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_get_link_status *resp =
1722 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1723 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1724 i40e_status status;
1725 bool tx_pause, rx_pause;
1726 u16 command_flags;
1727
1728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1729
1730 if (enable_lse)
1731 command_flags = I40E_AQ_LSE_ENABLE;
1732 else
1733 command_flags = I40E_AQ_LSE_DISABLE;
1734 resp->command_flags = cpu_to_le16(command_flags);
1735
1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1737
1738 if (status)
1739 goto aq_get_link_info_exit;
1740
1741 /* save off old link status information */
1742 hw->phy.link_info_old = *hw_link_info;
1743
1744 /* update link status */
1745 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1746 hw->phy.media_type = i40e_get_media_type(hw);
1747 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1748 hw_link_info->link_info = resp->link_info;
1749 hw_link_info->an_info = resp->an_info;
1750 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1751 I40E_AQ_CONFIG_FEC_RS_ENA);
1752 hw_link_info->ext_info = resp->ext_info;
1753 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1754 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1755 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1756
1757 /* update fc info */
1758 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1759 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1760 if (tx_pause & rx_pause)
1761 hw->fc.current_mode = I40E_FC_FULL;
1762 else if (tx_pause)
1763 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1764 else if (rx_pause)
1765 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1766 else
1767 hw->fc.current_mode = I40E_FC_NONE;
1768
1769 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1770 hw_link_info->crc_enable = true;
1771 else
1772 hw_link_info->crc_enable = false;
1773
1774 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1775 hw_link_info->lse_enable = true;
1776 else
1777 hw_link_info->lse_enable = false;
1778
1779 if ((hw->mac.type == I40E_MAC_XL710) &&
1780 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1781 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1782 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1783
1784 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1785 hw->mac.type != I40E_MAC_X722) {
1786 __le32 tmp;
1787
1788 memcpy(&tmp, resp->link_type, sizeof(tmp));
1789 hw->phy.phy_types = le32_to_cpu(tmp);
1790 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1791 }
1792
1793 /* save link status information */
1794 if (link)
1795 *link = *hw_link_info;
1796
1797 /* flag cleared so helper functions don't call AQ again */
1798 hw->phy.get_link_info = false;
1799
1800aq_get_link_info_exit:
1801 return status;
1802}
1803
1804/**
1805 * i40e_aq_set_phy_int_mask
1806 * @hw: pointer to the hw struct
1807 * @mask: interrupt mask to be set
1808 * @cmd_details: pointer to command details structure or NULL
1809 *
1810 * Set link interrupt mask.
1811 **/
1812i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1813 u16 mask,
1814 struct i40e_asq_cmd_details *cmd_details)
1815{
1816 struct i40e_aq_desc desc;
1817 struct i40e_aqc_set_phy_int_mask *cmd =
1818 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1819 i40e_status status;
1820
1821 i40e_fill_default_direct_cmd_desc(&desc,
1822 i40e_aqc_opc_set_phy_int_mask);
1823
1824 cmd->event_mask = cpu_to_le16(mask);
1825
1826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1827
1828 return status;
1829}
1830
1831/**
1832 * i40e_aq_set_phy_debug
1833 * @hw: pointer to the hw struct
1834 * @cmd_flags: debug command flags
1835 * @cmd_details: pointer to command details structure or NULL
1836 *
1837 * Reset the external PHY.
1838 **/
1839i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1840 struct i40e_asq_cmd_details *cmd_details)
1841{
1842 struct i40e_aq_desc desc;
1843 struct i40e_aqc_set_phy_debug *cmd =
1844 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1845 i40e_status status;
1846
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_set_phy_debug);
1849
1850 cmd->command_flags = cmd_flags;
1851
1852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1853
1854 return status;
1855}
1856
1857/**
1858 * i40e_is_aq_api_ver_ge
1859 * @aq: pointer to AdminQ info containing HW API version to compare
1860 * @maj: API major value
1861 * @min: API minor value
1862 *
1863 * Assert whether current HW API version is greater/equal than provided.
1864 **/
1865static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1866 u16 min)
1867{
1868 return (aq->api_maj_ver > maj ||
1869 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1870}
1871
1872/**
1873 * i40e_aq_add_vsi
1874 * @hw: pointer to the hw struct
1875 * @vsi_ctx: pointer to a vsi context struct
1876 * @cmd_details: pointer to command details structure or NULL
1877 *
1878 * Add a VSI context to the hardware.
1879**/
1880i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1881 struct i40e_vsi_context *vsi_ctx,
1882 struct i40e_asq_cmd_details *cmd_details)
1883{
1884 struct i40e_aq_desc desc;
1885 struct i40e_aqc_add_get_update_vsi *cmd =
1886 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1887 struct i40e_aqc_add_get_update_vsi_completion *resp =
1888 (struct i40e_aqc_add_get_update_vsi_completion *)
1889 &desc.params.raw;
1890 i40e_status status;
1891
1892 i40e_fill_default_direct_cmd_desc(&desc,
1893 i40e_aqc_opc_add_vsi);
1894
1895 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1896 cmd->connection_type = vsi_ctx->connection_type;
1897 cmd->vf_id = vsi_ctx->vf_num;
1898 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1899
1900 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1901
1902 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1903 sizeof(vsi_ctx->info), cmd_details);
1904
1905 if (status)
1906 goto aq_add_vsi_exit;
1907
1908 vsi_ctx->seid = le16_to_cpu(resp->seid);
1909 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1910 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1911 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1912
1913aq_add_vsi_exit:
1914 return status;
1915}
1916
1917/**
1918 * i40e_aq_set_default_vsi
1919 * @hw: pointer to the hw struct
1920 * @seid: vsi number
1921 * @cmd_details: pointer to command details structure or NULL
1922 **/
1923i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1924 u16 seid,
1925 struct i40e_asq_cmd_details *cmd_details)
1926{
1927 struct i40e_aq_desc desc;
1928 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1929 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1930 &desc.params.raw;
1931 i40e_status status;
1932
1933 i40e_fill_default_direct_cmd_desc(&desc,
1934 i40e_aqc_opc_set_vsi_promiscuous_modes);
1935
1936 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1937 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1938 cmd->seid = cpu_to_le16(seid);
1939
1940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942 return status;
1943}
1944
1945/**
1946 * i40e_aq_clear_default_vsi
1947 * @hw: pointer to the hw struct
1948 * @seid: vsi number
1949 * @cmd_details: pointer to command details structure or NULL
1950 **/
1951i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1952 u16 seid,
1953 struct i40e_asq_cmd_details *cmd_details)
1954{
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1957 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1958 &desc.params.raw;
1959 i40e_status status;
1960
1961 i40e_fill_default_direct_cmd_desc(&desc,
1962 i40e_aqc_opc_set_vsi_promiscuous_modes);
1963
1964 cmd->promiscuous_flags = cpu_to_le16(0);
1965 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1966 cmd->seid = cpu_to_le16(seid);
1967
1968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1969
1970 return status;
1971}
1972
1973/**
1974 * i40e_aq_set_vsi_unicast_promiscuous
1975 * @hw: pointer to the hw struct
1976 * @seid: vsi number
1977 * @set: set unicast promiscuous enable/disable
1978 * @cmd_details: pointer to command details structure or NULL
1979 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
1980 **/
1981i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1982 u16 seid, bool set,
1983 struct i40e_asq_cmd_details *cmd_details,
1984 bool rx_only_promisc)
1985{
1986 struct i40e_aq_desc desc;
1987 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1988 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1989 i40e_status status;
1990 u16 flags = 0;
1991
1992 i40e_fill_default_direct_cmd_desc(&desc,
1993 i40e_aqc_opc_set_vsi_promiscuous_modes);
1994
1995 if (set) {
1996 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1997 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
1998 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1999 }
2000
2001 cmd->promiscuous_flags = cpu_to_le16(flags);
2002
2003 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2004 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2005 cmd->valid_flags |=
2006 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2007
2008 cmd->seid = cpu_to_le16(seid);
2009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010
2011 return status;
2012}
2013
2014/**
2015 * i40e_aq_set_vsi_multicast_promiscuous
2016 * @hw: pointer to the hw struct
2017 * @seid: vsi number
2018 * @set: set multicast promiscuous enable/disable
2019 * @cmd_details: pointer to command details structure or NULL
2020 **/
2021i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2022 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2023{
2024 struct i40e_aq_desc desc;
2025 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2026 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2027 i40e_status status;
2028 u16 flags = 0;
2029
2030 i40e_fill_default_direct_cmd_desc(&desc,
2031 i40e_aqc_opc_set_vsi_promiscuous_modes);
2032
2033 if (set)
2034 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2035
2036 cmd->promiscuous_flags = cpu_to_le16(flags);
2037
2038 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2039
2040 cmd->seid = cpu_to_le16(seid);
2041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2042
2043 return status;
2044}
2045
2046/**
2047 * i40e_aq_set_vsi_mc_promisc_on_vlan
2048 * @hw: pointer to the hw struct
2049 * @seid: vsi number
2050 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2051 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2052 * @cmd_details: pointer to command details structure or NULL
2053 **/
2054enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2055 u16 seid, bool enable,
2056 u16 vid,
2057 struct i40e_asq_cmd_details *cmd_details)
2058{
2059 struct i40e_aq_desc desc;
2060 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2061 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2062 enum i40e_status_code status;
2063 u16 flags = 0;
2064
2065 i40e_fill_default_direct_cmd_desc(&desc,
2066 i40e_aqc_opc_set_vsi_promiscuous_modes);
2067
2068 if (enable)
2069 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2070
2071 cmd->promiscuous_flags = cpu_to_le16(flags);
2072 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2073 cmd->seid = cpu_to_le16(seid);
2074 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2075
2076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2077
2078 return status;
2079}
2080
2081/**
2082 * i40e_aq_set_vsi_uc_promisc_on_vlan
2083 * @hw: pointer to the hw struct
2084 * @seid: vsi number
2085 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2086 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2087 * @cmd_details: pointer to command details structure or NULL
2088 **/
2089enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2090 u16 seid, bool enable,
2091 u16 vid,
2092 struct i40e_asq_cmd_details *cmd_details)
2093{
2094 struct i40e_aq_desc desc;
2095 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2096 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2097 enum i40e_status_code status;
2098 u16 flags = 0;
2099
2100 i40e_fill_default_direct_cmd_desc(&desc,
2101 i40e_aqc_opc_set_vsi_promiscuous_modes);
2102
2103 if (enable) {
2104 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2105 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2106 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2107 }
2108
2109 cmd->promiscuous_flags = cpu_to_le16(flags);
2110 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2111 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2112 cmd->valid_flags |=
2113 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2114 cmd->seid = cpu_to_le16(seid);
2115 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2116
2117 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2118
2119 return status;
2120}
2121
2122/**
2123 * i40e_aq_set_vsi_bc_promisc_on_vlan
2124 * @hw: pointer to the hw struct
2125 * @seid: vsi number
2126 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2127 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2128 * @cmd_details: pointer to command details structure or NULL
2129 **/
2130i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2131 u16 seid, bool enable, u16 vid,
2132 struct i40e_asq_cmd_details *cmd_details)
2133{
2134 struct i40e_aq_desc desc;
2135 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2136 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2137 i40e_status status;
2138 u16 flags = 0;
2139
2140 i40e_fill_default_direct_cmd_desc(&desc,
2141 i40e_aqc_opc_set_vsi_promiscuous_modes);
2142
2143 if (enable)
2144 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2145
2146 cmd->promiscuous_flags = cpu_to_le16(flags);
2147 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2148 cmd->seid = cpu_to_le16(seid);
2149 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2150
2151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152
2153 return status;
2154}
2155
2156/**
2157 * i40e_aq_set_vsi_broadcast
2158 * @hw: pointer to the hw struct
2159 * @seid: vsi number
2160 * @set_filter: true to set filter, false to clear filter
2161 * @cmd_details: pointer to command details structure or NULL
2162 *
2163 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2164 **/
2165i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2166 u16 seid, bool set_filter,
2167 struct i40e_asq_cmd_details *cmd_details)
2168{
2169 struct i40e_aq_desc desc;
2170 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2171 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2172 i40e_status status;
2173
2174 i40e_fill_default_direct_cmd_desc(&desc,
2175 i40e_aqc_opc_set_vsi_promiscuous_modes);
2176
2177 if (set_filter)
2178 cmd->promiscuous_flags
2179 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2180 else
2181 cmd->promiscuous_flags
2182 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2183
2184 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2185 cmd->seid = cpu_to_le16(seid);
2186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187
2188 return status;
2189}
2190
2191/**
2192 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2193 * @hw: pointer to the hw struct
2194 * @seid: vsi number
2195 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2196 * @cmd_details: pointer to command details structure or NULL
2197 **/
2198i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2199 u16 seid, bool enable,
2200 struct i40e_asq_cmd_details *cmd_details)
2201{
2202 struct i40e_aq_desc desc;
2203 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2204 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2205 i40e_status status;
2206 u16 flags = 0;
2207
2208 i40e_fill_default_direct_cmd_desc(&desc,
2209 i40e_aqc_opc_set_vsi_promiscuous_modes);
2210 if (enable)
2211 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2212
2213 cmd->promiscuous_flags = cpu_to_le16(flags);
2214 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2215 cmd->seid = cpu_to_le16(seid);
2216
2217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2218
2219 return status;
2220}
2221
2222/**
2223 * i40e_aq_get_vsi_params - get VSI configuration info
2224 * @hw: pointer to the hw struct
2225 * @vsi_ctx: pointer to a vsi context struct
2226 * @cmd_details: pointer to command details structure or NULL
2227 **/
2228i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2229 struct i40e_vsi_context *vsi_ctx,
2230 struct i40e_asq_cmd_details *cmd_details)
2231{
2232 struct i40e_aq_desc desc;
2233 struct i40e_aqc_add_get_update_vsi *cmd =
2234 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2235 struct i40e_aqc_add_get_update_vsi_completion *resp =
2236 (struct i40e_aqc_add_get_update_vsi_completion *)
2237 &desc.params.raw;
2238 i40e_status status;
2239
2240 i40e_fill_default_direct_cmd_desc(&desc,
2241 i40e_aqc_opc_get_vsi_parameters);
2242
2243 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2244
2245 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2246
2247 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2248 sizeof(vsi_ctx->info), NULL);
2249
2250 if (status)
2251 goto aq_get_vsi_params_exit;
2252
2253 vsi_ctx->seid = le16_to_cpu(resp->seid);
2254 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2255 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2256 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2257
2258aq_get_vsi_params_exit:
2259 return status;
2260}
2261
2262/**
2263 * i40e_aq_update_vsi_params
2264 * @hw: pointer to the hw struct
2265 * @vsi_ctx: pointer to a vsi context struct
2266 * @cmd_details: pointer to command details structure or NULL
2267 *
2268 * Update a VSI context.
2269 **/
2270i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2271 struct i40e_vsi_context *vsi_ctx,
2272 struct i40e_asq_cmd_details *cmd_details)
2273{
2274 struct i40e_aq_desc desc;
2275 struct i40e_aqc_add_get_update_vsi *cmd =
2276 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2277 struct i40e_aqc_add_get_update_vsi_completion *resp =
2278 (struct i40e_aqc_add_get_update_vsi_completion *)
2279 &desc.params.raw;
2280 i40e_status status;
2281
2282 i40e_fill_default_direct_cmd_desc(&desc,
2283 i40e_aqc_opc_update_vsi_parameters);
2284 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2285
2286 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2287
2288 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2289 sizeof(vsi_ctx->info), cmd_details);
2290
2291 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2292 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2293
2294 return status;
2295}
2296
2297/**
2298 * i40e_aq_get_switch_config
2299 * @hw: pointer to the hardware structure
2300 * @buf: pointer to the result buffer
2301 * @buf_size: length of input buffer
2302 * @start_seid: seid to start for the report, 0 == beginning
2303 * @cmd_details: pointer to command details structure or NULL
2304 *
2305 * Fill the buf with switch configuration returned from AdminQ command
2306 **/
2307i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2308 struct i40e_aqc_get_switch_config_resp *buf,
2309 u16 buf_size, u16 *start_seid,
2310 struct i40e_asq_cmd_details *cmd_details)
2311{
2312 struct i40e_aq_desc desc;
2313 struct i40e_aqc_switch_seid *scfg =
2314 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2315 i40e_status status;
2316
2317 i40e_fill_default_direct_cmd_desc(&desc,
2318 i40e_aqc_opc_get_switch_config);
2319 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2320 if (buf_size > I40E_AQ_LARGE_BUF)
2321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2322 scfg->seid = cpu_to_le16(*start_seid);
2323
2324 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2325 *start_seid = le16_to_cpu(scfg->seid);
2326
2327 return status;
2328}
2329
2330/**
2331 * i40e_aq_set_switch_config
2332 * @hw: pointer to the hardware structure
2333 * @flags: bit flag values to set
2334 * @mode: cloud filter mode
2335 * @valid_flags: which bit flags to set
2336 * @mode: cloud filter mode
2337 * @cmd_details: pointer to command details structure or NULL
2338 *
2339 * Set switch configuration bits
2340 **/
2341enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2342 u16 flags,
2343 u16 valid_flags, u8 mode,
2344 struct i40e_asq_cmd_details *cmd_details)
2345{
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_set_switch_config *scfg =
2348 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2349 enum i40e_status_code status;
2350
2351 i40e_fill_default_direct_cmd_desc(&desc,
2352 i40e_aqc_opc_set_switch_config);
2353 scfg->flags = cpu_to_le16(flags);
2354 scfg->valid_flags = cpu_to_le16(valid_flags);
2355 scfg->mode = mode;
2356 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2357 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2358 scfg->first_tag = cpu_to_le16(hw->first_tag);
2359 scfg->second_tag = cpu_to_le16(hw->second_tag);
2360 }
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2362
2363 return status;
2364}
2365
2366/**
2367 * i40e_aq_get_firmware_version
2368 * @hw: pointer to the hw struct
2369 * @fw_major_version: firmware major version
2370 * @fw_minor_version: firmware minor version
2371 * @fw_build: firmware build number
2372 * @api_major_version: major queue version
2373 * @api_minor_version: minor queue version
2374 * @cmd_details: pointer to command details structure or NULL
2375 *
2376 * Get the firmware version from the admin queue commands
2377 **/
2378i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2379 u16 *fw_major_version, u16 *fw_minor_version,
2380 u32 *fw_build,
2381 u16 *api_major_version, u16 *api_minor_version,
2382 struct i40e_asq_cmd_details *cmd_details)
2383{
2384 struct i40e_aq_desc desc;
2385 struct i40e_aqc_get_version *resp =
2386 (struct i40e_aqc_get_version *)&desc.params.raw;
2387 i40e_status status;
2388
2389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2390
2391 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2392
2393 if (!status) {
2394 if (fw_major_version)
2395 *fw_major_version = le16_to_cpu(resp->fw_major);
2396 if (fw_minor_version)
2397 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2398 if (fw_build)
2399 *fw_build = le32_to_cpu(resp->fw_build);
2400 if (api_major_version)
2401 *api_major_version = le16_to_cpu(resp->api_major);
2402 if (api_minor_version)
2403 *api_minor_version = le16_to_cpu(resp->api_minor);
2404 }
2405
2406 return status;
2407}
2408
2409/**
2410 * i40e_aq_send_driver_version
2411 * @hw: pointer to the hw struct
2412 * @dv: driver's major, minor version
2413 * @cmd_details: pointer to command details structure or NULL
2414 *
2415 * Send the driver version to the firmware
2416 **/
2417i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2418 struct i40e_driver_version *dv,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_driver_version *cmd =
2423 (struct i40e_aqc_driver_version *)&desc.params.raw;
2424 i40e_status status;
2425 u16 len;
2426
2427 if (dv == NULL)
2428 return I40E_ERR_PARAM;
2429
2430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2431
2432 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2433 cmd->driver_major_ver = dv->major_version;
2434 cmd->driver_minor_ver = dv->minor_version;
2435 cmd->driver_build_ver = dv->build_version;
2436 cmd->driver_subbuild_ver = dv->subbuild_version;
2437
2438 len = 0;
2439 while (len < sizeof(dv->driver_string) &&
2440 (dv->driver_string[len] < 0x80) &&
2441 dv->driver_string[len])
2442 len++;
2443 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2444 len, cmd_details);
2445
2446 return status;
2447}
2448
2449/**
2450 * i40e_get_link_status - get status of the HW network link
2451 * @hw: pointer to the hw struct
2452 * @link_up: pointer to bool (true/false = linkup/linkdown)
2453 *
2454 * Variable link_up true if link is up, false if link is down.
2455 * The variable link_up is invalid if returned value of status != 0
2456 *
2457 * Side effect: LinkStatusEvent reporting becomes enabled
2458 **/
2459i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2460{
2461 i40e_status status = 0;
2462
2463 if (hw->phy.get_link_info) {
2464 status = i40e_update_link_info(hw);
2465
2466 if (status)
2467 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2468 status);
2469 }
2470
2471 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2472
2473 return status;
2474}
2475
2476/**
2477 * i40e_update_link_info - update status of the HW network link
2478 * @hw: pointer to the hw struct
2479 **/
2480noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2481{
2482 struct i40e_aq_get_phy_abilities_resp abilities;
2483 i40e_status status = 0;
2484
2485 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2486 if (status)
2487 return status;
2488
2489 /* extra checking needed to ensure link info to user is timely */
2490 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2491 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2492 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2493 status = i40e_aq_get_phy_capabilities(hw, false, false,
2494 &abilities, NULL);
2495 if (status)
2496 return status;
2497
2498 if (abilities.fec_cfg_curr_mod_ext_info &
2499 I40E_AQ_ENABLE_FEC_AUTO)
2500 hw->phy.link_info.req_fec_info =
2501 (I40E_AQ_REQUEST_FEC_KR |
2502 I40E_AQ_REQUEST_FEC_RS);
2503 else
2504 hw->phy.link_info.req_fec_info =
2505 abilities.fec_cfg_curr_mod_ext_info &
2506 (I40E_AQ_REQUEST_FEC_KR |
2507 I40E_AQ_REQUEST_FEC_RS);
2508
2509 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2510 sizeof(hw->phy.link_info.module_type));
2511 }
2512
2513 return status;
2514}
2515
2516/**
2517 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2518 * @hw: pointer to the hw struct
2519 * @uplink_seid: the MAC or other gizmo SEID
2520 * @downlink_seid: the VSI SEID
2521 * @enabled_tc: bitmap of TCs to be enabled
2522 * @default_port: true for default port VSI, false for control port
2523 * @veb_seid: pointer to where to put the resulting VEB SEID
2524 * @enable_stats: true to turn on VEB stats
2525 * @cmd_details: pointer to command details structure or NULL
2526 *
2527 * This asks the FW to add a VEB between the uplink and downlink
2528 * elements. If the uplink SEID is 0, this will be a floating VEB.
2529 **/
2530i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2531 u16 downlink_seid, u8 enabled_tc,
2532 bool default_port, u16 *veb_seid,
2533 bool enable_stats,
2534 struct i40e_asq_cmd_details *cmd_details)
2535{
2536 struct i40e_aq_desc desc;
2537 struct i40e_aqc_add_veb *cmd =
2538 (struct i40e_aqc_add_veb *)&desc.params.raw;
2539 struct i40e_aqc_add_veb_completion *resp =
2540 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2541 i40e_status status;
2542 u16 veb_flags = 0;
2543
2544 /* SEIDs need to either both be set or both be 0 for floating VEB */
2545 if (!!uplink_seid != !!downlink_seid)
2546 return I40E_ERR_PARAM;
2547
2548 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2549
2550 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2551 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2552 cmd->enable_tcs = enabled_tc;
2553 if (!uplink_seid)
2554 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2555 if (default_port)
2556 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2557 else
2558 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2559
2560 /* reverse logic here: set the bitflag to disable the stats */
2561 if (!enable_stats)
2562 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2563
2564 cmd->veb_flags = cpu_to_le16(veb_flags);
2565
2566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2567
2568 if (!status && veb_seid)
2569 *veb_seid = le16_to_cpu(resp->veb_seid);
2570
2571 return status;
2572}
2573
2574/**
2575 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2576 * @hw: pointer to the hw struct
2577 * @veb_seid: the SEID of the VEB to query
2578 * @switch_id: the uplink switch id
2579 * @floating: set to true if the VEB is floating
2580 * @statistic_index: index of the stats counter block for this VEB
2581 * @vebs_used: number of VEB's used by function
2582 * @vebs_free: total VEB's not reserved by any function
2583 * @cmd_details: pointer to command details structure or NULL
2584 *
2585 * This retrieves the parameters for a particular VEB, specified by
2586 * uplink_seid, and returns them to the caller.
2587 **/
2588i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2589 u16 veb_seid, u16 *switch_id,
2590 bool *floating, u16 *statistic_index,
2591 u16 *vebs_used, u16 *vebs_free,
2592 struct i40e_asq_cmd_details *cmd_details)
2593{
2594 struct i40e_aq_desc desc;
2595 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2596 (struct i40e_aqc_get_veb_parameters_completion *)
2597 &desc.params.raw;
2598 i40e_status status;
2599
2600 if (veb_seid == 0)
2601 return I40E_ERR_PARAM;
2602
2603 i40e_fill_default_direct_cmd_desc(&desc,
2604 i40e_aqc_opc_get_veb_parameters);
2605 cmd_resp->seid = cpu_to_le16(veb_seid);
2606
2607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2608 if (status)
2609 goto get_veb_exit;
2610
2611 if (switch_id)
2612 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2613 if (statistic_index)
2614 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2615 if (vebs_used)
2616 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2617 if (vebs_free)
2618 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2619 if (floating) {
2620 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2621
2622 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2623 *floating = true;
2624 else
2625 *floating = false;
2626 }
2627
2628get_veb_exit:
2629 return status;
2630}
2631
2632/**
2633 * i40e_aq_add_macvlan
2634 * @hw: pointer to the hw struct
2635 * @seid: VSI for the mac address
2636 * @mv_list: list of macvlans to be added
2637 * @count: length of the list
2638 * @cmd_details: pointer to command details structure or NULL
2639 *
2640 * Add MAC/VLAN addresses to the HW filtering
2641 **/
2642i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2643 struct i40e_aqc_add_macvlan_element_data *mv_list,
2644 u16 count, struct i40e_asq_cmd_details *cmd_details)
2645{
2646 struct i40e_aq_desc desc;
2647 struct i40e_aqc_macvlan *cmd =
2648 (struct i40e_aqc_macvlan *)&desc.params.raw;
2649 i40e_status status;
2650 u16 buf_size;
2651 int i;
2652
2653 if (count == 0 || !mv_list || !hw)
2654 return I40E_ERR_PARAM;
2655
2656 buf_size = count * sizeof(*mv_list);
2657
2658 /* prep the rest of the request */
2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2660 cmd->num_addresses = cpu_to_le16(count);
2661 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2662 cmd->seid[1] = 0;
2663 cmd->seid[2] = 0;
2664
2665 for (i = 0; i < count; i++)
2666 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2667 mv_list[i].flags |=
2668 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2669
2670 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2671 if (buf_size > I40E_AQ_LARGE_BUF)
2672 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2673
2674 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2675 cmd_details);
2676
2677 return status;
2678}
2679
2680/**
2681 * i40e_aq_remove_macvlan
2682 * @hw: pointer to the hw struct
2683 * @seid: VSI for the mac address
2684 * @mv_list: list of macvlans to be removed
2685 * @count: length of the list
2686 * @cmd_details: pointer to command details structure or NULL
2687 *
2688 * Remove MAC/VLAN addresses from the HW filtering
2689 **/
2690i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2691 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2692 u16 count, struct i40e_asq_cmd_details *cmd_details)
2693{
2694 struct i40e_aq_desc desc;
2695 struct i40e_aqc_macvlan *cmd =
2696 (struct i40e_aqc_macvlan *)&desc.params.raw;
2697 i40e_status status;
2698 u16 buf_size;
2699
2700 if (count == 0 || !mv_list || !hw)
2701 return I40E_ERR_PARAM;
2702
2703 buf_size = count * sizeof(*mv_list);
2704
2705 /* prep the rest of the request */
2706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2707 cmd->num_addresses = cpu_to_le16(count);
2708 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2709 cmd->seid[1] = 0;
2710 cmd->seid[2] = 0;
2711
2712 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2713 if (buf_size > I40E_AQ_LARGE_BUF)
2714 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2715
2716 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2717 cmd_details);
2718
2719 return status;
2720}
2721
2722/**
2723 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2724 * @hw: pointer to the hw struct
2725 * @opcode: AQ opcode for add or delete mirror rule
2726 * @sw_seid: Switch SEID (to which rule refers)
2727 * @rule_type: Rule Type (ingress/egress/VLAN)
2728 * @id: Destination VSI SEID or Rule ID
2729 * @count: length of the list
2730 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2731 * @cmd_details: pointer to command details structure or NULL
2732 * @rule_id: Rule ID returned from FW
2733 * @rules_used: Number of rules used in internal switch
2734 * @rules_free: Number of rules free in internal switch
2735 *
2736 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2737 * VEBs/VEPA elements only
2738 **/
2739static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2740 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2741 u16 count, __le16 *mr_list,
2742 struct i40e_asq_cmd_details *cmd_details,
2743 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2744{
2745 struct i40e_aq_desc desc;
2746 struct i40e_aqc_add_delete_mirror_rule *cmd =
2747 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2748 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2749 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2750 i40e_status status;
2751 u16 buf_size;
2752
2753 buf_size = count * sizeof(*mr_list);
2754
2755 /* prep the rest of the request */
2756 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2757 cmd->seid = cpu_to_le16(sw_seid);
2758 cmd->rule_type = cpu_to_le16(rule_type &
2759 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2760 cmd->num_entries = cpu_to_le16(count);
2761 /* Dest VSI for add, rule_id for delete */
2762 cmd->destination = cpu_to_le16(id);
2763 if (mr_list) {
2764 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2765 I40E_AQ_FLAG_RD));
2766 if (buf_size > I40E_AQ_LARGE_BUF)
2767 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2768 }
2769
2770 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2771 cmd_details);
2772 if (!status ||
2773 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2774 if (rule_id)
2775 *rule_id = le16_to_cpu(resp->rule_id);
2776 if (rules_used)
2777 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2778 if (rules_free)
2779 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2780 }
2781 return status;
2782}
2783
2784/**
2785 * i40e_aq_add_mirrorrule - add a mirror rule
2786 * @hw: pointer to the hw struct
2787 * @sw_seid: Switch SEID (to which rule refers)
2788 * @rule_type: Rule Type (ingress/egress/VLAN)
2789 * @dest_vsi: SEID of VSI to which packets will be mirrored
2790 * @count: length of the list
2791 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2792 * @cmd_details: pointer to command details structure or NULL
2793 * @rule_id: Rule ID returned from FW
2794 * @rules_used: Number of rules used in internal switch
2795 * @rules_free: Number of rules free in internal switch
2796 *
2797 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2798 **/
2799i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2800 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2801 struct i40e_asq_cmd_details *cmd_details,
2802 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2803{
2804 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2805 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2806 if (count == 0 || !mr_list)
2807 return I40E_ERR_PARAM;
2808 }
2809
2810 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2811 rule_type, dest_vsi, count, mr_list,
2812 cmd_details, rule_id, rules_used, rules_free);
2813}
2814
2815/**
2816 * i40e_aq_delete_mirrorrule - delete a mirror rule
2817 * @hw: pointer to the hw struct
2818 * @sw_seid: Switch SEID (to which rule refers)
2819 * @rule_type: Rule Type (ingress/egress/VLAN)
2820 * @count: length of the list
2821 * @rule_id: Rule ID that is returned in the receive desc as part of
2822 * add_mirrorrule.
2823 * @mr_list: list of mirrored VLAN IDs to be removed
2824 * @cmd_details: pointer to command details structure or NULL
2825 * @rules_used: Number of rules used in internal switch
2826 * @rules_free: Number of rules free in internal switch
2827 *
2828 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2829 **/
2830i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2831 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2832 struct i40e_asq_cmd_details *cmd_details,
2833 u16 *rules_used, u16 *rules_free)
2834{
2835 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2836 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2837 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2838 * mirroring. For other rule_type, count and rule_type should
2839 * not matter.
2840 */
2841 if (count == 0 || !mr_list)
2842 return I40E_ERR_PARAM;
2843 }
2844
2845 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2846 rule_type, rule_id, count, mr_list,
2847 cmd_details, NULL, rules_used, rules_free);
2848}
2849
2850/**
2851 * i40e_aq_send_msg_to_vf
2852 * @hw: pointer to the hardware structure
2853 * @vfid: VF id to send msg
2854 * @v_opcode: opcodes for VF-PF communication
2855 * @v_retval: return error code
2856 * @msg: pointer to the msg buffer
2857 * @msglen: msg length
2858 * @cmd_details: pointer to command details
2859 *
2860 * send msg to vf
2861 **/
2862i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2863 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2864 struct i40e_asq_cmd_details *cmd_details)
2865{
2866 struct i40e_aq_desc desc;
2867 struct i40e_aqc_pf_vf_message *cmd =
2868 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2869 i40e_status status;
2870
2871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2872 cmd->id = cpu_to_le32(vfid);
2873 desc.cookie_high = cpu_to_le32(v_opcode);
2874 desc.cookie_low = cpu_to_le32(v_retval);
2875 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2876 if (msglen) {
2877 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2878 I40E_AQ_FLAG_RD));
2879 if (msglen > I40E_AQ_LARGE_BUF)
2880 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2881 desc.datalen = cpu_to_le16(msglen);
2882 }
2883 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2884
2885 return status;
2886}
2887
2888/**
2889 * i40e_aq_debug_read_register
2890 * @hw: pointer to the hw struct
2891 * @reg_addr: register address
2892 * @reg_val: register value
2893 * @cmd_details: pointer to command details structure or NULL
2894 *
2895 * Read the register using the admin queue commands
2896 **/
2897i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2898 u32 reg_addr, u64 *reg_val,
2899 struct i40e_asq_cmd_details *cmd_details)
2900{
2901 struct i40e_aq_desc desc;
2902 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2903 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2904 i40e_status status;
2905
2906 if (reg_val == NULL)
2907 return I40E_ERR_PARAM;
2908
2909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2910
2911 cmd_resp->address = cpu_to_le32(reg_addr);
2912
2913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2914
2915 if (!status) {
2916 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2917 (u64)le32_to_cpu(cmd_resp->value_low);
2918 }
2919
2920 return status;
2921}
2922
2923/**
2924 * i40e_aq_debug_write_register
2925 * @hw: pointer to the hw struct
2926 * @reg_addr: register address
2927 * @reg_val: register value
2928 * @cmd_details: pointer to command details structure or NULL
2929 *
2930 * Write to a register using the admin queue commands
2931 **/
2932i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2933 u32 reg_addr, u64 reg_val,
2934 struct i40e_asq_cmd_details *cmd_details)
2935{
2936 struct i40e_aq_desc desc;
2937 struct i40e_aqc_debug_reg_read_write *cmd =
2938 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2939 i40e_status status;
2940
2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2942
2943 cmd->address = cpu_to_le32(reg_addr);
2944 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2945 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2946
2947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2948
2949 return status;
2950}
2951
2952/**
2953 * i40e_aq_request_resource
2954 * @hw: pointer to the hw struct
2955 * @resource: resource id
2956 * @access: access type
2957 * @sdp_number: resource number
2958 * @timeout: the maximum time in ms that the driver may hold the resource
2959 * @cmd_details: pointer to command details structure or NULL
2960 *
2961 * requests common resource using the admin queue commands
2962 **/
2963i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2964 enum i40e_aq_resources_ids resource,
2965 enum i40e_aq_resource_access_type access,
2966 u8 sdp_number, u64 *timeout,
2967 struct i40e_asq_cmd_details *cmd_details)
2968{
2969 struct i40e_aq_desc desc;
2970 struct i40e_aqc_request_resource *cmd_resp =
2971 (struct i40e_aqc_request_resource *)&desc.params.raw;
2972 i40e_status status;
2973
2974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2975
2976 cmd_resp->resource_id = cpu_to_le16(resource);
2977 cmd_resp->access_type = cpu_to_le16(access);
2978 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2979
2980 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2981 /* The completion specifies the maximum time in ms that the driver
2982 * may hold the resource in the Timeout field.
2983 * If the resource is held by someone else, the command completes with
2984 * busy return value and the timeout field indicates the maximum time
2985 * the current owner of the resource has to free it.
2986 */
2987 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2988 *timeout = le32_to_cpu(cmd_resp->timeout);
2989
2990 return status;
2991}
2992
2993/**
2994 * i40e_aq_release_resource
2995 * @hw: pointer to the hw struct
2996 * @resource: resource id
2997 * @sdp_number: resource number
2998 * @cmd_details: pointer to command details structure or NULL
2999 *
3000 * release common resource using the admin queue commands
3001 **/
3002i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3003 enum i40e_aq_resources_ids resource,
3004 u8 sdp_number,
3005 struct i40e_asq_cmd_details *cmd_details)
3006{
3007 struct i40e_aq_desc desc;
3008 struct i40e_aqc_request_resource *cmd =
3009 (struct i40e_aqc_request_resource *)&desc.params.raw;
3010 i40e_status status;
3011
3012 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3013
3014 cmd->resource_id = cpu_to_le16(resource);
3015 cmd->resource_number = cpu_to_le32(sdp_number);
3016
3017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3018
3019 return status;
3020}
3021
3022/**
3023 * i40e_aq_read_nvm
3024 * @hw: pointer to the hw struct
3025 * @module_pointer: module pointer location in words from the NVM beginning
3026 * @offset: byte offset from the module beginning
3027 * @length: length of the section to be read (in bytes from the offset)
3028 * @data: command buffer (size [bytes] = length)
3029 * @last_command: tells if this is the last command in a series
3030 * @cmd_details: pointer to command details structure or NULL
3031 *
3032 * Read the NVM using the admin queue commands
3033 **/
3034i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3035 u32 offset, u16 length, void *data,
3036 bool last_command,
3037 struct i40e_asq_cmd_details *cmd_details)
3038{
3039 struct i40e_aq_desc desc;
3040 struct i40e_aqc_nvm_update *cmd =
3041 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3042 i40e_status status;
3043
3044 /* In offset the highest byte must be zeroed. */
3045 if (offset & 0xFF000000) {
3046 status = I40E_ERR_PARAM;
3047 goto i40e_aq_read_nvm_exit;
3048 }
3049
3050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3051
3052 /* If this is the last command in a series, set the proper flag. */
3053 if (last_command)
3054 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3055 cmd->module_pointer = module_pointer;
3056 cmd->offset = cpu_to_le32(offset);
3057 cmd->length = cpu_to_le16(length);
3058
3059 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3060 if (length > I40E_AQ_LARGE_BUF)
3061 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3062
3063 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3064
3065i40e_aq_read_nvm_exit:
3066 return status;
3067}
3068
3069/**
3070 * i40e_aq_erase_nvm
3071 * @hw: pointer to the hw struct
3072 * @module_pointer: module pointer location in words from the NVM beginning
3073 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3074 * @length: length of the section to be erased (expressed in 4 KB)
3075 * @last_command: tells if this is the last command in a series
3076 * @cmd_details: pointer to command details structure or NULL
3077 *
3078 * Erase the NVM sector using the admin queue commands
3079 **/
3080i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3081 u32 offset, u16 length, bool last_command,
3082 struct i40e_asq_cmd_details *cmd_details)
3083{
3084 struct i40e_aq_desc desc;
3085 struct i40e_aqc_nvm_update *cmd =
3086 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3087 i40e_status status;
3088
3089 /* In offset the highest byte must be zeroed. */
3090 if (offset & 0xFF000000) {
3091 status = I40E_ERR_PARAM;
3092 goto i40e_aq_erase_nvm_exit;
3093 }
3094
3095 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3096
3097 /* If this is the last command in a series, set the proper flag. */
3098 if (last_command)
3099 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3100 cmd->module_pointer = module_pointer;
3101 cmd->offset = cpu_to_le32(offset);
3102 cmd->length = cpu_to_le16(length);
3103
3104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3105
3106i40e_aq_erase_nvm_exit:
3107 return status;
3108}
3109
3110/**
3111 * i40e_parse_discover_capabilities
3112 * @hw: pointer to the hw struct
3113 * @buff: pointer to a buffer containing device/function capability records
3114 * @cap_count: number of capability records in the list
3115 * @list_type_opc: type of capabilities list to parse
3116 *
3117 * Parse the device/function capabilities list.
3118 **/
3119static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3120 u32 cap_count,
3121 enum i40e_admin_queue_opc list_type_opc)
3122{
3123 struct i40e_aqc_list_capabilities_element_resp *cap;
3124 u32 valid_functions, num_functions;
3125 u32 number, logical_id, phys_id;
3126 struct i40e_hw_capabilities *p;
3127 u16 id, ocp_cfg_word0;
3128 i40e_status status;
3129 u8 major_rev;
3130 u32 i = 0;
3131
3132 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3133
3134 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3135 p = &hw->dev_caps;
3136 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3137 p = &hw->func_caps;
3138 else
3139 return;
3140
3141 for (i = 0; i < cap_count; i++, cap++) {
3142 id = le16_to_cpu(cap->id);
3143 number = le32_to_cpu(cap->number);
3144 logical_id = le32_to_cpu(cap->logical_id);
3145 phys_id = le32_to_cpu(cap->phys_id);
3146 major_rev = cap->major_rev;
3147
3148 switch (id) {
3149 case I40E_AQ_CAP_ID_SWITCH_MODE:
3150 p->switch_mode = number;
3151 break;
3152 case I40E_AQ_CAP_ID_MNG_MODE:
3153 p->management_mode = number;
3154 if (major_rev > 1) {
3155 p->mng_protocols_over_mctp = logical_id;
3156 i40e_debug(hw, I40E_DEBUG_INIT,
3157 "HW Capability: Protocols over MCTP = %d\n",
3158 p->mng_protocols_over_mctp);
3159 } else {
3160 p->mng_protocols_over_mctp = 0;
3161 }
3162 break;
3163 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3164 p->npar_enable = number;
3165 break;
3166 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3167 p->os2bmc = number;
3168 break;
3169 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3170 p->valid_functions = number;
3171 break;
3172 case I40E_AQ_CAP_ID_SRIOV:
3173 if (number == 1)
3174 p->sr_iov_1_1 = true;
3175 break;
3176 case I40E_AQ_CAP_ID_VF:
3177 p->num_vfs = number;
3178 p->vf_base_id = logical_id;
3179 break;
3180 case I40E_AQ_CAP_ID_VMDQ:
3181 if (number == 1)
3182 p->vmdq = true;
3183 break;
3184 case I40E_AQ_CAP_ID_8021QBG:
3185 if (number == 1)
3186 p->evb_802_1_qbg = true;
3187 break;
3188 case I40E_AQ_CAP_ID_8021QBR:
3189 if (number == 1)
3190 p->evb_802_1_qbh = true;
3191 break;
3192 case I40E_AQ_CAP_ID_VSI:
3193 p->num_vsis = number;
3194 break;
3195 case I40E_AQ_CAP_ID_DCB:
3196 if (number == 1) {
3197 p->dcb = true;
3198 p->enabled_tcmap = logical_id;
3199 p->maxtc = phys_id;
3200 }
3201 break;
3202 case I40E_AQ_CAP_ID_FCOE:
3203 if (number == 1)
3204 p->fcoe = true;
3205 break;
3206 case I40E_AQ_CAP_ID_ISCSI:
3207 if (number == 1)
3208 p->iscsi = true;
3209 break;
3210 case I40E_AQ_CAP_ID_RSS:
3211 p->rss = true;
3212 p->rss_table_size = number;
3213 p->rss_table_entry_width = logical_id;
3214 break;
3215 case I40E_AQ_CAP_ID_RXQ:
3216 p->num_rx_qp = number;
3217 p->base_queue = phys_id;
3218 break;
3219 case I40E_AQ_CAP_ID_TXQ:
3220 p->num_tx_qp = number;
3221 p->base_queue = phys_id;
3222 break;
3223 case I40E_AQ_CAP_ID_MSIX:
3224 p->num_msix_vectors = number;
3225 i40e_debug(hw, I40E_DEBUG_INIT,
3226 "HW Capability: MSIX vector count = %d\n",
3227 p->num_msix_vectors);
3228 break;
3229 case I40E_AQ_CAP_ID_VF_MSIX:
3230 p->num_msix_vectors_vf = number;
3231 break;
3232 case I40E_AQ_CAP_ID_FLEX10:
3233 if (major_rev == 1) {
3234 if (number == 1) {
3235 p->flex10_enable = true;
3236 p->flex10_capable = true;
3237 }
3238 } else {
3239 /* Capability revision >= 2 */
3240 if (number & 1)
3241 p->flex10_enable = true;
3242 if (number & 2)
3243 p->flex10_capable = true;
3244 }
3245 p->flex10_mode = logical_id;
3246 p->flex10_status = phys_id;
3247 break;
3248 case I40E_AQ_CAP_ID_CEM:
3249 if (number == 1)
3250 p->mgmt_cem = true;
3251 break;
3252 case I40E_AQ_CAP_ID_IWARP:
3253 if (number == 1)
3254 p->iwarp = true;
3255 break;
3256 case I40E_AQ_CAP_ID_LED:
3257 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3258 p->led[phys_id] = true;
3259 break;
3260 case I40E_AQ_CAP_ID_SDP:
3261 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3262 p->sdp[phys_id] = true;
3263 break;
3264 case I40E_AQ_CAP_ID_MDIO:
3265 if (number == 1) {
3266 p->mdio_port_num = phys_id;
3267 p->mdio_port_mode = logical_id;
3268 }
3269 break;
3270 case I40E_AQ_CAP_ID_1588:
3271 if (number == 1)
3272 p->ieee_1588 = true;
3273 break;
3274 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3275 p->fd = true;
3276 p->fd_filters_guaranteed = number;
3277 p->fd_filters_best_effort = logical_id;
3278 break;
3279 case I40E_AQ_CAP_ID_WSR_PROT:
3280 p->wr_csr_prot = (u64)number;
3281 p->wr_csr_prot |= (u64)logical_id << 32;
3282 break;
3283 case I40E_AQ_CAP_ID_NVM_MGMT:
3284 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3285 p->sec_rev_disabled = true;
3286 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3287 p->update_disabled = true;
3288 break;
3289 default:
3290 break;
3291 }
3292 }
3293
3294 if (p->fcoe)
3295 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3296
3297 /* Software override ensuring FCoE is disabled if npar or mfp
3298 * mode because it is not supported in these modes.
3299 */
3300 if (p->npar_enable || p->flex10_enable)
3301 p->fcoe = false;
3302
3303 /* count the enabled ports (aka the "not disabled" ports) */
3304 hw->num_ports = 0;
3305 for (i = 0; i < 4; i++) {
3306 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3307 u64 port_cfg = 0;
3308
3309 /* use AQ read to get the physical register offset instead
3310 * of the port relative offset
3311 */
3312 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3313 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3314 hw->num_ports++;
3315 }
3316
3317 /* OCP cards case: if a mezz is removed the Ethernet port is at
3318 * disabled state in PRTGEN_CNF register. Additional NVM read is
3319 * needed in order to check if we are dealing with OCP card.
3320 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3321 * physical ports results in wrong partition id calculation and thus
3322 * not supporting WoL.
3323 */
3324 if (hw->mac.type == I40E_MAC_X722) {
3325 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3326 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3327 2 * I40E_SR_OCP_CFG_WORD0,
3328 sizeof(ocp_cfg_word0),
3329 &ocp_cfg_word0, true, NULL);
3330 if (!status &&
3331 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3332 hw->num_ports = 4;
3333 i40e_release_nvm(hw);
3334 }
3335 }
3336
3337 valid_functions = p->valid_functions;
3338 num_functions = 0;
3339 while (valid_functions) {
3340 if (valid_functions & 1)
3341 num_functions++;
3342 valid_functions >>= 1;
3343 }
3344
3345 /* partition id is 1-based, and functions are evenly spread
3346 * across the ports as partitions
3347 */
3348 if (hw->num_ports != 0) {
3349 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3350 hw->num_partitions = num_functions / hw->num_ports;
3351 }
3352
3353 /* additional HW specific goodies that might
3354 * someday be HW version specific
3355 */
3356 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3357}
3358
3359/**
3360 * i40e_aq_discover_capabilities
3361 * @hw: pointer to the hw struct
3362 * @buff: a virtual buffer to hold the capabilities
3363 * @buff_size: Size of the virtual buffer
3364 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3365 * @list_type_opc: capabilities type to discover - pass in the command opcode
3366 * @cmd_details: pointer to command details structure or NULL
3367 *
3368 * Get the device capabilities descriptions from the firmware
3369 **/
3370i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3371 void *buff, u16 buff_size, u16 *data_size,
3372 enum i40e_admin_queue_opc list_type_opc,
3373 struct i40e_asq_cmd_details *cmd_details)
3374{
3375 struct i40e_aqc_list_capabilites *cmd;
3376 struct i40e_aq_desc desc;
3377 i40e_status status = 0;
3378
3379 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3380
3381 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3382 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3383 status = I40E_ERR_PARAM;
3384 goto exit;
3385 }
3386
3387 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3388
3389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3390 if (buff_size > I40E_AQ_LARGE_BUF)
3391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3392
3393 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3394 *data_size = le16_to_cpu(desc.datalen);
3395
3396 if (status)
3397 goto exit;
3398
3399 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3400 list_type_opc);
3401
3402exit:
3403 return status;
3404}
3405
3406/**
3407 * i40e_aq_update_nvm
3408 * @hw: pointer to the hw struct
3409 * @module_pointer: module pointer location in words from the NVM beginning
3410 * @offset: byte offset from the module beginning
3411 * @length: length of the section to be written (in bytes from the offset)
3412 * @data: command buffer (size [bytes] = length)
3413 * @last_command: tells if this is the last command in a series
3414 * @preservation_flags: Preservation mode flags
3415 * @cmd_details: pointer to command details structure or NULL
3416 *
3417 * Update the NVM using the admin queue commands
3418 **/
3419i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3420 u32 offset, u16 length, void *data,
3421 bool last_command, u8 preservation_flags,
3422 struct i40e_asq_cmd_details *cmd_details)
3423{
3424 struct i40e_aq_desc desc;
3425 struct i40e_aqc_nvm_update *cmd =
3426 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3427 i40e_status status;
3428
3429 /* In offset the highest byte must be zeroed. */
3430 if (offset & 0xFF000000) {
3431 status = I40E_ERR_PARAM;
3432 goto i40e_aq_update_nvm_exit;
3433 }
3434
3435 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3436
3437 /* If this is the last command in a series, set the proper flag. */
3438 if (last_command)
3439 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3440 if (hw->mac.type == I40E_MAC_X722) {
3441 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3442 cmd->command_flags |=
3443 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3444 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3445 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3446 cmd->command_flags |=
3447 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3448 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3449 }
3450 cmd->module_pointer = module_pointer;
3451 cmd->offset = cpu_to_le32(offset);
3452 cmd->length = cpu_to_le16(length);
3453
3454 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3455 if (length > I40E_AQ_LARGE_BUF)
3456 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3457
3458 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3459
3460i40e_aq_update_nvm_exit:
3461 return status;
3462}
3463
3464/**
3465 * i40e_aq_rearrange_nvm
3466 * @hw: pointer to the hw struct
3467 * @rearrange_nvm: defines direction of rearrangement
3468 * @cmd_details: pointer to command details structure or NULL
3469 *
3470 * Rearrange NVM structure, available only for transition FW
3471 **/
3472i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3473 u8 rearrange_nvm,
3474 struct i40e_asq_cmd_details *cmd_details)
3475{
3476 struct i40e_aqc_nvm_update *cmd;
3477 i40e_status status;
3478 struct i40e_aq_desc desc;
3479
3480 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481
3482 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3483
3484 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3485 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3486
3487 if (!rearrange_nvm) {
3488 status = I40E_ERR_PARAM;
3489 goto i40e_aq_rearrange_nvm_exit;
3490 }
3491
3492 cmd->command_flags |= rearrange_nvm;
3493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3494
3495i40e_aq_rearrange_nvm_exit:
3496 return status;
3497}
3498
3499/**
3500 * i40e_aq_get_lldp_mib
3501 * @hw: pointer to the hw struct
3502 * @bridge_type: type of bridge requested
3503 * @mib_type: Local, Remote or both Local and Remote MIBs
3504 * @buff: pointer to a user supplied buffer to store the MIB block
3505 * @buff_size: size of the buffer (in bytes)
3506 * @local_len : length of the returned Local LLDP MIB
3507 * @remote_len: length of the returned Remote LLDP MIB
3508 * @cmd_details: pointer to command details structure or NULL
3509 *
3510 * Requests the complete LLDP MIB (entire packet).
3511 **/
3512i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3513 u8 mib_type, void *buff, u16 buff_size,
3514 u16 *local_len, u16 *remote_len,
3515 struct i40e_asq_cmd_details *cmd_details)
3516{
3517 struct i40e_aq_desc desc;
3518 struct i40e_aqc_lldp_get_mib *cmd =
3519 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3520 struct i40e_aqc_lldp_get_mib *resp =
3521 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3522 i40e_status status;
3523
3524 if (buff_size == 0 || !buff)
3525 return I40E_ERR_PARAM;
3526
3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3528 /* Indirect Command */
3529 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3530
3531 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3532 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3533 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3534
3535 desc.datalen = cpu_to_le16(buff_size);
3536
3537 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3538 if (buff_size > I40E_AQ_LARGE_BUF)
3539 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3540
3541 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3542 if (!status) {
3543 if (local_len != NULL)
3544 *local_len = le16_to_cpu(resp->local_len);
3545 if (remote_len != NULL)
3546 *remote_len = le16_to_cpu(resp->remote_len);
3547 }
3548
3549 return status;
3550}
3551
3552/**
3553 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3554 * @hw: pointer to the hw struct
3555 * @mib_type: Local, Remote or both Local and Remote MIBs
3556 * @buff: pointer to a user supplied buffer to store the MIB block
3557 * @buff_size: size of the buffer (in bytes)
3558 * @cmd_details: pointer to command details structure or NULL
3559 *
3560 * Set the LLDP MIB.
3561 **/
3562enum i40e_status_code
3563i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3564 u8 mib_type, void *buff, u16 buff_size,
3565 struct i40e_asq_cmd_details *cmd_details)
3566{
3567 struct i40e_aqc_lldp_set_local_mib *cmd;
3568 enum i40e_status_code status;
3569 struct i40e_aq_desc desc;
3570
3571 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3572 if (buff_size == 0 || !buff)
3573 return I40E_ERR_PARAM;
3574
3575 i40e_fill_default_direct_cmd_desc(&desc,
3576 i40e_aqc_opc_lldp_set_local_mib);
3577 /* Indirect Command */
3578 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3579 if (buff_size > I40E_AQ_LARGE_BUF)
3580 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3581 desc.datalen = cpu_to_le16(buff_size);
3582
3583 cmd->type = mib_type;
3584 cmd->length = cpu_to_le16(buff_size);
3585 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3586 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3587
3588 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3589 return status;
3590}
3591
3592/**
3593 * i40e_aq_cfg_lldp_mib_change_event
3594 * @hw: pointer to the hw struct
3595 * @enable_update: Enable or Disable event posting
3596 * @cmd_details: pointer to command details structure or NULL
3597 *
3598 * Enable or Disable posting of an event on ARQ when LLDP MIB
3599 * associated with the interface changes
3600 **/
3601i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3602 bool enable_update,
3603 struct i40e_asq_cmd_details *cmd_details)
3604{
3605 struct i40e_aq_desc desc;
3606 struct i40e_aqc_lldp_update_mib *cmd =
3607 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3608 i40e_status status;
3609
3610 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3611
3612 if (!enable_update)
3613 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3614
3615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3616
3617 return status;
3618}
3619
3620/**
3621 * i40e_aq_restore_lldp
3622 * @hw: pointer to the hw struct
3623 * @setting: pointer to factory setting variable or NULL
3624 * @restore: True if factory settings should be restored
3625 * @cmd_details: pointer to command details structure or NULL
3626 *
3627 * Restore LLDP Agent factory settings if @restore set to True. In other case
3628 * only returns factory setting in AQ response.
3629 **/
3630enum i40e_status_code
3631i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3632 struct i40e_asq_cmd_details *cmd_details)
3633{
3634 struct i40e_aq_desc desc;
3635 struct i40e_aqc_lldp_restore *cmd =
3636 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3637 i40e_status status;
3638
3639 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3640 i40e_debug(hw, I40E_DEBUG_ALL,
3641 "Restore LLDP not supported by current FW version.\n");
3642 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3643 }
3644
3645 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3646
3647 if (restore)
3648 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3649
3650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3651
3652 if (setting)
3653 *setting = cmd->command & 1;
3654
3655 return status;
3656}
3657
3658/**
3659 * i40e_aq_stop_lldp
3660 * @hw: pointer to the hw struct
3661 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3662 * @persist: True if stop of LLDP should be persistent across power cycles
3663 * @cmd_details: pointer to command details structure or NULL
3664 *
3665 * Stop or Shutdown the embedded LLDP Agent
3666 **/
3667i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3668 bool persist,
3669 struct i40e_asq_cmd_details *cmd_details)
3670{
3671 struct i40e_aq_desc desc;
3672 struct i40e_aqc_lldp_stop *cmd =
3673 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3674 i40e_status status;
3675
3676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3677
3678 if (shutdown_agent)
3679 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3680
3681 if (persist) {
3682 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3683 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3684 else
3685 i40e_debug(hw, I40E_DEBUG_ALL,
3686 "Persistent Stop LLDP not supported by current FW version.\n");
3687 }
3688
3689 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3690
3691 return status;
3692}
3693
3694/**
3695 * i40e_aq_start_lldp
3696 * @hw: pointer to the hw struct
3697 * @persist: True if start of LLDP should be persistent across power cycles
3698 * @cmd_details: pointer to command details structure or NULL
3699 *
3700 * Start the embedded LLDP Agent on all ports.
3701 **/
3702i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3703 struct i40e_asq_cmd_details *cmd_details)
3704{
3705 struct i40e_aq_desc desc;
3706 struct i40e_aqc_lldp_start *cmd =
3707 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3708 i40e_status status;
3709
3710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3711
3712 cmd->command = I40E_AQ_LLDP_AGENT_START;
3713
3714 if (persist) {
3715 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3716 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3717 else
3718 i40e_debug(hw, I40E_DEBUG_ALL,
3719 "Persistent Start LLDP not supported by current FW version.\n");
3720 }
3721
3722 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3723
3724 return status;
3725}
3726
3727/**
3728 * i40e_aq_set_dcb_parameters
3729 * @hw: pointer to the hw struct
3730 * @cmd_details: pointer to command details structure or NULL
3731 * @dcb_enable: True if DCB configuration needs to be applied
3732 *
3733 **/
3734enum i40e_status_code
3735i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3736 struct i40e_asq_cmd_details *cmd_details)
3737{
3738 struct i40e_aq_desc desc;
3739 struct i40e_aqc_set_dcb_parameters *cmd =
3740 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3741 i40e_status status;
3742
3743 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3744 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3745
3746 i40e_fill_default_direct_cmd_desc(&desc,
3747 i40e_aqc_opc_set_dcb_parameters);
3748
3749 if (dcb_enable) {
3750 cmd->valid_flags = I40E_DCB_VALID;
3751 cmd->command = I40E_AQ_DCB_SET_AGENT;
3752 }
3753 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3754
3755 return status;
3756}
3757
3758/**
3759 * i40e_aq_get_cee_dcb_config
3760 * @hw: pointer to the hw struct
3761 * @buff: response buffer that stores CEE operational configuration
3762 * @buff_size: size of the buffer passed
3763 * @cmd_details: pointer to command details structure or NULL
3764 *
3765 * Get CEE DCBX mode operational configuration from firmware
3766 **/
3767i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3768 void *buff, u16 buff_size,
3769 struct i40e_asq_cmd_details *cmd_details)
3770{
3771 struct i40e_aq_desc desc;
3772 i40e_status status;
3773
3774 if (buff_size == 0 || !buff)
3775 return I40E_ERR_PARAM;
3776
3777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3778
3779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3780 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3781 cmd_details);
3782
3783 return status;
3784}
3785
3786/**
3787 * i40e_aq_add_udp_tunnel
3788 * @hw: pointer to the hw struct
3789 * @udp_port: the UDP port to add in Host byte order
3790 * @protocol_index: protocol index type
3791 * @filter_index: pointer to filter index
3792 * @cmd_details: pointer to command details structure or NULL
3793 *
3794 * Note: Firmware expects the udp_port value to be in Little Endian format,
3795 * and this function will call cpu_to_le16 to convert from Host byte order to
3796 * Little Endian order.
3797 **/
3798i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3799 u16 udp_port, u8 protocol_index,
3800 u8 *filter_index,
3801 struct i40e_asq_cmd_details *cmd_details)
3802{
3803 struct i40e_aq_desc desc;
3804 struct i40e_aqc_add_udp_tunnel *cmd =
3805 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3806 struct i40e_aqc_del_udp_tunnel_completion *resp =
3807 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3808 i40e_status status;
3809
3810 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3811
3812 cmd->udp_port = cpu_to_le16(udp_port);
3813 cmd->protocol_type = protocol_index;
3814
3815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3816
3817 if (!status && filter_index)
3818 *filter_index = resp->index;
3819
3820 return status;
3821}
3822
3823/**
3824 * i40e_aq_del_udp_tunnel
3825 * @hw: pointer to the hw struct
3826 * @index: filter index
3827 * @cmd_details: pointer to command details structure or NULL
3828 **/
3829i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3830 struct i40e_asq_cmd_details *cmd_details)
3831{
3832 struct i40e_aq_desc desc;
3833 struct i40e_aqc_remove_udp_tunnel *cmd =
3834 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3835 i40e_status status;
3836
3837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3838
3839 cmd->index = index;
3840
3841 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3842
3843 return status;
3844}
3845
3846/**
3847 * i40e_aq_delete_element - Delete switch element
3848 * @hw: pointer to the hw struct
3849 * @seid: the SEID to delete from the switch
3850 * @cmd_details: pointer to command details structure or NULL
3851 *
3852 * This deletes a switch element from the switch.
3853 **/
3854i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3855 struct i40e_asq_cmd_details *cmd_details)
3856{
3857 struct i40e_aq_desc desc;
3858 struct i40e_aqc_switch_seid *cmd =
3859 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3860 i40e_status status;
3861
3862 if (seid == 0)
3863 return I40E_ERR_PARAM;
3864
3865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3866
3867 cmd->seid = cpu_to_le16(seid);
3868
3869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3870
3871 return status;
3872}
3873
3874/**
3875 * i40e_aq_dcb_updated - DCB Updated Command
3876 * @hw: pointer to the hw struct
3877 * @cmd_details: pointer to command details structure or NULL
3878 *
3879 * EMP will return when the shared RPB settings have been
3880 * recomputed and modified. The retval field in the descriptor
3881 * will be set to 0 when RPB is modified.
3882 **/
3883i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3884 struct i40e_asq_cmd_details *cmd_details)
3885{
3886 struct i40e_aq_desc desc;
3887 i40e_status status;
3888
3889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3890
3891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3892
3893 return status;
3894}
3895
3896/**
3897 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3898 * @hw: pointer to the hw struct
3899 * @seid: seid for the physical port/switching component/vsi
3900 * @buff: Indirect buffer to hold data parameters and response
3901 * @buff_size: Indirect buffer size
3902 * @opcode: Tx scheduler AQ command opcode
3903 * @cmd_details: pointer to command details structure or NULL
3904 *
3905 * Generic command handler for Tx scheduler AQ commands
3906 **/
3907static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3908 void *buff, u16 buff_size,
3909 enum i40e_admin_queue_opc opcode,
3910 struct i40e_asq_cmd_details *cmd_details)
3911{
3912 struct i40e_aq_desc desc;
3913 struct i40e_aqc_tx_sched_ind *cmd =
3914 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3915 i40e_status status;
3916 bool cmd_param_flag = false;
3917
3918 switch (opcode) {
3919 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3920 case i40e_aqc_opc_configure_vsi_tc_bw:
3921 case i40e_aqc_opc_enable_switching_comp_ets:
3922 case i40e_aqc_opc_modify_switching_comp_ets:
3923 case i40e_aqc_opc_disable_switching_comp_ets:
3924 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3925 case i40e_aqc_opc_configure_switching_comp_bw_config:
3926 cmd_param_flag = true;
3927 break;
3928 case i40e_aqc_opc_query_vsi_bw_config:
3929 case i40e_aqc_opc_query_vsi_ets_sla_config:
3930 case i40e_aqc_opc_query_switching_comp_ets_config:
3931 case i40e_aqc_opc_query_port_ets_config:
3932 case i40e_aqc_opc_query_switching_comp_bw_config:
3933 cmd_param_flag = false;
3934 break;
3935 default:
3936 return I40E_ERR_PARAM;
3937 }
3938
3939 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3940
3941 /* Indirect command */
3942 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3943 if (cmd_param_flag)
3944 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3945 if (buff_size > I40E_AQ_LARGE_BUF)
3946 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3947
3948 desc.datalen = cpu_to_le16(buff_size);
3949
3950 cmd->vsi_seid = cpu_to_le16(seid);
3951
3952 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3953
3954 return status;
3955}
3956
3957/**
3958 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3959 * @hw: pointer to the hw struct
3960 * @seid: VSI seid
3961 * @credit: BW limit credits (0 = disabled)
3962 * @max_credit: Max BW limit credits
3963 * @cmd_details: pointer to command details structure or NULL
3964 **/
3965i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3966 u16 seid, u16 credit, u8 max_credit,
3967 struct i40e_asq_cmd_details *cmd_details)
3968{
3969 struct i40e_aq_desc desc;
3970 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3971 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3972 i40e_status status;
3973
3974 i40e_fill_default_direct_cmd_desc(&desc,
3975 i40e_aqc_opc_configure_vsi_bw_limit);
3976
3977 cmd->vsi_seid = cpu_to_le16(seid);
3978 cmd->credit = cpu_to_le16(credit);
3979 cmd->max_credit = max_credit;
3980
3981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3982
3983 return status;
3984}
3985
3986/**
3987 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3988 * @hw: pointer to the hw struct
3989 * @seid: VSI seid
3990 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3991 * @cmd_details: pointer to command details structure or NULL
3992 **/
3993i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3994 u16 seid,
3995 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3996 struct i40e_asq_cmd_details *cmd_details)
3997{
3998 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3999 i40e_aqc_opc_configure_vsi_tc_bw,
4000 cmd_details);
4001}
4002
4003/**
4004 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4005 * @hw: pointer to the hw struct
4006 * @seid: seid of the switching component connected to Physical Port
4007 * @ets_data: Buffer holding ETS parameters
4008 * @opcode: Tx scheduler AQ command opcode
4009 * @cmd_details: pointer to command details structure or NULL
4010 **/
4011i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4012 u16 seid,
4013 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4014 enum i40e_admin_queue_opc opcode,
4015 struct i40e_asq_cmd_details *cmd_details)
4016{
4017 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4018 sizeof(*ets_data), opcode, cmd_details);
4019}
4020
4021/**
4022 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4023 * @hw: pointer to the hw struct
4024 * @seid: seid of the switching component
4025 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4026 * @cmd_details: pointer to command details structure or NULL
4027 **/
4028i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4029 u16 seid,
4030 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4031 struct i40e_asq_cmd_details *cmd_details)
4032{
4033 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4034 i40e_aqc_opc_configure_switching_comp_bw_config,
4035 cmd_details);
4036}
4037
4038/**
4039 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4040 * @hw: pointer to the hw struct
4041 * @seid: seid of the VSI
4042 * @bw_data: Buffer to hold VSI BW configuration
4043 * @cmd_details: pointer to command details structure or NULL
4044 **/
4045i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4046 u16 seid,
4047 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4048 struct i40e_asq_cmd_details *cmd_details)
4049{
4050 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4051 i40e_aqc_opc_query_vsi_bw_config,
4052 cmd_details);
4053}
4054
4055/**
4056 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4057 * @hw: pointer to the hw struct
4058 * @seid: seid of the VSI
4059 * @bw_data: Buffer to hold VSI BW configuration per TC
4060 * @cmd_details: pointer to command details structure or NULL
4061 **/
4062i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4063 u16 seid,
4064 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4065 struct i40e_asq_cmd_details *cmd_details)
4066{
4067 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4068 i40e_aqc_opc_query_vsi_ets_sla_config,
4069 cmd_details);
4070}
4071
4072/**
4073 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4074 * @hw: pointer to the hw struct
4075 * @seid: seid of the switching component
4076 * @bw_data: Buffer to hold switching component's per TC BW config
4077 * @cmd_details: pointer to command details structure or NULL
4078 **/
4079i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4080 u16 seid,
4081 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4082 struct i40e_asq_cmd_details *cmd_details)
4083{
4084 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4085 i40e_aqc_opc_query_switching_comp_ets_config,
4086 cmd_details);
4087}
4088
4089/**
4090 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4091 * @hw: pointer to the hw struct
4092 * @seid: seid of the VSI or switching component connected to Physical Port
4093 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4094 * @cmd_details: pointer to command details structure or NULL
4095 **/
4096i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4097 u16 seid,
4098 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4099 struct i40e_asq_cmd_details *cmd_details)
4100{
4101 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4102 i40e_aqc_opc_query_port_ets_config,
4103 cmd_details);
4104}
4105
4106/**
4107 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4108 * @hw: pointer to the hw struct
4109 * @seid: seid of the switching component
4110 * @bw_data: Buffer to hold switching component's BW configuration
4111 * @cmd_details: pointer to command details structure or NULL
4112 **/
4113i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4114 u16 seid,
4115 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4116 struct i40e_asq_cmd_details *cmd_details)
4117{
4118 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4119 i40e_aqc_opc_query_switching_comp_bw_config,
4120 cmd_details);
4121}
4122
4123/**
4124 * i40e_validate_filter_settings
4125 * @hw: pointer to the hardware structure
4126 * @settings: Filter control settings
4127 *
4128 * Check and validate the filter control settings passed.
4129 * The function checks for the valid filter/context sizes being
4130 * passed for FCoE and PE.
4131 *
4132 * Returns 0 if the values passed are valid and within
4133 * range else returns an error.
4134 **/
4135static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4136 struct i40e_filter_control_settings *settings)
4137{
4138 u32 fcoe_cntx_size, fcoe_filt_size;
4139 u32 pe_cntx_size, pe_filt_size;
4140 u32 fcoe_fmax;
4141 u32 val;
4142
4143 /* Validate FCoE settings passed */
4144 switch (settings->fcoe_filt_num) {
4145 case I40E_HASH_FILTER_SIZE_1K:
4146 case I40E_HASH_FILTER_SIZE_2K:
4147 case I40E_HASH_FILTER_SIZE_4K:
4148 case I40E_HASH_FILTER_SIZE_8K:
4149 case I40E_HASH_FILTER_SIZE_16K:
4150 case I40E_HASH_FILTER_SIZE_32K:
4151 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4152 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4153 break;
4154 default:
4155 return I40E_ERR_PARAM;
4156 }
4157
4158 switch (settings->fcoe_cntx_num) {
4159 case I40E_DMA_CNTX_SIZE_512:
4160 case I40E_DMA_CNTX_SIZE_1K:
4161 case I40E_DMA_CNTX_SIZE_2K:
4162 case I40E_DMA_CNTX_SIZE_4K:
4163 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4164 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4165 break;
4166 default:
4167 return I40E_ERR_PARAM;
4168 }
4169
4170 /* Validate PE settings passed */
4171 switch (settings->pe_filt_num) {
4172 case I40E_HASH_FILTER_SIZE_1K:
4173 case I40E_HASH_FILTER_SIZE_2K:
4174 case I40E_HASH_FILTER_SIZE_4K:
4175 case I40E_HASH_FILTER_SIZE_8K:
4176 case I40E_HASH_FILTER_SIZE_16K:
4177 case I40E_HASH_FILTER_SIZE_32K:
4178 case I40E_HASH_FILTER_SIZE_64K:
4179 case I40E_HASH_FILTER_SIZE_128K:
4180 case I40E_HASH_FILTER_SIZE_256K:
4181 case I40E_HASH_FILTER_SIZE_512K:
4182 case I40E_HASH_FILTER_SIZE_1M:
4183 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4184 pe_filt_size <<= (u32)settings->pe_filt_num;
4185 break;
4186 default:
4187 return I40E_ERR_PARAM;
4188 }
4189
4190 switch (settings->pe_cntx_num) {
4191 case I40E_DMA_CNTX_SIZE_512:
4192 case I40E_DMA_CNTX_SIZE_1K:
4193 case I40E_DMA_CNTX_SIZE_2K:
4194 case I40E_DMA_CNTX_SIZE_4K:
4195 case I40E_DMA_CNTX_SIZE_8K:
4196 case I40E_DMA_CNTX_SIZE_16K:
4197 case I40E_DMA_CNTX_SIZE_32K:
4198 case I40E_DMA_CNTX_SIZE_64K:
4199 case I40E_DMA_CNTX_SIZE_128K:
4200 case I40E_DMA_CNTX_SIZE_256K:
4201 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4202 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4203 break;
4204 default:
4205 return I40E_ERR_PARAM;
4206 }
4207
4208 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4209 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4210 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4211 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4212 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4213 return I40E_ERR_INVALID_SIZE;
4214
4215 return 0;
4216}
4217
4218/**
4219 * i40e_set_filter_control
4220 * @hw: pointer to the hardware structure
4221 * @settings: Filter control settings
4222 *
4223 * Set the Queue Filters for PE/FCoE and enable filters required
4224 * for a single PF. It is expected that these settings are programmed
4225 * at the driver initialization time.
4226 **/
4227i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4228 struct i40e_filter_control_settings *settings)
4229{
4230 i40e_status ret = 0;
4231 u32 hash_lut_size = 0;
4232 u32 val;
4233
4234 if (!settings)
4235 return I40E_ERR_PARAM;
4236
4237 /* Validate the input settings */
4238 ret = i40e_validate_filter_settings(hw, settings);
4239 if (ret)
4240 return ret;
4241
4242 /* Read the PF Queue Filter control register */
4243 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4244
4245 /* Program required PE hash buckets for the PF */
4246 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4247 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4248 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4249 /* Program required PE contexts for the PF */
4250 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4251 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4252 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4253
4254 /* Program required FCoE hash buckets for the PF */
4255 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4256 val |= ((u32)settings->fcoe_filt_num <<
4257 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4258 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4259 /* Program required FCoE DDP contexts for the PF */
4260 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4261 val |= ((u32)settings->fcoe_cntx_num <<
4262 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4263 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4264
4265 /* Program Hash LUT size for the PF */
4266 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4267 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4268 hash_lut_size = 1;
4269 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4270 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4271
4272 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4273 if (settings->enable_fdir)
4274 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4275 if (settings->enable_ethtype)
4276 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4277 if (settings->enable_macvlan)
4278 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4279
4280 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4281
4282 return 0;
4283}
4284
4285/**
4286 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4287 * @hw: pointer to the hw struct
4288 * @mac_addr: MAC address to use in the filter
4289 * @ethtype: Ethertype to use in the filter
4290 * @flags: Flags that needs to be applied to the filter
4291 * @vsi_seid: seid of the control VSI
4292 * @queue: VSI queue number to send the packet to
4293 * @is_add: Add control packet filter if True else remove
4294 * @stats: Structure to hold information on control filter counts
4295 * @cmd_details: pointer to command details structure or NULL
4296 *
4297 * This command will Add or Remove control packet filter for a control VSI.
4298 * In return it will update the total number of perfect filter count in
4299 * the stats member.
4300 **/
4301i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4302 u8 *mac_addr, u16 ethtype, u16 flags,
4303 u16 vsi_seid, u16 queue, bool is_add,
4304 struct i40e_control_filter_stats *stats,
4305 struct i40e_asq_cmd_details *cmd_details)
4306{
4307 struct i40e_aq_desc desc;
4308 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4309 (struct i40e_aqc_add_remove_control_packet_filter *)
4310 &desc.params.raw;
4311 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4312 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4313 &desc.params.raw;
4314 i40e_status status;
4315
4316 if (vsi_seid == 0)
4317 return I40E_ERR_PARAM;
4318
4319 if (is_add) {
4320 i40e_fill_default_direct_cmd_desc(&desc,
4321 i40e_aqc_opc_add_control_packet_filter);
4322 cmd->queue = cpu_to_le16(queue);
4323 } else {
4324 i40e_fill_default_direct_cmd_desc(&desc,
4325 i40e_aqc_opc_remove_control_packet_filter);
4326 }
4327
4328 if (mac_addr)
4329 ether_addr_copy(cmd->mac, mac_addr);
4330
4331 cmd->etype = cpu_to_le16(ethtype);
4332 cmd->flags = cpu_to_le16(flags);
4333 cmd->seid = cpu_to_le16(vsi_seid);
4334
4335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4336
4337 if (!status && stats) {
4338 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4339 stats->etype_used = le16_to_cpu(resp->etype_used);
4340 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4341 stats->etype_free = le16_to_cpu(resp->etype_free);
4342 }
4343
4344 return status;
4345}
4346
4347/**
4348 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4349 * @hw: pointer to the hw struct
4350 * @seid: VSI seid to add ethertype filter from
4351 **/
4352void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4353 u16 seid)
4354{
4355#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4356 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4357 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4358 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4359 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4360 i40e_status status;
4361
4362 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4363 seid, 0, true, NULL,
4364 NULL);
4365 if (status)
4366 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4367}
4368
4369/**
4370 * i40e_aq_alternate_read
4371 * @hw: pointer to the hardware structure
4372 * @reg_addr0: address of first dword to be read
4373 * @reg_val0: pointer for data read from 'reg_addr0'
4374 * @reg_addr1: address of second dword to be read
4375 * @reg_val1: pointer for data read from 'reg_addr1'
4376 *
4377 * Read one or two dwords from alternate structure. Fields are indicated
4378 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4379 * is not passed then only register at 'reg_addr0' is read.
4380 *
4381 **/
4382static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4383 u32 reg_addr0, u32 *reg_val0,
4384 u32 reg_addr1, u32 *reg_val1)
4385{
4386 struct i40e_aq_desc desc;
4387 struct i40e_aqc_alternate_write *cmd_resp =
4388 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4389 i40e_status status;
4390
4391 if (!reg_val0)
4392 return I40E_ERR_PARAM;
4393
4394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4395 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4396 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4397
4398 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4399
4400 if (!status) {
4401 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4402
4403 if (reg_val1)
4404 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4405 }
4406
4407 return status;
4408}
4409
4410/**
4411 * i40e_aq_suspend_port_tx
4412 * @hw: pointer to the hardware structure
4413 * @seid: port seid
4414 * @cmd_details: pointer to command details structure or NULL
4415 *
4416 * Suspend port's Tx traffic
4417 **/
4418i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4419 struct i40e_asq_cmd_details *cmd_details)
4420{
4421 struct i40e_aqc_tx_sched_ind *cmd;
4422 struct i40e_aq_desc desc;
4423 i40e_status status;
4424
4425 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4427 cmd->vsi_seid = cpu_to_le16(seid);
4428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4429
4430 return status;
4431}
4432
4433/**
4434 * i40e_aq_resume_port_tx
4435 * @hw: pointer to the hardware structure
4436 * @cmd_details: pointer to command details structure or NULL
4437 *
4438 * Resume port's Tx traffic
4439 **/
4440i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4441 struct i40e_asq_cmd_details *cmd_details)
4442{
4443 struct i40e_aq_desc desc;
4444 i40e_status status;
4445
4446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4447
4448 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4449
4450 return status;
4451}
4452
4453/**
4454 * i40e_set_pci_config_data - store PCI bus info
4455 * @hw: pointer to hardware structure
4456 * @link_status: the link status word from PCI config space
4457 *
4458 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4459 **/
4460void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4461{
4462 hw->bus.type = i40e_bus_type_pci_express;
4463
4464 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4465 case PCI_EXP_LNKSTA_NLW_X1:
4466 hw->bus.width = i40e_bus_width_pcie_x1;
4467 break;
4468 case PCI_EXP_LNKSTA_NLW_X2:
4469 hw->bus.width = i40e_bus_width_pcie_x2;
4470 break;
4471 case PCI_EXP_LNKSTA_NLW_X4:
4472 hw->bus.width = i40e_bus_width_pcie_x4;
4473 break;
4474 case PCI_EXP_LNKSTA_NLW_X8:
4475 hw->bus.width = i40e_bus_width_pcie_x8;
4476 break;
4477 default:
4478 hw->bus.width = i40e_bus_width_unknown;
4479 break;
4480 }
4481
4482 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4483 case PCI_EXP_LNKSTA_CLS_2_5GB:
4484 hw->bus.speed = i40e_bus_speed_2500;
4485 break;
4486 case PCI_EXP_LNKSTA_CLS_5_0GB:
4487 hw->bus.speed = i40e_bus_speed_5000;
4488 break;
4489 case PCI_EXP_LNKSTA_CLS_8_0GB:
4490 hw->bus.speed = i40e_bus_speed_8000;
4491 break;
4492 default:
4493 hw->bus.speed = i40e_bus_speed_unknown;
4494 break;
4495 }
4496}
4497
4498/**
4499 * i40e_aq_debug_dump
4500 * @hw: pointer to the hardware structure
4501 * @cluster_id: specific cluster to dump
4502 * @table_id: table id within cluster
4503 * @start_index: index of line in the block to read
4504 * @buff_size: dump buffer size
4505 * @buff: dump buffer
4506 * @ret_buff_size: actual buffer size returned
4507 * @ret_next_table: next block to read
4508 * @ret_next_index: next index to read
4509 * @cmd_details: pointer to command details structure or NULL
4510 *
4511 * Dump internal FW/HW data for debug purposes.
4512 *
4513 **/
4514i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4515 u8 table_id, u32 start_index, u16 buff_size,
4516 void *buff, u16 *ret_buff_size,
4517 u8 *ret_next_table, u32 *ret_next_index,
4518 struct i40e_asq_cmd_details *cmd_details)
4519{
4520 struct i40e_aq_desc desc;
4521 struct i40e_aqc_debug_dump_internals *cmd =
4522 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4523 struct i40e_aqc_debug_dump_internals *resp =
4524 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4525 i40e_status status;
4526
4527 if (buff_size == 0 || !buff)
4528 return I40E_ERR_PARAM;
4529
4530 i40e_fill_default_direct_cmd_desc(&desc,
4531 i40e_aqc_opc_debug_dump_internals);
4532 /* Indirect Command */
4533 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4534 if (buff_size > I40E_AQ_LARGE_BUF)
4535 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4536
4537 cmd->cluster_id = cluster_id;
4538 cmd->table_id = table_id;
4539 cmd->idx = cpu_to_le32(start_index);
4540
4541 desc.datalen = cpu_to_le16(buff_size);
4542
4543 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4544 if (!status) {
4545 if (ret_buff_size)
4546 *ret_buff_size = le16_to_cpu(desc.datalen);
4547 if (ret_next_table)
4548 *ret_next_table = resp->table_id;
4549 if (ret_next_index)
4550 *ret_next_index = le32_to_cpu(resp->idx);
4551 }
4552
4553 return status;
4554}
4555
4556/**
4557 * i40e_read_bw_from_alt_ram
4558 * @hw: pointer to the hardware structure
4559 * @max_bw: pointer for max_bw read
4560 * @min_bw: pointer for min_bw read
4561 * @min_valid: pointer for bool that is true if min_bw is a valid value
4562 * @max_valid: pointer for bool that is true if max_bw is a valid value
4563 *
4564 * Read bw from the alternate ram for the given pf
4565 **/
4566i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4567 u32 *max_bw, u32 *min_bw,
4568 bool *min_valid, bool *max_valid)
4569{
4570 i40e_status status;
4571 u32 max_bw_addr, min_bw_addr;
4572
4573 /* Calculate the address of the min/max bw registers */
4574 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4575 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4576 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4577 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4578 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4579 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4580
4581 /* Read the bandwidths from alt ram */
4582 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4583 min_bw_addr, min_bw);
4584
4585 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4586 *min_valid = true;
4587 else
4588 *min_valid = false;
4589
4590 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4591 *max_valid = true;
4592 else
4593 *max_valid = false;
4594
4595 return status;
4596}
4597
4598/**
4599 * i40e_aq_configure_partition_bw
4600 * @hw: pointer to the hardware structure
4601 * @bw_data: Buffer holding valid pfs and bw limits
4602 * @cmd_details: pointer to command details
4603 *
4604 * Configure partitions guaranteed/max bw
4605 **/
4606i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4607 struct i40e_aqc_configure_partition_bw_data *bw_data,
4608 struct i40e_asq_cmd_details *cmd_details)
4609{
4610 i40e_status status;
4611 struct i40e_aq_desc desc;
4612 u16 bwd_size = sizeof(*bw_data);
4613
4614 i40e_fill_default_direct_cmd_desc(&desc,
4615 i40e_aqc_opc_configure_partition_bw);
4616
4617 /* Indirect command */
4618 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4620
4621 if (bwd_size > I40E_AQ_LARGE_BUF)
4622 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4623
4624 desc.datalen = cpu_to_le16(bwd_size);
4625
4626 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4627 cmd_details);
4628
4629 return status;
4630}
4631
4632/**
4633 * i40e_read_phy_register_clause22
4634 * @hw: pointer to the HW structure
4635 * @reg: register address in the page
4636 * @phy_addr: PHY address on MDIO interface
4637 * @value: PHY register value
4638 *
4639 * Reads specified PHY register value
4640 **/
4641i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4642 u16 reg, u8 phy_addr, u16 *value)
4643{
4644 i40e_status status = I40E_ERR_TIMEOUT;
4645 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4646 u32 command = 0;
4647 u16 retry = 1000;
4648
4649 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4650 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4651 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4652 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4653 (I40E_GLGEN_MSCA_MDICMD_MASK);
4654 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4655 do {
4656 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4657 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4658 status = 0;
4659 break;
4660 }
4661 udelay(10);
4662 retry--;
4663 } while (retry);
4664
4665 if (status) {
4666 i40e_debug(hw, I40E_DEBUG_PHY,
4667 "PHY: Can't write command to external PHY.\n");
4668 } else {
4669 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4670 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4671 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4672 }
4673
4674 return status;
4675}
4676
4677/**
4678 * i40e_write_phy_register_clause22
4679 * @hw: pointer to the HW structure
4680 * @reg: register address in the page
4681 * @phy_addr: PHY address on MDIO interface
4682 * @value: PHY register value
4683 *
4684 * Writes specified PHY register value
4685 **/
4686i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4687 u16 reg, u8 phy_addr, u16 value)
4688{
4689 i40e_status status = I40E_ERR_TIMEOUT;
4690 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4691 u32 command = 0;
4692 u16 retry = 1000;
4693
4694 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4695 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4696
4697 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4698 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4699 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4700 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4701 (I40E_GLGEN_MSCA_MDICMD_MASK);
4702
4703 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4704 do {
4705 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4706 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4707 status = 0;
4708 break;
4709 }
4710 udelay(10);
4711 retry--;
4712 } while (retry);
4713
4714 return status;
4715}
4716
4717/**
4718 * i40e_read_phy_register_clause45
4719 * @hw: pointer to the HW structure
4720 * @page: registers page number
4721 * @reg: register address in the page
4722 * @phy_addr: PHY address on MDIO interface
4723 * @value: PHY register value
4724 *
4725 * Reads specified PHY register value
4726 **/
4727i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4728 u8 page, u16 reg, u8 phy_addr, u16 *value)
4729{
4730 i40e_status status = I40E_ERR_TIMEOUT;
4731 u32 command = 0;
4732 u16 retry = 1000;
4733 u8 port_num = hw->func_caps.mdio_port_num;
4734
4735 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4736 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4737 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4738 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4739 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4740 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4741 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4742 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4743 do {
4744 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4745 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4746 status = 0;
4747 break;
4748 }
4749 usleep_range(10, 20);
4750 retry--;
4751 } while (retry);
4752
4753 if (status) {
4754 i40e_debug(hw, I40E_DEBUG_PHY,
4755 "PHY: Can't write command to external PHY.\n");
4756 goto phy_read_end;
4757 }
4758
4759 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4760 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4761 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4762 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4763 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4764 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4765 status = I40E_ERR_TIMEOUT;
4766 retry = 1000;
4767 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4768 do {
4769 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4770 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4771 status = 0;
4772 break;
4773 }
4774 usleep_range(10, 20);
4775 retry--;
4776 } while (retry);
4777
4778 if (!status) {
4779 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4780 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4781 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4782 } else {
4783 i40e_debug(hw, I40E_DEBUG_PHY,
4784 "PHY: Can't read register value from external PHY.\n");
4785 }
4786
4787phy_read_end:
4788 return status;
4789}
4790
4791/**
4792 * i40e_write_phy_register_clause45
4793 * @hw: pointer to the HW structure
4794 * @page: registers page number
4795 * @reg: register address in the page
4796 * @phy_addr: PHY address on MDIO interface
4797 * @value: PHY register value
4798 *
4799 * Writes value to specified PHY register
4800 **/
4801i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4802 u8 page, u16 reg, u8 phy_addr, u16 value)
4803{
4804 i40e_status status = I40E_ERR_TIMEOUT;
4805 u32 command = 0;
4806 u16 retry = 1000;
4807 u8 port_num = hw->func_caps.mdio_port_num;
4808
4809 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4810 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4811 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4812 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4813 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4814 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4815 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4816 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4817 do {
4818 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4819 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4820 status = 0;
4821 break;
4822 }
4823 usleep_range(10, 20);
4824 retry--;
4825 } while (retry);
4826 if (status) {
4827 i40e_debug(hw, I40E_DEBUG_PHY,
4828 "PHY: Can't write command to external PHY.\n");
4829 goto phy_write_end;
4830 }
4831
4832 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4833 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4834
4835 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4836 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4837 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4838 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4839 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4840 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4841 status = I40E_ERR_TIMEOUT;
4842 retry = 1000;
4843 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4844 do {
4845 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4846 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4847 status = 0;
4848 break;
4849 }
4850 usleep_range(10, 20);
4851 retry--;
4852 } while (retry);
4853
4854phy_write_end:
4855 return status;
4856}
4857
4858/**
4859 * i40e_write_phy_register
4860 * @hw: pointer to the HW structure
4861 * @page: registers page number
4862 * @reg: register address in the page
4863 * @phy_addr: PHY address on MDIO interface
4864 * @value: PHY register value
4865 *
4866 * Writes value to specified PHY register
4867 **/
4868i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4869 u8 page, u16 reg, u8 phy_addr, u16 value)
4870{
4871 i40e_status status;
4872
4873 switch (hw->device_id) {
4874 case I40E_DEV_ID_1G_BASE_T_X722:
4875 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4876 value);
4877 break;
4878 case I40E_DEV_ID_5G_BASE_T_BC:
4879 case I40E_DEV_ID_10G_BASE_T:
4880 case I40E_DEV_ID_10G_BASE_T4:
4881 case I40E_DEV_ID_10G_BASE_T_BC:
4882 case I40E_DEV_ID_10G_BASE_T_X722:
4883 case I40E_DEV_ID_25G_B:
4884 case I40E_DEV_ID_25G_SFP28:
4885 status = i40e_write_phy_register_clause45(hw, page, reg,
4886 phy_addr, value);
4887 break;
4888 default:
4889 status = I40E_ERR_UNKNOWN_PHY;
4890 break;
4891 }
4892
4893 return status;
4894}
4895
4896/**
4897 * i40e_read_phy_register
4898 * @hw: pointer to the HW structure
4899 * @page: registers page number
4900 * @reg: register address in the page
4901 * @phy_addr: PHY address on MDIO interface
4902 * @value: PHY register value
4903 *
4904 * Reads specified PHY register value
4905 **/
4906i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4907 u8 page, u16 reg, u8 phy_addr, u16 *value)
4908{
4909 i40e_status status;
4910
4911 switch (hw->device_id) {
4912 case I40E_DEV_ID_1G_BASE_T_X722:
4913 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4914 value);
4915 break;
4916 case I40E_DEV_ID_5G_BASE_T_BC:
4917 case I40E_DEV_ID_10G_BASE_T:
4918 case I40E_DEV_ID_10G_BASE_T4:
4919 case I40E_DEV_ID_10G_BASE_T_BC:
4920 case I40E_DEV_ID_10G_BASE_T_X722:
4921 case I40E_DEV_ID_25G_B:
4922 case I40E_DEV_ID_25G_SFP28:
4923 status = i40e_read_phy_register_clause45(hw, page, reg,
4924 phy_addr, value);
4925 break;
4926 default:
4927 status = I40E_ERR_UNKNOWN_PHY;
4928 break;
4929 }
4930
4931 return status;
4932}
4933
4934/**
4935 * i40e_get_phy_address
4936 * @hw: pointer to the HW structure
4937 * @dev_num: PHY port num that address we want
4938 *
4939 * Gets PHY address for current port
4940 **/
4941u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4942{
4943 u8 port_num = hw->func_caps.mdio_port_num;
4944 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4945
4946 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4947}
4948
4949/**
4950 * i40e_blink_phy_link_led
4951 * @hw: pointer to the HW structure
4952 * @time: time how long led will blinks in secs
4953 * @interval: gap between LED on and off in msecs
4954 *
4955 * Blinks PHY link LED
4956 **/
4957i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4958 u32 time, u32 interval)
4959{
4960 i40e_status status = 0;
4961 u32 i;
4962 u16 led_ctl;
4963 u16 gpio_led_port;
4964 u16 led_reg;
4965 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4966 u8 phy_addr = 0;
4967 u8 port_num;
4968
4969 i = rd32(hw, I40E_PFGEN_PORTNUM);
4970 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4971 phy_addr = i40e_get_phy_address(hw, port_num);
4972
4973 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4974 led_addr++) {
4975 status = i40e_read_phy_register_clause45(hw,
4976 I40E_PHY_COM_REG_PAGE,
4977 led_addr, phy_addr,
4978 &led_reg);
4979 if (status)
4980 goto phy_blinking_end;
4981 led_ctl = led_reg;
4982 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4983 led_reg = 0;
4984 status = i40e_write_phy_register_clause45(hw,
4985 I40E_PHY_COM_REG_PAGE,
4986 led_addr, phy_addr,
4987 led_reg);
4988 if (status)
4989 goto phy_blinking_end;
4990 break;
4991 }
4992 }
4993
4994 if (time > 0 && interval > 0) {
4995 for (i = 0; i < time * 1000; i += interval) {
4996 status = i40e_read_phy_register_clause45(hw,
4997 I40E_PHY_COM_REG_PAGE,
4998 led_addr, phy_addr, &led_reg);
4999 if (status)
5000 goto restore_config;
5001 if (led_reg & I40E_PHY_LED_MANUAL_ON)
5002 led_reg = 0;
5003 else
5004 led_reg = I40E_PHY_LED_MANUAL_ON;
5005 status = i40e_write_phy_register_clause45(hw,
5006 I40E_PHY_COM_REG_PAGE,
5007 led_addr, phy_addr, led_reg);
5008 if (status)
5009 goto restore_config;
5010 msleep(interval);
5011 }
5012 }
5013
5014restore_config:
5015 status = i40e_write_phy_register_clause45(hw,
5016 I40E_PHY_COM_REG_PAGE,
5017 led_addr, phy_addr, led_ctl);
5018
5019phy_blinking_end:
5020 return status;
5021}
5022
5023/**
5024 * i40e_led_get_reg - read LED register
5025 * @hw: pointer to the HW structure
5026 * @led_addr: LED register address
5027 * @reg_val: read register value
5028 **/
5029static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5030 u32 *reg_val)
5031{
5032 enum i40e_status_code status;
5033 u8 phy_addr = 0;
5034 u8 port_num;
5035 u32 i;
5036
5037 *reg_val = 0;
5038 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5039 status =
5040 i40e_aq_get_phy_register(hw,
5041 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5042 I40E_PHY_COM_REG_PAGE, true,
5043 I40E_PHY_LED_PROV_REG_1,
5044 reg_val, NULL);
5045 } else {
5046 i = rd32(hw, I40E_PFGEN_PORTNUM);
5047 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5048 phy_addr = i40e_get_phy_address(hw, port_num);
5049 status = i40e_read_phy_register_clause45(hw,
5050 I40E_PHY_COM_REG_PAGE,
5051 led_addr, phy_addr,
5052 (u16 *)reg_val);
5053 }
5054 return status;
5055}
5056
5057/**
5058 * i40e_led_set_reg - write LED register
5059 * @hw: pointer to the HW structure
5060 * @led_addr: LED register address
5061 * @reg_val: register value to write
5062 **/
5063static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5064 u32 reg_val)
5065{
5066 enum i40e_status_code status;
5067 u8 phy_addr = 0;
5068 u8 port_num;
5069 u32 i;
5070
5071 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5072 status =
5073 i40e_aq_set_phy_register(hw,
5074 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5075 I40E_PHY_COM_REG_PAGE, true,
5076 I40E_PHY_LED_PROV_REG_1,
5077 reg_val, NULL);
5078 } else {
5079 i = rd32(hw, I40E_PFGEN_PORTNUM);
5080 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5081 phy_addr = i40e_get_phy_address(hw, port_num);
5082 status = i40e_write_phy_register_clause45(hw,
5083 I40E_PHY_COM_REG_PAGE,
5084 led_addr, phy_addr,
5085 (u16)reg_val);
5086 }
5087
5088 return status;
5089}
5090
5091/**
5092 * i40e_led_get_phy - return current on/off mode
5093 * @hw: pointer to the hw struct
5094 * @led_addr: address of led register to use
5095 * @val: original value of register to use
5096 *
5097 **/
5098i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5099 u16 *val)
5100{
5101 i40e_status status = 0;
5102 u16 gpio_led_port;
5103 u8 phy_addr = 0;
5104 u16 reg_val;
5105 u16 temp_addr;
5106 u8 port_num;
5107 u32 i;
5108 u32 reg_val_aq;
5109
5110 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5111 status =
5112 i40e_aq_get_phy_register(hw,
5113 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5114 I40E_PHY_COM_REG_PAGE, true,
5115 I40E_PHY_LED_PROV_REG_1,
5116 ®_val_aq, NULL);
5117 if (status == I40E_SUCCESS)
5118 *val = (u16)reg_val_aq;
5119 return status;
5120 }
5121 temp_addr = I40E_PHY_LED_PROV_REG_1;
5122 i = rd32(hw, I40E_PFGEN_PORTNUM);
5123 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5124 phy_addr = i40e_get_phy_address(hw, port_num);
5125
5126 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5127 temp_addr++) {
5128 status = i40e_read_phy_register_clause45(hw,
5129 I40E_PHY_COM_REG_PAGE,
5130 temp_addr, phy_addr,
5131 ®_val);
5132 if (status)
5133 return status;
5134 *val = reg_val;
5135 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5136 *led_addr = temp_addr;
5137 break;
5138 }
5139 }
5140 return status;
5141}
5142
5143/**
5144 * i40e_led_set_phy
5145 * @hw: pointer to the HW structure
5146 * @on: true or false
5147 * @led_addr: address of led register to use
5148 * @mode: original val plus bit for set or ignore
5149 *
5150 * Set led's on or off when controlled by the PHY
5151 *
5152 **/
5153i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5154 u16 led_addr, u32 mode)
5155{
5156 i40e_status status = 0;
5157 u32 led_ctl = 0;
5158 u32 led_reg = 0;
5159
5160 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5161 if (status)
5162 return status;
5163 led_ctl = led_reg;
5164 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5165 led_reg = 0;
5166 status = i40e_led_set_reg(hw, led_addr, led_reg);
5167 if (status)
5168 return status;
5169 }
5170 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5171 if (status)
5172 goto restore_config;
5173 if (on)
5174 led_reg = I40E_PHY_LED_MANUAL_ON;
5175 else
5176 led_reg = 0;
5177
5178 status = i40e_led_set_reg(hw, led_addr, led_reg);
5179 if (status)
5180 goto restore_config;
5181 if (mode & I40E_PHY_LED_MODE_ORIG) {
5182 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5183 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5184 }
5185 return status;
5186
5187restore_config:
5188 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5189 return status;
5190}
5191
5192/**
5193 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5194 * @hw: pointer to the hw struct
5195 * @reg_addr: register address
5196 * @reg_val: ptr to register value
5197 * @cmd_details: pointer to command details structure or NULL
5198 *
5199 * Use the firmware to read the Rx control register,
5200 * especially useful if the Rx unit is under heavy pressure
5201 **/
5202i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5203 u32 reg_addr, u32 *reg_val,
5204 struct i40e_asq_cmd_details *cmd_details)
5205{
5206 struct i40e_aq_desc desc;
5207 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5208 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5209 i40e_status status;
5210
5211 if (!reg_val)
5212 return I40E_ERR_PARAM;
5213
5214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5215
5216 cmd_resp->address = cpu_to_le32(reg_addr);
5217
5218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5219
5220 if (status == 0)
5221 *reg_val = le32_to_cpu(cmd_resp->value);
5222
5223 return status;
5224}
5225
5226/**
5227 * i40e_read_rx_ctl - read from an Rx control register
5228 * @hw: pointer to the hw struct
5229 * @reg_addr: register address
5230 **/
5231u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5232{
5233 i40e_status status = 0;
5234 bool use_register;
5235 int retry = 5;
5236 u32 val = 0;
5237
5238 use_register = (((hw->aq.api_maj_ver == 1) &&
5239 (hw->aq.api_min_ver < 5)) ||
5240 (hw->mac.type == I40E_MAC_X722));
5241 if (!use_register) {
5242do_retry:
5243 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5244 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5245 usleep_range(1000, 2000);
5246 retry--;
5247 goto do_retry;
5248 }
5249 }
5250
5251 /* if the AQ access failed, try the old-fashioned way */
5252 if (status || use_register)
5253 val = rd32(hw, reg_addr);
5254
5255 return val;
5256}
5257
5258/**
5259 * i40e_aq_rx_ctl_write_register
5260 * @hw: pointer to the hw struct
5261 * @reg_addr: register address
5262 * @reg_val: register value
5263 * @cmd_details: pointer to command details structure or NULL
5264 *
5265 * Use the firmware to write to an Rx control register,
5266 * especially useful if the Rx unit is under heavy pressure
5267 **/
5268i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5269 u32 reg_addr, u32 reg_val,
5270 struct i40e_asq_cmd_details *cmd_details)
5271{
5272 struct i40e_aq_desc desc;
5273 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5274 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5275 i40e_status status;
5276
5277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5278
5279 cmd->address = cpu_to_le32(reg_addr);
5280 cmd->value = cpu_to_le32(reg_val);
5281
5282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5283
5284 return status;
5285}
5286
5287/**
5288 * i40e_write_rx_ctl - write to an Rx control register
5289 * @hw: pointer to the hw struct
5290 * @reg_addr: register address
5291 * @reg_val: register value
5292 **/
5293void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5294{
5295 i40e_status status = 0;
5296 bool use_register;
5297 int retry = 5;
5298
5299 use_register = (((hw->aq.api_maj_ver == 1) &&
5300 (hw->aq.api_min_ver < 5)) ||
5301 (hw->mac.type == I40E_MAC_X722));
5302 if (!use_register) {
5303do_retry:
5304 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5305 reg_val, NULL);
5306 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5307 usleep_range(1000, 2000);
5308 retry--;
5309 goto do_retry;
5310 }
5311 }
5312
5313 /* if the AQ access failed, try the old-fashioned way */
5314 if (status || use_register)
5315 wr32(hw, reg_addr, reg_val);
5316}
5317
5318/**
5319 * i40e_mdio_if_number_selection - MDIO I/F number selection
5320 * @hw: pointer to the hw struct
5321 * @set_mdio: use MDIO I/F number specified by mdio_num
5322 * @mdio_num: MDIO I/F number
5323 * @cmd: pointer to PHY Register command structure
5324 **/
5325static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5326 u8 mdio_num,
5327 struct i40e_aqc_phy_register_access *cmd)
5328{
5329 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
5330 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
5331 cmd->cmd_flags |=
5332 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5333 ((mdio_num <<
5334 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
5335 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
5336 else
5337 i40e_debug(hw, I40E_DEBUG_PHY,
5338 "MDIO I/F number selection not supported by current FW version.\n");
5339 }
5340}
5341
5342/**
5343 * i40e_aq_set_phy_register_ext
5344 * @hw: pointer to the hw struct
5345 * @phy_select: select which phy should be accessed
5346 * @dev_addr: PHY device address
5347 * @page_change: flag to indicate if phy page should be updated
5348 * @set_mdio: use MDIO I/F number specified by mdio_num
5349 * @mdio_num: MDIO I/F number
5350 * @reg_addr: PHY register address
5351 * @reg_val: new register value
5352 * @cmd_details: pointer to command details structure or NULL
5353 *
5354 * Write the external PHY register.
5355 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5356 * may use simple wrapper i40e_aq_set_phy_register.
5357 **/
5358enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5359 u8 phy_select, u8 dev_addr, bool page_change,
5360 bool set_mdio, u8 mdio_num,
5361 u32 reg_addr, u32 reg_val,
5362 struct i40e_asq_cmd_details *cmd_details)
5363{
5364 struct i40e_aq_desc desc;
5365 struct i40e_aqc_phy_register_access *cmd =
5366 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5367 i40e_status status;
5368
5369 i40e_fill_default_direct_cmd_desc(&desc,
5370 i40e_aqc_opc_set_phy_register);
5371
5372 cmd->phy_interface = phy_select;
5373 cmd->dev_address = dev_addr;
5374 cmd->reg_address = cpu_to_le32(reg_addr);
5375 cmd->reg_value = cpu_to_le32(reg_val);
5376
5377 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5378
5379 if (!page_change)
5380 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5381
5382 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5383
5384 return status;
5385}
5386
5387/**
5388 * i40e_aq_get_phy_register_ext
5389 * @hw: pointer to the hw struct
5390 * @phy_select: select which phy should be accessed
5391 * @dev_addr: PHY device address
5392 * @page_change: flag to indicate if phy page should be updated
5393 * @set_mdio: use MDIO I/F number specified by mdio_num
5394 * @mdio_num: MDIO I/F number
5395 * @reg_addr: PHY register address
5396 * @reg_val: read register value
5397 * @cmd_details: pointer to command details structure or NULL
5398 *
5399 * Read the external PHY register.
5400 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5401 * may use simple wrapper i40e_aq_get_phy_register.
5402 **/
5403enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5404 u8 phy_select, u8 dev_addr, bool page_change,
5405 bool set_mdio, u8 mdio_num,
5406 u32 reg_addr, u32 *reg_val,
5407 struct i40e_asq_cmd_details *cmd_details)
5408{
5409 struct i40e_aq_desc desc;
5410 struct i40e_aqc_phy_register_access *cmd =
5411 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5412 i40e_status status;
5413
5414 i40e_fill_default_direct_cmd_desc(&desc,
5415 i40e_aqc_opc_get_phy_register);
5416
5417 cmd->phy_interface = phy_select;
5418 cmd->dev_address = dev_addr;
5419 cmd->reg_address = cpu_to_le32(reg_addr);
5420
5421 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5422
5423 if (!page_change)
5424 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5425
5426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5427 if (!status)
5428 *reg_val = le32_to_cpu(cmd->reg_value);
5429
5430 return status;
5431}
5432
5433/**
5434 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5435 * @hw: pointer to the hw struct
5436 * @buff: command buffer (size in bytes = buff_size)
5437 * @buff_size: buffer size in bytes
5438 * @track_id: package tracking id
5439 * @error_offset: returns error offset
5440 * @error_info: returns error information
5441 * @cmd_details: pointer to command details structure or NULL
5442 **/
5443enum
5444i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5445 u16 buff_size, u32 track_id,
5446 u32 *error_offset, u32 *error_info,
5447 struct i40e_asq_cmd_details *cmd_details)
5448{
5449 struct i40e_aq_desc desc;
5450 struct i40e_aqc_write_personalization_profile *cmd =
5451 (struct i40e_aqc_write_personalization_profile *)
5452 &desc.params.raw;
5453 struct i40e_aqc_write_ddp_resp *resp;
5454 i40e_status status;
5455
5456 i40e_fill_default_direct_cmd_desc(&desc,
5457 i40e_aqc_opc_write_personalization_profile);
5458
5459 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5460 if (buff_size > I40E_AQ_LARGE_BUF)
5461 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5462
5463 desc.datalen = cpu_to_le16(buff_size);
5464
5465 cmd->profile_track_id = cpu_to_le32(track_id);
5466
5467 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5468 if (!status) {
5469 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5470 if (error_offset)
5471 *error_offset = le32_to_cpu(resp->error_offset);
5472 if (error_info)
5473 *error_info = le32_to_cpu(resp->error_info);
5474 }
5475
5476 return status;
5477}
5478
5479/**
5480 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5481 * @hw: pointer to the hw struct
5482 * @buff: command buffer (size in bytes = buff_size)
5483 * @buff_size: buffer size in bytes
5484 * @flags: AdminQ command flags
5485 * @cmd_details: pointer to command details structure or NULL
5486 **/
5487enum
5488i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5489 u16 buff_size, u8 flags,
5490 struct i40e_asq_cmd_details *cmd_details)
5491{
5492 struct i40e_aq_desc desc;
5493 struct i40e_aqc_get_applied_profiles *cmd =
5494 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5495 i40e_status status;
5496
5497 i40e_fill_default_direct_cmd_desc(&desc,
5498 i40e_aqc_opc_get_personalization_profile_list);
5499
5500 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5501 if (buff_size > I40E_AQ_LARGE_BUF)
5502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5503 desc.datalen = cpu_to_le16(buff_size);
5504
5505 cmd->flags = flags;
5506
5507 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5508
5509 return status;
5510}
5511
5512/**
5513 * i40e_find_segment_in_package
5514 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5515 * @pkg_hdr: pointer to the package header to be searched
5516 *
5517 * This function searches a package file for a particular segment type. On
5518 * success it returns a pointer to the segment header, otherwise it will
5519 * return NULL.
5520 **/
5521struct i40e_generic_seg_header *
5522i40e_find_segment_in_package(u32 segment_type,
5523 struct i40e_package_header *pkg_hdr)
5524{
5525 struct i40e_generic_seg_header *segment;
5526 u32 i;
5527
5528 /* Search all package segments for the requested segment type */
5529 for (i = 0; i < pkg_hdr->segment_count; i++) {
5530 segment =
5531 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5532 pkg_hdr->segment_offset[i]);
5533
5534 if (segment->type == segment_type)
5535 return segment;
5536 }
5537
5538 return NULL;
5539}
5540
5541/* Get section table in profile */
5542#define I40E_SECTION_TABLE(profile, sec_tbl) \
5543 do { \
5544 struct i40e_profile_segment *p = (profile); \
5545 u32 count; \
5546 u32 *nvm; \
5547 count = p->device_table_count; \
5548 nvm = (u32 *)&p->device_table[count]; \
5549 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5550 } while (0)
5551
5552/* Get section header in profile */
5553#define I40E_SECTION_HEADER(profile, offset) \
5554 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5555
5556/**
5557 * i40e_find_section_in_profile
5558 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5559 * @profile: pointer to the i40e segment header to be searched
5560 *
5561 * This function searches i40e segment for a particular section type. On
5562 * success it returns a pointer to the section header, otherwise it will
5563 * return NULL.
5564 **/
5565struct i40e_profile_section_header *
5566i40e_find_section_in_profile(u32 section_type,
5567 struct i40e_profile_segment *profile)
5568{
5569 struct i40e_profile_section_header *sec;
5570 struct i40e_section_table *sec_tbl;
5571 u32 sec_off;
5572 u32 i;
5573
5574 if (profile->header.type != SEGMENT_TYPE_I40E)
5575 return NULL;
5576
5577 I40E_SECTION_TABLE(profile, sec_tbl);
5578
5579 for (i = 0; i < sec_tbl->section_count; i++) {
5580 sec_off = sec_tbl->section_offset[i];
5581 sec = I40E_SECTION_HEADER(profile, sec_off);
5582 if (sec->section.type == section_type)
5583 return sec;
5584 }
5585
5586 return NULL;
5587}
5588
5589/**
5590 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5591 * @hw: pointer to the hw struct
5592 * @aq: command buffer containing all data to execute AQ
5593 **/
5594static enum
5595i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5596 struct i40e_profile_aq_section *aq)
5597{
5598 i40e_status status;
5599 struct i40e_aq_desc desc;
5600 u8 *msg = NULL;
5601 u16 msglen;
5602
5603 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5604 desc.flags |= cpu_to_le16(aq->flags);
5605 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5606
5607 msglen = aq->datalen;
5608 if (msglen) {
5609 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5610 I40E_AQ_FLAG_RD));
5611 if (msglen > I40E_AQ_LARGE_BUF)
5612 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5613 desc.datalen = cpu_to_le16(msglen);
5614 msg = &aq->data[0];
5615 }
5616
5617 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5618
5619 if (status) {
5620 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5621 "unable to exec DDP AQ opcode %u, error %d\n",
5622 aq->opcode, status);
5623 return status;
5624 }
5625
5626 /* copy returned desc to aq_buf */
5627 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5628
5629 return 0;
5630}
5631
5632/**
5633 * i40e_validate_profile
5634 * @hw: pointer to the hardware structure
5635 * @profile: pointer to the profile segment of the package to be validated
5636 * @track_id: package tracking id
5637 * @rollback: flag if the profile is for rollback.
5638 *
5639 * Validates supported devices and profile's sections.
5640 */
5641static enum i40e_status_code
5642i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5643 u32 track_id, bool rollback)
5644{
5645 struct i40e_profile_section_header *sec = NULL;
5646 i40e_status status = 0;
5647 struct i40e_section_table *sec_tbl;
5648 u32 vendor_dev_id;
5649 u32 dev_cnt;
5650 u32 sec_off;
5651 u32 i;
5652
5653 if (track_id == I40E_DDP_TRACKID_INVALID) {
5654 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5655 return I40E_NOT_SUPPORTED;
5656 }
5657
5658 dev_cnt = profile->device_table_count;
5659 for (i = 0; i < dev_cnt; i++) {
5660 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5661 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5662 hw->device_id == (vendor_dev_id & 0xFFFF))
5663 break;
5664 }
5665 if (dev_cnt && i == dev_cnt) {
5666 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5667 "Device doesn't support DDP\n");
5668 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5669 }
5670
5671 I40E_SECTION_TABLE(profile, sec_tbl);
5672
5673 /* Validate sections types */
5674 for (i = 0; i < sec_tbl->section_count; i++) {
5675 sec_off = sec_tbl->section_offset[i];
5676 sec = I40E_SECTION_HEADER(profile, sec_off);
5677 if (rollback) {
5678 if (sec->section.type == SECTION_TYPE_MMIO ||
5679 sec->section.type == SECTION_TYPE_AQ ||
5680 sec->section.type == SECTION_TYPE_RB_AQ) {
5681 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5682 "Not a roll-back package\n");
5683 return I40E_NOT_SUPPORTED;
5684 }
5685 } else {
5686 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5687 sec->section.type == SECTION_TYPE_RB_MMIO) {
5688 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5689 "Not an original package\n");
5690 return I40E_NOT_SUPPORTED;
5691 }
5692 }
5693 }
5694
5695 return status;
5696}
5697
5698/**
5699 * i40e_write_profile
5700 * @hw: pointer to the hardware structure
5701 * @profile: pointer to the profile segment of the package to be downloaded
5702 * @track_id: package tracking id
5703 *
5704 * Handles the download of a complete package.
5705 */
5706enum i40e_status_code
5707i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5708 u32 track_id)
5709{
5710 i40e_status status = 0;
5711 struct i40e_section_table *sec_tbl;
5712 struct i40e_profile_section_header *sec = NULL;
5713 struct i40e_profile_aq_section *ddp_aq;
5714 u32 section_size = 0;
5715 u32 offset = 0, info = 0;
5716 u32 sec_off;
5717 u32 i;
5718
5719 status = i40e_validate_profile(hw, profile, track_id, false);
5720 if (status)
5721 return status;
5722
5723 I40E_SECTION_TABLE(profile, sec_tbl);
5724
5725 for (i = 0; i < sec_tbl->section_count; i++) {
5726 sec_off = sec_tbl->section_offset[i];
5727 sec = I40E_SECTION_HEADER(profile, sec_off);
5728 /* Process generic admin command */
5729 if (sec->section.type == SECTION_TYPE_AQ) {
5730 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5731 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5732 if (status) {
5733 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5734 "Failed to execute aq: section %d, opcode %u\n",
5735 i, ddp_aq->opcode);
5736 break;
5737 }
5738 sec->section.type = SECTION_TYPE_RB_AQ;
5739 }
5740
5741 /* Skip any non-mmio sections */
5742 if (sec->section.type != SECTION_TYPE_MMIO)
5743 continue;
5744
5745 section_size = sec->section.size +
5746 sizeof(struct i40e_profile_section_header);
5747
5748 /* Write MMIO section */
5749 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5750 track_id, &offset, &info, NULL);
5751 if (status) {
5752 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5753 "Failed to write profile: section %d, offset %d, info %d\n",
5754 i, offset, info);
5755 break;
5756 }
5757 }
5758 return status;
5759}
5760
5761/**
5762 * i40e_rollback_profile
5763 * @hw: pointer to the hardware structure
5764 * @profile: pointer to the profile segment of the package to be removed
5765 * @track_id: package tracking id
5766 *
5767 * Rolls back previously loaded package.
5768 */
5769enum i40e_status_code
5770i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5771 u32 track_id)
5772{
5773 struct i40e_profile_section_header *sec = NULL;
5774 i40e_status status = 0;
5775 struct i40e_section_table *sec_tbl;
5776 u32 offset = 0, info = 0;
5777 u32 section_size = 0;
5778 u32 sec_off;
5779 int i;
5780
5781 status = i40e_validate_profile(hw, profile, track_id, true);
5782 if (status)
5783 return status;
5784
5785 I40E_SECTION_TABLE(profile, sec_tbl);
5786
5787 /* For rollback write sections in reverse */
5788 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5789 sec_off = sec_tbl->section_offset[i];
5790 sec = I40E_SECTION_HEADER(profile, sec_off);
5791
5792 /* Skip any non-rollback sections */
5793 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5794 continue;
5795
5796 section_size = sec->section.size +
5797 sizeof(struct i40e_profile_section_header);
5798
5799 /* Write roll-back MMIO section */
5800 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5801 track_id, &offset, &info, NULL);
5802 if (status) {
5803 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5804 "Failed to write profile: section %d, offset %d, info %d\n",
5805 i, offset, info);
5806 break;
5807 }
5808 }
5809 return status;
5810}
5811
5812/**
5813 * i40e_add_pinfo_to_list
5814 * @hw: pointer to the hardware structure
5815 * @profile: pointer to the profile segment of the package
5816 * @profile_info_sec: buffer for information section
5817 * @track_id: package tracking id
5818 *
5819 * Register a profile to the list of loaded profiles.
5820 */
5821enum i40e_status_code
5822i40e_add_pinfo_to_list(struct i40e_hw *hw,
5823 struct i40e_profile_segment *profile,
5824 u8 *profile_info_sec, u32 track_id)
5825{
5826 i40e_status status = 0;
5827 struct i40e_profile_section_header *sec = NULL;
5828 struct i40e_profile_info *pinfo;
5829 u32 offset = 0, info = 0;
5830
5831 sec = (struct i40e_profile_section_header *)profile_info_sec;
5832 sec->tbl_size = 1;
5833 sec->data_end = sizeof(struct i40e_profile_section_header) +
5834 sizeof(struct i40e_profile_info);
5835 sec->section.type = SECTION_TYPE_INFO;
5836 sec->section.offset = sizeof(struct i40e_profile_section_header);
5837 sec->section.size = sizeof(struct i40e_profile_info);
5838 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5839 sec->section.offset);
5840 pinfo->track_id = track_id;
5841 pinfo->version = profile->version;
5842 pinfo->op = I40E_DDP_ADD_TRACKID;
5843 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5844
5845 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5846 track_id, &offset, &info, NULL);
5847
5848 return status;
5849}
5850
5851/**
5852 * i40e_aq_add_cloud_filters
5853 * @hw: pointer to the hardware structure
5854 * @seid: VSI seid to add cloud filters from
5855 * @filters: Buffer which contains the filters to be added
5856 * @filter_count: number of filters contained in the buffer
5857 *
5858 * Set the cloud filters for a given VSI. The contents of the
5859 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5860 * of the function.
5861 *
5862 **/
5863enum i40e_status_code
5864i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5865 struct i40e_aqc_cloud_filters_element_data *filters,
5866 u8 filter_count)
5867{
5868 struct i40e_aq_desc desc;
5869 struct i40e_aqc_add_remove_cloud_filters *cmd =
5870 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5871 enum i40e_status_code status;
5872 u16 buff_len;
5873
5874 i40e_fill_default_direct_cmd_desc(&desc,
5875 i40e_aqc_opc_add_cloud_filters);
5876
5877 buff_len = filter_count * sizeof(*filters);
5878 desc.datalen = cpu_to_le16(buff_len);
5879 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5880 cmd->num_filters = filter_count;
5881 cmd->seid = cpu_to_le16(seid);
5882
5883 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5884
5885 return status;
5886}
5887
5888/**
5889 * i40e_aq_add_cloud_filters_bb
5890 * @hw: pointer to the hardware structure
5891 * @seid: VSI seid to add cloud filters from
5892 * @filters: Buffer which contains the filters in big buffer to be added
5893 * @filter_count: number of filters contained in the buffer
5894 *
5895 * Set the big buffer cloud filters for a given VSI. The contents of the
5896 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5897 * function.
5898 *
5899 **/
5900enum i40e_status_code
5901i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5902 struct i40e_aqc_cloud_filters_element_bb *filters,
5903 u8 filter_count)
5904{
5905 struct i40e_aq_desc desc;
5906 struct i40e_aqc_add_remove_cloud_filters *cmd =
5907 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5908 i40e_status status;
5909 u16 buff_len;
5910 int i;
5911
5912 i40e_fill_default_direct_cmd_desc(&desc,
5913 i40e_aqc_opc_add_cloud_filters);
5914
5915 buff_len = filter_count * sizeof(*filters);
5916 desc.datalen = cpu_to_le16(buff_len);
5917 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5918 cmd->num_filters = filter_count;
5919 cmd->seid = cpu_to_le16(seid);
5920 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5921
5922 for (i = 0; i < filter_count; i++) {
5923 u16 tnl_type;
5924 u32 ti;
5925
5926 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5927 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5928 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5929
5930 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5931 * one more byte further than normally used for Tenant ID in
5932 * other tunnel types.
5933 */
5934 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5935 ti = le32_to_cpu(filters[i].element.tenant_id);
5936 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5937 }
5938 }
5939
5940 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5941
5942 return status;
5943}
5944
5945/**
5946 * i40e_aq_rem_cloud_filters
5947 * @hw: pointer to the hardware structure
5948 * @seid: VSI seid to remove cloud filters from
5949 * @filters: Buffer which contains the filters to be removed
5950 * @filter_count: number of filters contained in the buffer
5951 *
5952 * Remove the cloud filters for a given VSI. The contents of the
5953 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5954 * of the function.
5955 *
5956 **/
5957enum i40e_status_code
5958i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5959 struct i40e_aqc_cloud_filters_element_data *filters,
5960 u8 filter_count)
5961{
5962 struct i40e_aq_desc desc;
5963 struct i40e_aqc_add_remove_cloud_filters *cmd =
5964 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5965 enum i40e_status_code status;
5966 u16 buff_len;
5967
5968 i40e_fill_default_direct_cmd_desc(&desc,
5969 i40e_aqc_opc_remove_cloud_filters);
5970
5971 buff_len = filter_count * sizeof(*filters);
5972 desc.datalen = cpu_to_le16(buff_len);
5973 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5974 cmd->num_filters = filter_count;
5975 cmd->seid = cpu_to_le16(seid);
5976
5977 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5978
5979 return status;
5980}
5981
5982/**
5983 * i40e_aq_rem_cloud_filters_bb
5984 * @hw: pointer to the hardware structure
5985 * @seid: VSI seid to remove cloud filters from
5986 * @filters: Buffer which contains the filters in big buffer to be removed
5987 * @filter_count: number of filters contained in the buffer
5988 *
5989 * Remove the big buffer cloud filters for a given VSI. The contents of the
5990 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5991 * function.
5992 *
5993 **/
5994enum i40e_status_code
5995i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5996 struct i40e_aqc_cloud_filters_element_bb *filters,
5997 u8 filter_count)
5998{
5999 struct i40e_aq_desc desc;
6000 struct i40e_aqc_add_remove_cloud_filters *cmd =
6001 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6002 i40e_status status;
6003 u16 buff_len;
6004 int i;
6005
6006 i40e_fill_default_direct_cmd_desc(&desc,
6007 i40e_aqc_opc_remove_cloud_filters);
6008
6009 buff_len = filter_count * sizeof(*filters);
6010 desc.datalen = cpu_to_le16(buff_len);
6011 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6012 cmd->num_filters = filter_count;
6013 cmd->seid = cpu_to_le16(seid);
6014 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6015
6016 for (i = 0; i < filter_count; i++) {
6017 u16 tnl_type;
6018 u32 ti;
6019
6020 tnl_type = (le16_to_cpu(filters[i].element.flags) &
6021 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6022 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6023
6024 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6025 * one more byte further than normally used for Tenant ID in
6026 * other tunnel types.
6027 */
6028 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6029 ti = le32_to_cpu(filters[i].element.tenant_id);
6030 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
6031 }
6032 }
6033
6034 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6035
6036 return status;
6037}