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1/*
2 * Tegra host1x Channel
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/host1x.h>
20#include <linux/slab.h>
21
22#include <trace/events/host1x.h>
23
24#include "../channel.h"
25#include "../dev.h"
26#include "../intr.h"
27#include "../job.h"
28
29#define HOST1X_CHANNEL_SIZE 16384
30#define TRACE_MAX_LENGTH 128U
31
32static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
33 u32 offset, u32 words)
34{
35 struct device *dev = cdma_to_channel(cdma)->dev;
36 void *mem = NULL;
37
38 if (host1x_debug_trace_cmdbuf)
39 mem = host1x_bo_mmap(bo);
40
41 if (mem) {
42 u32 i;
43 /*
44 * Write in batches of 128 as there seems to be a limit
45 * of how much you can output to ftrace at once.
46 */
47 for (i = 0; i < words; i += TRACE_MAX_LENGTH) {
48 u32 num_words = min(words - i, TRACE_MAX_LENGTH);
49 offset += i * sizeof(u32);
50
51 trace_host1x_cdma_push_gather(dev_name(dev), bo,
52 num_words, offset,
53 mem);
54 }
55
56 host1x_bo_munmap(bo, mem);
57 }
58}
59
60static void submit_gathers(struct host1x_job *job)
61{
62 struct host1x_cdma *cdma = &job->channel->cdma;
63 unsigned int i;
64
65 for (i = 0; i < job->num_gathers; i++) {
66 struct host1x_job_gather *g = &job->gathers[i];
67 u32 op1 = host1x_opcode_gather(g->words);
68 u32 op2 = g->base + g->offset;
69 trace_write_gather(cdma, g->bo, g->offset, op1 & 0xffff);
70 host1x_cdma_push(cdma, op1, op2);
71 }
72}
73
74static inline void synchronize_syncpt_base(struct host1x_job *job)
75{
76 struct host1x *host = dev_get_drvdata(job->channel->dev->parent);
77 struct host1x_syncpt *sp = host->syncpt + job->syncpt_id;
78 u32 id, value;
79
80 value = host1x_syncpt_read_max(sp);
81 id = sp->base->id;
82
83 host1x_cdma_push(&job->channel->cdma,
84 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
85 HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1),
86 HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) |
87 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
88}
89
90static int channel_submit(struct host1x_job *job)
91{
92 struct host1x_channel *ch = job->channel;
93 struct host1x_syncpt *sp;
94 u32 user_syncpt_incrs = job->syncpt_incrs;
95 u32 prev_max = 0;
96 u32 syncval;
97 int err;
98 struct host1x_waitlist *completed_waiter = NULL;
99 struct host1x *host = dev_get_drvdata(ch->dev->parent);
100
101 sp = host->syncpt + job->syncpt_id;
102 trace_host1x_channel_submit(dev_name(ch->dev),
103 job->num_gathers, job->num_relocs,
104 job->num_waitchk, job->syncpt_id,
105 job->syncpt_incrs);
106
107 /* before error checks, return current max */
108 prev_max = job->syncpt_end = host1x_syncpt_read_max(sp);
109
110 /* get submit lock */
111 err = mutex_lock_interruptible(&ch->submitlock);
112 if (err)
113 goto error;
114
115 completed_waiter = kzalloc(sizeof(*completed_waiter), GFP_KERNEL);
116 if (!completed_waiter) {
117 mutex_unlock(&ch->submitlock);
118 err = -ENOMEM;
119 goto error;
120 }
121
122 /* begin a CDMA submit */
123 err = host1x_cdma_begin(&ch->cdma, job);
124 if (err) {
125 mutex_unlock(&ch->submitlock);
126 goto error;
127 }
128
129 if (job->serialize) {
130 /*
131 * Force serialization by inserting a host wait for the
132 * previous job to finish before this one can commence.
133 */
134 host1x_cdma_push(&ch->cdma,
135 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
136 host1x_uclass_wait_syncpt_r(), 1),
137 host1x_class_host_wait_syncpt(job->syncpt_id,
138 host1x_syncpt_read_max(sp)));
139 }
140
141 /* Synchronize base register to allow using it for relative waiting */
142 if (sp->base)
143 synchronize_syncpt_base(job);
144
145 syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
146
147 job->syncpt_end = syncval;
148
149 /* add a setclass for modules that require it */
150 if (job->class)
151 host1x_cdma_push(&ch->cdma,
152 host1x_opcode_setclass(job->class, 0, 0),
153 HOST1X_OPCODE_NOP);
154
155 submit_gathers(job);
156
157 /* end CDMA submit & stash pinned hMems into sync queue */
158 host1x_cdma_end(&ch->cdma, job);
159
160 trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval);
161
162 /* schedule a submit complete interrupt */
163 err = host1x_intr_add_action(host, job->syncpt_id, syncval,
164 HOST1X_INTR_ACTION_SUBMIT_COMPLETE, ch,
165 completed_waiter, NULL);
166 completed_waiter = NULL;
167 WARN(err, "Failed to set submit complete interrupt");
168
169 mutex_unlock(&ch->submitlock);
170
171 return 0;
172
173error:
174 kfree(completed_waiter);
175 return err;
176}
177
178static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
179 unsigned int index)
180{
181 ch->id = index;
182 mutex_init(&ch->reflock);
183 mutex_init(&ch->submitlock);
184
185 ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
186 return 0;
187}
188
189static const struct host1x_channel_ops host1x_channel_ops = {
190 .init = host1x_channel_init,
191 .submit = channel_submit,
192};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Tegra host1x Channel
4 *
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
6 */
7
8#include <linux/host1x.h>
9#include <linux/iommu.h>
10#include <linux/slab.h>
11
12#include <trace/events/host1x.h>
13
14#include "../channel.h"
15#include "../dev.h"
16#include "../intr.h"
17#include "../job.h"
18
19#define TRACE_MAX_LENGTH 128U
20
21static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
22 u32 offset, u32 words)
23{
24 struct device *dev = cdma_to_channel(cdma)->dev;
25 void *mem = NULL;
26
27 if (host1x_debug_trace_cmdbuf)
28 mem = host1x_bo_mmap(bo);
29
30 if (mem) {
31 u32 i;
32 /*
33 * Write in batches of 128 as there seems to be a limit
34 * of how much you can output to ftrace at once.
35 */
36 for (i = 0; i < words; i += TRACE_MAX_LENGTH) {
37 u32 num_words = min(words - i, TRACE_MAX_LENGTH);
38
39 offset += i * sizeof(u32);
40
41 trace_host1x_cdma_push_gather(dev_name(dev), bo,
42 num_words, offset,
43 mem);
44 }
45
46 host1x_bo_munmap(bo, mem);
47 }
48}
49
50static void submit_gathers(struct host1x_job *job)
51{
52 struct host1x_cdma *cdma = &job->channel->cdma;
53#if HOST1X_HW < 6
54 struct device *dev = job->channel->dev;
55#endif
56 unsigned int i;
57
58 for (i = 0; i < job->num_gathers; i++) {
59 struct host1x_job_gather *g = &job->gathers[i];
60 dma_addr_t addr = g->base + g->offset;
61 u32 op2, op3;
62
63 op2 = lower_32_bits(addr);
64 op3 = upper_32_bits(addr);
65
66 trace_write_gather(cdma, g->bo, g->offset, g->words);
67
68 if (op3 != 0) {
69#if HOST1X_HW >= 6
70 u32 op1 = host1x_opcode_gather_wide(g->words);
71 u32 op4 = HOST1X_OPCODE_NOP;
72
73 host1x_cdma_push_wide(cdma, op1, op2, op3, op4);
74#else
75 dev_err(dev, "invalid gather for push buffer %pad\n",
76 &addr);
77 continue;
78#endif
79 } else {
80 u32 op1 = host1x_opcode_gather(g->words);
81
82 host1x_cdma_push(cdma, op1, op2);
83 }
84 }
85}
86
87static inline void synchronize_syncpt_base(struct host1x_job *job)
88{
89 struct host1x_syncpt *sp = job->syncpt;
90 unsigned int id;
91 u32 value;
92
93 value = host1x_syncpt_read_max(sp);
94 id = sp->base->id;
95
96 host1x_cdma_push(&job->channel->cdma,
97 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
98 HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1),
99 HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) |
100 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
101}
102
103static void host1x_channel_set_streamid(struct host1x_channel *channel)
104{
105#if HOST1X_HW >= 6
106 u32 sid = 0x7f;
107#ifdef CONFIG_IOMMU_API
108 struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
109 if (spec)
110 sid = spec->ids[0] & 0xffff;
111#endif
112
113 host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
114#endif
115}
116
117static int channel_submit(struct host1x_job *job)
118{
119 struct host1x_channel *ch = job->channel;
120 struct host1x_syncpt *sp = job->syncpt;
121 u32 user_syncpt_incrs = job->syncpt_incrs;
122 u32 prev_max = 0;
123 u32 syncval;
124 int err;
125 struct host1x_waitlist *completed_waiter = NULL;
126 struct host1x *host = dev_get_drvdata(ch->dev->parent);
127
128 trace_host1x_channel_submit(dev_name(ch->dev),
129 job->num_gathers, job->num_relocs,
130 job->syncpt->id, job->syncpt_incrs);
131
132 /* before error checks, return current max */
133 prev_max = job->syncpt_end = host1x_syncpt_read_max(sp);
134
135 /* get submit lock */
136 err = mutex_lock_interruptible(&ch->submitlock);
137 if (err)
138 goto error;
139
140 completed_waiter = kzalloc(sizeof(*completed_waiter), GFP_KERNEL);
141 if (!completed_waiter) {
142 mutex_unlock(&ch->submitlock);
143 err = -ENOMEM;
144 goto error;
145 }
146
147 host1x_channel_set_streamid(ch);
148
149 /* begin a CDMA submit */
150 err = host1x_cdma_begin(&ch->cdma, job);
151 if (err) {
152 mutex_unlock(&ch->submitlock);
153 goto error;
154 }
155
156 if (job->serialize) {
157 /*
158 * Force serialization by inserting a host wait for the
159 * previous job to finish before this one can commence.
160 */
161 host1x_cdma_push(&ch->cdma,
162 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
163 host1x_uclass_wait_syncpt_r(), 1),
164 host1x_class_host_wait_syncpt(job->syncpt->id,
165 host1x_syncpt_read_max(sp)));
166 }
167
168 /* Synchronize base register to allow using it for relative waiting */
169 if (sp->base)
170 synchronize_syncpt_base(job);
171
172 syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
173
174 host1x_hw_syncpt_assign_to_channel(host, sp, ch);
175
176 job->syncpt_end = syncval;
177
178 /* add a setclass for modules that require it */
179 if (job->class)
180 host1x_cdma_push(&ch->cdma,
181 host1x_opcode_setclass(job->class, 0, 0),
182 HOST1X_OPCODE_NOP);
183
184 submit_gathers(job);
185
186 /* end CDMA submit & stash pinned hMems into sync queue */
187 host1x_cdma_end(&ch->cdma, job);
188
189 trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval);
190
191 /* schedule a submit complete interrupt */
192 err = host1x_intr_add_action(host, sp, syncval,
193 HOST1X_INTR_ACTION_SUBMIT_COMPLETE, ch,
194 completed_waiter, NULL);
195 completed_waiter = NULL;
196 WARN(err, "Failed to set submit complete interrupt");
197
198 mutex_unlock(&ch->submitlock);
199
200 return 0;
201
202error:
203 kfree(completed_waiter);
204 return err;
205}
206
207static void enable_gather_filter(struct host1x *host,
208 struct host1x_channel *ch)
209{
210#if HOST1X_HW >= 6
211 u32 val;
212
213 if (!host->hv_regs)
214 return;
215
216 val = host1x_hypervisor_readl(
217 host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
218 val |= BIT(ch->id % 32);
219 host1x_hypervisor_writel(
220 host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
221#elif HOST1X_HW >= 4
222 host1x_ch_writel(ch,
223 HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(1),
224 HOST1X_CHANNEL_CHANNELCTRL);
225#endif
226}
227
228static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
229 unsigned int index)
230{
231#if HOST1X_HW < 6
232 ch->regs = dev->regs + index * 0x4000;
233#else
234 ch->regs = dev->regs + index * 0x100;
235#endif
236 enable_gather_filter(dev, ch);
237 return 0;
238}
239
240static const struct host1x_channel_ops host1x_channel_ops = {
241 .init = host1x_channel_init,
242 .submit = channel_submit,
243};