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1#ifndef DSI_PHY_7NM_XML
2#define DSI_PHY_7NM_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
31Copyright (C) 2013-2021 by the following authors:
32- Rob Clark <robdclark@gmail.com> (robclark)
33- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
35Permission is hereby granted, free of charge, to any person obtaining
36a copy of this software and associated documentation files (the
37"Software"), to deal in the Software without restriction, including
38without limitation the rights to use, copy, modify, merge, publish,
39distribute, sublicense, and/or sell copies of the Software, and to
40permit persons to whom the Software is furnished to do so, subject to
41the following conditions:
42
43The above copyright notice and this permission notice (including the
44next paragraph) shall be included in all copies or substantial
45portions of the Software.
46
47THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54*/
55
56
57#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58
59#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60
61#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62
63#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64
65#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66
67#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68
69#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70
71#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72
73#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74
75#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
76
77#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
78
79#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
80
81#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
82
83#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
84
85#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
86
87#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
88
89#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
90
91#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
92
93#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
94
95#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
96
97#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
98
99#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
100
101#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102
103#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104
105#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106
107#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108
109#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110
111#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112
113#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114
115#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116
117#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118
119#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120
121#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122
123#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124
125#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126
127#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128
129#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130
131#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132
133#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134
135#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136
137#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138
139#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140
141#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142
143#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144
145#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146
147#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
148
149#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
150
151#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
152
153#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
154
155#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
156
157#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
158
159static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
160
161static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
162
163static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
164
165static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
166
167static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
168
169static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
170
171static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
172
173static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
174
175#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
176
177#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
178
179#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
180
181#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
182
183#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
184
185#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
186
187#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
188
189#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
190
191#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
192
193#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
194
195#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
196
197#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
198
199#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
200
201#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
202
203#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
204
205#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
206
207#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
208
209#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
210
211#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
212
213#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
214
215#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
216
217#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
218
219#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
220
221#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
222
223#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
224
225#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
226
227#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
228
229#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
230
231#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
232
233#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
234
235#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
236
237#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
238
239#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
240
241#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
242
243#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
244
245#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
246
247#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
248
249#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
250
251#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
252
253#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
254
255#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
256
257#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
258
259#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
260
261#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
262
263#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
264
265#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
266
267#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
268
269#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
270
271#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
272
273#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
274
275#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
276
277#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
278
279#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
280
281#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
282
283#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
284
285#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
286
287#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
288
289#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
290
291#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
292
293#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
294
295#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
296
297#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
298
299#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
300
301#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
302
303#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
304
305#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
306
307#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
308
309#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
310
311#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
312
313#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
314
315#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
316
317#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
318
319#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
320
321#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
322
323#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
324
325#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
326
327#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
328
329#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
330
331#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
332
333#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
334
335#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
336
337#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
338
339#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
340
341#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
342
343#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
344
345#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
346
347#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
348
349#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
350
351#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
352
353#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
354
355#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
356
357#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
358
359#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
360
361#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
362
363#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
364
365#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
366
367#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
368
369#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
370
371#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
372
373#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
374
375#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
376
377#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
378
379#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
380
381#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
382
383#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
384
385#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
386
387#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
388
389#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
390
391#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
392
393#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
394
395#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
396
397#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
398
399#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
400
401#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
402
403#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
404
405#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
406
407#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
408
409#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
410
411#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
412
413#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
414
415#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
416
417#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
418
419#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
420
421#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
422
423#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
424
425#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
426
427#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
428
429#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
430
431#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
432
433#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
434
435#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
436
437#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
438
439#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
440
441#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
442
443#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
444
445#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
446
447#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
448
449#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
450
451#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
452
453#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
454
455#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
456
457#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
458
459#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
460
461#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
462
463#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
464
465#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
466
467#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
468
469#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
470
471#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
472
473#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
474
475#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
476
477#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
478
479#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
480
481
482#endif /* DSI_PHY_7NM_XML */