Loading...
Note: File does not exist in v4.6.
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <drm/drm_atomic_helper.h>
25
26#include "display/intel_dp.h"
27
28#include "i915_drv.h"
29#include "intel_atomic.h"
30#include "intel_de.h"
31#include "intel_display_types.h"
32#include "intel_dp_aux.h"
33#include "intel_hdmi.h"
34#include "intel_psr.h"
35#include "intel_sprite.h"
36#include "skl_universal_plane.h"
37
38/**
39 * DOC: Panel Self Refresh (PSR/SRD)
40 *
41 * Since Haswell Display controller supports Panel Self-Refresh on display
42 * panels witch have a remote frame buffer (RFB) implemented according to PSR
43 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
44 * when system is idle but display is on as it eliminates display refresh
45 * request to DDR memory completely as long as the frame buffer for that
46 * display is unchanged.
47 *
48 * Panel Self Refresh must be supported by both Hardware (source) and
49 * Panel (sink).
50 *
51 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
52 * to power down the link and memory controller. For DSI panels the same idea
53 * is called "manual mode".
54 *
55 * The implementation uses the hardware-based PSR support which automatically
56 * enters/exits self-refresh mode. The hardware takes care of sending the
57 * required DP aux message and could even retrain the link (that part isn't
58 * enabled yet though). The hardware also keeps track of any frontbuffer
59 * changes to know when to exit self-refresh mode again. Unfortunately that
60 * part doesn't work too well, hence why the i915 PSR support uses the
61 * software frontbuffer tracking to make sure it doesn't miss a screen
62 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
63 * get called by the frontbuffer tracking code. Note that because of locking
64 * issues the self-refresh re-enable code is done from a work queue, which
65 * must be correctly synchronized/cancelled when shutting down the pipe."
66 *
67 * DC3CO (DC3 clock off)
68 *
69 * On top of PSR2, GEN12 adds a intermediate power savings state that turns
70 * clock off automatically during PSR2 idle state.
71 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
72 * entry/exit allows the HW to enter a low-power state even when page flipping
73 * periodically (for instance a 30fps video playback scenario).
74 *
75 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
76 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
77 * frames, if no other flip occurs and the function above is executed, DC3CO is
78 * disabled and PSR2 is configured to enter deep sleep, resetting again in case
79 * of another flip.
80 * Front buffer modifications do not trigger DC3CO activation on purpose as it
81 * would bring a lot of complexity and most of the moderns systems will only
82 * use page flips.
83 */
84
85static bool psr_global_enabled(struct intel_dp *intel_dp)
86{
87 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
88
89 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
90 case I915_PSR_DEBUG_DEFAULT:
91 return i915->params.enable_psr;
92 case I915_PSR_DEBUG_DISABLE:
93 return false;
94 default:
95 return true;
96 }
97}
98
99static bool psr2_global_enabled(struct intel_dp *intel_dp)
100{
101 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
102 case I915_PSR_DEBUG_DISABLE:
103 case I915_PSR_DEBUG_FORCE_PSR1:
104 return false;
105 default:
106 return true;
107 }
108}
109
110static void psr_irq_control(struct intel_dp *intel_dp)
111{
112 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
113 enum transcoder trans_shift;
114 i915_reg_t imr_reg;
115 u32 mask, val;
116
117 /*
118 * gen12+ has registers relative to transcoder and one per transcoder
119 * using the same bit definition: handle it as TRANSCODER_EDP to force
120 * 0 shift in bit definition
121 */
122 if (DISPLAY_VER(dev_priv) >= 12) {
123 trans_shift = 0;
124 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
125 } else {
126 trans_shift = intel_dp->psr.transcoder;
127 imr_reg = EDP_PSR_IMR;
128 }
129
130 mask = EDP_PSR_ERROR(trans_shift);
131 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
132 mask |= EDP_PSR_POST_EXIT(trans_shift) |
133 EDP_PSR_PRE_ENTRY(trans_shift);
134
135 /* Warning: it is masking/setting reserved bits too */
136 val = intel_de_read(dev_priv, imr_reg);
137 val &= ~EDP_PSR_TRANS_MASK(trans_shift);
138 val |= ~mask;
139 intel_de_write(dev_priv, imr_reg, val);
140}
141
142static void psr_event_print(struct drm_i915_private *i915,
143 u32 val, bool psr2_enabled)
144{
145 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
146 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
147 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
148 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
149 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
150 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
151 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
152 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
153 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
154 if (val & PSR_EVENT_GRAPHICS_RESET)
155 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
156 if (val & PSR_EVENT_PCH_INTERRUPT)
157 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
158 if (val & PSR_EVENT_MEMORY_UP)
159 drm_dbg_kms(&i915->drm, "\tMemory up\n");
160 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
161 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
162 if (val & PSR_EVENT_WD_TIMER_EXPIRE)
163 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
164 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
165 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
166 if (val & PSR_EVENT_REGISTER_UPDATE)
167 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
168 if (val & PSR_EVENT_HDCP_ENABLE)
169 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
170 if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
171 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
172 if (val & PSR_EVENT_VBI_ENABLE)
173 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
174 if (val & PSR_EVENT_LPSP_MODE_EXIT)
175 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
176 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
177 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
178}
179
180void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
181{
182 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
183 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
184 ktime_t time_ns = ktime_get();
185 enum transcoder trans_shift;
186 i915_reg_t imr_reg;
187
188 if (DISPLAY_VER(dev_priv) >= 12) {
189 trans_shift = 0;
190 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
191 } else {
192 trans_shift = intel_dp->psr.transcoder;
193 imr_reg = EDP_PSR_IMR;
194 }
195
196 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
197 intel_dp->psr.last_entry_attempt = time_ns;
198 drm_dbg_kms(&dev_priv->drm,
199 "[transcoder %s] PSR entry attempt in 2 vblanks\n",
200 transcoder_name(cpu_transcoder));
201 }
202
203 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
204 intel_dp->psr.last_exit = time_ns;
205 drm_dbg_kms(&dev_priv->drm,
206 "[transcoder %s] PSR exit completed\n",
207 transcoder_name(cpu_transcoder));
208
209 if (DISPLAY_VER(dev_priv) >= 9) {
210 u32 val = intel_de_read(dev_priv,
211 PSR_EVENT(cpu_transcoder));
212 bool psr2_enabled = intel_dp->psr.psr2_enabled;
213
214 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
215 val);
216 psr_event_print(dev_priv, val, psr2_enabled);
217 }
218 }
219
220 if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
221 u32 val;
222
223 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
224 transcoder_name(cpu_transcoder));
225
226 intel_dp->psr.irq_aux_error = true;
227
228 /*
229 * If this interruption is not masked it will keep
230 * interrupting so fast that it prevents the scheduled
231 * work to run.
232 * Also after a PSR error, we don't want to arm PSR
233 * again so we don't care about unmask the interruption
234 * or unset irq_aux_error.
235 */
236 val = intel_de_read(dev_priv, imr_reg);
237 val |= EDP_PSR_ERROR(trans_shift);
238 intel_de_write(dev_priv, imr_reg, val);
239
240 schedule_work(&intel_dp->psr.work);
241 }
242}
243
244static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
245{
246 u8 alpm_caps = 0;
247
248 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
249 &alpm_caps) != 1)
250 return false;
251 return alpm_caps & DP_ALPM_CAP;
252}
253
254static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
255{
256 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
257 u8 val = 8; /* assume the worst if we can't read the value */
258
259 if (drm_dp_dpcd_readb(&intel_dp->aux,
260 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
261 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
262 else
263 drm_dbg_kms(&i915->drm,
264 "Unable to get sink synchronization latency, assuming 8 frames\n");
265 return val;
266}
267
268static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
269{
270 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
271 u16 val;
272 ssize_t r;
273
274 /*
275 * Returning the default X granularity if granularity not required or
276 * if DPCD read fails
277 */
278 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
279 return 4;
280
281 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
282 if (r != 2)
283 drm_dbg_kms(&i915->drm,
284 "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
285
286 /*
287 * Spec says that if the value read is 0 the default granularity should
288 * be used instead.
289 */
290 if (r != 2 || val == 0)
291 val = 4;
292
293 return val;
294}
295
296void intel_psr_init_dpcd(struct intel_dp *intel_dp)
297{
298 struct drm_i915_private *dev_priv =
299 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
300
301 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
302 sizeof(intel_dp->psr_dpcd));
303
304 if (!intel_dp->psr_dpcd[0])
305 return;
306 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
307 intel_dp->psr_dpcd[0]);
308
309 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
310 drm_dbg_kms(&dev_priv->drm,
311 "PSR support not currently available for this panel\n");
312 return;
313 }
314
315 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
316 drm_dbg_kms(&dev_priv->drm,
317 "Panel lacks power state control, PSR cannot be enabled\n");
318 return;
319 }
320
321 intel_dp->psr.sink_support = true;
322 intel_dp->psr.sink_sync_latency =
323 intel_dp_get_sink_sync_latency(intel_dp);
324
325 if (DISPLAY_VER(dev_priv) >= 9 &&
326 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
327 bool y_req = intel_dp->psr_dpcd[1] &
328 DP_PSR2_SU_Y_COORDINATE_REQUIRED;
329 bool alpm = intel_dp_get_alpm_status(intel_dp);
330
331 /*
332 * All panels that supports PSR version 03h (PSR2 +
333 * Y-coordinate) can handle Y-coordinates in VSC but we are
334 * only sure that it is going to be used when required by the
335 * panel. This way panel is capable to do selective update
336 * without a aux frame sync.
337 *
338 * To support PSR version 02h and PSR version 03h without
339 * Y-coordinate requirement panels we would need to enable
340 * GTC first.
341 */
342 intel_dp->psr.sink_psr2_support = y_req && alpm;
343 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
344 intel_dp->psr.sink_psr2_support ? "" : "not ");
345
346 if (intel_dp->psr.sink_psr2_support) {
347 intel_dp->psr.colorimetry_support =
348 intel_dp_get_colorimetry_status(intel_dp);
349 intel_dp->psr.su_x_granularity =
350 intel_dp_get_su_x_granulartiy(intel_dp);
351 }
352 }
353}
354
355static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
356{
357 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
358 u32 aux_clock_divider, aux_ctl;
359 int i;
360 static const u8 aux_msg[] = {
361 [0] = DP_AUX_NATIVE_WRITE << 4,
362 [1] = DP_SET_POWER >> 8,
363 [2] = DP_SET_POWER & 0xff,
364 [3] = 1 - 1,
365 [4] = DP_SET_POWER_D0,
366 };
367 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
368 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
369 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
370 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
371
372 BUILD_BUG_ON(sizeof(aux_msg) > 20);
373 for (i = 0; i < sizeof(aux_msg); i += 4)
374 intel_de_write(dev_priv,
375 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
376 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
377
378 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
379
380 /* Start with bits set for DDI_AUX_CTL register */
381 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
382 aux_clock_divider);
383
384 /* Select only valid bits for SRD_AUX_CTL */
385 aux_ctl &= psr_aux_mask;
386 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
387 aux_ctl);
388}
389
390static void intel_psr_enable_sink(struct intel_dp *intel_dp)
391{
392 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
393 u8 dpcd_val = DP_PSR_ENABLE;
394
395 /* Enable ALPM at sink for psr2 */
396 if (intel_dp->psr.psr2_enabled) {
397 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
398 DP_ALPM_ENABLE |
399 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
400
401 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
402 } else {
403 if (intel_dp->psr.link_standby)
404 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
405
406 if (DISPLAY_VER(dev_priv) >= 8)
407 dpcd_val |= DP_PSR_CRC_VERIFICATION;
408 }
409
410 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
411
412 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
413}
414
415static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
416{
417 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
418 u32 val = 0;
419
420 if (DISPLAY_VER(dev_priv) >= 11)
421 val |= EDP_PSR_TP4_TIME_0US;
422
423 if (dev_priv->params.psr_safest_params) {
424 val |= EDP_PSR_TP1_TIME_2500us;
425 val |= EDP_PSR_TP2_TP3_TIME_2500us;
426 goto check_tp3_sel;
427 }
428
429 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
430 val |= EDP_PSR_TP1_TIME_0us;
431 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
432 val |= EDP_PSR_TP1_TIME_100us;
433 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
434 val |= EDP_PSR_TP1_TIME_500us;
435 else
436 val |= EDP_PSR_TP1_TIME_2500us;
437
438 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
439 val |= EDP_PSR_TP2_TP3_TIME_0us;
440 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
441 val |= EDP_PSR_TP2_TP3_TIME_100us;
442 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
443 val |= EDP_PSR_TP2_TP3_TIME_500us;
444 else
445 val |= EDP_PSR_TP2_TP3_TIME_2500us;
446
447check_tp3_sel:
448 if (intel_dp_source_supports_hbr2(intel_dp) &&
449 drm_dp_tps3_supported(intel_dp->dpcd))
450 val |= EDP_PSR_TP1_TP3_SEL;
451 else
452 val |= EDP_PSR_TP1_TP2_SEL;
453
454 return val;
455}
456
457static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
458{
459 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
460 int idle_frames;
461
462 /* Let's use 6 as the minimum to cover all known cases including the
463 * off-by-one issue that HW has in some cases.
464 */
465 idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
466 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
467
468 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
469 idle_frames = 0xf;
470
471 return idle_frames;
472}
473
474static void hsw_activate_psr1(struct intel_dp *intel_dp)
475{
476 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
477 u32 max_sleep_time = 0x1f;
478 u32 val = EDP_PSR_ENABLE;
479
480 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
481
482 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
483 if (IS_HASWELL(dev_priv))
484 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
485
486 if (intel_dp->psr.link_standby)
487 val |= EDP_PSR_LINK_STANDBY;
488
489 val |= intel_psr1_get_tp_time(intel_dp);
490
491 if (DISPLAY_VER(dev_priv) >= 8)
492 val |= EDP_PSR_CRC_ENABLE;
493
494 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
495 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
496 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
497}
498
499static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
500{
501 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
502 u32 val = 0;
503
504 if (dev_priv->params.psr_safest_params)
505 return EDP_PSR2_TP2_TIME_2500us;
506
507 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
508 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
509 val |= EDP_PSR2_TP2_TIME_50us;
510 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
511 val |= EDP_PSR2_TP2_TIME_100us;
512 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
513 val |= EDP_PSR2_TP2_TIME_500us;
514 else
515 val |= EDP_PSR2_TP2_TIME_2500us;
516
517 return val;
518}
519
520static void hsw_activate_psr2(struct intel_dp *intel_dp)
521{
522 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
523 u32 val;
524
525 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
526
527 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
528 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
529 val |= EDP_Y_COORDINATE_ENABLE;
530
531 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
532 val |= intel_psr2_get_tp_time(intel_dp);
533
534 if (DISPLAY_VER(dev_priv) >= 12) {
535 /*
536 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
537 * values from BSpec. In order to setting an optimal power
538 * consumption, lower than 4k resoluition mode needs to decrese
539 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
540 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
541 */
542 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
543 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
544 val |= TGL_EDP_PSR2_FAST_WAKE(7);
545 } else if (DISPLAY_VER(dev_priv) >= 9) {
546 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
547 val |= EDP_PSR2_FAST_WAKE(7);
548 }
549
550 if (intel_dp->psr.psr2_sel_fetch_enabled) {
551 /* WA 1408330847 */
552 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
553 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
554 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
555 DIS_RAM_BYPASS_PSR2_MAN_TRACK,
556 DIS_RAM_BYPASS_PSR2_MAN_TRACK);
557
558 intel_de_write(dev_priv,
559 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
560 PSR2_MAN_TRK_CTL_ENABLE);
561 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
562 intel_de_write(dev_priv,
563 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
564 }
565
566 /*
567 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
568 * recommending keep this bit unset while PSR2 is enabled.
569 */
570 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
571
572 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
573}
574
575static bool
576transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
577{
578 if (DISPLAY_VER(dev_priv) < 9)
579 return false;
580 else if (DISPLAY_VER(dev_priv) >= 12)
581 return trans == TRANSCODER_A;
582 else
583 return trans == TRANSCODER_EDP;
584}
585
586static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
587{
588 if (!cstate || !cstate->hw.active)
589 return 0;
590
591 return DIV_ROUND_UP(1000 * 1000,
592 drm_mode_vrefresh(&cstate->hw.adjusted_mode));
593}
594
595static void psr2_program_idle_frames(struct intel_dp *intel_dp,
596 u32 idle_frames)
597{
598 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
599 u32 val;
600
601 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
602 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
603 val &= ~EDP_PSR2_IDLE_FRAME_MASK;
604 val |= idle_frames;
605 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
606}
607
608static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
609{
610 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
611
612 psr2_program_idle_frames(intel_dp, 0);
613 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
614}
615
616static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
617{
618 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
619
620 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
621 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
622}
623
624static void tgl_dc3co_disable_work(struct work_struct *work)
625{
626 struct intel_dp *intel_dp =
627 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
628
629 mutex_lock(&intel_dp->psr.lock);
630 /* If delayed work is pending, it is not idle */
631 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
632 goto unlock;
633
634 tgl_psr2_disable_dc3co(intel_dp);
635unlock:
636 mutex_unlock(&intel_dp->psr.lock);
637}
638
639static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
640{
641 if (!intel_dp->psr.dc3co_exitline)
642 return;
643
644 cancel_delayed_work(&intel_dp->psr.dc3co_work);
645 /* Before PSR2 exit disallow dc3co*/
646 tgl_psr2_disable_dc3co(intel_dp);
647}
648
649static bool
650dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
651 struct intel_crtc_state *crtc_state)
652{
653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
654 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
655 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
656 enum port port = dig_port->base.port;
657
658 if (IS_ALDERLAKE_P(dev_priv))
659 return pipe <= PIPE_B && port <= PORT_B;
660 else
661 return pipe == PIPE_A && port == PORT_A;
662}
663
664static void
665tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
666 struct intel_crtc_state *crtc_state)
667{
668 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
669 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
670 u32 exit_scanlines;
671
672 /*
673 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
674 * disable DC3CO until the changed dc3co activating/deactivating sequence
675 * is applied. B.Specs:49196
676 */
677 return;
678
679 /*
680 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
681 * TODO: when the issue is addressed, this restriction should be removed.
682 */
683 if (crtc_state->enable_psr2_sel_fetch)
684 return;
685
686 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
687 return;
688
689 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
690 return;
691
692 /*
693 * DC3CO Exit time 200us B.Spec 49196
694 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
695 */
696 exit_scanlines =
697 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
698
699 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
700 return;
701
702 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
703}
704
705static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
706 struct intel_crtc_state *crtc_state)
707{
708 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
709 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
710 struct intel_plane_state *plane_state;
711 struct intel_plane *plane;
712 int i;
713
714 if (!dev_priv->params.enable_psr2_sel_fetch &&
715 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
716 drm_dbg_kms(&dev_priv->drm,
717 "PSR2 sel fetch not enabled, disabled by parameter\n");
718 return false;
719 }
720
721 if (crtc_state->uapi.async_flip) {
722 drm_dbg_kms(&dev_priv->drm,
723 "PSR2 sel fetch not enabled, async flip enabled\n");
724 return false;
725 }
726
727 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
728 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) {
729 drm_dbg_kms(&dev_priv->drm,
730 "PSR2 sel fetch not enabled, plane rotated\n");
731 return false;
732 }
733 }
734
735 /* Wa_14010254185 Wa_14010103792 */
736 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
737 drm_dbg_kms(&dev_priv->drm,
738 "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
739 return false;
740 }
741
742 return crtc_state->enable_psr2_sel_fetch = true;
743}
744
745static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
746 struct intel_crtc_state *crtc_state)
747{
748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
749 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
750 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
751 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
752
753 if (!intel_dp->psr.sink_psr2_support)
754 return false;
755
756 /* JSL and EHL only supports eDP 1.3 */
757 if (IS_JSL_EHL(dev_priv)) {
758 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
759 return false;
760 }
761
762 /* Wa_16011181250 */
763 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) {
764 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
765 return false;
766 }
767
768 /*
769 * We are missing the implementation of some workarounds to enabled PSR2
770 * in Alderlake_P, until ready PSR2 should be kept disabled.
771 */
772 if (IS_ALDERLAKE_P(dev_priv)) {
773 drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n");
774 return false;
775 }
776
777 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
778 drm_dbg_kms(&dev_priv->drm,
779 "PSR2 not supported in transcoder %s\n",
780 transcoder_name(crtc_state->cpu_transcoder));
781 return false;
782 }
783
784 if (!psr2_global_enabled(intel_dp)) {
785 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
786 return false;
787 }
788
789 /*
790 * DSC and PSR2 cannot be enabled simultaneously. If a requested
791 * resolution requires DSC to be enabled, priority is given to DSC
792 * over PSR2.
793 */
794 if (crtc_state->dsc.compression_enable) {
795 drm_dbg_kms(&dev_priv->drm,
796 "PSR2 cannot be enabled since DSC is enabled\n");
797 return false;
798 }
799
800 if (crtc_state->crc_enabled) {
801 drm_dbg_kms(&dev_priv->drm,
802 "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
803 return false;
804 }
805
806 if (DISPLAY_VER(dev_priv) >= 12) {
807 psr_max_h = 5120;
808 psr_max_v = 3200;
809 max_bpp = 30;
810 } else if (DISPLAY_VER(dev_priv) >= 10) {
811 psr_max_h = 4096;
812 psr_max_v = 2304;
813 max_bpp = 24;
814 } else if (DISPLAY_VER(dev_priv) == 9) {
815 psr_max_h = 3640;
816 psr_max_v = 2304;
817 max_bpp = 24;
818 }
819
820 if (crtc_state->pipe_bpp > max_bpp) {
821 drm_dbg_kms(&dev_priv->drm,
822 "PSR2 not enabled, pipe bpp %d > max supported %d\n",
823 crtc_state->pipe_bpp, max_bpp);
824 return false;
825 }
826
827 /*
828 * HW sends SU blocks of size four scan lines, which means the starting
829 * X coordinate and Y granularity requirements will always be met. We
830 * only need to validate the SU block width is a multiple of
831 * x granularity.
832 */
833 if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
834 drm_dbg_kms(&dev_priv->drm,
835 "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
836 crtc_hdisplay, intel_dp->psr.su_x_granularity);
837 return false;
838 }
839
840 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
841 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
842 !HAS_PSR_HW_TRACKING(dev_priv)) {
843 drm_dbg_kms(&dev_priv->drm,
844 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
845 return false;
846 }
847 }
848
849 /* Wa_2209313811 */
850 if (!crtc_state->enable_psr2_sel_fetch &&
851 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
852 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
853 return false;
854 }
855
856 if (!crtc_state->enable_psr2_sel_fetch &&
857 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
858 drm_dbg_kms(&dev_priv->drm,
859 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
860 crtc_hdisplay, crtc_vdisplay,
861 psr_max_h, psr_max_v);
862 return false;
863 }
864
865 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
866 return true;
867}
868
869void intel_psr_compute_config(struct intel_dp *intel_dp,
870 struct intel_crtc_state *crtc_state)
871{
872 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
873 const struct drm_display_mode *adjusted_mode =
874 &crtc_state->hw.adjusted_mode;
875 int psr_setup_time;
876
877 /*
878 * Current PSR panels dont work reliably with VRR enabled
879 * So if VRR is enabled, do not enable PSR.
880 */
881 if (crtc_state->vrr.enable)
882 return;
883
884 if (!CAN_PSR(intel_dp))
885 return;
886
887 if (!psr_global_enabled(intel_dp)) {
888 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
889 return;
890 }
891
892 if (intel_dp->psr.sink_not_reliable) {
893 drm_dbg_kms(&dev_priv->drm,
894 "PSR sink implementation is not reliable\n");
895 return;
896 }
897
898 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
899 drm_dbg_kms(&dev_priv->drm,
900 "PSR condition failed: Interlaced mode enabled\n");
901 return;
902 }
903
904 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
905 if (psr_setup_time < 0) {
906 drm_dbg_kms(&dev_priv->drm,
907 "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
908 intel_dp->psr_dpcd[1]);
909 return;
910 }
911
912 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
913 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
914 drm_dbg_kms(&dev_priv->drm,
915 "PSR condition failed: PSR setup time (%d us) too long\n",
916 psr_setup_time);
917 return;
918 }
919
920 crtc_state->has_psr = true;
921 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
922 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
923}
924
925void intel_psr_get_config(struct intel_encoder *encoder,
926 struct intel_crtc_state *pipe_config)
927{
928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
929 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
930 struct intel_dp *intel_dp;
931 u32 val;
932
933 if (!dig_port)
934 return;
935
936 intel_dp = &dig_port->dp;
937 if (!CAN_PSR(intel_dp))
938 return;
939
940 mutex_lock(&intel_dp->psr.lock);
941 if (!intel_dp->psr.enabled)
942 goto unlock;
943
944 /*
945 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
946 * enabled/disabled because of frontbuffer tracking and others.
947 */
948 pipe_config->has_psr = true;
949 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
950 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
951
952 if (!intel_dp->psr.psr2_enabled)
953 goto unlock;
954
955 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
956 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
957 if (val & PSR2_MAN_TRK_CTL_ENABLE)
958 pipe_config->enable_psr2_sel_fetch = true;
959 }
960
961 if (DISPLAY_VER(dev_priv) >= 12) {
962 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
963 val &= EXITLINE_MASK;
964 pipe_config->dc3co_exitline = val;
965 }
966unlock:
967 mutex_unlock(&intel_dp->psr.lock);
968}
969
970static void intel_psr_activate(struct intel_dp *intel_dp)
971{
972 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
973 enum transcoder transcoder = intel_dp->psr.transcoder;
974
975 if (transcoder_has_psr2(dev_priv, transcoder))
976 drm_WARN_ON(&dev_priv->drm,
977 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
978
979 drm_WARN_ON(&dev_priv->drm,
980 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
981 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
982 lockdep_assert_held(&intel_dp->psr.lock);
983
984 /* psr1 and psr2 are mutually exclusive.*/
985 if (intel_dp->psr.psr2_enabled)
986 hsw_activate_psr2(intel_dp);
987 else
988 hsw_activate_psr1(intel_dp);
989
990 intel_dp->psr.active = true;
991}
992
993static void intel_psr_enable_source(struct intel_dp *intel_dp)
994{
995 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
996 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
997 u32 mask;
998
999 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
1000 * use hardcoded values PSR AUX transactions
1001 */
1002 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1003 hsw_psr_setup_aux(intel_dp);
1004
1005 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
1006 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
1007 u32 chicken = intel_de_read(dev_priv, reg);
1008
1009 chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
1010 PSR2_ADD_VERTICAL_LINE_COUNT;
1011 intel_de_write(dev_priv, reg, chicken);
1012 }
1013
1014 /*
1015 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
1016 * mask LPSP to avoid dependency on other drivers that might block
1017 * runtime_pm besides preventing other hw tracking issues now we
1018 * can rely on frontbuffer tracking.
1019 */
1020 mask = EDP_PSR_DEBUG_MASK_MEMUP |
1021 EDP_PSR_DEBUG_MASK_HPD |
1022 EDP_PSR_DEBUG_MASK_LPSP |
1023 EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1024
1025 if (DISPLAY_VER(dev_priv) < 11)
1026 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1027
1028 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1029 mask);
1030
1031 psr_irq_control(intel_dp);
1032
1033 if (intel_dp->psr.dc3co_exitline) {
1034 u32 val;
1035
1036 /*
1037 * TODO: if future platforms supports DC3CO in more than one
1038 * transcoder, EXITLINE will need to be unset when disabling PSR
1039 */
1040 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1041 val &= ~EXITLINE_MASK;
1042 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1043 val |= EXITLINE_ENABLE;
1044 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1045 }
1046
1047 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1048 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1049 intel_dp->psr.psr2_sel_fetch_enabled ?
1050 IGNORE_PSR2_HW_TRACKING : 0);
1051}
1052
1053static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1054{
1055 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1056 u32 val;
1057
1058 /*
1059 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1060 * will still keep the error set even after the reset done in the
1061 * irq_preinstall and irq_uninstall hooks.
1062 * And enabling in this situation cause the screen to freeze in the
1063 * first time that PSR HW tries to activate so lets keep PSR disabled
1064 * to avoid any rendering problems.
1065 */
1066 if (DISPLAY_VER(dev_priv) >= 12) {
1067 val = intel_de_read(dev_priv,
1068 TRANS_PSR_IIR(intel_dp->psr.transcoder));
1069 val &= EDP_PSR_ERROR(0);
1070 } else {
1071 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1072 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
1073 }
1074 if (val) {
1075 intel_dp->psr.sink_not_reliable = true;
1076 drm_dbg_kms(&dev_priv->drm,
1077 "PSR interruption error set, not enabling PSR\n");
1078 return false;
1079 }
1080
1081 return true;
1082}
1083
1084static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1085 const struct intel_crtc_state *crtc_state,
1086 const struct drm_connector_state *conn_state)
1087{
1088 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1089 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1090 struct intel_encoder *encoder = &dig_port->base;
1091 u32 val;
1092
1093 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1094
1095 intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1096 intel_dp->psr.busy_frontbuffer_bits = 0;
1097 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1098 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1099 /* DC5/DC6 requires at least 6 idle frames */
1100 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1101 intel_dp->psr.dc3co_exit_delay = val;
1102 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1103 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1104
1105 if (!psr_interrupt_error_check(intel_dp))
1106 return;
1107
1108 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1109 intel_dp->psr.psr2_enabled ? "2" : "1");
1110 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1111 &intel_dp->psr.vsc);
1112 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
1113 intel_psr_enable_sink(intel_dp);
1114 intel_psr_enable_source(intel_dp);
1115 intel_dp->psr.enabled = true;
1116 intel_dp->psr.paused = false;
1117
1118 intel_psr_activate(intel_dp);
1119}
1120
1121/**
1122 * intel_psr_enable - Enable PSR
1123 * @intel_dp: Intel DP
1124 * @crtc_state: new CRTC state
1125 * @conn_state: new CONNECTOR state
1126 *
1127 * This function can only be called after the pipe is fully trained and enabled.
1128 */
1129void intel_psr_enable(struct intel_dp *intel_dp,
1130 const struct intel_crtc_state *crtc_state,
1131 const struct drm_connector_state *conn_state)
1132{
1133 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1134
1135 if (!CAN_PSR(intel_dp))
1136 return;
1137
1138 if (!crtc_state->has_psr)
1139 return;
1140
1141 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
1142
1143 mutex_lock(&intel_dp->psr.lock);
1144 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1145 mutex_unlock(&intel_dp->psr.lock);
1146}
1147
1148static void intel_psr_exit(struct intel_dp *intel_dp)
1149{
1150 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1151 u32 val;
1152
1153 if (!intel_dp->psr.active) {
1154 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1155 val = intel_de_read(dev_priv,
1156 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1157 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1158 }
1159
1160 val = intel_de_read(dev_priv,
1161 EDP_PSR_CTL(intel_dp->psr.transcoder));
1162 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1163
1164 return;
1165 }
1166
1167 if (intel_dp->psr.psr2_enabled) {
1168 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1169 val = intel_de_read(dev_priv,
1170 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1171 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1172 val &= ~EDP_PSR2_ENABLE;
1173 intel_de_write(dev_priv,
1174 EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1175 } else {
1176 val = intel_de_read(dev_priv,
1177 EDP_PSR_CTL(intel_dp->psr.transcoder));
1178 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1179 val &= ~EDP_PSR_ENABLE;
1180 intel_de_write(dev_priv,
1181 EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1182 }
1183 intel_dp->psr.active = false;
1184}
1185
1186static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1187{
1188 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1189 i915_reg_t psr_status;
1190 u32 psr_status_mask;
1191
1192 if (intel_dp->psr.psr2_enabled) {
1193 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1194 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1195 } else {
1196 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1197 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1198 }
1199
1200 /* Wait till PSR is idle */
1201 if (intel_de_wait_for_clear(dev_priv, psr_status,
1202 psr_status_mask, 2000))
1203 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1204}
1205
1206static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1207{
1208 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1209
1210 lockdep_assert_held(&intel_dp->psr.lock);
1211
1212 if (!intel_dp->psr.enabled)
1213 return;
1214
1215 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1216 intel_dp->psr.psr2_enabled ? "2" : "1");
1217
1218 intel_psr_exit(intel_dp);
1219 intel_psr_wait_exit_locked(intel_dp);
1220
1221 /* WA 1408330847 */
1222 if (intel_dp->psr.psr2_sel_fetch_enabled &&
1223 (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
1224 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
1225 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1226 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1227
1228 /* Disable PSR on Sink */
1229 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1230
1231 if (intel_dp->psr.psr2_enabled)
1232 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1233
1234 intel_dp->psr.enabled = false;
1235}
1236
1237/**
1238 * intel_psr_disable - Disable PSR
1239 * @intel_dp: Intel DP
1240 * @old_crtc_state: old CRTC state
1241 *
1242 * This function needs to be called before disabling pipe.
1243 */
1244void intel_psr_disable(struct intel_dp *intel_dp,
1245 const struct intel_crtc_state *old_crtc_state)
1246{
1247 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1248
1249 if (!old_crtc_state->has_psr)
1250 return;
1251
1252 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1253 return;
1254
1255 mutex_lock(&intel_dp->psr.lock);
1256
1257 intel_psr_disable_locked(intel_dp);
1258
1259 mutex_unlock(&intel_dp->psr.lock);
1260 cancel_work_sync(&intel_dp->psr.work);
1261 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1262}
1263
1264/**
1265 * intel_psr_pause - Pause PSR
1266 * @intel_dp: Intel DP
1267 *
1268 * This function need to be called after enabling psr.
1269 */
1270void intel_psr_pause(struct intel_dp *intel_dp)
1271{
1272 struct intel_psr *psr = &intel_dp->psr;
1273
1274 if (!CAN_PSR(intel_dp))
1275 return;
1276
1277 mutex_lock(&psr->lock);
1278
1279 if (!psr->enabled) {
1280 mutex_unlock(&psr->lock);
1281 return;
1282 }
1283
1284 intel_psr_exit(intel_dp);
1285 intel_psr_wait_exit_locked(intel_dp);
1286 psr->paused = true;
1287
1288 mutex_unlock(&psr->lock);
1289
1290 cancel_work_sync(&psr->work);
1291 cancel_delayed_work_sync(&psr->dc3co_work);
1292}
1293
1294/**
1295 * intel_psr_resume - Resume PSR
1296 * @intel_dp: Intel DP
1297 *
1298 * This function need to be called after pausing psr.
1299 */
1300void intel_psr_resume(struct intel_dp *intel_dp)
1301{
1302 struct intel_psr *psr = &intel_dp->psr;
1303
1304 if (!CAN_PSR(intel_dp))
1305 return;
1306
1307 mutex_lock(&psr->lock);
1308
1309 if (!psr->paused)
1310 goto unlock;
1311
1312 psr->paused = false;
1313 intel_psr_activate(intel_dp);
1314
1315unlock:
1316 mutex_unlock(&psr->lock);
1317}
1318
1319static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1320{
1321 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1322
1323 if (DISPLAY_VER(dev_priv) >= 9)
1324 /*
1325 * Display WA #0884: skl+
1326 * This documented WA for bxt can be safely applied
1327 * broadly so we can force HW tracking to exit PSR
1328 * instead of disabling and re-enabling.
1329 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1330 * but it makes more sense write to the current active
1331 * pipe.
1332 */
1333 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1334 else
1335 /*
1336 * A write to CURSURFLIVE do not cause HW tracking to exit PSR
1337 * on older gens so doing the manual exit instead.
1338 */
1339 intel_psr_exit(intel_dp);
1340}
1341
1342void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1343 const struct intel_crtc_state *crtc_state,
1344 const struct intel_plane_state *plane_state,
1345 int color_plane)
1346{
1347 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1348 enum pipe pipe = plane->pipe;
1349 const struct drm_rect *clip;
1350 u32 val, offset;
1351 int ret, x, y;
1352
1353 if (!crtc_state->enable_psr2_sel_fetch)
1354 return;
1355
1356 val = plane_state ? plane_state->ctl : 0;
1357 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
1358 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
1359 if (!val || plane->id == PLANE_CURSOR)
1360 return;
1361
1362 clip = &plane_state->psr2_sel_fetch_area;
1363
1364 val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1365 val |= plane_state->uapi.dst.x1;
1366 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1367
1368 /* TODO: consider auxiliary surfaces */
1369 x = plane_state->uapi.src.x1 >> 16;
1370 y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
1371 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1372 if (ret)
1373 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n",
1374 ret);
1375 val = y << 16 | x;
1376 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1377 val);
1378
1379 /* Sizes are 0 based */
1380 val = (drm_rect_height(clip) - 1) << 16;
1381 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1382 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1383}
1384
1385void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1386{
1387 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1388
1389 if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
1390 !crtc_state->enable_psr2_sel_fetch)
1391 return;
1392
1393 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1394 crtc_state->psr2_man_track_ctl);
1395}
1396
1397static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1398 struct drm_rect *clip, bool full_update)
1399{
1400 u32 val = PSR2_MAN_TRK_CTL_ENABLE;
1401
1402 if (full_update) {
1403 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1404 goto exit;
1405 }
1406
1407 if (clip->y1 == -1)
1408 goto exit;
1409
1410 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1411
1412 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1413 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1414 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1415exit:
1416 crtc_state->psr2_man_track_ctl = val;
1417}
1418
1419static void clip_area_update(struct drm_rect *overlap_damage_area,
1420 struct drm_rect *damage_area)
1421{
1422 if (overlap_damage_area->y1 == -1) {
1423 overlap_damage_area->y1 = damage_area->y1;
1424 overlap_damage_area->y2 = damage_area->y2;
1425 return;
1426 }
1427
1428 if (damage_area->y1 < overlap_damage_area->y1)
1429 overlap_damage_area->y1 = damage_area->y1;
1430
1431 if (damage_area->y2 > overlap_damage_area->y2)
1432 overlap_damage_area->y2 = damage_area->y2;
1433}
1434
1435int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1436 struct intel_crtc *crtc)
1437{
1438 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1439 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1440 struct intel_plane_state *new_plane_state, *old_plane_state;
1441 struct intel_plane *plane;
1442 bool full_update = false;
1443 int i, ret;
1444
1445 if (!crtc_state->enable_psr2_sel_fetch)
1446 return 0;
1447
1448 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1449 if (ret)
1450 return ret;
1451
1452 /*
1453 * Calculate minimal selective fetch area of each plane and calculate
1454 * the pipe damaged area.
1455 * In the next loop the plane selective fetch area will actually be set
1456 * using whole pipe damaged area.
1457 */
1458 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1459 new_plane_state, i) {
1460 struct drm_rect src, damaged_area = { .y1 = -1 };
1461 struct drm_mode_rect *damaged_clips;
1462 u32 num_clips, j;
1463
1464 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1465 continue;
1466
1467 if (!new_plane_state->uapi.visible &&
1468 !old_plane_state->uapi.visible)
1469 continue;
1470
1471 /*
1472 * TODO: Not clear how to handle planes with negative position,
1473 * also planes are not updated if they have a negative X
1474 * position so for now doing a full update in this cases
1475 */
1476 if (new_plane_state->uapi.dst.y1 < 0 ||
1477 new_plane_state->uapi.dst.x1 < 0) {
1478 full_update = true;
1479 break;
1480 }
1481
1482 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
1483
1484 /*
1485 * If visibility or plane moved, mark the whole plane area as
1486 * damaged as it needs to be complete redraw in the new and old
1487 * position.
1488 */
1489 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1490 !drm_rect_equals(&new_plane_state->uapi.dst,
1491 &old_plane_state->uapi.dst)) {
1492 if (old_plane_state->uapi.visible) {
1493 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1494 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1495 clip_area_update(&pipe_clip, &damaged_area);
1496 }
1497
1498 if (new_plane_state->uapi.visible) {
1499 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1500 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1501 clip_area_update(&pipe_clip, &damaged_area);
1502 }
1503 continue;
1504 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
1505 (!num_clips &&
1506 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
1507 /*
1508 * If the plane don't have damaged areas but the
1509 * framebuffer changed or alpha changed, mark the whole
1510 * plane area as damaged.
1511 */
1512 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1513 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1514 clip_area_update(&pipe_clip, &damaged_area);
1515 continue;
1516 }
1517
1518 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
1519 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
1520
1521 for (j = 0; j < num_clips; j++) {
1522 struct drm_rect clip;
1523
1524 clip.x1 = damaged_clips[j].x1;
1525 clip.y1 = damaged_clips[j].y1;
1526 clip.x2 = damaged_clips[j].x2;
1527 clip.y2 = damaged_clips[j].y2;
1528 if (drm_rect_intersect(&clip, &src))
1529 clip_area_update(&damaged_area, &clip);
1530 }
1531
1532 if (damaged_area.y1 == -1)
1533 continue;
1534
1535 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1536 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1537 clip_area_update(&pipe_clip, &damaged_area);
1538 }
1539
1540 if (full_update)
1541 goto skip_sel_fetch_set_loop;
1542
1543 /* It must be aligned to 4 lines */
1544 pipe_clip.y1 -= pipe_clip.y1 % 4;
1545 if (pipe_clip.y2 % 4)
1546 pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
1547
1548 /*
1549 * Now that we have the pipe damaged area check if it intersect with
1550 * every plane, if it does set the plane selective fetch area.
1551 */
1552 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1553 new_plane_state, i) {
1554 struct drm_rect *sel_fetch_area, inter;
1555
1556 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1557 !new_plane_state->uapi.visible)
1558 continue;
1559
1560 inter = pipe_clip;
1561 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1562 continue;
1563
1564 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1565 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1566 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1567 }
1568
1569skip_sel_fetch_set_loop:
1570 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1571 return 0;
1572}
1573
1574/**
1575 * intel_psr_update - Update PSR state
1576 * @intel_dp: Intel DP
1577 * @crtc_state: new CRTC state
1578 * @conn_state: new CONNECTOR state
1579 *
1580 * This functions will update PSR states, disabling, enabling or switching PSR
1581 * version when executing fastsets. For full modeset, intel_psr_disable() and
1582 * intel_psr_enable() should be called instead.
1583 */
1584void intel_psr_update(struct intel_dp *intel_dp,
1585 const struct intel_crtc_state *crtc_state,
1586 const struct drm_connector_state *conn_state)
1587{
1588 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1589 struct intel_psr *psr = &intel_dp->psr;
1590 bool enable, psr2_enable;
1591
1592 if (!CAN_PSR(intel_dp))
1593 return;
1594
1595 mutex_lock(&intel_dp->psr.lock);
1596
1597 enable = crtc_state->has_psr;
1598 psr2_enable = crtc_state->has_psr2;
1599
1600 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled &&
1601 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) {
1602 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1603 if (crtc_state->crc_enabled && psr->enabled)
1604 psr_force_hw_tracking_exit(intel_dp);
1605 else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {
1606 /*
1607 * Activate PSR again after a force exit when enabling
1608 * CRC in older gens
1609 */
1610 if (!intel_dp->psr.active &&
1611 !intel_dp->psr.busy_frontbuffer_bits)
1612 schedule_work(&intel_dp->psr.work);
1613 }
1614
1615 goto unlock;
1616 }
1617
1618 if (psr->enabled)
1619 intel_psr_disable_locked(intel_dp);
1620
1621 if (enable)
1622 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1623
1624unlock:
1625 mutex_unlock(&intel_dp->psr.lock);
1626}
1627
1628/**
1629 * psr_wait_for_idle - wait for PSR1 to idle
1630 * @intel_dp: Intel DP
1631 * @out_value: PSR status in case of failure
1632 *
1633 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
1634 *
1635 */
1636static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
1637{
1638 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1639
1640 /*
1641 * From bspec: Panel Self Refresh (BDW+)
1642 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1643 * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1644 * defensive enough to cover everything.
1645 */
1646 return __intel_wait_for_register(&dev_priv->uncore,
1647 EDP_PSR_STATUS(intel_dp->psr.transcoder),
1648 EDP_PSR_STATUS_STATE_MASK,
1649 EDP_PSR_STATUS_STATE_IDLE, 2, 50,
1650 out_value);
1651}
1652
1653/**
1654 * intel_psr_wait_for_idle - wait for PSR1 to idle
1655 * @new_crtc_state: new CRTC state
1656 *
1657 * This function is expected to be called from pipe_update_start() where it is
1658 * not expected to race with PSR enable or disable.
1659 */
1660void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
1661{
1662 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1663 struct intel_encoder *encoder;
1664
1665 if (!new_crtc_state->has_psr)
1666 return;
1667
1668 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1669 new_crtc_state->uapi.encoder_mask) {
1670 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1671 u32 psr_status;
1672
1673 mutex_lock(&intel_dp->psr.lock);
1674 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
1675 mutex_unlock(&intel_dp->psr.lock);
1676 continue;
1677 }
1678
1679 /* when the PSR1 is enabled */
1680 if (psr_wait_for_idle(intel_dp, &psr_status))
1681 drm_err(&dev_priv->drm,
1682 "PSR idle timed out 0x%x, atomic update may fail\n",
1683 psr_status);
1684 mutex_unlock(&intel_dp->psr.lock);
1685 }
1686}
1687
1688static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
1689{
1690 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1691 i915_reg_t reg;
1692 u32 mask;
1693 int err;
1694
1695 if (!intel_dp->psr.enabled)
1696 return false;
1697
1698 if (intel_dp->psr.psr2_enabled) {
1699 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1700 mask = EDP_PSR2_STATUS_STATE_MASK;
1701 } else {
1702 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1703 mask = EDP_PSR_STATUS_STATE_MASK;
1704 }
1705
1706 mutex_unlock(&intel_dp->psr.lock);
1707
1708 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
1709 if (err)
1710 drm_err(&dev_priv->drm,
1711 "Timed out waiting for PSR Idle for re-enable\n");
1712
1713 /* After the unlocked wait, verify that PSR is still wanted! */
1714 mutex_lock(&intel_dp->psr.lock);
1715 return err == 0 && intel_dp->psr.enabled;
1716}
1717
1718static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
1719{
1720 struct drm_connector_list_iter conn_iter;
1721 struct drm_device *dev = &dev_priv->drm;
1722 struct drm_modeset_acquire_ctx ctx;
1723 struct drm_atomic_state *state;
1724 struct drm_connector *conn;
1725 int err = 0;
1726
1727 state = drm_atomic_state_alloc(dev);
1728 if (!state)
1729 return -ENOMEM;
1730
1731 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1732 state->acquire_ctx = &ctx;
1733
1734retry:
1735
1736 drm_connector_list_iter_begin(dev, &conn_iter);
1737 drm_for_each_connector_iter(conn, &conn_iter) {
1738 struct drm_connector_state *conn_state;
1739 struct drm_crtc_state *crtc_state;
1740
1741 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
1742 continue;
1743
1744 conn_state = drm_atomic_get_connector_state(state, conn);
1745 if (IS_ERR(conn_state)) {
1746 err = PTR_ERR(conn_state);
1747 break;
1748 }
1749
1750 if (!conn_state->crtc)
1751 continue;
1752
1753 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
1754 if (IS_ERR(crtc_state)) {
1755 err = PTR_ERR(crtc_state);
1756 break;
1757 }
1758
1759 /* Mark mode as changed to trigger a pipe->update() */
1760 crtc_state->mode_changed = true;
1761 }
1762 drm_connector_list_iter_end(&conn_iter);
1763
1764 if (err == 0)
1765 err = drm_atomic_commit(state);
1766
1767 if (err == -EDEADLK) {
1768 drm_atomic_state_clear(state);
1769 err = drm_modeset_backoff(&ctx);
1770 if (!err)
1771 goto retry;
1772 }
1773
1774 drm_modeset_drop_locks(&ctx);
1775 drm_modeset_acquire_fini(&ctx);
1776 drm_atomic_state_put(state);
1777
1778 return err;
1779}
1780
1781int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
1782{
1783 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1784 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
1785 u32 old_mode;
1786 int ret;
1787
1788 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
1789 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1790 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
1791 return -EINVAL;
1792 }
1793
1794 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
1795 if (ret)
1796 return ret;
1797
1798 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
1799 intel_dp->psr.debug = val;
1800
1801 /*
1802 * Do it right away if it's already enabled, otherwise it will be done
1803 * when enabling the source.
1804 */
1805 if (intel_dp->psr.enabled)
1806 psr_irq_control(intel_dp);
1807
1808 mutex_unlock(&intel_dp->psr.lock);
1809
1810 if (old_mode != mode)
1811 ret = intel_psr_fastset_force(dev_priv);
1812
1813 return ret;
1814}
1815
1816static void intel_psr_handle_irq(struct intel_dp *intel_dp)
1817{
1818 struct intel_psr *psr = &intel_dp->psr;
1819
1820 intel_psr_disable_locked(intel_dp);
1821 psr->sink_not_reliable = true;
1822 /* let's make sure that sink is awaken */
1823 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1824}
1825
1826static void intel_psr_work(struct work_struct *work)
1827{
1828 struct intel_dp *intel_dp =
1829 container_of(work, typeof(*intel_dp), psr.work);
1830
1831 mutex_lock(&intel_dp->psr.lock);
1832
1833 if (!intel_dp->psr.enabled)
1834 goto unlock;
1835
1836 if (READ_ONCE(intel_dp->psr.irq_aux_error))
1837 intel_psr_handle_irq(intel_dp);
1838
1839 /*
1840 * We have to make sure PSR is ready for re-enable
1841 * otherwise it keeps disabled until next full enable/disable cycle.
1842 * PSR might take some time to get fully disabled
1843 * and be ready for re-enable.
1844 */
1845 if (!__psr_wait_for_idle_locked(intel_dp))
1846 goto unlock;
1847
1848 /*
1849 * The delayed work can race with an invalidate hence we need to
1850 * recheck. Since psr_flush first clears this and then reschedules we
1851 * won't ever miss a flush when bailing out here.
1852 */
1853 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
1854 goto unlock;
1855
1856 intel_psr_activate(intel_dp);
1857unlock:
1858 mutex_unlock(&intel_dp->psr.lock);
1859}
1860
1861/**
1862 * intel_psr_invalidate - Invalidade PSR
1863 * @dev_priv: i915 device
1864 * @frontbuffer_bits: frontbuffer plane tracking bits
1865 * @origin: which operation caused the invalidate
1866 *
1867 * Since the hardware frontbuffer tracking has gaps we need to integrate
1868 * with the software frontbuffer tracking. This function gets called every
1869 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
1870 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
1871 *
1872 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
1873 */
1874void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1875 unsigned frontbuffer_bits, enum fb_op_origin origin)
1876{
1877 struct intel_encoder *encoder;
1878
1879 if (origin == ORIGIN_FLIP)
1880 return;
1881
1882 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
1883 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
1884 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1885
1886 mutex_lock(&intel_dp->psr.lock);
1887 if (!intel_dp->psr.enabled) {
1888 mutex_unlock(&intel_dp->psr.lock);
1889 continue;
1890 }
1891
1892 pipe_frontbuffer_bits &=
1893 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
1894 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
1895
1896 if (pipe_frontbuffer_bits)
1897 intel_psr_exit(intel_dp);
1898
1899 mutex_unlock(&intel_dp->psr.lock);
1900 }
1901}
1902/*
1903 * When we will be completely rely on PSR2 S/W tracking in future,
1904 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
1905 * event also therefore tgl_dc3co_flush() require to be changed
1906 * accordingly in future.
1907 */
1908static void
1909tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
1910 enum fb_op_origin origin)
1911{
1912 mutex_lock(&intel_dp->psr.lock);
1913
1914 if (!intel_dp->psr.dc3co_exitline)
1915 goto unlock;
1916
1917 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
1918 goto unlock;
1919
1920 /*
1921 * At every frontbuffer flush flip event modified delay of delayed work,
1922 * when delayed work schedules that means display has been idle.
1923 */
1924 if (!(frontbuffer_bits &
1925 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
1926 goto unlock;
1927
1928 tgl_psr2_enable_dc3co(intel_dp);
1929 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
1930 intel_dp->psr.dc3co_exit_delay);
1931
1932unlock:
1933 mutex_unlock(&intel_dp->psr.lock);
1934}
1935
1936/**
1937 * intel_psr_flush - Flush PSR
1938 * @dev_priv: i915 device
1939 * @frontbuffer_bits: frontbuffer plane tracking bits
1940 * @origin: which operation caused the flush
1941 *
1942 * Since the hardware frontbuffer tracking has gaps we need to integrate
1943 * with the software frontbuffer tracking. This function gets called every
1944 * time frontbuffer rendering has completed and flushed out to memory. PSR
1945 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
1946 *
1947 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
1948 */
1949void intel_psr_flush(struct drm_i915_private *dev_priv,
1950 unsigned frontbuffer_bits, enum fb_op_origin origin)
1951{
1952 struct intel_encoder *encoder;
1953
1954 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
1955 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
1956 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1957
1958 if (origin == ORIGIN_FLIP) {
1959 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
1960 continue;
1961 }
1962
1963 mutex_lock(&intel_dp->psr.lock);
1964 if (!intel_dp->psr.enabled) {
1965 mutex_unlock(&intel_dp->psr.lock);
1966 continue;
1967 }
1968
1969 pipe_frontbuffer_bits &=
1970 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
1971 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
1972
1973 /*
1974 * If the PSR is paused by an explicit intel_psr_paused() call,
1975 * we have to ensure that the PSR is not activated until
1976 * intel_psr_resume() is called.
1977 */
1978 if (intel_dp->psr.paused) {
1979 mutex_unlock(&intel_dp->psr.lock);
1980 continue;
1981 }
1982
1983 /* By definition flush = invalidate + flush */
1984 if (pipe_frontbuffer_bits)
1985 psr_force_hw_tracking_exit(intel_dp);
1986
1987 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
1988 schedule_work(&intel_dp->psr.work);
1989 mutex_unlock(&intel_dp->psr.lock);
1990 }
1991}
1992
1993/**
1994 * intel_psr_init - Init basic PSR work and mutex.
1995 * @intel_dp: Intel DP
1996 *
1997 * This function is called after the initializing connector.
1998 * (the initializing of connector treats the handling of connector capabilities)
1999 * And it initializes basic PSR stuff for each DP Encoder.
2000 */
2001void intel_psr_init(struct intel_dp *intel_dp)
2002{
2003 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2004 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2005
2006 if (!HAS_PSR(dev_priv))
2007 return;
2008
2009 /*
2010 * HSW spec explicitly says PSR is tied to port A.
2011 * BDW+ platforms have a instance of PSR registers per transcoder but
2012 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
2013 * than eDP one.
2014 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
2015 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
2016 * But GEN12 supports a instance of PSR registers per transcoder.
2017 */
2018 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2019 drm_dbg_kms(&dev_priv->drm,
2020 "PSR condition failed: Port not supported\n");
2021 return;
2022 }
2023
2024 intel_dp->psr.source_support = true;
2025
2026 if (IS_HASWELL(dev_priv))
2027 /*
2028 * HSW don't have PSR registers on the same space as transcoder
2029 * so set this to a value that when subtract to the register
2030 * in transcoder space results in the right offset for HSW
2031 */
2032 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
2033
2034 if (dev_priv->params.enable_psr == -1)
2035 if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
2036 dev_priv->params.enable_psr = 0;
2037
2038 /* Set link_standby x link_off defaults */
2039 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2040 /* HSW and BDW require workarounds that we don't implement. */
2041 intel_dp->psr.link_standby = false;
2042 else if (DISPLAY_VER(dev_priv) < 12)
2043 /* For new platforms up to TGL let's respect VBT back again */
2044 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
2045
2046 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2047 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2048 mutex_init(&intel_dp->psr.lock);
2049}
2050
2051static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2052 u8 *status, u8 *error_status)
2053{
2054 struct drm_dp_aux *aux = &intel_dp->aux;
2055 int ret;
2056
2057 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2058 if (ret != 1)
2059 return ret;
2060
2061 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2062 if (ret != 1)
2063 return ret;
2064
2065 *status = *status & DP_PSR_SINK_STATE_MASK;
2066
2067 return 0;
2068}
2069
2070static void psr_alpm_check(struct intel_dp *intel_dp)
2071{
2072 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2073 struct drm_dp_aux *aux = &intel_dp->aux;
2074 struct intel_psr *psr = &intel_dp->psr;
2075 u8 val;
2076 int r;
2077
2078 if (!psr->psr2_enabled)
2079 return;
2080
2081 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2082 if (r != 1) {
2083 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2084 return;
2085 }
2086
2087 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2088 intel_psr_disable_locked(intel_dp);
2089 psr->sink_not_reliable = true;
2090 drm_dbg_kms(&dev_priv->drm,
2091 "ALPM lock timeout error, disabling PSR\n");
2092
2093 /* Clearing error */
2094 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2095 }
2096}
2097
2098static void psr_capability_changed_check(struct intel_dp *intel_dp)
2099{
2100 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2101 struct intel_psr *psr = &intel_dp->psr;
2102 u8 val;
2103 int r;
2104
2105 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2106 if (r != 1) {
2107 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2108 return;
2109 }
2110
2111 if (val & DP_PSR_CAPS_CHANGE) {
2112 intel_psr_disable_locked(intel_dp);
2113 psr->sink_not_reliable = true;
2114 drm_dbg_kms(&dev_priv->drm,
2115 "Sink PSR capability changed, disabling PSR\n");
2116
2117 /* Clearing it */
2118 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2119 }
2120}
2121
2122void intel_psr_short_pulse(struct intel_dp *intel_dp)
2123{
2124 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2125 struct intel_psr *psr = &intel_dp->psr;
2126 u8 status, error_status;
2127 const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2128 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2129 DP_PSR_LINK_CRC_ERROR;
2130
2131 if (!CAN_PSR(intel_dp))
2132 return;
2133
2134 mutex_lock(&psr->lock);
2135
2136 if (!psr->enabled)
2137 goto exit;
2138
2139 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2140 drm_err(&dev_priv->drm,
2141 "Error reading PSR status or error status\n");
2142 goto exit;
2143 }
2144
2145 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2146 intel_psr_disable_locked(intel_dp);
2147 psr->sink_not_reliable = true;
2148 }
2149
2150 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2151 drm_dbg_kms(&dev_priv->drm,
2152 "PSR sink internal error, disabling PSR\n");
2153 if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2154 drm_dbg_kms(&dev_priv->drm,
2155 "PSR RFB storage error, disabling PSR\n");
2156 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2157 drm_dbg_kms(&dev_priv->drm,
2158 "PSR VSC SDP uncorrectable error, disabling PSR\n");
2159 if (error_status & DP_PSR_LINK_CRC_ERROR)
2160 drm_dbg_kms(&dev_priv->drm,
2161 "PSR Link CRC error, disabling PSR\n");
2162
2163 if (error_status & ~errors)
2164 drm_err(&dev_priv->drm,
2165 "PSR_ERROR_STATUS unhandled errors %x\n",
2166 error_status & ~errors);
2167 /* clear status register */
2168 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2169
2170 psr_alpm_check(intel_dp);
2171 psr_capability_changed_check(intel_dp);
2172
2173exit:
2174 mutex_unlock(&psr->lock);
2175}
2176
2177bool intel_psr_enabled(struct intel_dp *intel_dp)
2178{
2179 bool ret;
2180
2181 if (!CAN_PSR(intel_dp))
2182 return false;
2183
2184 mutex_lock(&intel_dp->psr.lock);
2185 ret = intel_dp->psr.enabled;
2186 mutex_unlock(&intel_dp->psr.lock);
2187
2188 return ret;
2189}