1/*
   2 * Samsung SoC MIPI DSI Master driver.
   3 *
   4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
   5 *
   6 * Contacts: Tomasz Figa <t.figa@samsung.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11*/
  12
  13#include <asm/unaligned.h>
  14
  15#include <drm/drmP.h>
  16#include <drm/drm_crtc_helper.h>
  17#include <drm/drm_mipi_dsi.h>
  18#include <drm/drm_panel.h>
  19#include <drm/drm_atomic_helper.h>
  20
  21#include <linux/clk.h>
 
 
  22#include <linux/gpio/consumer.h>
  23#include <linux/irq.h>
  24#include <linux/of_device.h>
  25#include <linux/of_gpio.h>
  26#include <linux/of_graph.h>
  27#include <linux/phy/phy.h>
  28#include <linux/regulator/consumer.h>
  29#include <linux/component.h>
 
  30
  31#include <video/mipi_display.h>
  32#include <video/videomode.h>
  33
 
 
 
 
 
 
 
 
 
  34#include "exynos_drm_crtc.h"
  35#include "exynos_drm_drv.h"
  36
  37/* returns true iff both arguments logically differs */
  38#define NEQV(a, b) (!(a) ^ !(b))
  39
  40/* DSIM_STATUS */
  41#define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
  42#define DSIM_STOP_STATE_CLK		(1 << 8)
  43#define DSIM_TX_READY_HS_CLK		(1 << 10)
  44#define DSIM_PLL_STABLE			(1 << 31)
  45
  46/* DSIM_SWRST */
  47#define DSIM_FUNCRST			(1 << 16)
  48#define DSIM_SWRST			(1 << 0)
  49
  50/* DSIM_TIMEOUT */
  51#define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
  52#define DSIM_BTA_TIMEOUT(x)		((x) << 16)
  53
  54/* DSIM_CLKCTRL */
  55#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
  56#define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
  57#define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
  58#define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
  59#define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
  60#define DSIM_BYTE_CLKEN			(1 << 24)
  61#define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
  62#define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
  63#define DSIM_PLL_BYPASS			(1 << 27)
  64#define DSIM_ESC_CLKEN			(1 << 28)
  65#define DSIM_TX_REQUEST_HSCLK		(1 << 31)
  66
  67/* DSIM_CONFIG */
  68#define DSIM_LANE_EN_CLK		(1 << 0)
  69#define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
  70#define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
  71#define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
  72#define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
  73#define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
  74#define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
  75#define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
  76#define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
  77#define DSIM_SUB_VC			(((x) & 0x3) << 16)
  78#define DSIM_MAIN_VC			(((x) & 0x3) << 18)
  79#define DSIM_HSA_MODE			(1 << 20)
  80#define DSIM_HBP_MODE			(1 << 21)
  81#define DSIM_HFP_MODE			(1 << 22)
  82#define DSIM_HSE_MODE			(1 << 23)
  83#define DSIM_AUTO_MODE			(1 << 24)
  84#define DSIM_VIDEO_MODE			(1 << 25)
  85#define DSIM_BURST_MODE			(1 << 26)
  86#define DSIM_SYNC_INFORM		(1 << 27)
  87#define DSIM_EOT_DISABLE		(1 << 28)
  88#define DSIM_MFLUSH_VS			(1 << 29)
  89/* This flag is valid only for exynos3250/3472/4415/5260/5430 */
  90#define DSIM_CLKLANE_STOP		(1 << 30)
  91
  92/* DSIM_ESCMODE */
  93#define DSIM_TX_TRIGGER_RST		(1 << 4)
  94#define DSIM_TX_LPDT_LP			(1 << 6)
  95#define DSIM_CMD_LPDT_LP		(1 << 7)
  96#define DSIM_FORCE_BTA			(1 << 16)
  97#define DSIM_FORCE_STOP_STATE		(1 << 20)
  98#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
  99#define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
 100
 101/* DSIM_MDRESOL */
 102#define DSIM_MAIN_STAND_BY		(1 << 31)
 103#define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
 104#define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
 105
 106/* DSIM_MVPORCH */
 107#define DSIM_CMD_ALLOW(x)		((x) << 28)
 108#define DSIM_STABLE_VFP(x)		((x) << 16)
 109#define DSIM_MAIN_VBP(x)		((x) << 0)
 110#define DSIM_CMD_ALLOW_MASK		(0xf << 28)
 111#define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
 112#define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
 113
 114/* DSIM_MHPORCH */
 115#define DSIM_MAIN_HFP(x)		((x) << 16)
 116#define DSIM_MAIN_HBP(x)		((x) << 0)
 117#define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
 118#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
 119
 120/* DSIM_MSYNC */
 121#define DSIM_MAIN_VSA(x)		((x) << 22)
 122#define DSIM_MAIN_HSA(x)		((x) << 0)
 123#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
 124#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
 125
 126/* DSIM_SDRESOL */
 127#define DSIM_SUB_STANDY(x)		((x) << 31)
 128#define DSIM_SUB_VRESOL(x)		((x) << 16)
 129#define DSIM_SUB_HRESOL(x)		((x) << 0)
 130#define DSIM_SUB_STANDY_MASK		((0x1) << 31)
 131#define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
 132#define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
 133
 134/* DSIM_INTSRC */
 135#define DSIM_INT_PLL_STABLE		(1 << 31)
 136#define DSIM_INT_SW_RST_RELEASE		(1 << 30)
 137#define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
 138#define DSIM_INT_SFR_HDR_FIFO_EMPTY	(1 << 28)
 139#define DSIM_INT_BTA			(1 << 25)
 140#define DSIM_INT_FRAME_DONE		(1 << 24)
 141#define DSIM_INT_RX_TIMEOUT		(1 << 21)
 142#define DSIM_INT_BTA_TIMEOUT		(1 << 20)
 143#define DSIM_INT_RX_DONE		(1 << 18)
 144#define DSIM_INT_RX_TE			(1 << 17)
 145#define DSIM_INT_RX_ACK			(1 << 16)
 146#define DSIM_INT_RX_ECC_ERR		(1 << 15)
 147#define DSIM_INT_RX_CRC_ERR		(1 << 14)
 148
 149/* DSIM_FIFOCTRL */
 150#define DSIM_RX_DATA_FULL		(1 << 25)
 151#define DSIM_RX_DATA_EMPTY		(1 << 24)
 152#define DSIM_SFR_HEADER_FULL		(1 << 23)
 153#define DSIM_SFR_HEADER_EMPTY		(1 << 22)
 154#define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
 155#define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
 156#define DSIM_I80_HEADER_FULL		(1 << 19)
 157#define DSIM_I80_HEADER_EMPTY		(1 << 18)
 158#define DSIM_I80_PAYLOAD_FULL		(1 << 17)
 159#define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
 160#define DSIM_SD_HEADER_FULL		(1 << 15)
 161#define DSIM_SD_HEADER_EMPTY		(1 << 14)
 162#define DSIM_SD_PAYLOAD_FULL		(1 << 13)
 163#define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
 164#define DSIM_MD_HEADER_FULL		(1 << 11)
 165#define DSIM_MD_HEADER_EMPTY		(1 << 10)
 166#define DSIM_MD_PAYLOAD_FULL		(1 << 9)
 167#define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
 168#define DSIM_RX_FIFO			(1 << 4)
 169#define DSIM_SFR_FIFO			(1 << 3)
 170#define DSIM_I80_FIFO			(1 << 2)
 171#define DSIM_SD_FIFO			(1 << 1)
 172#define DSIM_MD_FIFO			(1 << 0)
 173
 174/* DSIM_PHYACCHR */
 175#define DSIM_AFC_EN			(1 << 14)
 176#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
 177
 178/* DSIM_PLLCTRL */
 179#define DSIM_FREQ_BAND(x)		((x) << 24)
 180#define DSIM_PLL_EN			(1 << 23)
 181#define DSIM_PLL_P(x)			((x) << 13)
 182#define DSIM_PLL_M(x)			((x) << 4)
 183#define DSIM_PLL_S(x)			((x) << 1)
 184
 185/* DSIM_PHYCTRL */
 186#define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
 187#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	(1 << 30)
 188#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	(1 << 14)
 189
 190/* DSIM_PHYTIMING */
 191#define DSIM_PHYTIMING_LPX(x)		((x) << 8)
 192#define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
 193
 194/* DSIM_PHYTIMING1 */
 195#define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
 196#define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
 197#define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
 198#define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
 199
 200/* DSIM_PHYTIMING2 */
 201#define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
 202#define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
 203#define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
 204
 205#define DSI_MAX_BUS_WIDTH		4
 206#define DSI_NUM_VIRTUAL_CHANNELS	4
 207#define DSI_TX_FIFO_SIZE		2048
 208#define DSI_RX_FIFO_SIZE		256
 209#define DSI_XFER_TIMEOUT_MS		100
 210#define DSI_RX_FIFO_EMPTY		0x30800002
 211
 212#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
 213
 214static char *clk_names[5] = { "bus_clk", "sclk_mipi",
 215	"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
 216	"sclk_rgb_vclk_to_dsim0" };
 217
 218enum exynos_dsi_transfer_type {
 219	EXYNOS_DSI_TX,
 220	EXYNOS_DSI_RX,
 221};
 222
 223struct exynos_dsi_transfer {
 224	struct list_head list;
 225	struct completion completed;
 226	int result;
 227	struct mipi_dsi_packet packet;
 228	u16 flags;
 229	u16 tx_done;
 230
 231	u8 *rx_payload;
 232	u16 rx_len;
 233	u16 rx_done;
 234};
 235
 236#define DSIM_STATE_ENABLED		BIT(0)
 237#define DSIM_STATE_INITIALIZED		BIT(1)
 238#define DSIM_STATE_CMD_LPM		BIT(2)
 239#define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
 240
 241struct exynos_dsi_driver_data {
 242	const unsigned int *reg_ofs;
 243	unsigned int plltmr_reg;
 244	unsigned int has_freqband:1;
 245	unsigned int has_clklane_stop:1;
 246	unsigned int num_clks;
 247	unsigned int max_freq;
 248	unsigned int wait_for_reset;
 249	unsigned int num_bits_resol;
 250	const unsigned int *reg_values;
 251};
 252
 253struct exynos_dsi {
 254	struct drm_encoder encoder;
 255	struct mipi_dsi_host dsi_host;
 256	struct drm_connector connector;
 257	struct device_node *panel_node;
 258	struct drm_panel *panel;
 
 
 259	struct device *dev;
 260
 261	void __iomem *reg_base;
 262	struct phy *phy;
 263	struct clk **clks;
 264	struct regulator_bulk_data supplies[2];
 265	int irq;
 266	int te_gpio;
 267
 268	u32 pll_clk_rate;
 269	u32 burst_clk_rate;
 270	u32 esc_clk_rate;
 271	u32 lanes;
 272	u32 mode_flags;
 273	u32 format;
 274	struct videomode vm;
 275
 276	int state;
 277	struct drm_property *brightness;
 278	struct completion completed;
 279
 280	spinlock_t transfer_lock; /* protects transfer_list */
 281	struct list_head transfer_list;
 282
 283	struct exynos_dsi_driver_data *driver_data;
 284	struct device_node *bridge_node;
 285};
 286
 287#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 288#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
 289
 290static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
 291{
 292	return container_of(e, struct exynos_dsi, encoder);
 293}
 294
 295enum reg_idx {
 296	DSIM_STATUS_REG,	/* Status register */
 297	DSIM_SWRST_REG,		/* Software reset register */
 298	DSIM_CLKCTRL_REG,	/* Clock control register */
 299	DSIM_TIMEOUT_REG,	/* Time out register */
 300	DSIM_CONFIG_REG,	/* Configuration register */
 301	DSIM_ESCMODE_REG,	/* Escape mode register */
 302	DSIM_MDRESOL_REG,
 303	DSIM_MVPORCH_REG,	/* Main display Vporch register */
 304	DSIM_MHPORCH_REG,	/* Main display Hporch register */
 305	DSIM_MSYNC_REG,		/* Main display sync area register */
 306	DSIM_INTSRC_REG,	/* Interrupt source register */
 307	DSIM_INTMSK_REG,	/* Interrupt mask register */
 308	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
 309	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
 310	DSIM_RXFIFO_REG,	/* Read FIFO register */
 311	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
 312	DSIM_PLLCTRL_REG,	/* PLL control register */
 313	DSIM_PHYCTRL_REG,
 314	DSIM_PHYTIMING_REG,
 315	DSIM_PHYTIMING1_REG,
 316	DSIM_PHYTIMING2_REG,
 317	NUM_REGS
 318};
 319
 320static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
 321				    u32 val)
 322{
 323
 324	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 325}
 326
 327static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
 328{
 329	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 330}
 331
 332static const unsigned int exynos_reg_ofs[] = {
 333	[DSIM_STATUS_REG] =  0x00,
 334	[DSIM_SWRST_REG] =  0x04,
 335	[DSIM_CLKCTRL_REG] =  0x08,
 336	[DSIM_TIMEOUT_REG] =  0x0c,
 337	[DSIM_CONFIG_REG] =  0x10,
 338	[DSIM_ESCMODE_REG] =  0x14,
 339	[DSIM_MDRESOL_REG] =  0x18,
 340	[DSIM_MVPORCH_REG] =  0x1c,
 341	[DSIM_MHPORCH_REG] =  0x20,
 342	[DSIM_MSYNC_REG] =  0x24,
 343	[DSIM_INTSRC_REG] =  0x2c,
 344	[DSIM_INTMSK_REG] =  0x30,
 345	[DSIM_PKTHDR_REG] =  0x34,
 346	[DSIM_PAYLOAD_REG] =  0x38,
 347	[DSIM_RXFIFO_REG] =  0x3c,
 348	[DSIM_FIFOCTRL_REG] =  0x44,
 349	[DSIM_PLLCTRL_REG] =  0x4c,
 350	[DSIM_PHYCTRL_REG] =  0x5c,
 351	[DSIM_PHYTIMING_REG] =  0x64,
 352	[DSIM_PHYTIMING1_REG] =  0x68,
 353	[DSIM_PHYTIMING2_REG] =  0x6c,
 354};
 355
 356static const unsigned int exynos5433_reg_ofs[] = {
 357	[DSIM_STATUS_REG] = 0x04,
 358	[DSIM_SWRST_REG] = 0x0C,
 359	[DSIM_CLKCTRL_REG] = 0x10,
 360	[DSIM_TIMEOUT_REG] = 0x14,
 361	[DSIM_CONFIG_REG] = 0x18,
 362	[DSIM_ESCMODE_REG] = 0x1C,
 363	[DSIM_MDRESOL_REG] = 0x20,
 364	[DSIM_MVPORCH_REG] = 0x24,
 365	[DSIM_MHPORCH_REG] = 0x28,
 366	[DSIM_MSYNC_REG] = 0x2C,
 367	[DSIM_INTSRC_REG] = 0x34,
 368	[DSIM_INTMSK_REG] = 0x38,
 369	[DSIM_PKTHDR_REG] = 0x3C,
 370	[DSIM_PAYLOAD_REG] = 0x40,
 371	[DSIM_RXFIFO_REG] = 0x44,
 372	[DSIM_FIFOCTRL_REG] = 0x4C,
 373	[DSIM_PLLCTRL_REG] = 0x94,
 374	[DSIM_PHYCTRL_REG] = 0xA4,
 375	[DSIM_PHYTIMING_REG] = 0xB4,
 376	[DSIM_PHYTIMING1_REG] = 0xB8,
 377	[DSIM_PHYTIMING2_REG] = 0xBC,
 378};
 379
 380enum reg_value_idx {
 381	RESET_TYPE,
 382	PLL_TIMER,
 383	STOP_STATE_CNT,
 384	PHYCTRL_ULPS_EXIT,
 385	PHYCTRL_VREG_LP,
 386	PHYCTRL_SLEW_UP,
 387	PHYTIMING_LPX,
 388	PHYTIMING_HS_EXIT,
 389	PHYTIMING_CLK_PREPARE,
 390	PHYTIMING_CLK_ZERO,
 391	PHYTIMING_CLK_POST,
 392	PHYTIMING_CLK_TRAIL,
 393	PHYTIMING_HS_PREPARE,
 394	PHYTIMING_HS_ZERO,
 395	PHYTIMING_HS_TRAIL
 396};
 397
 398static const unsigned int reg_values[] = {
 399	[RESET_TYPE] = DSIM_SWRST,
 400	[PLL_TIMER] = 500,
 401	[STOP_STATE_CNT] = 0xf,
 402	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
 403	[PHYCTRL_VREG_LP] = 0,
 404	[PHYCTRL_SLEW_UP] = 0,
 405	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 406	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 407	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 408	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
 409	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 410	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 411	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
 412	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 413	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 414};
 415
 416static const unsigned int exynos5422_reg_values[] = {
 417	[RESET_TYPE] = DSIM_SWRST,
 418	[PLL_TIMER] = 500,
 419	[STOP_STATE_CNT] = 0xf,
 420	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
 421	[PHYCTRL_VREG_LP] = 0,
 422	[PHYCTRL_SLEW_UP] = 0,
 423	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
 424	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
 425	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 426	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
 427	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 428	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
 429	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
 430	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
 431	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
 432};
 433
 434static const unsigned int exynos5433_reg_values[] = {
 435	[RESET_TYPE] = DSIM_FUNCRST,
 436	[PLL_TIMER] = 22200,
 437	[STOP_STATE_CNT] = 0xa,
 438	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
 439	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
 440	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
 441	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
 442	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
 443	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 444	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
 445	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 446	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
 447	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
 448	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
 449	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 450};
 451
 452static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
 453	.reg_ofs = exynos_reg_ofs,
 454	.plltmr_reg = 0x50,
 455	.has_freqband = 1,
 456	.has_clklane_stop = 1,
 457	.num_clks = 2,
 458	.max_freq = 1000,
 459	.wait_for_reset = 1,
 460	.num_bits_resol = 11,
 461	.reg_values = reg_values,
 462};
 463
 464static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
 465	.reg_ofs = exynos_reg_ofs,
 466	.plltmr_reg = 0x50,
 467	.has_freqband = 1,
 468	.has_clklane_stop = 1,
 469	.num_clks = 2,
 470	.max_freq = 1000,
 471	.wait_for_reset = 1,
 472	.num_bits_resol = 11,
 473	.reg_values = reg_values,
 474};
 475
 476static const struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
 477	.reg_ofs = exynos_reg_ofs,
 478	.plltmr_reg = 0x58,
 479	.has_clklane_stop = 1,
 480	.num_clks = 2,
 481	.max_freq = 1000,
 482	.wait_for_reset = 1,
 483	.num_bits_resol = 11,
 484	.reg_values = reg_values,
 485};
 486
 487static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
 488	.reg_ofs = exynos_reg_ofs,
 489	.plltmr_reg = 0x58,
 490	.num_clks = 2,
 491	.max_freq = 1000,
 492	.wait_for_reset = 1,
 493	.num_bits_resol = 11,
 494	.reg_values = reg_values,
 495};
 496
 497static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
 498	.reg_ofs = exynos5433_reg_ofs,
 499	.plltmr_reg = 0xa0,
 500	.has_clklane_stop = 1,
 501	.num_clks = 5,
 502	.max_freq = 1500,
 503	.wait_for_reset = 0,
 504	.num_bits_resol = 12,
 505	.reg_values = exynos5433_reg_values,
 506};
 507
 508static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
 509	.reg_ofs = exynos5433_reg_ofs,
 510	.plltmr_reg = 0xa0,
 511	.has_clklane_stop = 1,
 512	.num_clks = 2,
 513	.max_freq = 1500,
 514	.wait_for_reset = 1,
 515	.num_bits_resol = 12,
 516	.reg_values = exynos5422_reg_values,
 517};
 518
 519static const struct of_device_id exynos_dsi_of_match[] = {
 520	{ .compatible = "samsung,exynos3250-mipi-dsi",
 521	  .data = &exynos3_dsi_driver_data },
 522	{ .compatible = "samsung,exynos4210-mipi-dsi",
 523	  .data = &exynos4_dsi_driver_data },
 524	{ .compatible = "samsung,exynos4415-mipi-dsi",
 525	  .data = &exynos4415_dsi_driver_data },
 526	{ .compatible = "samsung,exynos5410-mipi-dsi",
 527	  .data = &exynos5_dsi_driver_data },
 528	{ .compatible = "samsung,exynos5422-mipi-dsi",
 529	  .data = &exynos5422_dsi_driver_data },
 530	{ .compatible = "samsung,exynos5433-mipi-dsi",
 531	  .data = &exynos5433_dsi_driver_data },
 532	{ }
 533};
 534
 535static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
 536						struct platform_device *pdev)
 537{
 538	const struct of_device_id *of_id =
 539			of_match_device(exynos_dsi_of_match, &pdev->dev);
 540
 541	return (struct exynos_dsi_driver_data *)of_id->data;
 542}
 543
 544static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 545{
 546	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
 547		return;
 548
 549	dev_err(dsi->dev, "timeout waiting for reset\n");
 550}
 551
 552static void exynos_dsi_reset(struct exynos_dsi *dsi)
 553{
 554	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
 555
 556	reinit_completion(&dsi->completed);
 557	exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
 558}
 559
 560#ifndef MHZ
 561#define MHZ	(1000*1000)
 562#endif
 563
 564static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
 565		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
 566{
 567	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 568	unsigned long best_freq = 0;
 569	u32 min_delta = 0xffffffff;
 570	u8 p_min, p_max;
 571	u8 _p, uninitialized_var(best_p);
 572	u16 _m, uninitialized_var(best_m);
 573	u8 _s, uninitialized_var(best_s);
 574
 575	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
 576	p_max = fin / (6 * MHZ);
 577
 578	for (_p = p_min; _p <= p_max; ++_p) {
 579		for (_s = 0; _s <= 5; ++_s) {
 580			u64 tmp;
 581			u32 delta;
 582
 583			tmp = (u64)fout * (_p << _s);
 584			do_div(tmp, fin);
 585			_m = tmp;
 586			if (_m < 41 || _m > 125)
 587				continue;
 588
 589			tmp = (u64)_m * fin;
 590			do_div(tmp, _p);
 591			if (tmp < 500 * MHZ ||
 592					tmp > driver_data->max_freq * MHZ)
 593				continue;
 594
 595			tmp = (u64)_m * fin;
 596			do_div(tmp, _p << _s);
 597
 598			delta = abs(fout - tmp);
 599			if (delta < min_delta) {
 600				best_p = _p;
 601				best_m = _m;
 602				best_s = _s;
 603				min_delta = delta;
 604				best_freq = tmp;
 605			}
 606		}
 607	}
 608
 609	if (best_freq) {
 610		*p = best_p;
 611		*m = best_m;
 612		*s = best_s;
 613	}
 614
 615	return best_freq;
 616}
 617
 618static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
 619					unsigned long freq)
 620{
 621	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 622	unsigned long fin, fout;
 623	int timeout;
 624	u8 p, s;
 625	u16 m;
 626	u32 reg;
 627
 628	fin = dsi->pll_clk_rate;
 629	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
 630	if (!fout) {
 631		dev_err(dsi->dev,
 632			"failed to find PLL PMS for requested frequency\n");
 633		return 0;
 634	}
 635	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
 636
 637	writel(driver_data->reg_values[PLL_TIMER],
 638			dsi->reg_base + driver_data->plltmr_reg);
 639
 640	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
 641
 642	if (driver_data->has_freqband) {
 643		static const unsigned long freq_bands[] = {
 644			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
 645			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
 646			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
 647			770 * MHZ, 870 * MHZ, 950 * MHZ,
 648		};
 649		int band;
 650
 651		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
 652			if (fout < freq_bands[band])
 653				break;
 654
 655		dev_dbg(dsi->dev, "band %d\n", band);
 656
 657		reg |= DSIM_FREQ_BAND(band);
 658	}
 659
 660	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
 661
 662	timeout = 1000;
 663	do {
 664		if (timeout-- == 0) {
 665			dev_err(dsi->dev, "PLL failed to stabilize\n");
 666			return 0;
 667		}
 668		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
 669	} while ((reg & DSIM_PLL_STABLE) == 0);
 670
 671	return fout;
 672}
 673
 674static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
 675{
 676	unsigned long hs_clk, byte_clk, esc_clk;
 677	unsigned long esc_div;
 678	u32 reg;
 679
 680	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
 681	if (!hs_clk) {
 682		dev_err(dsi->dev, "failed to configure DSI PLL\n");
 683		return -EFAULT;
 684	}
 685
 686	byte_clk = hs_clk / 8;
 687	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
 688	esc_clk = byte_clk / esc_div;
 689
 690	if (esc_clk > 20 * MHZ) {
 691		++esc_div;
 692		esc_clk = byte_clk / esc_div;
 693	}
 694
 695	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
 696		hs_clk, byte_clk, esc_clk);
 697
 698	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
 699	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
 700			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
 701			| DSIM_BYTE_CLK_SRC_MASK);
 702	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
 703			| DSIM_ESC_PRESCALER(esc_div)
 704			| DSIM_LANE_ESC_CLK_EN_CLK
 705			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
 706			| DSIM_BYTE_CLK_SRC(0)
 707			| DSIM_TX_REQUEST_HSCLK;
 708	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
 709
 710	return 0;
 711}
 712
 713static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
 714{
 715	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 716	const unsigned int *reg_values = driver_data->reg_values;
 717	u32 reg;
 718
 719	if (driver_data->has_freqband)
 720		return;
 721
 722	/* B D-PHY: D-PHY Master & Slave Analog Block control */
 723	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
 724		reg_values[PHYCTRL_SLEW_UP];
 725	exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
 726
 727	/*
 728	 * T LPX: Transmitted length of any Low-Power state period
 729	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
 730	 *	burst
 731	 */
 732	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
 733	exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
 734
 735	/*
 736	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
 737	 *	Line state immediately before the HS-0 Line state starting the
 738	 *	HS transmission
 739	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
 740	 *	transmitting the Clock.
 741	 * T CLK_POST: Time that the transmitter continues to send HS clock
 742	 *	after the last associated Data Lane has transitioned to LP Mode
 743	 *	Interval is defined as the period from the end of T HS-TRAIL to
 744	 *	the beginning of T CLK-TRAIL
 745	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
 746	 *	the last payload clock bit of a HS transmission burst
 747	 */
 748	reg = reg_values[PHYTIMING_CLK_PREPARE] |
 749		reg_values[PHYTIMING_CLK_ZERO] |
 750		reg_values[PHYTIMING_CLK_POST] |
 751		reg_values[PHYTIMING_CLK_TRAIL];
 752
 753	exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
 754
 755	/*
 756	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
 757	 *	Line state immediately before the HS-0 Line state starting the
 758	 *	HS transmission
 759	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
 760	 *	transmitting the Sync sequence.
 761	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
 762	 *	state after last payload data bit of a HS transmission burst
 763	 */
 764	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
 765		reg_values[PHYTIMING_HS_TRAIL];
 766	exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
 767}
 768
 769static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
 770{
 771	u32 reg;
 772
 773	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
 774	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
 775			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
 776	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
 777
 778	reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
 779	reg &= ~DSIM_PLL_EN;
 780	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
 781}
 782
 783static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
 784{
 785	u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
 786	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
 787			DSIM_LANE_EN(lane));
 788	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
 789}
 790
 791static int exynos_dsi_init_link(struct exynos_dsi *dsi)
 792{
 793	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 794	int timeout;
 795	u32 reg;
 796	u32 lanes_mask;
 797
 798	/* Initialize FIFO pointers */
 799	reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
 800	reg &= ~0x1f;
 801	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
 802
 803	usleep_range(9000, 11000);
 804
 805	reg |= 0x1f;
 806	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
 807	usleep_range(9000, 11000);
 808
 809	/* DSI configuration */
 810	reg = 0;
 811
 812	/*
 813	 * The first bit of mode_flags specifies display configuration.
 814	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
 815	 * mode, otherwise it will support command mode.
 816	 */
 817	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 818		reg |= DSIM_VIDEO_MODE;
 819
 820		/*
 821		 * The user manual describes that following bits are ignored in
 822		 * command mode.
 823		 */
 824		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
 825			reg |= DSIM_MFLUSH_VS;
 826		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 827			reg |= DSIM_SYNC_INFORM;
 828		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 829			reg |= DSIM_BURST_MODE;
 830		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
 831			reg |= DSIM_AUTO_MODE;
 832		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
 833			reg |= DSIM_HSE_MODE;
 834		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
 835			reg |= DSIM_HFP_MODE;
 836		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
 837			reg |= DSIM_HBP_MODE;
 838		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
 839			reg |= DSIM_HSA_MODE;
 840	}
 841
 842	if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
 843		reg |= DSIM_EOT_DISABLE;
 844
 845	switch (dsi->format) {
 846	case MIPI_DSI_FMT_RGB888:
 847		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
 848		break;
 849	case MIPI_DSI_FMT_RGB666:
 850		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
 851		break;
 852	case MIPI_DSI_FMT_RGB666_PACKED:
 853		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
 854		break;
 855	case MIPI_DSI_FMT_RGB565:
 856		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
 857		break;
 858	default:
 859		dev_err(dsi->dev, "invalid pixel format\n");
 860		return -EINVAL;
 861	}
 862
 863	/*
 864	 * Use non-continuous clock mode if the periparal wants and
 865	 * host controller supports
 866	 *
 867	 * In non-continous clock mode, host controller will turn off
 868	 * the HS clock between high-speed transmissions to reduce
 869	 * power consumption.
 870	 */
 871	if (driver_data->has_clklane_stop &&
 872			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
 873		reg |= DSIM_CLKLANE_STOP;
 874	}
 875	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
 876
 877	lanes_mask = BIT(dsi->lanes) - 1;
 878	exynos_dsi_enable_lane(dsi, lanes_mask);
 879
 880	/* Check clock and data lane state are stop state */
 881	timeout = 100;
 882	do {
 883		if (timeout-- == 0) {
 884			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
 885			return -EFAULT;
 886		}
 887
 888		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
 889		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
 890		    != DSIM_STOP_STATE_DAT(lanes_mask))
 891			continue;
 892	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
 893
 894	reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 895	reg &= ~DSIM_STOP_STATE_CNT_MASK;
 896	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
 897	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
 898
 899	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
 900	exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
 901
 902	return 0;
 903}
 904
 905static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
 906{
 907	struct videomode *vm = &dsi->vm;
 908	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
 909	u32 reg;
 910
 911	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 912		reg = DSIM_CMD_ALLOW(0xf)
 913			| DSIM_STABLE_VFP(vm->vfront_porch)
 914			| DSIM_MAIN_VBP(vm->vback_porch);
 915		exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
 916
 917		reg = DSIM_MAIN_HFP(vm->hfront_porch)
 918			| DSIM_MAIN_HBP(vm->hback_porch);
 919		exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
 920
 921		reg = DSIM_MAIN_VSA(vm->vsync_len)
 922			| DSIM_MAIN_HSA(vm->hsync_len);
 923		exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
 924	}
 925	reg =  DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
 926		DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
 927
 928	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
 929
 930	dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
 931}
 932
 933static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
 934{
 935	u32 reg;
 936
 937	reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
 938	if (enable)
 939		reg |= DSIM_MAIN_STAND_BY;
 940	else
 941		reg &= ~DSIM_MAIN_STAND_BY;
 942	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
 943}
 944
 945static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
 946{
 947	int timeout = 2000;
 948
 949	do {
 950		u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
 951
 952		if (!(reg & DSIM_SFR_HEADER_FULL))
 953			return 0;
 954
 955		if (!cond_resched())
 956			usleep_range(950, 1050);
 957	} while (--timeout);
 958
 959	return -ETIMEDOUT;
 960}
 961
 962static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
 963{
 964	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 965
 966	if (lpm)
 967		v |= DSIM_CMD_LPDT_LP;
 968	else
 969		v &= ~DSIM_CMD_LPDT_LP;
 970
 971	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
 972}
 973
 974static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
 975{
 976	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 977	v |= DSIM_FORCE_BTA;
 978	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
 979}
 980
 981static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
 982					struct exynos_dsi_transfer *xfer)
 983{
 984	struct device *dev = dsi->dev;
 985	struct mipi_dsi_packet *pkt = &xfer->packet;
 986	const u8 *payload = pkt->payload + xfer->tx_done;
 987	u16 length = pkt->payload_length - xfer->tx_done;
 988	bool first = !xfer->tx_done;
 989	u32 reg;
 990
 991	dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
 992		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
 993
 994	if (length > DSI_TX_FIFO_SIZE)
 995		length = DSI_TX_FIFO_SIZE;
 996
 997	xfer->tx_done += length;
 998
 999	/* Send payload */
1000	while (length >= 4) {
1001		reg = get_unaligned_le32(payload);
1002		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
1003		payload += 4;
1004		length -= 4;
1005	}
1006
1007	reg = 0;
1008	switch (length) {
1009	case 3:
1010		reg |= payload[2] << 16;
1011		/* Fall through */
1012	case 2:
1013		reg |= payload[1] << 8;
1014		/* Fall through */
1015	case 1:
1016		reg |= payload[0];
1017		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
1018		break;
1019	}
1020
1021	/* Send packet header */
1022	if (!first)
1023		return;
1024
1025	reg = get_unaligned_le32(pkt->header);
1026	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1027		dev_err(dev, "waiting for header FIFO timed out\n");
1028		return;
1029	}
1030
1031	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1032		 dsi->state & DSIM_STATE_CMD_LPM)) {
1033		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1034		dsi->state ^= DSIM_STATE_CMD_LPM;
1035	}
1036
1037	exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1038
1039	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1040		exynos_dsi_force_bta(dsi);
1041}
1042
1043static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1044					struct exynos_dsi_transfer *xfer)
1045{
1046	u8 *payload = xfer->rx_payload + xfer->rx_done;
1047	bool first = !xfer->rx_done;
1048	struct device *dev = dsi->dev;
1049	u16 length;
1050	u32 reg;
1051
1052	if (first) {
1053		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1054
1055		switch (reg & 0x3f) {
1056		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1057		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1058			if (xfer->rx_len >= 2) {
1059				payload[1] = reg >> 16;
1060				++xfer->rx_done;
1061			}
1062			/* Fall through */
1063		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1064		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1065			payload[0] = reg >> 8;
1066			++xfer->rx_done;
1067			xfer->rx_len = xfer->rx_done;
1068			xfer->result = 0;
1069			goto clear_fifo;
1070		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1071			dev_err(dev, "DSI Error Report: 0x%04x\n",
1072				(reg >> 8) & 0xffff);
1073			xfer->result = 0;
1074			goto clear_fifo;
1075		}
1076
1077		length = (reg >> 8) & 0xffff;
1078		if (length > xfer->rx_len) {
1079			dev_err(dev,
1080				"response too long (%u > %u bytes), stripping\n",
1081				xfer->rx_len, length);
1082			length = xfer->rx_len;
1083		} else if (length < xfer->rx_len)
1084			xfer->rx_len = length;
1085	}
1086
1087	length = xfer->rx_len - xfer->rx_done;
1088	xfer->rx_done += length;
1089
1090	/* Receive payload */
1091	while (length >= 4) {
1092		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1093		payload[0] = (reg >>  0) & 0xff;
1094		payload[1] = (reg >>  8) & 0xff;
1095		payload[2] = (reg >> 16) & 0xff;
1096		payload[3] = (reg >> 24) & 0xff;
1097		payload += 4;
1098		length -= 4;
1099	}
1100
1101	if (length) {
1102		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1103		switch (length) {
1104		case 3:
1105			payload[2] = (reg >> 16) & 0xff;
1106			/* Fall through */
1107		case 2:
1108			payload[1] = (reg >> 8) & 0xff;
1109			/* Fall through */
1110		case 1:
1111			payload[0] = reg & 0xff;
1112		}
1113	}
1114
1115	if (xfer->rx_done == xfer->rx_len)
1116		xfer->result = 0;
1117
1118clear_fifo:
1119	length = DSI_RX_FIFO_SIZE / 4;
1120	do {
1121		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1122		if (reg == DSI_RX_FIFO_EMPTY)
1123			break;
1124	} while (--length);
1125}
1126
1127static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1128{
1129	unsigned long flags;
1130	struct exynos_dsi_transfer *xfer;
1131	bool start = false;
1132
1133again:
1134	spin_lock_irqsave(&dsi->transfer_lock, flags);
1135
1136	if (list_empty(&dsi->transfer_list)) {
1137		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1138		return;
1139	}
1140
1141	xfer = list_first_entry(&dsi->transfer_list,
1142					struct exynos_dsi_transfer, list);
1143
1144	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1145
1146	if (xfer->packet.payload_length &&
1147	    xfer->tx_done == xfer->packet.payload_length)
1148		/* waiting for RX */
1149		return;
1150
1151	exynos_dsi_send_to_fifo(dsi, xfer);
1152
1153	if (xfer->packet.payload_length || xfer->rx_len)
1154		return;
1155
1156	xfer->result = 0;
1157	complete(&xfer->completed);
1158
1159	spin_lock_irqsave(&dsi->transfer_lock, flags);
1160
1161	list_del_init(&xfer->list);
1162	start = !list_empty(&dsi->transfer_list);
1163
1164	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1165
1166	if (start)
1167		goto again;
1168}
1169
1170static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1171{
1172	struct exynos_dsi_transfer *xfer;
1173	unsigned long flags;
1174	bool start = true;
1175
1176	spin_lock_irqsave(&dsi->transfer_lock, flags);
1177
1178	if (list_empty(&dsi->transfer_list)) {
1179		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1180		return false;
1181	}
1182
1183	xfer = list_first_entry(&dsi->transfer_list,
1184					struct exynos_dsi_transfer, list);
1185
1186	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1187
1188	dev_dbg(dsi->dev,
1189		"> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1190		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1191		xfer->rx_done);
1192
1193	if (xfer->tx_done != xfer->packet.payload_length)
1194		return true;
1195
1196	if (xfer->rx_done != xfer->rx_len)
1197		exynos_dsi_read_from_fifo(dsi, xfer);
1198
1199	if (xfer->rx_done != xfer->rx_len)
1200		return true;
1201
1202	spin_lock_irqsave(&dsi->transfer_lock, flags);
1203
1204	list_del_init(&xfer->list);
1205	start = !list_empty(&dsi->transfer_list);
1206
1207	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1208
1209	if (!xfer->rx_len)
1210		xfer->result = 0;
1211	complete(&xfer->completed);
1212
1213	return start;
1214}
1215
1216static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1217					struct exynos_dsi_transfer *xfer)
1218{
1219	unsigned long flags;
1220	bool start;
1221
1222	spin_lock_irqsave(&dsi->transfer_lock, flags);
1223
1224	if (!list_empty(&dsi->transfer_list) &&
1225	    xfer == list_first_entry(&dsi->transfer_list,
1226				     struct exynos_dsi_transfer, list)) {
1227		list_del_init(&xfer->list);
1228		start = !list_empty(&dsi->transfer_list);
1229		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1230		if (start)
1231			exynos_dsi_transfer_start(dsi);
1232		return;
1233	}
1234
1235	list_del_init(&xfer->list);
1236
1237	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1238}
1239
1240static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1241					struct exynos_dsi_transfer *xfer)
1242{
1243	unsigned long flags;
1244	bool stopped;
1245
1246	xfer->tx_done = 0;
1247	xfer->rx_done = 0;
1248	xfer->result = -ETIMEDOUT;
1249	init_completion(&xfer->completed);
1250
1251	spin_lock_irqsave(&dsi->transfer_lock, flags);
1252
1253	stopped = list_empty(&dsi->transfer_list);
1254	list_add_tail(&xfer->list, &dsi->transfer_list);
1255
1256	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1257
1258	if (stopped)
1259		exynos_dsi_transfer_start(dsi);
1260
1261	wait_for_completion_timeout(&xfer->completed,
1262				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1263	if (xfer->result == -ETIMEDOUT) {
1264		struct mipi_dsi_packet *pkt = &xfer->packet;
1265		exynos_dsi_remove_transfer(dsi, xfer);
1266		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1267			(int)pkt->payload_length, pkt->payload);
1268		return -ETIMEDOUT;
1269	}
1270
1271	/* Also covers hardware timeout condition */
1272	return xfer->result;
1273}
1274
1275static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1276{
1277	struct exynos_dsi *dsi = dev_id;
1278	u32 status;
1279
1280	status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1281	if (!status) {
1282		static unsigned long int j;
1283		if (printk_timed_ratelimit(&j, 500))
1284			dev_warn(dsi->dev, "spurious interrupt\n");
1285		return IRQ_HANDLED;
1286	}
1287	exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1288
1289	if (status & DSIM_INT_SW_RST_RELEASE) {
1290		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1291			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |
1292			DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);
1293		exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1294		complete(&dsi->completed);
1295		return IRQ_HANDLED;
1296	}
1297
1298	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1299			DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))
1300		return IRQ_HANDLED;
1301
1302	if (exynos_dsi_transfer_finish(dsi))
1303		exynos_dsi_transfer_start(dsi);
1304
1305	return IRQ_HANDLED;
1306}
1307
1308static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1309{
1310	struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1311	struct drm_encoder *encoder = &dsi->encoder;
1312
1313	if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1314		exynos_drm_crtc_te_handler(encoder->crtc);
1315
1316	return IRQ_HANDLED;
1317}
1318
1319static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1320{
1321	enable_irq(dsi->irq);
1322
1323	if (gpio_is_valid(dsi->te_gpio))
1324		enable_irq(gpio_to_irq(dsi->te_gpio));
1325}
1326
1327static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1328{
1329	if (gpio_is_valid(dsi->te_gpio))
1330		disable_irq(gpio_to_irq(dsi->te_gpio));
1331
1332	disable_irq(dsi->irq);
1333}
1334
1335static int exynos_dsi_init(struct exynos_dsi *dsi)
1336{
1337	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1338
1339	exynos_dsi_reset(dsi);
1340	exynos_dsi_enable_irq(dsi);
1341
1342	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1343		exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1344
1345	exynos_dsi_enable_clock(dsi);
1346	if (driver_data->wait_for_reset)
1347		exynos_dsi_wait_for_reset(dsi);
1348	exynos_dsi_set_phy_ctrl(dsi);
1349	exynos_dsi_init_link(dsi);
1350
1351	return 0;
1352}
1353
1354static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
 
1355{
1356	int ret;
1357	int te_gpio_irq;
1358
1359	dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
 
 
 
1360	if (!gpio_is_valid(dsi->te_gpio)) {
1361		dev_err(dsi->dev, "no te-gpios specified\n");
1362		ret = dsi->te_gpio;
 
1363		goto out;
1364	}
1365
1366	ret = gpio_request(dsi->te_gpio, "te_gpio");
1367	if (ret) {
1368		dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1369		goto out;
1370	}
1371
1372	te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1373	irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1374
1375	ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1376					IRQF_TRIGGER_RISING, "TE", dsi);
1377	if (ret) {
1378		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1379		gpio_free(dsi->te_gpio);
1380		goto out;
1381	}
1382
1383out:
1384	return ret;
1385}
1386
1387static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1388{
1389	if (gpio_is_valid(dsi->te_gpio)) {
1390		free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1391		gpio_free(dsi->te_gpio);
1392		dsi->te_gpio = -ENOENT;
1393	}
1394}
1395
1396static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1397				  struct mipi_dsi_device *device)
1398{
1399	struct exynos_dsi *dsi = host_to_dsi(host);
1400
1401	dsi->lanes = device->lanes;
1402	dsi->format = device->format;
1403	dsi->mode_flags = device->mode_flags;
1404	dsi->panel_node = device->dev.of_node;
1405
1406	/*
1407	 * This is a temporary solution and should be made by more generic way.
1408	 *
1409	 * If attached panel device is for command mode one, dsi should register
1410	 * TE interrupt handler.
1411	 */
1412	if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1413		int ret = exynos_dsi_register_te_irq(dsi);
1414
1415		if (ret)
1416			return ret;
1417	}
1418
1419	if (dsi->connector.dev)
1420		drm_helper_hpd_irq_event(dsi->connector.dev);
1421
1422	return 0;
1423}
1424
1425static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1426				  struct mipi_dsi_device *device)
1427{
1428	struct exynos_dsi *dsi = host_to_dsi(host);
1429
1430	exynos_dsi_unregister_te_irq(dsi);
1431
1432	dsi->panel_node = NULL;
1433
1434	if (dsi->connector.dev)
1435		drm_helper_hpd_irq_event(dsi->connector.dev);
1436
1437	return 0;
1438}
1439
1440static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1441				        const struct mipi_dsi_msg *msg)
1442{
1443	struct exynos_dsi *dsi = host_to_dsi(host);
1444	struct exynos_dsi_transfer xfer;
1445	int ret;
1446
1447	if (!(dsi->state & DSIM_STATE_ENABLED))
1448		return -EINVAL;
1449
1450	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1451		ret = exynos_dsi_init(dsi);
1452		if (ret)
1453			return ret;
1454		dsi->state |= DSIM_STATE_INITIALIZED;
1455	}
1456
1457	ret = mipi_dsi_create_packet(&xfer.packet, msg);
1458	if (ret < 0)
1459		return ret;
1460
1461	xfer.rx_len = msg->rx_len;
1462	xfer.rx_payload = msg->rx_buf;
1463	xfer.flags = msg->flags;
1464
1465	ret = exynos_dsi_transfer(dsi, &xfer);
1466	return (ret < 0) ? ret : xfer.rx_done;
1467}
1468
1469static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1470	.attach = exynos_dsi_host_attach,
1471	.detach = exynos_dsi_host_detach,
1472	.transfer = exynos_dsi_host_transfer,
1473};
1474
1475static void exynos_dsi_enable(struct drm_encoder *encoder)
1476{
1477	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
 
1478	int ret;
1479
1480	if (dsi->state & DSIM_STATE_ENABLED)
1481		return;
1482
1483	pm_runtime_get_sync(dsi->dev);
 
 
 
 
1484
1485	dsi->state |= DSIM_STATE_ENABLED;
1486
1487	ret = drm_panel_prepare(dsi->panel);
1488	if (ret < 0) {
1489		dsi->state &= ~DSIM_STATE_ENABLED;
1490		pm_runtime_put_sync(dsi->dev);
1491		return;
 
 
 
 
 
1492	}
1493
1494	exynos_dsi_set_display_mode(dsi);
1495	exynos_dsi_set_display_enable(dsi, true);
1496
1497	ret = drm_panel_enable(dsi->panel);
1498	if (ret < 0) {
1499		dsi->state &= ~DSIM_STATE_ENABLED;
1500		exynos_dsi_set_display_enable(dsi, false);
1501		drm_panel_unprepare(dsi->panel);
1502		pm_runtime_put_sync(dsi->dev);
1503		return;
 
 
1504	}
1505
1506	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
 
 
 
 
 
 
 
 
 
1507}
1508
1509static void exynos_dsi_disable(struct drm_encoder *encoder)
1510{
1511	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
 
1512
1513	if (!(dsi->state & DSIM_STATE_ENABLED))
1514		return;
1515
1516	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1517
1518	drm_panel_disable(dsi->panel);
 
 
 
 
 
 
1519	exynos_dsi_set_display_enable(dsi, false);
1520	drm_panel_unprepare(dsi->panel);
1521
1522	dsi->state &= ~DSIM_STATE_ENABLED;
 
 
 
1523
 
1524	pm_runtime_put_sync(dsi->dev);
1525}
1526
1527static enum drm_connector_status
1528exynos_dsi_detect(struct drm_connector *connector, bool force)
1529{
1530	struct exynos_dsi *dsi = connector_to_dsi(connector);
1531
1532	if (!dsi->panel) {
1533		dsi->panel = of_drm_find_panel(dsi->panel_node);
1534		if (dsi->panel)
1535			drm_panel_attach(dsi->panel, &dsi->connector);
1536	} else if (!dsi->panel_node) {
1537		struct drm_encoder *encoder;
1538
1539		encoder = platform_get_drvdata(to_platform_device(dsi->dev));
1540		exynos_dsi_disable(encoder);
1541		drm_panel_detach(dsi->panel);
1542		dsi->panel = NULL;
1543	}
1544
1545	if (dsi->panel)
1546		return connector_status_connected;
1547
1548	return connector_status_disconnected;
1549}
1550
1551static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1552{
1553	drm_connector_unregister(connector);
1554	drm_connector_cleanup(connector);
1555	connector->dev = NULL;
1556}
1557
1558static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1559	.dpms = drm_atomic_helper_connector_dpms,
1560	.detect = exynos_dsi_detect,
1561	.fill_modes = drm_helper_probe_single_connector_modes,
1562	.destroy = exynos_dsi_connector_destroy,
1563	.reset = drm_atomic_helper_connector_reset,
1564	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1565	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1566};
1567
1568static int exynos_dsi_get_modes(struct drm_connector *connector)
1569{
1570	struct exynos_dsi *dsi = connector_to_dsi(connector);
1571
1572	if (dsi->panel)
1573		return dsi->panel->funcs->get_modes(dsi->panel);
1574
1575	return 0;
1576}
1577
1578static struct drm_encoder *
1579exynos_dsi_best_encoder(struct drm_connector *connector)
1580{
1581	struct exynos_dsi *dsi = connector_to_dsi(connector);
1582
1583	return &dsi->encoder;
1584}
1585
1586static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1587	.get_modes = exynos_dsi_get_modes,
1588	.best_encoder = exynos_dsi_best_encoder,
1589};
1590
1591static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1592{
1593	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1594	struct drm_connector *connector = &dsi->connector;
 
1595	int ret;
1596
1597	connector->polled = DRM_CONNECTOR_POLL_HPD;
1598
1599	ret = drm_connector_init(encoder->dev, connector,
1600				 &exynos_dsi_connector_funcs,
1601				 DRM_MODE_CONNECTOR_DSI);
1602	if (ret) {
1603		DRM_ERROR("Failed to initialize connector with drm\n");
 
1604		return ret;
1605	}
1606
 
1607	drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1608	drm_connector_register(connector);
1609	drm_mode_connector_attach_encoder(connector, encoder);
 
1610
 
 
1611	return 0;
1612}
1613
1614static void exynos_dsi_mode_set(struct drm_encoder *encoder,
1615				struct drm_display_mode *mode,
1616				struct drm_display_mode *adjusted_mode)
1617{
1618	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1619	struct videomode *vm = &dsi->vm;
1620	struct drm_display_mode *m = adjusted_mode;
1621
1622	vm->hactive = m->hdisplay;
1623	vm->vactive = m->vdisplay;
1624	vm->vfront_porch = m->vsync_start - m->vdisplay;
1625	vm->vback_porch = m->vtotal - m->vsync_end;
1626	vm->vsync_len = m->vsync_end - m->vsync_start;
1627	vm->hfront_porch = m->hsync_start - m->hdisplay;
1628	vm->hback_porch = m->htotal - m->hsync_end;
1629	vm->hsync_len = m->hsync_end - m->hsync_start;
1630}
1631
1632static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1633	.mode_set = exynos_dsi_mode_set,
1634	.enable = exynos_dsi_enable,
1635	.disable = exynos_dsi_disable,
1636};
1637
1638static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = {
1639	.destroy = drm_encoder_cleanup,
1640};
1641
1642MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1643
1644/* of_* functions will be removed after merge of of_graph patches */
1645static struct device_node *
1646of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1647{
1648	struct device_node *np;
1649
1650	for_each_child_of_node(parent, np) {
1651		u32 r;
1652
1653		if (!np->name || of_node_cmp(np->name, name))
1654			continue;
 
 
 
 
 
 
 
 
 
 
 
 
 
1655
1656		if (of_property_read_u32(np, "reg", &r) < 0)
1657			r = 0;
 
 
 
 
1658
1659		if (reg == r)
1660			break;
 
 
 
 
 
 
 
 
1661	}
1662
1663	return np;
 
 
 
 
 
 
 
 
 
 
 
 
 
1664}
1665
1666static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1667						    u32 reg)
1668{
1669	struct device_node *ports, *port;
 
1670
1671	ports = of_get_child_by_name(parent, "ports");
1672	if (ports)
1673		parent = ports;
 
 
 
 
 
 
 
 
 
1674
1675	port = of_get_child_by_name_reg(parent, "port", reg);
 
1676
1677	of_node_put(ports);
1678
1679	return port;
1680}
1681
1682static struct device_node *
1683of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1684{
1685	return of_get_child_by_name_reg(port, "endpoint", reg);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1686}
1687
 
 
 
 
 
 
1688static int exynos_dsi_of_read_u32(const struct device_node *np,
1689				  const char *propname, u32 *out_value)
1690{
1691	int ret = of_property_read_u32(np, propname, out_value);
1692
1693	if (ret < 0)
1694		pr_err("%s: failed to get '%s' property\n", np->full_name,
1695		       propname);
1696
1697	return ret;
1698}
1699
1700enum {
1701	DSI_PORT_IN,
1702	DSI_PORT_OUT
1703};
1704
1705static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1706{
1707	struct device *dev = dsi->dev;
1708	struct device_node *node = dev->of_node;
1709	struct device_node *port, *ep;
1710	int ret;
1711
1712	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1713				     &dsi->pll_clk_rate);
1714	if (ret < 0)
1715		return ret;
1716
1717	port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1718	if (!port) {
1719		dev_err(dev, "no output port specified\n");
1720		return -EINVAL;
1721	}
1722
1723	ep = of_graph_get_endpoint_by_reg(port, 0);
1724	of_node_put(port);
1725	if (!ep) {
1726		dev_err(dev, "no endpoint specified in output port\n");
1727		return -EINVAL;
1728	}
1729
1730	ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1731				     &dsi->burst_clk_rate);
1732	if (ret < 0)
1733		goto end;
1734
1735	ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1736				     &dsi->esc_clk_rate);
1737	if (ret < 0)
1738		goto end;
1739
1740	of_node_put(ep);
1741
1742	ep = of_graph_get_next_endpoint(node, NULL);
1743	if (!ep) {
1744		ret = -EINVAL;
1745		goto end;
1746	}
1747
1748	dsi->bridge_node = of_graph_get_remote_port_parent(ep);
1749	if (!dsi->bridge_node) {
1750		ret = -EINVAL;
1751		goto end;
1752	}
1753end:
1754	of_node_put(ep);
1755
1756	return ret;
1757}
1758
1759static int exynos_dsi_bind(struct device *dev, struct device *master,
1760				void *data)
1761{
1762	struct drm_encoder *encoder = dev_get_drvdata(dev);
1763	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1764	struct drm_device *drm_dev = data;
1765	struct drm_bridge *bridge;
 
1766	int ret;
1767
1768	ret = exynos_drm_crtc_get_pipe_from_type(drm_dev,
1769						  EXYNOS_DISPLAY_TYPE_LCD);
1770	if (ret < 0)
1771		return ret;
1772
1773	encoder->possible_crtcs = 1 << ret;
1774
1775	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
1776
1777	drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs,
1778			 DRM_MODE_ENCODER_TMDS, NULL);
1779
1780	drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1781
1782	ret = exynos_dsi_create_connector(encoder);
1783	if (ret) {
1784		DRM_ERROR("failed to create connector ret = %d\n", ret);
1785		drm_encoder_cleanup(encoder);
1786		return ret;
1787	}
1788
1789	bridge = of_drm_find_bridge(dsi->bridge_node);
1790	if (bridge) {
1791		encoder->bridge = bridge;
1792		drm_bridge_attach(drm_dev, bridge);
 
 
1793	}
1794
1795	return mipi_dsi_host_register(&dsi->dsi_host);
1796}
1797
1798static void exynos_dsi_unbind(struct device *dev, struct device *master,
1799				void *data)
1800{
1801	struct drm_encoder *encoder = dev_get_drvdata(dev);
1802	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1803
1804	exynos_dsi_disable(encoder);
1805
1806	mipi_dsi_host_unregister(&dsi->dsi_host);
1807}
1808
1809static const struct component_ops exynos_dsi_component_ops = {
1810	.bind	= exynos_dsi_bind,
1811	.unbind	= exynos_dsi_unbind,
1812};
1813
1814static int exynos_dsi_probe(struct platform_device *pdev)
1815{
1816	struct device *dev = &pdev->dev;
1817	struct resource *res;
1818	struct exynos_dsi *dsi;
1819	int ret, i;
1820
1821	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1822	if (!dsi)
1823		return -ENOMEM;
1824
1825	/* To be checked as invalid one */
1826	dsi->te_gpio = -ENOENT;
1827
1828	init_completion(&dsi->completed);
1829	spin_lock_init(&dsi->transfer_lock);
1830	INIT_LIST_HEAD(&dsi->transfer_list);
 
1831
1832	dsi->dsi_host.ops = &exynos_dsi_ops;
1833	dsi->dsi_host.dev = dev;
1834
1835	dsi->dev = dev;
1836	dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1837
1838	ret = exynos_dsi_parse_dt(dsi);
1839	if (ret)
1840		return ret;
1841
1842	dsi->supplies[0].supply = "vddcore";
1843	dsi->supplies[1].supply = "vddio";
1844	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1845				      dsi->supplies);
1846	if (ret) {
1847		dev_info(dev, "failed to get regulators: %d\n", ret);
1848		return -EPROBE_DEFER;
1849	}
1850
1851	dsi->clks = devm_kzalloc(dev,
1852			sizeof(*dsi->clks) * dsi->driver_data->num_clks,
1853			GFP_KERNEL);
1854	if (!dsi->clks)
1855		return -ENOMEM;
1856
1857	for (i = 0; i < dsi->driver_data->num_clks; i++) {
1858		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1859		if (IS_ERR(dsi->clks[i])) {
1860			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1861				strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1862				i--;
1863				continue;
 
1864			}
1865
1866			dev_info(dev, "failed to get the clock: %s\n",
1867					clk_names[i]);
1868			return PTR_ERR(dsi->clks[i]);
1869		}
1870	}
1871
1872	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1873	dsi->reg_base = devm_ioremap_resource(dev, res);
1874	if (IS_ERR(dsi->reg_base)) {
1875		dev_err(dev, "failed to remap io region\n");
1876		return PTR_ERR(dsi->reg_base);
1877	}
1878
1879	dsi->phy = devm_phy_get(dev, "dsim");
1880	if (IS_ERR(dsi->phy)) {
1881		dev_info(dev, "failed to get dsim phy\n");
1882		return PTR_ERR(dsi->phy);
1883	}
1884
1885	dsi->irq = platform_get_irq(pdev, 0);
1886	if (dsi->irq < 0) {
1887		dev_err(dev, "failed to request dsi irq resource\n");
1888		return dsi->irq;
1889	}
1890
1891	irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1892	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1893					exynos_dsi_irq, IRQF_ONESHOT,
 
1894					dev_name(dev), dsi);
1895	if (ret) {
1896		dev_err(dev, "failed to request dsi irq\n");
1897		return ret;
1898	}
1899
1900	platform_set_drvdata(pdev, &dsi->encoder);
 
 
 
 
1901
1902	pm_runtime_enable(dev);
1903
1904	return component_add(dev, &exynos_dsi_component_ops);
 
 
 
 
 
 
 
 
 
1905}
1906
1907static int exynos_dsi_remove(struct platform_device *pdev)
1908{
1909	pm_runtime_disable(&pdev->dev);
1910
1911	component_del(&pdev->dev, &exynos_dsi_component_ops);
1912
1913	return 0;
1914}
1915
1916static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1917{
1918	struct drm_encoder *encoder = dev_get_drvdata(dev);
1919	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1920	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1921	int ret, i;
1922
1923	usleep_range(10000, 20000);
1924
1925	if (dsi->state & DSIM_STATE_INITIALIZED) {
1926		dsi->state &= ~DSIM_STATE_INITIALIZED;
1927
1928		exynos_dsi_disable_clock(dsi);
1929
1930		exynos_dsi_disable_irq(dsi);
1931	}
1932
1933	dsi->state &= ~DSIM_STATE_CMD_LPM;
1934
1935	phy_power_off(dsi->phy);
1936
1937	for (i = driver_data->num_clks - 1; i > -1; i--)
1938		clk_disable_unprepare(dsi->clks[i]);
1939
1940	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1941	if (ret < 0)
1942		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1943
1944	return 0;
1945}
1946
1947static int __maybe_unused exynos_dsi_resume(struct device *dev)
1948{
1949	struct drm_encoder *encoder = dev_get_drvdata(dev);
1950	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1951	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1952	int ret, i;
1953
1954	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1955	if (ret < 0) {
1956		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1957		return ret;
1958	}
1959
1960	for (i = 0; i < driver_data->num_clks; i++) {
1961		ret = clk_prepare_enable(dsi->clks[i]);
1962		if (ret < 0)
1963			goto err_clk;
1964	}
1965
1966	ret = phy_power_on(dsi->phy);
1967	if (ret < 0) {
1968		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1969		goto err_clk;
1970	}
1971
1972	return 0;
1973
1974err_clk:
1975	while (--i > -1)
1976		clk_disable_unprepare(dsi->clks[i]);
1977	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1978
1979	return ret;
1980}
1981
1982static const struct dev_pm_ops exynos_dsi_pm_ops = {
1983	SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
 
 
1984};
1985
1986struct platform_driver dsi_driver = {
1987	.probe = exynos_dsi_probe,
1988	.remove = exynos_dsi_remove,
1989	.driver = {
1990		   .name = "exynos-dsi",
1991		   .owner = THIS_MODULE,
1992		   .pm = &exynos_dsi_pm_ops,
1993		   .of_match_table = exynos_dsi_of_match,
1994	},
1995};
1996
1997MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1998MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1999MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
2000MODULE_LICENSE("GPL v2");