Loading...
1/**************************************************************************
2 *
3 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27/*
28 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
29 */
30
31#include <linux/export.h>
32#include <drm/drmP.h>
33
34#if defined(CONFIG_X86)
35#include <asm/smp.h>
36
37/*
38 * clflushopt is an unordered instruction which needs fencing with mfence or
39 * sfence to avoid ordering issues. For drm_clflush_page this fencing happens
40 * in the caller.
41 */
42static void
43drm_clflush_page(struct page *page)
44{
45 uint8_t *page_virtual;
46 unsigned int i;
47 const int size = boot_cpu_data.x86_clflush_size;
48
49 if (unlikely(page == NULL))
50 return;
51
52 page_virtual = kmap_atomic(page);
53 for (i = 0; i < PAGE_SIZE; i += size)
54 clflushopt(page_virtual + i);
55 kunmap_atomic(page_virtual);
56}
57
58static void drm_cache_flush_clflush(struct page *pages[],
59 unsigned long num_pages)
60{
61 unsigned long i;
62
63 mb();
64 for (i = 0; i < num_pages; i++)
65 drm_clflush_page(*pages++);
66 mb();
67}
68#endif
69
70void
71drm_clflush_pages(struct page *pages[], unsigned long num_pages)
72{
73
74#if defined(CONFIG_X86)
75 if (cpu_has_clflush) {
76 drm_cache_flush_clflush(pages, num_pages);
77 return;
78 }
79
80 if (wbinvd_on_all_cpus())
81 printk(KERN_ERR "Timed out waiting for cache flush.\n");
82
83#elif defined(__powerpc__)
84 unsigned long i;
85 for (i = 0; i < num_pages; i++) {
86 struct page *page = pages[i];
87 void *page_virtual;
88
89 if (unlikely(page == NULL))
90 continue;
91
92 page_virtual = kmap_atomic(page);
93 flush_dcache_range((unsigned long)page_virtual,
94 (unsigned long)page_virtual + PAGE_SIZE);
95 kunmap_atomic(page_virtual);
96 }
97#else
98 printk(KERN_ERR "Architecture has no drm_cache.c support\n");
99 WARN_ON_ONCE(1);
100#endif
101}
102EXPORT_SYMBOL(drm_clflush_pages);
103
104void
105drm_clflush_sg(struct sg_table *st)
106{
107#if defined(CONFIG_X86)
108 if (cpu_has_clflush) {
109 struct sg_page_iter sg_iter;
110
111 mb();
112 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
113 drm_clflush_page(sg_page_iter_page(&sg_iter));
114 mb();
115
116 return;
117 }
118
119 if (wbinvd_on_all_cpus())
120 printk(KERN_ERR "Timed out waiting for cache flush.\n");
121#else
122 printk(KERN_ERR "Architecture has no drm_cache.c support\n");
123 WARN_ON_ONCE(1);
124#endif
125}
126EXPORT_SYMBOL(drm_clflush_sg);
127
128void
129drm_clflush_virt_range(void *addr, unsigned long length)
130{
131#if defined(CONFIG_X86)
132 if (cpu_has_clflush) {
133 const int size = boot_cpu_data.x86_clflush_size;
134 void *end = addr + length;
135 addr = (void *)(((unsigned long)addr) & -size);
136 mb();
137 for (; addr < end; addr += size)
138 clflushopt(addr);
139 mb();
140 return;
141 }
142
143 if (wbinvd_on_all_cpus())
144 printk(KERN_ERR "Timed out waiting for cache flush.\n");
145#else
146 printk(KERN_ERR "Architecture has no drm_cache.c support\n");
147 WARN_ON_ONCE(1);
148#endif
149}
150EXPORT_SYMBOL(drm_clflush_virt_range);
1/**************************************************************************
2 *
3 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27/*
28 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
29 */
30
31#include <linux/dma-buf-map.h>
32#include <linux/export.h>
33#include <linux/highmem.h>
34#include <linux/mem_encrypt.h>
35#include <xen/xen.h>
36
37#include <drm/drm_cache.h>
38
39/* A small bounce buffer that fits on the stack. */
40#define MEMCPY_BOUNCE_SIZE 128
41
42#if defined(CONFIG_X86)
43#include <asm/smp.h>
44
45/*
46 * clflushopt is an unordered instruction which needs fencing with mfence or
47 * sfence to avoid ordering issues. For drm_clflush_page this fencing happens
48 * in the caller.
49 */
50static void
51drm_clflush_page(struct page *page)
52{
53 uint8_t *page_virtual;
54 unsigned int i;
55 const int size = boot_cpu_data.x86_clflush_size;
56
57 if (unlikely(page == NULL))
58 return;
59
60 page_virtual = kmap_atomic(page);
61 for (i = 0; i < PAGE_SIZE; i += size)
62 clflushopt(page_virtual + i);
63 kunmap_atomic(page_virtual);
64}
65
66static void drm_cache_flush_clflush(struct page *pages[],
67 unsigned long num_pages)
68{
69 unsigned long i;
70
71 mb(); /*Full memory barrier used before so that CLFLUSH is ordered*/
72 for (i = 0; i < num_pages; i++)
73 drm_clflush_page(*pages++);
74 mb(); /*Also used after CLFLUSH so that all cache is flushed*/
75}
76#endif
77
78/**
79 * drm_clflush_pages - Flush dcache lines of a set of pages.
80 * @pages: List of pages to be flushed.
81 * @num_pages: Number of pages in the array.
82 *
83 * Flush every data cache line entry that points to an address belonging
84 * to a page in the array.
85 */
86void
87drm_clflush_pages(struct page *pages[], unsigned long num_pages)
88{
89
90#if defined(CONFIG_X86)
91 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
92 drm_cache_flush_clflush(pages, num_pages);
93 return;
94 }
95
96 if (wbinvd_on_all_cpus())
97 pr_err("Timed out waiting for cache flush\n");
98
99#elif defined(__powerpc__)
100 unsigned long i;
101
102 for (i = 0; i < num_pages; i++) {
103 struct page *page = pages[i];
104 void *page_virtual;
105
106 if (unlikely(page == NULL))
107 continue;
108
109 page_virtual = kmap_atomic(page);
110 flush_dcache_range((unsigned long)page_virtual,
111 (unsigned long)page_virtual + PAGE_SIZE);
112 kunmap_atomic(page_virtual);
113 }
114#else
115 pr_err("Architecture has no drm_cache.c support\n");
116 WARN_ON_ONCE(1);
117#endif
118}
119EXPORT_SYMBOL(drm_clflush_pages);
120
121/**
122 * drm_clflush_sg - Flush dcache lines pointing to a scather-gather.
123 * @st: struct sg_table.
124 *
125 * Flush every data cache line entry that points to an address in the
126 * sg.
127 */
128void
129drm_clflush_sg(struct sg_table *st)
130{
131#if defined(CONFIG_X86)
132 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
133 struct sg_page_iter sg_iter;
134
135 mb(); /*CLFLUSH is ordered only by using memory barriers*/
136 for_each_sgtable_page(st, &sg_iter, 0)
137 drm_clflush_page(sg_page_iter_page(&sg_iter));
138 mb(); /*Make sure that all cache line entry is flushed*/
139
140 return;
141 }
142
143 if (wbinvd_on_all_cpus())
144 pr_err("Timed out waiting for cache flush\n");
145#else
146 pr_err("Architecture has no drm_cache.c support\n");
147 WARN_ON_ONCE(1);
148#endif
149}
150EXPORT_SYMBOL(drm_clflush_sg);
151
152/**
153 * drm_clflush_virt_range - Flush dcache lines of a region
154 * @addr: Initial kernel memory address.
155 * @length: Region size.
156 *
157 * Flush every data cache line entry that points to an address in the
158 * region requested.
159 */
160void
161drm_clflush_virt_range(void *addr, unsigned long length)
162{
163#if defined(CONFIG_X86)
164 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
165 const int size = boot_cpu_data.x86_clflush_size;
166 void *end = addr + length;
167
168 addr = (void *)(((unsigned long)addr) & -size);
169 mb(); /*CLFLUSH is only ordered with a full memory barrier*/
170 for (; addr < end; addr += size)
171 clflushopt(addr);
172 clflushopt(end - 1); /* force serialisation */
173 mb(); /*Ensure that evry data cache line entry is flushed*/
174 return;
175 }
176
177 if (wbinvd_on_all_cpus())
178 pr_err("Timed out waiting for cache flush\n");
179#else
180 pr_err("Architecture has no drm_cache.c support\n");
181 WARN_ON_ONCE(1);
182#endif
183}
184EXPORT_SYMBOL(drm_clflush_virt_range);
185
186bool drm_need_swiotlb(int dma_bits)
187{
188 struct resource *tmp;
189 resource_size_t max_iomem = 0;
190
191 /*
192 * Xen paravirtual hosts require swiotlb regardless of requested dma
193 * transfer size.
194 *
195 * NOTE: Really, what it requires is use of the dma_alloc_coherent
196 * allocator used in ttm_dma_populate() instead of
197 * ttm_populate_and_map_pages(), which bounce buffers so much in
198 * Xen it leads to swiotlb buffer exhaustion.
199 */
200 if (xen_pv_domain())
201 return true;
202
203 /*
204 * Enforce dma_alloc_coherent when memory encryption is active as well
205 * for the same reasons as for Xen paravirtual hosts.
206 */
207 if (mem_encrypt_active())
208 return true;
209
210 for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling)
211 max_iomem = max(max_iomem, tmp->end);
212
213 return max_iomem > ((u64)1 << dma_bits);
214}
215EXPORT_SYMBOL(drm_need_swiotlb);
216
217static void memcpy_fallback(struct dma_buf_map *dst,
218 const struct dma_buf_map *src,
219 unsigned long len)
220{
221 if (!dst->is_iomem && !src->is_iomem) {
222 memcpy(dst->vaddr, src->vaddr, len);
223 } else if (!src->is_iomem) {
224 dma_buf_map_memcpy_to(dst, src->vaddr, len);
225 } else if (!dst->is_iomem) {
226 memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
227 } else {
228 /*
229 * Bounce size is not performance tuned, but using a
230 * bounce buffer like this is significantly faster than
231 * resorting to ioreadxx() + iowritexx().
232 */
233 char bounce[MEMCPY_BOUNCE_SIZE];
234 void __iomem *_src = src->vaddr_iomem;
235 void __iomem *_dst = dst->vaddr_iomem;
236
237 while (len >= MEMCPY_BOUNCE_SIZE) {
238 memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
239 memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
240 _src += MEMCPY_BOUNCE_SIZE;
241 _dst += MEMCPY_BOUNCE_SIZE;
242 len -= MEMCPY_BOUNCE_SIZE;
243 }
244 if (len) {
245 memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
246 memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
247 }
248 }
249}
250
251#ifdef CONFIG_X86
252
253static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
254
255static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
256{
257 kernel_fpu_begin();
258
259 while (len >= 4) {
260 asm("movntdqa (%0), %%xmm0\n"
261 "movntdqa 16(%0), %%xmm1\n"
262 "movntdqa 32(%0), %%xmm2\n"
263 "movntdqa 48(%0), %%xmm3\n"
264 "movaps %%xmm0, (%1)\n"
265 "movaps %%xmm1, 16(%1)\n"
266 "movaps %%xmm2, 32(%1)\n"
267 "movaps %%xmm3, 48(%1)\n"
268 :: "r" (src), "r" (dst) : "memory");
269 src += 64;
270 dst += 64;
271 len -= 4;
272 }
273 while (len--) {
274 asm("movntdqa (%0), %%xmm0\n"
275 "movaps %%xmm0, (%1)\n"
276 :: "r" (src), "r" (dst) : "memory");
277 src += 16;
278 dst += 16;
279 }
280
281 kernel_fpu_end();
282}
283
284/*
285 * __drm_memcpy_from_wc copies @len bytes from @src to @dst using
286 * non-temporal instructions where available. Note that all arguments
287 * (@src, @dst) must be aligned to 16 bytes and @len must be a multiple
288 * of 16.
289 */
290static void __drm_memcpy_from_wc(void *dst, const void *src, unsigned long len)
291{
292 if (unlikely(((unsigned long)dst | (unsigned long)src | len) & 15))
293 memcpy(dst, src, len);
294 else if (likely(len))
295 __memcpy_ntdqa(dst, src, len >> 4);
296}
297
298/**
299 * drm_memcpy_from_wc - Perform the fastest available memcpy from a source
300 * that may be WC.
301 * @dst: The destination pointer
302 * @src: The source pointer
303 * @len: The size of the area o transfer in bytes
304 *
305 * Tries an arch optimized memcpy for prefetching reading out of a WC region,
306 * and if no such beast is available, falls back to a normal memcpy.
307 */
308void drm_memcpy_from_wc(struct dma_buf_map *dst,
309 const struct dma_buf_map *src,
310 unsigned long len)
311{
312 if (WARN_ON(in_interrupt())) {
313 memcpy_fallback(dst, src, len);
314 return;
315 }
316
317 if (static_branch_likely(&has_movntdqa)) {
318 __drm_memcpy_from_wc(dst->is_iomem ?
319 (void __force *)dst->vaddr_iomem :
320 dst->vaddr,
321 src->is_iomem ?
322 (void const __force *)src->vaddr_iomem :
323 src->vaddr,
324 len);
325 return;
326 }
327
328 memcpy_fallback(dst, src, len);
329}
330EXPORT_SYMBOL(drm_memcpy_from_wc);
331
332/*
333 * drm_memcpy_init_early - One time initialization of the WC memcpy code
334 */
335void drm_memcpy_init_early(void)
336{
337 /*
338 * Some hypervisors (e.g. KVM) don't support VEX-prefix instructions
339 * emulation. So don't enable movntdqa in hypervisor guest.
340 */
341 if (static_cpu_has(X86_FEATURE_XMM4_1) &&
342 !boot_cpu_has(X86_FEATURE_HYPERVISOR))
343 static_branch_enable(&has_movntdqa);
344}
345#else
346void drm_memcpy_from_wc(struct dma_buf_map *dst,
347 const struct dma_buf_map *src,
348 unsigned long len)
349{
350 WARN_ON(in_interrupt());
351
352 memcpy_fallback(dst, src, len);
353}
354EXPORT_SYMBOL(drm_memcpy_from_wc);
355
356void drm_memcpy_init_early(void)
357{
358}
359#endif /* CONFIG_X86 */