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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <drm/drmP.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "atom.h"
35
36/*
37 * Rings
38 * Most engines on the GPU are fed via ring buffers. Ring
39 * buffers are areas of GPU accessible memory that the host
40 * writes commands into and the GPU reads commands out of.
41 * There is a rptr (read pointer) that determines where the
42 * GPU is currently reading, and a wptr (write pointer)
43 * which determines where the host has written. When the
44 * pointers are equal, the ring is idle. When the host
45 * writes commands to the ring buffer, it increments the
46 * wptr. The GPU then starts fetching commands and executes
47 * them until the pointers are equal again.
48 */
49static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
50
51/**
52 * amdgpu_ring_alloc - allocate space on the ring buffer
53 *
54 * @adev: amdgpu_device pointer
55 * @ring: amdgpu_ring structure holding ring information
56 * @ndw: number of dwords to allocate in the ring buffer
57 *
58 * Allocate @ndw dwords in the ring buffer (all asics).
59 * Returns 0 on success, error on failure.
60 */
61int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
62{
63 /* Align requested size with padding so unlock_commit can
64 * pad safely */
65 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
66
67 /* Make sure we aren't trying to allocate more space
68 * than the maximum for one submission
69 */
70 if (WARN_ON_ONCE(ndw > ring->max_dw))
71 return -ENOMEM;
72
73 ring->count_dw = ndw;
74 ring->wptr_old = ring->wptr;
75 return 0;
76}
77
78/** amdgpu_ring_insert_nop - insert NOP packets
79 *
80 * @ring: amdgpu_ring structure holding ring information
81 * @count: the number of NOP packets to insert
82 *
83 * This is the generic insert_nop function for rings except SDMA
84 */
85void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
86{
87 int i;
88
89 for (i = 0; i < count; i++)
90 amdgpu_ring_write(ring, ring->nop);
91}
92
93/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
94 *
95 * @ring: amdgpu_ring structure holding ring information
96 * @ib: IB to add NOP packets to
97 *
98 * This is the generic pad_ib function for rings except SDMA
99 */
100void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
101{
102 while (ib->length_dw & ring->align_mask)
103 ib->ptr[ib->length_dw++] = ring->nop;
104}
105
106/**
107 * amdgpu_ring_commit - tell the GPU to execute the new
108 * commands on the ring buffer
109 *
110 * @adev: amdgpu_device pointer
111 * @ring: amdgpu_ring structure holding ring information
112 *
113 * Update the wptr (write pointer) to tell the GPU to
114 * execute new commands on the ring buffer (all asics).
115 */
116void amdgpu_ring_commit(struct amdgpu_ring *ring)
117{
118 uint32_t count;
119
120 /* We pad to match fetch size */
121 count = ring->align_mask + 1 - (ring->wptr & ring->align_mask);
122 count %= ring->align_mask + 1;
123 ring->funcs->insert_nop(ring, count);
124
125 mb();
126 amdgpu_ring_set_wptr(ring);
127}
128
129/**
130 * amdgpu_ring_undo - reset the wptr
131 *
132 * @ring: amdgpu_ring structure holding ring information
133 *
134 * Reset the driver's copy of the wptr (all asics).
135 */
136void amdgpu_ring_undo(struct amdgpu_ring *ring)
137{
138 ring->wptr = ring->wptr_old;
139}
140
141/**
142 * amdgpu_ring_backup - Back up the content of a ring
143 *
144 * @ring: the ring we want to back up
145 *
146 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
147 */
148unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
149 uint32_t **data)
150{
151 unsigned size, ptr, i;
152
153 *data = NULL;
154
155 if (ring->ring_obj == NULL)
156 return 0;
157
158 /* it doesn't make sense to save anything if all fences are signaled */
159 if (!amdgpu_fence_count_emitted(ring))
160 return 0;
161
162 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
163
164 size = ring->wptr + (ring->ring_size / 4);
165 size -= ptr;
166 size &= ring->ptr_mask;
167 if (size == 0)
168 return 0;
169
170 /* and then save the content of the ring */
171 *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
172 if (!*data)
173 return 0;
174 for (i = 0; i < size; ++i) {
175 (*data)[i] = ring->ring[ptr++];
176 ptr &= ring->ptr_mask;
177 }
178
179 return size;
180}
181
182/**
183 * amdgpu_ring_restore - append saved commands to the ring again
184 *
185 * @ring: ring to append commands to
186 * @size: number of dwords we want to write
187 * @data: saved commands
188 *
189 * Allocates space on the ring and restore the previously saved commands.
190 */
191int amdgpu_ring_restore(struct amdgpu_ring *ring,
192 unsigned size, uint32_t *data)
193{
194 int i, r;
195
196 if (!size || !data)
197 return 0;
198
199 /* restore the saved ring content */
200 r = amdgpu_ring_alloc(ring, size);
201 if (r)
202 return r;
203
204 for (i = 0; i < size; ++i) {
205 amdgpu_ring_write(ring, data[i]);
206 }
207
208 amdgpu_ring_commit(ring);
209 kfree(data);
210 return 0;
211}
212
213/**
214 * amdgpu_ring_init - init driver ring struct.
215 *
216 * @adev: amdgpu_device pointer
217 * @ring: amdgpu_ring structure holding ring information
218 * @ring_size: size of the ring
219 * @nop: nop packet for this ring
220 *
221 * Initialize the driver information for the selected ring (all asics).
222 * Returns 0 on success, error on failure.
223 */
224int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
225 unsigned ring_size, u32 nop, u32 align_mask,
226 struct amdgpu_irq_src *irq_src, unsigned irq_type,
227 enum amdgpu_ring_type ring_type)
228{
229 u32 rb_bufsz;
230 int r;
231
232 if (ring->adev == NULL) {
233 if (adev->num_rings >= AMDGPU_MAX_RINGS)
234 return -EINVAL;
235
236 ring->adev = adev;
237 ring->idx = adev->num_rings++;
238 adev->rings[ring->idx] = ring;
239 r = amdgpu_fence_driver_init_ring(ring,
240 amdgpu_sched_hw_submission);
241 if (r)
242 return r;
243 }
244
245 r = amdgpu_wb_get(adev, &ring->rptr_offs);
246 if (r) {
247 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
248 return r;
249 }
250
251 r = amdgpu_wb_get(adev, &ring->wptr_offs);
252 if (r) {
253 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
254 return r;
255 }
256
257 r = amdgpu_wb_get(adev, &ring->fence_offs);
258 if (r) {
259 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
260 return r;
261 }
262
263 r = amdgpu_wb_get(adev, &ring->next_rptr_offs);
264 if (r) {
265 dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
266 return r;
267 }
268 ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4);
269 ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
270 spin_lock_init(&ring->fence_lock);
271 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
272 if (r) {
273 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
274 return r;
275 }
276
277 /* Align ring size */
278 rb_bufsz = order_base_2(ring_size / 8);
279 ring_size = (1 << (rb_bufsz + 1)) * 4;
280 ring->ring_size = ring_size;
281 ring->align_mask = align_mask;
282 ring->nop = nop;
283 ring->type = ring_type;
284
285 /* Allocate ring buffer */
286 if (ring->ring_obj == NULL) {
287 r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true,
288 AMDGPU_GEM_DOMAIN_GTT, 0,
289 NULL, NULL, &ring->ring_obj);
290 if (r) {
291 dev_err(adev->dev, "(%d) ring create failed\n", r);
292 return r;
293 }
294 r = amdgpu_bo_reserve(ring->ring_obj, false);
295 if (unlikely(r != 0))
296 return r;
297 r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT,
298 &ring->gpu_addr);
299 if (r) {
300 amdgpu_bo_unreserve(ring->ring_obj);
301 dev_err(adev->dev, "(%d) ring pin failed\n", r);
302 return r;
303 }
304 r = amdgpu_bo_kmap(ring->ring_obj,
305 (void **)&ring->ring);
306 amdgpu_bo_unreserve(ring->ring_obj);
307 if (r) {
308 dev_err(adev->dev, "(%d) ring map failed\n", r);
309 return r;
310 }
311 }
312 ring->ptr_mask = (ring->ring_size / 4) - 1;
313 ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4,
314 amdgpu_sched_hw_submission);
315
316 if (amdgpu_debugfs_ring_init(adev, ring)) {
317 DRM_ERROR("Failed to register debugfs file for rings !\n");
318 }
319 return 0;
320}
321
322/**
323 * amdgpu_ring_fini - tear down the driver ring struct.
324 *
325 * @adev: amdgpu_device pointer
326 * @ring: amdgpu_ring structure holding ring information
327 *
328 * Tear down the driver information for the selected ring (all asics).
329 */
330void amdgpu_ring_fini(struct amdgpu_ring *ring)
331{
332 int r;
333 struct amdgpu_bo *ring_obj;
334
335 ring_obj = ring->ring_obj;
336 ring->ready = false;
337 ring->ring = NULL;
338 ring->ring_obj = NULL;
339
340 amdgpu_wb_free(ring->adev, ring->fence_offs);
341 amdgpu_wb_free(ring->adev, ring->rptr_offs);
342 amdgpu_wb_free(ring->adev, ring->wptr_offs);
343 amdgpu_wb_free(ring->adev, ring->next_rptr_offs);
344
345 if (ring_obj) {
346 r = amdgpu_bo_reserve(ring_obj, false);
347 if (likely(r == 0)) {
348 amdgpu_bo_kunmap(ring_obj);
349 amdgpu_bo_unpin(ring_obj);
350 amdgpu_bo_unreserve(ring_obj);
351 }
352 amdgpu_bo_unref(&ring_obj);
353 }
354}
355
356/*
357 * Debugfs info
358 */
359#if defined(CONFIG_DEBUG_FS)
360
361static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
362{
363 struct drm_info_node *node = (struct drm_info_node *) m->private;
364 struct drm_device *dev = node->minor->dev;
365 struct amdgpu_device *adev = dev->dev_private;
366 int roffset = *(int*)node->info_ent->data;
367 struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
368
369 uint32_t rptr, wptr, rptr_next;
370 unsigned i;
371
372 wptr = amdgpu_ring_get_wptr(ring);
373 seq_printf(m, "wptr: 0x%08x [%5d]\n", wptr, wptr);
374
375 rptr = amdgpu_ring_get_rptr(ring);
376 rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
377
378 seq_printf(m, "rptr: 0x%08x [%5d]\n", rptr, rptr);
379
380 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
381 ring->wptr, ring->wptr);
382
383 if (!ring->ready)
384 return 0;
385
386 /* print 8 dw before current rptr as often it's the last executed
387 * packet that is the root issue
388 */
389 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
390 while (i != rptr) {
391 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
392 if (i == rptr)
393 seq_puts(m, " *");
394 if (i == rptr_next)
395 seq_puts(m, " #");
396 seq_puts(m, "\n");
397 i = (i + 1) & ring->ptr_mask;
398 }
399 while (i != wptr) {
400 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
401 if (i == rptr)
402 seq_puts(m, " *");
403 if (i == rptr_next)
404 seq_puts(m, " #");
405 seq_puts(m, "\n");
406 i = (i + 1) & ring->ptr_mask;
407 }
408 return 0;
409}
410
411/* TODO: clean this up !*/
412static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
413static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
414static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
415static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring);
416static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring);
417static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
418static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
419static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
420
421static struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
422 {"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
423 {"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
424 {"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
425 {"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index},
426 {"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index},
427 {"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index},
428 {"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index},
429 {"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index},
430};
431
432#endif
433
434static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
435{
436#if defined(CONFIG_DEBUG_FS)
437 unsigned i;
438 for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
439 struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
440 int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
441 struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
442 unsigned r;
443
444 if (other != ring)
445 continue;
446
447 r = amdgpu_debugfs_add_files(adev, info, 1);
448 if (r)
449 return r;
450 }
451#endif
452 return 0;
453}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/debugfs.h>
33
34#include <drm/amdgpu_drm.h>
35#include "amdgpu.h"
36#include "atom.h"
37
38/*
39 * Rings
40 * Most engines on the GPU are fed via ring buffers. Ring
41 * buffers are areas of GPU accessible memory that the host
42 * writes commands into and the GPU reads commands out of.
43 * There is a rptr (read pointer) that determines where the
44 * GPU is currently reading, and a wptr (write pointer)
45 * which determines where the host has written. When the
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
48 * wptr. The GPU then starts fetching commands and executes
49 * them until the pointers are equal again.
50 */
51
52/**
53 * amdgpu_ring_alloc - allocate space on the ring buffer
54 *
55 * @ring: amdgpu_ring structure holding ring information
56 * @ndw: number of dwords to allocate in the ring buffer
57 *
58 * Allocate @ndw dwords in the ring buffer (all asics).
59 * Returns 0 on success, error on failure.
60 */
61int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
62{
63 /* Align requested size with padding so unlock_commit can
64 * pad safely */
65 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
66
67 /* Make sure we aren't trying to allocate more space
68 * than the maximum for one submission
69 */
70 if (WARN_ON_ONCE(ndw > ring->max_dw))
71 return -ENOMEM;
72
73 ring->count_dw = ndw;
74 ring->wptr_old = ring->wptr;
75
76 if (ring->funcs->begin_use)
77 ring->funcs->begin_use(ring);
78
79 return 0;
80}
81
82/** amdgpu_ring_insert_nop - insert NOP packets
83 *
84 * @ring: amdgpu_ring structure holding ring information
85 * @count: the number of NOP packets to insert
86 *
87 * This is the generic insert_nop function for rings except SDMA
88 */
89void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
90{
91 int i;
92
93 for (i = 0; i < count; i++)
94 amdgpu_ring_write(ring, ring->funcs->nop);
95}
96
97/**
98 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets
99 *
100 * @ring: amdgpu_ring structure holding ring information
101 * @ib: IB to add NOP packets to
102 *
103 * This is the generic pad_ib function for rings except SDMA
104 */
105void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
106{
107 while (ib->length_dw & ring->funcs->align_mask)
108 ib->ptr[ib->length_dw++] = ring->funcs->nop;
109}
110
111/**
112 * amdgpu_ring_commit - tell the GPU to execute the new
113 * commands on the ring buffer
114 *
115 * @ring: amdgpu_ring structure holding ring information
116 *
117 * Update the wptr (write pointer) to tell the GPU to
118 * execute new commands on the ring buffer (all asics).
119 */
120void amdgpu_ring_commit(struct amdgpu_ring *ring)
121{
122 uint32_t count;
123
124 /* We pad to match fetch size */
125 count = ring->funcs->align_mask + 1 -
126 (ring->wptr & ring->funcs->align_mask);
127 count %= ring->funcs->align_mask + 1;
128 ring->funcs->insert_nop(ring, count);
129
130 mb();
131 amdgpu_ring_set_wptr(ring);
132
133 if (ring->funcs->end_use)
134 ring->funcs->end_use(ring);
135}
136
137/**
138 * amdgpu_ring_undo - reset the wptr
139 *
140 * @ring: amdgpu_ring structure holding ring information
141 *
142 * Reset the driver's copy of the wptr (all asics).
143 */
144void amdgpu_ring_undo(struct amdgpu_ring *ring)
145{
146 ring->wptr = ring->wptr_old;
147
148 if (ring->funcs->end_use)
149 ring->funcs->end_use(ring);
150}
151
152/**
153 * amdgpu_ring_init - init driver ring struct.
154 *
155 * @adev: amdgpu_device pointer
156 * @ring: amdgpu_ring structure holding ring information
157 * @max_dw: maximum number of dw for ring alloc
158 * @irq_src: interrupt source to use for this ring
159 * @irq_type: interrupt type to use for this ring
160 * @hw_prio: ring priority (NORMAL/HIGH)
161 * @sched_score: optional score atomic shared with other schedulers
162 *
163 * Initialize the driver information for the selected ring (all asics).
164 * Returns 0 on success, error on failure.
165 */
166int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
167 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
168 unsigned int irq_type, unsigned int hw_prio,
169 atomic_t *sched_score)
170{
171 int r;
172 int sched_hw_submission = amdgpu_sched_hw_submission;
173 u32 *num_sched;
174 u32 hw_ip;
175
176 /* Set the hw submission limit higher for KIQ because
177 * it's used for a number of gfx/compute tasks by both
178 * KFD and KGD which may have outstanding fences and
179 * it doesn't really use the gpu scheduler anyway;
180 * KIQ tasks get submitted directly to the ring.
181 */
182 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
183 sched_hw_submission = max(sched_hw_submission, 256);
184 else if (ring == &adev->sdma.instance[0].page)
185 sched_hw_submission = 256;
186
187 if (ring->adev == NULL) {
188 if (adev->num_rings >= AMDGPU_MAX_RINGS)
189 return -EINVAL;
190
191 ring->adev = adev;
192 ring->idx = adev->num_rings++;
193 adev->rings[ring->idx] = ring;
194 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission,
195 sched_score);
196 if (r)
197 return r;
198 }
199
200 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
201 if (r) {
202 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
203 return r;
204 }
205
206 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
207 if (r) {
208 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
209 return r;
210 }
211
212 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
213 if (r) {
214 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
215 return r;
216 }
217
218 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
219 if (r) {
220 dev_err(adev->dev,
221 "(%d) ring trail_fence_offs wb alloc failed\n", r);
222 return r;
223 }
224 ring->trail_fence_gpu_addr =
225 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
226 ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
227
228 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
229 if (r) {
230 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
231 return r;
232 }
233 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
234 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
235 /* always set cond_exec_polling to CONTINUE */
236 *ring->cond_exe_cpu_addr = 1;
237
238 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
239 if (r) {
240 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
241 return r;
242 }
243
244 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
245
246 ring->buf_mask = (ring->ring_size / 4) - 1;
247 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
248 0xffffffffffffffff : ring->buf_mask;
249 /* Allocate ring buffer */
250 if (ring->ring_obj == NULL) {
251 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
252 AMDGPU_GEM_DOMAIN_GTT,
253 &ring->ring_obj,
254 &ring->gpu_addr,
255 (void **)&ring->ring);
256 if (r) {
257 dev_err(adev->dev, "(%d) ring create failed\n", r);
258 return r;
259 }
260 amdgpu_ring_clear_ring(ring);
261 }
262
263 ring->max_dw = max_dw;
264 ring->hw_prio = hw_prio;
265
266 if (!ring->no_scheduler) {
267 hw_ip = ring->funcs->type;
268 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
269 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
270 &ring->sched;
271 }
272
273 return 0;
274}
275
276/**
277 * amdgpu_ring_fini - tear down the driver ring struct.
278 *
279 * @ring: amdgpu_ring structure holding ring information
280 *
281 * Tear down the driver information for the selected ring (all asics).
282 */
283void amdgpu_ring_fini(struct amdgpu_ring *ring)
284{
285
286 /* Not to finish a ring which is not initialized */
287 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
288 return;
289
290 ring->sched.ready = false;
291
292 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
293 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
294
295 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
296 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
297
298 amdgpu_bo_free_kernel(&ring->ring_obj,
299 &ring->gpu_addr,
300 (void **)&ring->ring);
301
302 dma_fence_put(ring->vmid_wait);
303 ring->vmid_wait = NULL;
304 ring->me = 0;
305
306 ring->adev->rings[ring->idx] = NULL;
307}
308
309/**
310 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
311 *
312 * @ring: ring to write to
313 * @reg0: register to write
314 * @reg1: register to wait on
315 * @ref: reference value to write/wait on
316 * @mask: mask to wait on
317 *
318 * Helper for rings that don't support write and wait in a
319 * single oneshot packet.
320 */
321void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
322 uint32_t reg0, uint32_t reg1,
323 uint32_t ref, uint32_t mask)
324{
325 amdgpu_ring_emit_wreg(ring, reg0, ref);
326 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
327}
328
329/**
330 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
331 *
332 * @ring: ring to try the recovery on
333 * @vmid: VMID we try to get going again
334 * @fence: timedout fence
335 *
336 * Tries to get a ring proceeding again when it is stuck.
337 */
338bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
339 struct dma_fence *fence)
340{
341 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
342
343 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
344 return false;
345
346 atomic_inc(&ring->adev->gpu_reset_counter);
347 while (!dma_fence_is_signaled(fence) &&
348 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
349 ring->funcs->soft_recovery(ring, vmid);
350
351 return dma_fence_is_signaled(fence);
352}
353
354/*
355 * Debugfs info
356 */
357#if defined(CONFIG_DEBUG_FS)
358
359/* Layout of file is 12 bytes consisting of
360 * - rptr
361 * - wptr
362 * - driver's copy of wptr
363 *
364 * followed by n-words of ring data
365 */
366static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
367 size_t size, loff_t *pos)
368{
369 struct amdgpu_ring *ring = file_inode(f)->i_private;
370 int r, i;
371 uint32_t value, result, early[3];
372
373 if (*pos & 3 || size & 3)
374 return -EINVAL;
375
376 result = 0;
377
378 if (*pos < 12) {
379 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
380 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
381 early[2] = ring->wptr & ring->buf_mask;
382 for (i = *pos / 4; i < 3 && size; i++) {
383 r = put_user(early[i], (uint32_t *)buf);
384 if (r)
385 return r;
386 buf += 4;
387 result += 4;
388 size -= 4;
389 *pos += 4;
390 }
391 }
392
393 while (size) {
394 if (*pos >= (ring->ring_size + 12))
395 return result;
396
397 value = ring->ring[(*pos - 12)/4];
398 r = put_user(value, (uint32_t *)buf);
399 if (r)
400 return r;
401 buf += 4;
402 result += 4;
403 size -= 4;
404 *pos += 4;
405 }
406
407 return result;
408}
409
410static const struct file_operations amdgpu_debugfs_ring_fops = {
411 .owner = THIS_MODULE,
412 .read = amdgpu_debugfs_ring_read,
413 .llseek = default_llseek
414};
415
416#endif
417
418int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
419 struct amdgpu_ring *ring)
420{
421#if defined(CONFIG_DEBUG_FS)
422 struct drm_minor *minor = adev_to_drm(adev)->primary;
423 struct dentry *ent, *root = minor->debugfs_root;
424 char name[32];
425
426 sprintf(name, "amdgpu_ring_%s", ring->name);
427
428 ent = debugfs_create_file(name,
429 S_IFREG | S_IRUGO, root,
430 ring, &amdgpu_debugfs_ring_fops);
431 if (IS_ERR(ent))
432 return PTR_ERR(ent);
433
434 i_size_write(ent->d_inode, ring->ring_size + 12);
435 ring->ent = ent;
436#endif
437 return 0;
438}
439
440/**
441 * amdgpu_ring_test_helper - tests ring and set sched readiness status
442 *
443 * @ring: ring to try the recovery on
444 *
445 * Tests ring and set sched readiness status
446 *
447 * Returns 0 on success, error on failure.
448 */
449int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
450{
451 struct amdgpu_device *adev = ring->adev;
452 int r;
453
454 r = amdgpu_ring_test_ring(ring);
455 if (r)
456 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
457 ring->name, r);
458 else
459 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
460 ring->name);
461
462 ring->sched.ready = !r;
463 return r;
464}