Loading...
Note: File does not exist in v4.6.
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26#ifndef __AMDGPU_GMC_H__
27#define __AMDGPU_GMC_H__
28
29#include <linux/types.h>
30
31#include "amdgpu_irq.h"
32
33/* VA hole for 48bit addresses on Vega10 */
34#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
35#define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
36
37/*
38 * Hardware is programmed as if the hole doesn't exists with start and end
39 * address values.
40 *
41 * This mask is used to remove the upper 16bits of the VA and so come up with
42 * the linear addr value.
43 */
44#define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
45
46/*
47 * Ring size as power of two for the log of recent faults.
48 */
49#define AMDGPU_GMC_FAULT_RING_ORDER 8
50#define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER)
51
52/*
53 * Hash size as power of two for the log of recent faults
54 */
55#define AMDGPU_GMC_FAULT_HASH_ORDER 8
56#define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
57
58/*
59 * Number of IH timestamp ticks until a fault is considered handled
60 */
61#define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL
62
63struct firmware;
64
65/*
66 * GMC page fault information
67 */
68struct amdgpu_gmc_fault {
69 uint64_t timestamp:48;
70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
71 atomic64_t key;
72};
73
74/*
75 * VMHUB structures, functions & helpers
76 */
77struct amdgpu_vmhub_funcs {
78 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
79 uint32_t status);
80 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
81};
82
83struct amdgpu_vmhub {
84 uint32_t ctx0_ptb_addr_lo32;
85 uint32_t ctx0_ptb_addr_hi32;
86 uint32_t vm_inv_eng0_sem;
87 uint32_t vm_inv_eng0_req;
88 uint32_t vm_inv_eng0_ack;
89 uint32_t vm_context0_cntl;
90 uint32_t vm_l2_pro_fault_status;
91 uint32_t vm_l2_pro_fault_cntl;
92
93 /*
94 * store the register distances between two continuous context domain
95 * and invalidation engine.
96 */
97 uint32_t ctx_distance;
98 uint32_t ctx_addr_distance; /* include LO32/HI32 */
99 uint32_t eng_distance;
100 uint32_t eng_addr_distance; /* include LO32/HI32 */
101
102 uint32_t vm_cntx_cntl_vm_fault;
103
104 const struct amdgpu_vmhub_funcs *vmhub_funcs;
105};
106
107/*
108 * GPU MC structures, functions & helpers
109 */
110struct amdgpu_gmc_funcs {
111 /* flush the vm tlb via mmio */
112 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
113 uint32_t vmhub, uint32_t flush_type);
114 /* flush the vm tlb via pasid */
115 int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
116 uint32_t flush_type, bool all_hub);
117 /* flush the vm tlb via ring */
118 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
119 uint64_t pd_addr);
120 /* Change the VMID -> PASID mapping */
121 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
122 unsigned pasid);
123 /* enable/disable PRT support */
124 void (*set_prt)(struct amdgpu_device *adev, bool enable);
125 /* map mtype to hardware flags */
126 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
127 /* get the pde for a given mc addr */
128 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
129 u64 *dst, u64 *flags);
130 /* get the pte flags to use for a BO VA mapping */
131 void (*get_vm_pte)(struct amdgpu_device *adev,
132 struct amdgpu_bo_va_mapping *mapping,
133 uint64_t *flags);
134 /* get the amount of memory used by the vbios for pre-OS console */
135 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
136};
137
138struct amdgpu_xgmi_ras_funcs {
139 int (*ras_late_init)(struct amdgpu_device *adev);
140 void (*ras_fini)(struct amdgpu_device *adev);
141 int (*query_ras_error_count)(struct amdgpu_device *adev,
142 void *ras_error_status);
143 void (*reset_ras_error_count)(struct amdgpu_device *adev);
144};
145
146struct amdgpu_xgmi {
147 /* from psp */
148 u64 node_id;
149 u64 hive_id;
150 /* fixed per family */
151 u64 node_segment_size;
152 /* physical node (0-3) */
153 unsigned physical_node_id;
154 /* number of nodes (0-4) */
155 unsigned num_physical_nodes;
156 /* gpu list in the same hive */
157 struct list_head head;
158 bool supported;
159 struct ras_common_if *ras_if;
160 bool connected_to_cpu;
161 bool pending_reset;
162 const struct amdgpu_xgmi_ras_funcs *ras_funcs;
163};
164
165struct amdgpu_gmc {
166 /* FB's physical address in MMIO space (for CPU to
167 * map FB). This is different compared to the agp/
168 * gart/vram_start/end field as the later is from
169 * GPU's view and aper_base is from CPU's view.
170 */
171 resource_size_t aper_size;
172 resource_size_t aper_base;
173 /* for some chips with <= 32MB we need to lie
174 * about vram size near mc fb location */
175 u64 mc_vram_size;
176 u64 visible_vram_size;
177 /* AGP aperture start and end in MC address space
178 * Driver find a hole in the MC address space
179 * to place AGP by setting MC_VM_AGP_BOT/TOP registers
180 * Under VMID0, logical address == MC address. AGP
181 * aperture maps to physical bus or IOVA addressed.
182 * AGP aperture is used to simulate FB in ZFB case.
183 * AGP aperture is also used for page table in system
184 * memory (mainly for APU).
185 *
186 */
187 u64 agp_size;
188 u64 agp_start;
189 u64 agp_end;
190 /* GART aperture start and end in MC address space
191 * Driver find a hole in the MC address space
192 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
193 * registers
194 * Under VMID0, logical address inside GART aperture will
195 * be translated through gpuvm gart page table to access
196 * paged system memory
197 */
198 u64 gart_size;
199 u64 gart_start;
200 u64 gart_end;
201 /* Frame buffer aperture of this GPU device. Different from
202 * fb_start (see below), this only covers the local GPU device.
203 * If driver uses FB aperture to access FB, driver get fb_start from
204 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start
205 * of this local device by adding an offset inside the XGMI hive.
206 * If driver uses GART table for VMID0 FB access, driver finds a hole in
207 * VMID0's virtual address space to place the SYSVM aperture inside
208 * which the first part is vram and the second part is gart (covering
209 * system ram).
210 */
211 u64 vram_start;
212 u64 vram_end;
213 /* FB region , it's same as local vram region in single GPU, in XGMI
214 * configuration, this region covers all GPUs in the same hive ,
215 * each GPU in the hive has the same view of this FB region .
216 * GPU0's vram starts at offset (0 * segment size) ,
217 * GPU1 starts at offset (1 * segment size), etc.
218 */
219 u64 fb_start;
220 u64 fb_end;
221 unsigned vram_width;
222 u64 real_vram_size;
223 int vram_mtrr;
224 u64 mc_mask;
225 const struct firmware *fw; /* MC firmware */
226 uint32_t fw_version;
227 struct amdgpu_irq_src vm_fault;
228 uint32_t vram_type;
229 uint8_t vram_vendor;
230 uint32_t srbm_soft_reset;
231 bool prt_warning;
232 uint32_t sdpif_register;
233 /* apertures */
234 u64 shared_aperture_start;
235 u64 shared_aperture_end;
236 u64 private_aperture_start;
237 u64 private_aperture_end;
238 /* protects concurrent invalidation */
239 spinlock_t invalidate_lock;
240 bool translate_further;
241 struct kfd_vm_fault_info *vm_fault_info;
242 atomic_t vm_fault_info_updated;
243
244 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
245 struct {
246 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
247 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
248 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
249
250 bool tmz_enabled;
251
252 const struct amdgpu_gmc_funcs *gmc_funcs;
253
254 struct amdgpu_xgmi xgmi;
255 struct amdgpu_irq_src ecc_irq;
256 int noretry;
257
258 uint32_t vmid0_page_table_block_size;
259 uint32_t vmid0_page_table_depth;
260 struct amdgpu_bo *pdb0_bo;
261 /* CPU kmapped address of pdb0*/
262 void *ptr_pdb0;
263};
264
265#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
266#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
267 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
268 ((adev), (pasid), (type), (allhub)))
269#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
270#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
271#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
272#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
273#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
274#define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
275
276/**
277 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
278 *
279 * @adev: amdgpu_device pointer
280 *
281 * Returns:
282 * True if full VRAM is visible through the BAR
283 */
284static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
285{
286 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
287
288 return (gmc->real_vram_size == gmc->visible_vram_size);
289}
290
291/**
292 * amdgpu_gmc_sign_extend - sign extend the given gmc address
293 *
294 * @addr: address to extend
295 */
296static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
297{
298 if (addr >= AMDGPU_GMC_HOLE_START)
299 addr |= AMDGPU_GMC_HOLE_END;
300
301 return addr;
302}
303
304int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
305void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
306 uint64_t *addr, uint64_t *flags);
307int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
308 uint32_t gpu_page_idx, uint64_t addr,
309 uint64_t flags);
310uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
311uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
312void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc);
313void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
314 u64 base);
315void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
316 struct amdgpu_gmc *mc);
317void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
318 struct amdgpu_gmc *mc);
319bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
320 uint16_t pasid, uint64_t timestamp);
321void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
322 uint16_t pasid);
323int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
324void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
325int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
326
327extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
328extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev);
329
330extern void
331amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
332 bool enable);
333
334void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
335void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev);
336
337void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
338uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
339uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
340uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
341#endif