Loading...
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/slab.h>
24
25#define PCH_EDGE_FALLING 0
26#define PCH_EDGE_RISING BIT(0)
27#define PCH_LEVEL_L BIT(1)
28#define PCH_LEVEL_H (BIT(0) | BIT(1))
29#define PCH_EDGE_BOTH BIT(2)
30#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define PCH_IRQ_BASE 24
33
34struct pch_regs {
35 u32 ien;
36 u32 istatus;
37 u32 idisp;
38 u32 iclr;
39 u32 imask;
40 u32 imaskclr;
41 u32 po;
42 u32 pi;
43 u32 pm;
44 u32 im0;
45 u32 im1;
46 u32 reserved[3];
47 u32 gpio_use_sel;
48 u32 reset;
49};
50
51enum pch_type_t {
52 INTEL_EG20T_PCH,
53 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
54 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
55};
56
57/* Specifies number of GPIO PINS */
58static int gpio_pins[] = {
59 [INTEL_EG20T_PCH] = 12,
60 [OKISEMI_ML7223m_IOH] = 8,
61 [OKISEMI_ML7223n_IOH] = 8,
62};
63
64/**
65 * struct pch_gpio_reg_data - The register store data.
66 * @ien_reg: To store contents of IEN register.
67 * @imask_reg: To store contents of IMASK register.
68 * @po_reg: To store contents of PO register.
69 * @pm_reg: To store contents of PM register.
70 * @im0_reg: To store contents of IM0 register.
71 * @im1_reg: To store contents of IM1 register.
72 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
73 * (Only ML7223 Bus-n)
74 */
75struct pch_gpio_reg_data {
76 u32 ien_reg;
77 u32 imask_reg;
78 u32 po_reg;
79 u32 pm_reg;
80 u32 im0_reg;
81 u32 im1_reg;
82 u32 gpio_use_sel_reg;
83};
84
85/**
86 * struct pch_gpio - GPIO private data structure.
87 * @base: PCI base address of Memory mapped I/O register.
88 * @reg: Memory mapped PCH GPIO register list.
89 * @dev: Pointer to device structure.
90 * @gpio: Data for GPIO infrastructure.
91 * @pch_gpio_reg: Memory mapped Register data is saved here
92 * when suspend.
93 * @lock: Used for register access protection
94 * @irq_base: Save base of IRQ number for interrupt
95 * @ioh: IOH ID
96 * @spinlock: Used for register access protection
97 */
98struct pch_gpio {
99 void __iomem *base;
100 struct pch_regs __iomem *reg;
101 struct device *dev;
102 struct gpio_chip gpio;
103 struct pch_gpio_reg_data pch_gpio_reg;
104 int irq_base;
105 enum pch_type_t ioh;
106 spinlock_t spinlock;
107};
108
109static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
110{
111 u32 reg_val;
112 struct pch_gpio *chip = gpiochip_get_data(gpio);
113 unsigned long flags;
114
115 spin_lock_irqsave(&chip->spinlock, flags);
116 reg_val = ioread32(&chip->reg->po);
117 if (val)
118 reg_val |= (1 << nr);
119 else
120 reg_val &= ~(1 << nr);
121
122 iowrite32(reg_val, &chip->reg->po);
123 spin_unlock_irqrestore(&chip->spinlock, flags);
124}
125
126static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
127{
128 struct pch_gpio *chip = gpiochip_get_data(gpio);
129
130 return (ioread32(&chip->reg->pi) >> nr) & 1;
131}
132
133static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
134 int val)
135{
136 struct pch_gpio *chip = gpiochip_get_data(gpio);
137 u32 pm;
138 u32 reg_val;
139 unsigned long flags;
140
141 spin_lock_irqsave(&chip->spinlock, flags);
142
143 reg_val = ioread32(&chip->reg->po);
144 if (val)
145 reg_val |= (1 << nr);
146 else
147 reg_val &= ~(1 << nr);
148 iowrite32(reg_val, &chip->reg->po);
149
150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
151 pm |= (1 << nr);
152 iowrite32(pm, &chip->reg->pm);
153
154 spin_unlock_irqrestore(&chip->spinlock, flags);
155
156 return 0;
157}
158
159static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
160{
161 struct pch_gpio *chip = gpiochip_get_data(gpio);
162 u32 pm;
163 unsigned long flags;
164
165 spin_lock_irqsave(&chip->spinlock, flags);
166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
167 pm &= ~(1 << nr);
168 iowrite32(pm, &chip->reg->pm);
169 spin_unlock_irqrestore(&chip->spinlock, flags);
170
171 return 0;
172}
173
174#ifdef CONFIG_PM
175/*
176 * Save register configuration and disable interrupts.
177 */
178static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
179{
180 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
181 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
182 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
183 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
184 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
185 if (chip->ioh == INTEL_EG20T_PCH)
186 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
187 if (chip->ioh == OKISEMI_ML7223n_IOH)
188 chip->pch_gpio_reg.gpio_use_sel_reg =\
189 ioread32(&chip->reg->gpio_use_sel);
190}
191
192/*
193 * This function restores the register configuration of the GPIO device.
194 */
195static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
196{
197 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
198 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
199 /* to store contents of PO register */
200 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
201 /* to store contents of PM register */
202 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
203 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
204 if (chip->ioh == INTEL_EG20T_PCH)
205 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
206 if (chip->ioh == OKISEMI_ML7223n_IOH)
207 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
208 &chip->reg->gpio_use_sel);
209}
210#endif
211
212static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
213{
214 struct pch_gpio *chip = gpiochip_get_data(gpio);
215 return chip->irq_base + offset;
216}
217
218static void pch_gpio_setup(struct pch_gpio *chip)
219{
220 struct gpio_chip *gpio = &chip->gpio;
221
222 gpio->label = dev_name(chip->dev);
223 gpio->parent = chip->dev;
224 gpio->owner = THIS_MODULE;
225 gpio->direction_input = pch_gpio_direction_input;
226 gpio->get = pch_gpio_get;
227 gpio->direction_output = pch_gpio_direction_output;
228 gpio->set = pch_gpio_set;
229 gpio->dbg_show = NULL;
230 gpio->base = -1;
231 gpio->ngpio = gpio_pins[chip->ioh];
232 gpio->can_sleep = false;
233 gpio->to_irq = pch_gpio_to_irq;
234}
235
236static int pch_irq_type(struct irq_data *d, unsigned int type)
237{
238 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
239 struct pch_gpio *chip = gc->private;
240 u32 im, im_pos, val;
241 u32 __iomem *im_reg;
242 unsigned long flags;
243 int ch, irq = d->irq;
244
245 ch = irq - chip->irq_base;
246 if (irq <= chip->irq_base + 7) {
247 im_reg = &chip->reg->im0;
248 im_pos = ch;
249 } else {
250 im_reg = &chip->reg->im1;
251 im_pos = ch - 8;
252 }
253 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
254 __func__, irq, type, ch, im_pos);
255
256 spin_lock_irqsave(&chip->spinlock, flags);
257
258 switch (type) {
259 case IRQ_TYPE_EDGE_RISING:
260 val = PCH_EDGE_RISING;
261 break;
262 case IRQ_TYPE_EDGE_FALLING:
263 val = PCH_EDGE_FALLING;
264 break;
265 case IRQ_TYPE_EDGE_BOTH:
266 val = PCH_EDGE_BOTH;
267 break;
268 case IRQ_TYPE_LEVEL_HIGH:
269 val = PCH_LEVEL_H;
270 break;
271 case IRQ_TYPE_LEVEL_LOW:
272 val = PCH_LEVEL_L;
273 break;
274 default:
275 goto unlock;
276 }
277
278 /* Set interrupt mode */
279 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
280 iowrite32(im | (val << (im_pos * 4)), im_reg);
281
282 /* And the handler */
283 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
284 irq_set_handler_locked(d, handle_level_irq);
285 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
286 irq_set_handler_locked(d, handle_edge_irq);
287
288unlock:
289 spin_unlock_irqrestore(&chip->spinlock, flags);
290 return 0;
291}
292
293static void pch_irq_unmask(struct irq_data *d)
294{
295 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
296 struct pch_gpio *chip = gc->private;
297
298 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
299}
300
301static void pch_irq_mask(struct irq_data *d)
302{
303 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
304 struct pch_gpio *chip = gc->private;
305
306 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
307}
308
309static void pch_irq_ack(struct irq_data *d)
310{
311 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312 struct pch_gpio *chip = gc->private;
313
314 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
315}
316
317static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
318{
319 struct pch_gpio *chip = dev_id;
320 u32 reg_val = ioread32(&chip->reg->istatus);
321 int i, ret = IRQ_NONE;
322
323 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
324 if (reg_val & BIT(i)) {
325 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
326 __func__, i, irq, reg_val);
327 generic_handle_irq(chip->irq_base + i);
328 ret = IRQ_HANDLED;
329 }
330 }
331 return ret;
332}
333
334static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
335 unsigned int irq_start, unsigned int num)
336{
337 struct irq_chip_generic *gc;
338 struct irq_chip_type *ct;
339
340 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
341 handle_simple_irq);
342 gc->private = chip;
343 ct = gc->chip_types;
344
345 ct->chip.irq_ack = pch_irq_ack;
346 ct->chip.irq_mask = pch_irq_mask;
347 ct->chip.irq_unmask = pch_irq_unmask;
348 ct->chip.irq_set_type = pch_irq_type;
349
350 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
351 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
352}
353
354static int pch_gpio_probe(struct pci_dev *pdev,
355 const struct pci_device_id *id)
356{
357 s32 ret;
358 struct pch_gpio *chip;
359 int irq_base;
360 u32 msk;
361
362 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
363 if (chip == NULL)
364 return -ENOMEM;
365
366 chip->dev = &pdev->dev;
367 ret = pci_enable_device(pdev);
368 if (ret) {
369 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
370 goto err_pci_enable;
371 }
372
373 ret = pci_request_regions(pdev, KBUILD_MODNAME);
374 if (ret) {
375 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
376 goto err_request_regions;
377 }
378
379 chip->base = pci_iomap(pdev, 1, 0);
380 if (!chip->base) {
381 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
382 ret = -ENOMEM;
383 goto err_iomap;
384 }
385
386 if (pdev->device == 0x8803)
387 chip->ioh = INTEL_EG20T_PCH;
388 else if (pdev->device == 0x8014)
389 chip->ioh = OKISEMI_ML7223m_IOH;
390 else if (pdev->device == 0x8043)
391 chip->ioh = OKISEMI_ML7223n_IOH;
392
393 chip->reg = chip->base;
394 pci_set_drvdata(pdev, chip);
395 spin_lock_init(&chip->spinlock);
396 pch_gpio_setup(chip);
397#ifdef CONFIG_OF_GPIO
398 chip->gpio.of_node = pdev->dev.of_node;
399#endif
400 ret = gpiochip_add_data(&chip->gpio, chip);
401 if (ret) {
402 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
403 goto err_gpiochip_add;
404 }
405
406 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
407 if (irq_base < 0) {
408 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
409 chip->irq_base = -1;
410 goto end;
411 }
412 chip->irq_base = irq_base;
413
414 /* Mask all interrupts, but enable them */
415 msk = (1 << gpio_pins[chip->ioh]) - 1;
416 iowrite32(msk, &chip->reg->imask);
417 iowrite32(msk, &chip->reg->ien);
418
419 ret = request_irq(pdev->irq, pch_gpio_handler,
420 IRQF_SHARED, KBUILD_MODNAME, chip);
421 if (ret != 0) {
422 dev_err(&pdev->dev,
423 "%s request_irq failed\n", __func__);
424 goto err_request_irq;
425 }
426
427 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
428
429end:
430 return 0;
431
432err_request_irq:
433 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
434 gpiochip_remove(&chip->gpio);
435
436err_gpiochip_add:
437 pci_iounmap(pdev, chip->base);
438
439err_iomap:
440 pci_release_regions(pdev);
441
442err_request_regions:
443 pci_disable_device(pdev);
444
445err_pci_enable:
446 kfree(chip);
447 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
448 return ret;
449}
450
451static void pch_gpio_remove(struct pci_dev *pdev)
452{
453 struct pch_gpio *chip = pci_get_drvdata(pdev);
454
455 if (chip->irq_base != -1) {
456 free_irq(pdev->irq, chip);
457
458 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
459 }
460
461 gpiochip_remove(&chip->gpio);
462 pci_iounmap(pdev, chip->base);
463 pci_release_regions(pdev);
464 pci_disable_device(pdev);
465 kfree(chip);
466}
467
468#ifdef CONFIG_PM
469static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
470{
471 s32 ret;
472 struct pch_gpio *chip = pci_get_drvdata(pdev);
473 unsigned long flags;
474
475 spin_lock_irqsave(&chip->spinlock, flags);
476 pch_gpio_save_reg_conf(chip);
477 spin_unlock_irqrestore(&chip->spinlock, flags);
478
479 ret = pci_save_state(pdev);
480 if (ret) {
481 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
482 return ret;
483 }
484 pci_disable_device(pdev);
485 pci_set_power_state(pdev, PCI_D0);
486 ret = pci_enable_wake(pdev, PCI_D0, 1);
487 if (ret)
488 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
489
490 return 0;
491}
492
493static int pch_gpio_resume(struct pci_dev *pdev)
494{
495 s32 ret;
496 struct pch_gpio *chip = pci_get_drvdata(pdev);
497 unsigned long flags;
498
499 ret = pci_enable_wake(pdev, PCI_D0, 0);
500
501 pci_set_power_state(pdev, PCI_D0);
502 ret = pci_enable_device(pdev);
503 if (ret) {
504 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
505 return ret;
506 }
507 pci_restore_state(pdev);
508
509 spin_lock_irqsave(&chip->spinlock, flags);
510 iowrite32(0x01, &chip->reg->reset);
511 iowrite32(0x00, &chip->reg->reset);
512 pch_gpio_restore_reg_conf(chip);
513 spin_unlock_irqrestore(&chip->spinlock, flags);
514
515 return 0;
516}
517#else
518#define pch_gpio_suspend NULL
519#define pch_gpio_resume NULL
520#endif
521
522#define PCI_VENDOR_ID_ROHM 0x10DB
523static const struct pci_device_id pch_gpio_pcidev_id[] = {
524 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
525 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
526 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
527 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
528 { 0, }
529};
530MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
531
532static struct pci_driver pch_gpio_driver = {
533 .name = "pch_gpio",
534 .id_table = pch_gpio_pcidev_id,
535 .probe = pch_gpio_probe,
536 .remove = pch_gpio_remove,
537 .suspend = pch_gpio_suspend,
538 .resume = pch_gpio_resume
539};
540
541module_pci_driver(pch_gpio_driver);
542
543MODULE_DESCRIPTION("PCH GPIO PCI Driver");
544MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/bits.h>
6#include <linux/gpio/driver.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13
14#define PCH_EDGE_FALLING 0
15#define PCH_EDGE_RISING 1
16#define PCH_LEVEL_L 2
17#define PCH_LEVEL_H 3
18#define PCH_EDGE_BOTH 4
19#define PCH_IM_MASK GENMASK(2, 0)
20
21#define PCH_IRQ_BASE 24
22
23struct pch_regs {
24 u32 ien;
25 u32 istatus;
26 u32 idisp;
27 u32 iclr;
28 u32 imask;
29 u32 imaskclr;
30 u32 po;
31 u32 pi;
32 u32 pm;
33 u32 im0;
34 u32 im1;
35 u32 reserved[3];
36 u32 gpio_use_sel;
37 u32 reset;
38};
39
40enum pch_type_t {
41 INTEL_EG20T_PCH,
42 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
43 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
44};
45
46/* Specifies number of GPIO PINS */
47static int gpio_pins[] = {
48 [INTEL_EG20T_PCH] = 12,
49 [OKISEMI_ML7223m_IOH] = 8,
50 [OKISEMI_ML7223n_IOH] = 8,
51};
52
53/**
54 * struct pch_gpio_reg_data - The register store data.
55 * @ien_reg: To store contents of IEN register.
56 * @imask_reg: To store contents of IMASK register.
57 * @po_reg: To store contents of PO register.
58 * @pm_reg: To store contents of PM register.
59 * @im0_reg: To store contents of IM0 register.
60 * @im1_reg: To store contents of IM1 register.
61 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
62 * (Only ML7223 Bus-n)
63 */
64struct pch_gpio_reg_data {
65 u32 ien_reg;
66 u32 imask_reg;
67 u32 po_reg;
68 u32 pm_reg;
69 u32 im0_reg;
70 u32 im1_reg;
71 u32 gpio_use_sel_reg;
72};
73
74/**
75 * struct pch_gpio - GPIO private data structure.
76 * @base: PCI base address of Memory mapped I/O register.
77 * @reg: Memory mapped PCH GPIO register list.
78 * @dev: Pointer to device structure.
79 * @gpio: Data for GPIO infrastructure.
80 * @pch_gpio_reg: Memory mapped Register data is saved here
81 * when suspend.
82 * @lock: Used for register access protection
83 * @irq_base: Save base of IRQ number for interrupt
84 * @ioh: IOH ID
85 * @spinlock: Used for register access protection
86 */
87struct pch_gpio {
88 void __iomem *base;
89 struct pch_regs __iomem *reg;
90 struct device *dev;
91 struct gpio_chip gpio;
92 struct pch_gpio_reg_data pch_gpio_reg;
93 int irq_base;
94 enum pch_type_t ioh;
95 spinlock_t spinlock;
96};
97
98static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
99{
100 u32 reg_val;
101 struct pch_gpio *chip = gpiochip_get_data(gpio);
102 unsigned long flags;
103
104 spin_lock_irqsave(&chip->spinlock, flags);
105 reg_val = ioread32(&chip->reg->po);
106 if (val)
107 reg_val |= BIT(nr);
108 else
109 reg_val &= ~BIT(nr);
110
111 iowrite32(reg_val, &chip->reg->po);
112 spin_unlock_irqrestore(&chip->spinlock, flags);
113}
114
115static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
116{
117 struct pch_gpio *chip = gpiochip_get_data(gpio);
118
119 return !!(ioread32(&chip->reg->pi) & BIT(nr));
120}
121
122static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
123 int val)
124{
125 struct pch_gpio *chip = gpiochip_get_data(gpio);
126 u32 pm;
127 u32 reg_val;
128 unsigned long flags;
129
130 spin_lock_irqsave(&chip->spinlock, flags);
131
132 reg_val = ioread32(&chip->reg->po);
133 if (val)
134 reg_val |= BIT(nr);
135 else
136 reg_val &= ~BIT(nr);
137 iowrite32(reg_val, &chip->reg->po);
138
139 pm = ioread32(&chip->reg->pm);
140 pm &= BIT(gpio_pins[chip->ioh]) - 1;
141 pm |= BIT(nr);
142 iowrite32(pm, &chip->reg->pm);
143
144 spin_unlock_irqrestore(&chip->spinlock, flags);
145
146 return 0;
147}
148
149static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
150{
151 struct pch_gpio *chip = gpiochip_get_data(gpio);
152 u32 pm;
153 unsigned long flags;
154
155 spin_lock_irqsave(&chip->spinlock, flags);
156 pm = ioread32(&chip->reg->pm);
157 pm &= BIT(gpio_pins[chip->ioh]) - 1;
158 pm &= ~BIT(nr);
159 iowrite32(pm, &chip->reg->pm);
160 spin_unlock_irqrestore(&chip->spinlock, flags);
161
162 return 0;
163}
164
165/*
166 * Save register configuration and disable interrupts.
167 */
168static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
169{
170 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
171 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
172 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
173 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
174 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
175 if (chip->ioh == INTEL_EG20T_PCH)
176 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
177 if (chip->ioh == OKISEMI_ML7223n_IOH)
178 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
179}
180
181/*
182 * This function restores the register configuration of the GPIO device.
183 */
184static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
185{
186 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
187 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
188 /* to store contents of PO register */
189 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
190 /* to store contents of PM register */
191 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
192 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
193 if (chip->ioh == INTEL_EG20T_PCH)
194 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
195 if (chip->ioh == OKISEMI_ML7223n_IOH)
196 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
197}
198
199static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
200{
201 struct pch_gpio *chip = gpiochip_get_data(gpio);
202
203 return chip->irq_base + offset;
204}
205
206static void pch_gpio_setup(struct pch_gpio *chip)
207{
208 struct gpio_chip *gpio = &chip->gpio;
209
210 gpio->label = dev_name(chip->dev);
211 gpio->parent = chip->dev;
212 gpio->owner = THIS_MODULE;
213 gpio->direction_input = pch_gpio_direction_input;
214 gpio->get = pch_gpio_get;
215 gpio->direction_output = pch_gpio_direction_output;
216 gpio->set = pch_gpio_set;
217 gpio->base = -1;
218 gpio->ngpio = gpio_pins[chip->ioh];
219 gpio->can_sleep = false;
220 gpio->to_irq = pch_gpio_to_irq;
221}
222
223static int pch_irq_type(struct irq_data *d, unsigned int type)
224{
225 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
226 struct pch_gpio *chip = gc->private;
227 u32 im, im_pos, val;
228 u32 __iomem *im_reg;
229 unsigned long flags;
230 int ch, irq = d->irq;
231
232 ch = irq - chip->irq_base;
233 if (irq < chip->irq_base + 8) {
234 im_reg = &chip->reg->im0;
235 im_pos = ch - 0;
236 } else {
237 im_reg = &chip->reg->im1;
238 im_pos = ch - 8;
239 }
240 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
241
242 switch (type) {
243 case IRQ_TYPE_EDGE_RISING:
244 val = PCH_EDGE_RISING;
245 break;
246 case IRQ_TYPE_EDGE_FALLING:
247 val = PCH_EDGE_FALLING;
248 break;
249 case IRQ_TYPE_EDGE_BOTH:
250 val = PCH_EDGE_BOTH;
251 break;
252 case IRQ_TYPE_LEVEL_HIGH:
253 val = PCH_LEVEL_H;
254 break;
255 case IRQ_TYPE_LEVEL_LOW:
256 val = PCH_LEVEL_L;
257 break;
258 default:
259 return 0;
260 }
261
262 spin_lock_irqsave(&chip->spinlock, flags);
263
264 /* Set interrupt mode */
265 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
266 iowrite32(im | (val << (im_pos * 4)), im_reg);
267
268 /* And the handler */
269 if (type & IRQ_TYPE_LEVEL_MASK)
270 irq_set_handler_locked(d, handle_level_irq);
271 else if (type & IRQ_TYPE_EDGE_BOTH)
272 irq_set_handler_locked(d, handle_edge_irq);
273
274 spin_unlock_irqrestore(&chip->spinlock, flags);
275 return 0;
276}
277
278static void pch_irq_unmask(struct irq_data *d)
279{
280 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
281 struct pch_gpio *chip = gc->private;
282
283 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
284}
285
286static void pch_irq_mask(struct irq_data *d)
287{
288 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
289 struct pch_gpio *chip = gc->private;
290
291 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
292}
293
294static void pch_irq_ack(struct irq_data *d)
295{
296 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
297 struct pch_gpio *chip = gc->private;
298
299 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
300}
301
302static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
303{
304 struct pch_gpio *chip = dev_id;
305 unsigned long reg_val = ioread32(&chip->reg->istatus);
306 int i;
307
308 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
309
310 reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
311
312 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
313 generic_handle_irq(chip->irq_base + i);
314
315 return IRQ_RETVAL(reg_val);
316}
317
318static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
319 unsigned int irq_start,
320 unsigned int num)
321{
322 struct irq_chip_generic *gc;
323 struct irq_chip_type *ct;
324 int rv;
325
326 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
327 chip->base, handle_simple_irq);
328 if (!gc)
329 return -ENOMEM;
330
331 gc->private = chip;
332 ct = gc->chip_types;
333
334 ct->chip.irq_ack = pch_irq_ack;
335 ct->chip.irq_mask = pch_irq_mask;
336 ct->chip.irq_unmask = pch_irq_unmask;
337 ct->chip.irq_set_type = pch_irq_type;
338
339 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
340 IRQ_GC_INIT_MASK_CACHE,
341 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
342
343 return rv;
344}
345
346static int pch_gpio_probe(struct pci_dev *pdev,
347 const struct pci_device_id *id)
348{
349 s32 ret;
350 struct pch_gpio *chip;
351 int irq_base;
352
353 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
354 if (chip == NULL)
355 return -ENOMEM;
356
357 chip->dev = &pdev->dev;
358 ret = pcim_enable_device(pdev);
359 if (ret) {
360 dev_err(&pdev->dev, "pci_enable_device FAILED");
361 return ret;
362 }
363
364 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
365 if (ret) {
366 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
367 return ret;
368 }
369
370 chip->base = pcim_iomap_table(pdev)[1];
371
372 if (pdev->device == 0x8803)
373 chip->ioh = INTEL_EG20T_PCH;
374 else if (pdev->device == 0x8014)
375 chip->ioh = OKISEMI_ML7223m_IOH;
376 else if (pdev->device == 0x8043)
377 chip->ioh = OKISEMI_ML7223n_IOH;
378
379 chip->reg = chip->base;
380 pci_set_drvdata(pdev, chip);
381 spin_lock_init(&chip->spinlock);
382 pch_gpio_setup(chip);
383
384 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
385 if (ret) {
386 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
387 return ret;
388 }
389
390 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
391 gpio_pins[chip->ioh], NUMA_NO_NODE);
392 if (irq_base < 0) {
393 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
394 chip->irq_base = -1;
395 return 0;
396 }
397 chip->irq_base = irq_base;
398
399 /* Mask all interrupts, but enable them */
400 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
401 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
402
403 ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
404 IRQF_SHARED, KBUILD_MODNAME, chip);
405 if (ret) {
406 dev_err(&pdev->dev, "request_irq failed\n");
407 return ret;
408 }
409
410 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
411}
412
413static int __maybe_unused pch_gpio_suspend(struct device *dev)
414{
415 struct pch_gpio *chip = dev_get_drvdata(dev);
416 unsigned long flags;
417
418 spin_lock_irqsave(&chip->spinlock, flags);
419 pch_gpio_save_reg_conf(chip);
420 spin_unlock_irqrestore(&chip->spinlock, flags);
421
422 return 0;
423}
424
425static int __maybe_unused pch_gpio_resume(struct device *dev)
426{
427 struct pch_gpio *chip = dev_get_drvdata(dev);
428 unsigned long flags;
429
430 spin_lock_irqsave(&chip->spinlock, flags);
431 iowrite32(0x01, &chip->reg->reset);
432 iowrite32(0x00, &chip->reg->reset);
433 pch_gpio_restore_reg_conf(chip);
434 spin_unlock_irqrestore(&chip->spinlock, flags);
435
436 return 0;
437}
438
439static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
440
441static const struct pci_device_id pch_gpio_pcidev_id[] = {
442 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
443 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
444 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
445 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
446 { 0, }
447};
448MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
449
450static struct pci_driver pch_gpio_driver = {
451 .name = "pch_gpio",
452 .id_table = pch_gpio_pcidev_id,
453 .probe = pch_gpio_probe,
454 .driver = {
455 .pm = &pch_gpio_pm_ops,
456 },
457};
458
459module_pci_driver(pch_gpio_driver);
460
461MODULE_DESCRIPTION("PCH GPIO PCI Driver");
462MODULE_LICENSE("GPL v2");