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1/*
2 * GPIO driver for the ACCES 104-IDI-48 family
3 * Copyright (C) 2015 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned idi_48_base;
29module_param(idi_48_base, uint, 0);
30MODULE_PARM_DESC(idi_48_base, "ACCES 104-IDI-48 base address");
31static unsigned idi_48_irq;
32module_param(idi_48_irq, uint, 0);
33MODULE_PARM_DESC(idi_48_irq, "ACCES 104-IDI-48 interrupt line number");
34
35/**
36 * struct idi_48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @ack_lock: synchronization lock to prevent IRQ handler race conditions
40 * @irq_mask: input bits affected by interrupts
41 * @base: base port address of the GPIO device
42 * @irq: Interrupt line number
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
44 */
45struct idi_48_gpio {
46 struct gpio_chip chip;
47 spinlock_t lock;
48 spinlock_t ack_lock;
49 unsigned char irq_mask[6];
50 unsigned base;
51 unsigned irq;
52 unsigned char cos_enb;
53};
54
55static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
56{
57 return 1;
58}
59
60static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
61{
62 return 0;
63}
64
65static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
66{
67 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
68 unsigned i;
69 const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
70 unsigned base_offset;
71 unsigned mask;
72
73 for (i = 0; i < 48; i += 8)
74 if (offset < i + 8) {
75 base_offset = register_offset[i / 8];
76 mask = BIT(offset - i);
77
78 return !!(inb(idi48gpio->base + base_offset) & mask);
79 }
80
81 /* The following line should never execute since offset < 48 */
82 return 0;
83}
84
85static void idi_48_irq_ack(struct irq_data *data)
86{
87}
88
89static void idi_48_irq_mask(struct irq_data *data)
90{
91 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
92 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
93 const unsigned offset = irqd_to_hwirq(data);
94 unsigned i;
95 unsigned mask;
96 unsigned boundary;
97 unsigned long flags;
98
99 for (i = 0; i < 48; i += 8)
100 if (offset < i + 8) {
101 mask = BIT(offset - i);
102 boundary = i / 8;
103
104 idi48gpio->irq_mask[boundary] &= ~mask;
105
106 if (!idi48gpio->irq_mask[boundary]) {
107 idi48gpio->cos_enb &= ~BIT(boundary);
108
109 spin_lock_irqsave(&idi48gpio->lock, flags);
110
111 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
112
113 spin_unlock_irqrestore(&idi48gpio->lock, flags);
114 }
115
116 return;
117 }
118}
119
120static void idi_48_irq_unmask(struct irq_data *data)
121{
122 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
123 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
124 const unsigned offset = irqd_to_hwirq(data);
125 unsigned i;
126 unsigned mask;
127 unsigned boundary;
128 unsigned prev_irq_mask;
129 unsigned long flags;
130
131 for (i = 0; i < 48; i += 8)
132 if (offset < i + 8) {
133 mask = BIT(offset - i);
134 boundary = i / 8;
135 prev_irq_mask = idi48gpio->irq_mask[boundary];
136
137 idi48gpio->irq_mask[boundary] |= mask;
138
139 if (!prev_irq_mask) {
140 idi48gpio->cos_enb |= BIT(boundary);
141
142 spin_lock_irqsave(&idi48gpio->lock, flags);
143
144 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
145
146 spin_unlock_irqrestore(&idi48gpio->lock, flags);
147 }
148
149 return;
150 }
151}
152
153static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
154{
155 /* The only valid irq types are none and both-edges */
156 if (flow_type != IRQ_TYPE_NONE &&
157 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
158 return -EINVAL;
159
160 return 0;
161}
162
163static struct irq_chip idi_48_irqchip = {
164 .name = "104-idi-48",
165 .irq_ack = idi_48_irq_ack,
166 .irq_mask = idi_48_irq_mask,
167 .irq_unmask = idi_48_irq_unmask,
168 .irq_set_type = idi_48_irq_set_type
169};
170
171static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
172{
173 struct idi_48_gpio *const idi48gpio = dev_id;
174 unsigned long cos_status;
175 unsigned long boundary;
176 unsigned long irq_mask;
177 unsigned long bit_num;
178 unsigned long gpio;
179 struct gpio_chip *const chip = &idi48gpio->chip;
180
181 spin_lock(&idi48gpio->ack_lock);
182
183 spin_lock(&idi48gpio->lock);
184
185 cos_status = inb(idi48gpio->base + 7);
186
187 spin_unlock(&idi48gpio->lock);
188
189 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
190 if (cos_status & BIT(6)) {
191 spin_unlock(&idi48gpio->ack_lock);
192 return IRQ_NONE;
193 }
194
195 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
196 cos_status &= 0x3F;
197
198 for_each_set_bit(boundary, &cos_status, 6) {
199 irq_mask = idi48gpio->irq_mask[boundary];
200
201 for_each_set_bit(bit_num, &irq_mask, 8) {
202 gpio = bit_num + boundary * 8;
203
204 generic_handle_irq(irq_find_mapping(chip->irqdomain,
205 gpio));
206 }
207 }
208
209 spin_unlock(&idi48gpio->ack_lock);
210
211 return IRQ_HANDLED;
212}
213
214static int __init idi_48_probe(struct platform_device *pdev)
215{
216 struct device *dev = &pdev->dev;
217 struct idi_48_gpio *idi48gpio;
218 const unsigned base = idi_48_base;
219 const unsigned extent = 8;
220 const char *const name = dev_name(dev);
221 int err;
222 const unsigned irq = idi_48_irq;
223
224 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
225 if (!idi48gpio)
226 return -ENOMEM;
227
228 if (!devm_request_region(dev, base, extent, name)) {
229 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
230 base, base + extent);
231 return -EBUSY;
232 }
233
234 idi48gpio->chip.label = name;
235 idi48gpio->chip.parent = dev;
236 idi48gpio->chip.owner = THIS_MODULE;
237 idi48gpio->chip.base = -1;
238 idi48gpio->chip.ngpio = 48;
239 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
240 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
241 idi48gpio->chip.get = idi_48_gpio_get;
242 idi48gpio->base = base;
243 idi48gpio->irq = irq;
244
245 spin_lock_init(&idi48gpio->lock);
246
247 dev_set_drvdata(dev, idi48gpio);
248
249 err = gpiochip_add_data(&idi48gpio->chip, idi48gpio);
250 if (err) {
251 dev_err(dev, "GPIO registering failed (%d)\n", err);
252 return err;
253 }
254
255 /* Disable IRQ by default */
256 outb(0, base + 7);
257 inb(base + 7);
258
259 err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
260 handle_edge_irq, IRQ_TYPE_NONE);
261 if (err) {
262 dev_err(dev, "Could not add irqchip (%d)\n", err);
263 goto err_gpiochip_remove;
264 }
265
266 err = request_irq(irq, idi_48_irq_handler, IRQF_SHARED, name,
267 idi48gpio);
268 if (err) {
269 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
270 goto err_gpiochip_remove;
271 }
272
273 return 0;
274
275err_gpiochip_remove:
276 gpiochip_remove(&idi48gpio->chip);
277 return err;
278}
279
280static int idi_48_remove(struct platform_device *pdev)
281{
282 struct idi_48_gpio *const idi48gpio = platform_get_drvdata(pdev);
283
284 free_irq(idi48gpio->irq, idi48gpio);
285 gpiochip_remove(&idi48gpio->chip);
286
287 return 0;
288}
289
290static struct platform_device *idi_48_device;
291
292static struct platform_driver idi_48_driver = {
293 .driver = {
294 .name = "104-idi-48"
295 },
296 .remove = idi_48_remove
297};
298
299static void __exit idi_48_exit(void)
300{
301 platform_device_unregister(idi_48_device);
302 platform_driver_unregister(&idi_48_driver);
303}
304
305static int __init idi_48_init(void)
306{
307 int err;
308
309 idi_48_device = platform_device_alloc(idi_48_driver.driver.name, -1);
310 if (!idi_48_device)
311 return -ENOMEM;
312
313 err = platform_device_add(idi_48_device);
314 if (err)
315 goto err_platform_device;
316
317 err = platform_driver_probe(&idi_48_driver, idi_48_probe);
318 if (err)
319 goto err_platform_driver;
320
321 return 0;
322
323err_platform_driver:
324 platform_device_del(idi_48_device);
325err_platform_device:
326 platform_device_put(idi_48_device);
327 return err;
328}
329
330module_init(idi_48_init);
331module_exit(idi_48_exit);
332
333MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
334MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
335MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8 */
9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/device.h>
12#include <linux/errno.h>
13#include <linux/gpio/driver.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/interrupt.h>
17#include <linux/irqdesc.h>
18#include <linux/isa.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/spinlock.h>
23
24#define IDI_48_EXTENT 8
25#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
26
27static unsigned int base[MAX_NUM_IDI_48];
28static unsigned int num_idi_48;
29module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
30MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
31
32static unsigned int irq[MAX_NUM_IDI_48];
33module_param_hw_array(irq, uint, irq, NULL, 0);
34MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
35
36/**
37 * struct idi_48_gpio - GPIO device private data structure
38 * @chip: instance of the gpio_chip
39 * @lock: synchronization lock to prevent I/O race conditions
40 * @ack_lock: synchronization lock to prevent IRQ handler race conditions
41 * @irq_mask: input bits affected by interrupts
42 * @base: base port address of the GPIO device
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
44 */
45struct idi_48_gpio {
46 struct gpio_chip chip;
47 raw_spinlock_t lock;
48 spinlock_t ack_lock;
49 unsigned char irq_mask[6];
50 unsigned base;
51 unsigned char cos_enb;
52};
53
54static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
55{
56 return GPIO_LINE_DIRECTION_IN;
57}
58
59static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
60{
61 return 0;
62}
63
64static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
65{
66 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
67 unsigned i;
68 static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 };
69 unsigned base_offset;
70 unsigned mask;
71
72 for (i = 0; i < 48; i += 8)
73 if (offset < i + 8) {
74 base_offset = register_offset[i / 8];
75 mask = BIT(offset - i);
76
77 return !!(inb(idi48gpio->base + base_offset) & mask);
78 }
79
80 /* The following line should never execute since offset < 48 */
81 return 0;
82}
83
84static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
85 unsigned long *bits)
86{
87 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
88 unsigned long offset;
89 unsigned long gpio_mask;
90 static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
91 unsigned int port_addr;
92 unsigned long port_state;
93
94 /* clear bits array to a clean slate */
95 bitmap_zero(bits, chip->ngpio);
96
97 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
98 port_addr = idi48gpio->base + ports[offset / 8];
99 port_state = inb(port_addr) & gpio_mask;
100
101 bitmap_set_value8(bits, port_state, offset);
102 }
103
104 return 0;
105}
106
107static void idi_48_irq_ack(struct irq_data *data)
108{
109}
110
111static void idi_48_irq_mask(struct irq_data *data)
112{
113 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
114 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
115 const unsigned offset = irqd_to_hwirq(data);
116 unsigned i;
117 unsigned mask;
118 unsigned boundary;
119 unsigned long flags;
120
121 for (i = 0; i < 48; i += 8)
122 if (offset < i + 8) {
123 mask = BIT(offset - i);
124 boundary = i / 8;
125
126 idi48gpio->irq_mask[boundary] &= ~mask;
127
128 if (!idi48gpio->irq_mask[boundary]) {
129 idi48gpio->cos_enb &= ~BIT(boundary);
130
131 raw_spin_lock_irqsave(&idi48gpio->lock, flags);
132
133 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
134
135 raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
136 }
137
138 return;
139 }
140}
141
142static void idi_48_irq_unmask(struct irq_data *data)
143{
144 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
145 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
146 const unsigned offset = irqd_to_hwirq(data);
147 unsigned i;
148 unsigned mask;
149 unsigned boundary;
150 unsigned prev_irq_mask;
151 unsigned long flags;
152
153 for (i = 0; i < 48; i += 8)
154 if (offset < i + 8) {
155 mask = BIT(offset - i);
156 boundary = i / 8;
157 prev_irq_mask = idi48gpio->irq_mask[boundary];
158
159 idi48gpio->irq_mask[boundary] |= mask;
160
161 if (!prev_irq_mask) {
162 idi48gpio->cos_enb |= BIT(boundary);
163
164 raw_spin_lock_irqsave(&idi48gpio->lock, flags);
165
166 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
167
168 raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
169 }
170
171 return;
172 }
173}
174
175static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
176{
177 /* The only valid irq types are none and both-edges */
178 if (flow_type != IRQ_TYPE_NONE &&
179 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
180 return -EINVAL;
181
182 return 0;
183}
184
185static struct irq_chip idi_48_irqchip = {
186 .name = "104-idi-48",
187 .irq_ack = idi_48_irq_ack,
188 .irq_mask = idi_48_irq_mask,
189 .irq_unmask = idi_48_irq_unmask,
190 .irq_set_type = idi_48_irq_set_type
191};
192
193static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
194{
195 struct idi_48_gpio *const idi48gpio = dev_id;
196 unsigned long cos_status;
197 unsigned long boundary;
198 unsigned long irq_mask;
199 unsigned long bit_num;
200 unsigned long gpio;
201 struct gpio_chip *const chip = &idi48gpio->chip;
202
203 spin_lock(&idi48gpio->ack_lock);
204
205 raw_spin_lock(&idi48gpio->lock);
206
207 cos_status = inb(idi48gpio->base + 7);
208
209 raw_spin_unlock(&idi48gpio->lock);
210
211 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
212 if (cos_status & BIT(6)) {
213 spin_unlock(&idi48gpio->ack_lock);
214 return IRQ_NONE;
215 }
216
217 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
218 cos_status &= 0x3F;
219
220 for_each_set_bit(boundary, &cos_status, 6) {
221 irq_mask = idi48gpio->irq_mask[boundary];
222
223 for_each_set_bit(bit_num, &irq_mask, 8) {
224 gpio = bit_num + boundary * 8;
225
226 generic_handle_irq(irq_find_mapping(chip->irq.domain,
227 gpio));
228 }
229 }
230
231 spin_unlock(&idi48gpio->ack_lock);
232
233 return IRQ_HANDLED;
234}
235
236#define IDI48_NGPIO 48
237static const char *idi48_names[IDI48_NGPIO] = {
238 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
239 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
240 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
241 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
242 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
243 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
244 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
245 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
246};
247
248static int idi_48_irq_init_hw(struct gpio_chip *gc)
249{
250 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
251
252 /* Disable IRQ by default */
253 outb(0, idi48gpio->base + 7);
254 inb(idi48gpio->base + 7);
255
256 return 0;
257}
258
259static int idi_48_probe(struct device *dev, unsigned int id)
260{
261 struct idi_48_gpio *idi48gpio;
262 const char *const name = dev_name(dev);
263 struct gpio_irq_chip *girq;
264 int err;
265
266 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
267 if (!idi48gpio)
268 return -ENOMEM;
269
270 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
271 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
272 base[id], base[id] + IDI_48_EXTENT);
273 return -EBUSY;
274 }
275
276 idi48gpio->chip.label = name;
277 idi48gpio->chip.parent = dev;
278 idi48gpio->chip.owner = THIS_MODULE;
279 idi48gpio->chip.base = -1;
280 idi48gpio->chip.ngpio = IDI48_NGPIO;
281 idi48gpio->chip.names = idi48_names;
282 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
283 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
284 idi48gpio->chip.get = idi_48_gpio_get;
285 idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
286 idi48gpio->base = base[id];
287
288 girq = &idi48gpio->chip.irq;
289 girq->chip = &idi_48_irqchip;
290 /* This will let us handle the parent IRQ in the driver */
291 girq->parent_handler = NULL;
292 girq->num_parents = 0;
293 girq->parents = NULL;
294 girq->default_type = IRQ_TYPE_NONE;
295 girq->handler = handle_edge_irq;
296 girq->init_hw = idi_48_irq_init_hw;
297
298 raw_spin_lock_init(&idi48gpio->lock);
299 spin_lock_init(&idi48gpio->ack_lock);
300
301 err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
302 if (err) {
303 dev_err(dev, "GPIO registering failed (%d)\n", err);
304 return err;
305 }
306
307 err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
308 name, idi48gpio);
309 if (err) {
310 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
311 return err;
312 }
313
314 return 0;
315}
316
317static struct isa_driver idi_48_driver = {
318 .probe = idi_48_probe,
319 .driver = {
320 .name = "104-idi-48"
321 },
322};
323module_isa_driver(idi_48_driver, num_idi_48);
324
325MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
326MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
327MODULE_LICENSE("GPL v2");