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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for FPGA Device Feature List (DFL) Support
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
12 */
13#include <linux/dfl.h>
14#include <linux/fpga-dfl.h>
15#include <linux/module.h>
16#include <linux/uaccess.h>
17
18#include "dfl.h"
19
20static DEFINE_MUTEX(dfl_id_mutex);
21
22/*
23 * when adding a new feature dev support in DFL framework, it's required to
24 * add a new item in enum dfl_id_type and provide related information in below
25 * dfl_devs table which is indexed by dfl_id_type, e.g. name string used for
26 * platform device creation (define name strings in dfl.h, as they could be
27 * reused by platform device drivers).
28 *
29 * if the new feature dev needs chardev support, then it's required to add
30 * a new item in dfl_chardevs table and configure dfl_devs[i].devt_type as
31 * index to dfl_chardevs table. If no chardev support just set devt_type
32 * as one invalid index (DFL_FPGA_DEVT_MAX).
33 */
34enum dfl_fpga_devt_type {
35 DFL_FPGA_DEVT_FME,
36 DFL_FPGA_DEVT_PORT,
37 DFL_FPGA_DEVT_MAX,
38};
39
40static struct lock_class_key dfl_pdata_keys[DFL_ID_MAX];
41
42static const char *dfl_pdata_key_strings[DFL_ID_MAX] = {
43 "dfl-fme-pdata",
44 "dfl-port-pdata",
45};
46
47/**
48 * dfl_dev_info - dfl feature device information.
49 * @name: name string of the feature platform device.
50 * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec.
51 * @id: idr id of the feature dev.
52 * @devt_type: index to dfl_chrdevs[].
53 */
54struct dfl_dev_info {
55 const char *name;
56 u16 dfh_id;
57 struct idr id;
58 enum dfl_fpga_devt_type devt_type;
59};
60
61/* it is indexed by dfl_id_type */
62static struct dfl_dev_info dfl_devs[] = {
63 {.name = DFL_FPGA_FEATURE_DEV_FME, .dfh_id = DFH_ID_FIU_FME,
64 .devt_type = DFL_FPGA_DEVT_FME},
65 {.name = DFL_FPGA_FEATURE_DEV_PORT, .dfh_id = DFH_ID_FIU_PORT,
66 .devt_type = DFL_FPGA_DEVT_PORT},
67};
68
69/**
70 * dfl_chardev_info - chardev information of dfl feature device
71 * @name: nmae string of the char device.
72 * @devt: devt of the char device.
73 */
74struct dfl_chardev_info {
75 const char *name;
76 dev_t devt;
77};
78
79/* indexed by enum dfl_fpga_devt_type */
80static struct dfl_chardev_info dfl_chrdevs[] = {
81 {.name = DFL_FPGA_FEATURE_DEV_FME},
82 {.name = DFL_FPGA_FEATURE_DEV_PORT},
83};
84
85static void dfl_ids_init(void)
86{
87 int i;
88
89 for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
90 idr_init(&dfl_devs[i].id);
91}
92
93static void dfl_ids_destroy(void)
94{
95 int i;
96
97 for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
98 idr_destroy(&dfl_devs[i].id);
99}
100
101static int dfl_id_alloc(enum dfl_id_type type, struct device *dev)
102{
103 int id;
104
105 WARN_ON(type >= DFL_ID_MAX);
106 mutex_lock(&dfl_id_mutex);
107 id = idr_alloc(&dfl_devs[type].id, dev, 0, 0, GFP_KERNEL);
108 mutex_unlock(&dfl_id_mutex);
109
110 return id;
111}
112
113static void dfl_id_free(enum dfl_id_type type, int id)
114{
115 WARN_ON(type >= DFL_ID_MAX);
116 mutex_lock(&dfl_id_mutex);
117 idr_remove(&dfl_devs[type].id, id);
118 mutex_unlock(&dfl_id_mutex);
119}
120
121static enum dfl_id_type feature_dev_id_type(struct platform_device *pdev)
122{
123 int i;
124
125 for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
126 if (!strcmp(dfl_devs[i].name, pdev->name))
127 return i;
128
129 return DFL_ID_MAX;
130}
131
132static enum dfl_id_type dfh_id_to_type(u16 id)
133{
134 int i;
135
136 for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
137 if (dfl_devs[i].dfh_id == id)
138 return i;
139
140 return DFL_ID_MAX;
141}
142
143/*
144 * introduce a global port_ops list, it allows port drivers to register ops
145 * in such list, then other feature devices (e.g. FME), could use the port
146 * functions even related port platform device is hidden. Below is one example,
147 * in virtualization case of PCIe-based FPGA DFL device, when SRIOV is
148 * enabled, port (and it's AFU) is turned into VF and port platform device
149 * is hidden from system but it's still required to access port to finish FPGA
150 * reconfiguration function in FME.
151 */
152
153static DEFINE_MUTEX(dfl_port_ops_mutex);
154static LIST_HEAD(dfl_port_ops_list);
155
156/**
157 * dfl_fpga_port_ops_get - get matched port ops from the global list
158 * @pdev: platform device to match with associated port ops.
159 * Return: matched port ops on success, NULL otherwise.
160 *
161 * Please note that must dfl_fpga_port_ops_put after use the port_ops.
162 */
163struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev)
164{
165 struct dfl_fpga_port_ops *ops = NULL;
166
167 mutex_lock(&dfl_port_ops_mutex);
168 if (list_empty(&dfl_port_ops_list))
169 goto done;
170
171 list_for_each_entry(ops, &dfl_port_ops_list, node) {
172 /* match port_ops using the name of platform device */
173 if (!strcmp(pdev->name, ops->name)) {
174 if (!try_module_get(ops->owner))
175 ops = NULL;
176 goto done;
177 }
178 }
179
180 ops = NULL;
181done:
182 mutex_unlock(&dfl_port_ops_mutex);
183 return ops;
184}
185EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_get);
186
187/**
188 * dfl_fpga_port_ops_put - put port ops
189 * @ops: port ops.
190 */
191void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops)
192{
193 if (ops && ops->owner)
194 module_put(ops->owner);
195}
196EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_put);
197
198/**
199 * dfl_fpga_port_ops_add - add port_ops to global list
200 * @ops: port ops to add.
201 */
202void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops)
203{
204 mutex_lock(&dfl_port_ops_mutex);
205 list_add_tail(&ops->node, &dfl_port_ops_list);
206 mutex_unlock(&dfl_port_ops_mutex);
207}
208EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_add);
209
210/**
211 * dfl_fpga_port_ops_del - remove port_ops from global list
212 * @ops: port ops to del.
213 */
214void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops)
215{
216 mutex_lock(&dfl_port_ops_mutex);
217 list_del(&ops->node);
218 mutex_unlock(&dfl_port_ops_mutex);
219}
220EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_del);
221
222/**
223 * dfl_fpga_check_port_id - check the port id
224 * @pdev: port platform device.
225 * @pport_id: port id to compare.
226 *
227 * Return: 1 if port device matches with given port id, otherwise 0.
228 */
229int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id)
230{
231 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
232 struct dfl_fpga_port_ops *port_ops;
233
234 if (pdata->id != FEATURE_DEV_ID_UNUSED)
235 return pdata->id == *(int *)pport_id;
236
237 port_ops = dfl_fpga_port_ops_get(pdev);
238 if (!port_ops || !port_ops->get_id)
239 return 0;
240
241 pdata->id = port_ops->get_id(pdev);
242 dfl_fpga_port_ops_put(port_ops);
243
244 return pdata->id == *(int *)pport_id;
245}
246EXPORT_SYMBOL_GPL(dfl_fpga_check_port_id);
247
248static DEFINE_IDA(dfl_device_ida);
249
250static const struct dfl_device_id *
251dfl_match_one_device(const struct dfl_device_id *id, struct dfl_device *ddev)
252{
253 if (id->type == ddev->type && id->feature_id == ddev->feature_id)
254 return id;
255
256 return NULL;
257}
258
259static int dfl_bus_match(struct device *dev, struct device_driver *drv)
260{
261 struct dfl_device *ddev = to_dfl_dev(dev);
262 struct dfl_driver *ddrv = to_dfl_drv(drv);
263 const struct dfl_device_id *id_entry;
264
265 id_entry = ddrv->id_table;
266 if (id_entry) {
267 while (id_entry->feature_id) {
268 if (dfl_match_one_device(id_entry, ddev)) {
269 ddev->id_entry = id_entry;
270 return 1;
271 }
272 id_entry++;
273 }
274 }
275
276 return 0;
277}
278
279static int dfl_bus_probe(struct device *dev)
280{
281 struct dfl_driver *ddrv = to_dfl_drv(dev->driver);
282 struct dfl_device *ddev = to_dfl_dev(dev);
283
284 return ddrv->probe(ddev);
285}
286
287static int dfl_bus_remove(struct device *dev)
288{
289 struct dfl_driver *ddrv = to_dfl_drv(dev->driver);
290 struct dfl_device *ddev = to_dfl_dev(dev);
291
292 if (ddrv->remove)
293 ddrv->remove(ddev);
294
295 return 0;
296}
297
298static int dfl_bus_uevent(struct device *dev, struct kobj_uevent_env *env)
299{
300 struct dfl_device *ddev = to_dfl_dev(dev);
301
302 return add_uevent_var(env, "MODALIAS=dfl:t%04Xf%04X",
303 ddev->type, ddev->feature_id);
304}
305
306static ssize_t
307type_show(struct device *dev, struct device_attribute *attr, char *buf)
308{
309 struct dfl_device *ddev = to_dfl_dev(dev);
310
311 return sprintf(buf, "0x%x\n", ddev->type);
312}
313static DEVICE_ATTR_RO(type);
314
315static ssize_t
316feature_id_show(struct device *dev, struct device_attribute *attr, char *buf)
317{
318 struct dfl_device *ddev = to_dfl_dev(dev);
319
320 return sprintf(buf, "0x%x\n", ddev->feature_id);
321}
322static DEVICE_ATTR_RO(feature_id);
323
324static struct attribute *dfl_dev_attrs[] = {
325 &dev_attr_type.attr,
326 &dev_attr_feature_id.attr,
327 NULL,
328};
329ATTRIBUTE_GROUPS(dfl_dev);
330
331static struct bus_type dfl_bus_type = {
332 .name = "dfl",
333 .match = dfl_bus_match,
334 .probe = dfl_bus_probe,
335 .remove = dfl_bus_remove,
336 .uevent = dfl_bus_uevent,
337 .dev_groups = dfl_dev_groups,
338};
339
340static void release_dfl_dev(struct device *dev)
341{
342 struct dfl_device *ddev = to_dfl_dev(dev);
343
344 if (ddev->mmio_res.parent)
345 release_resource(&ddev->mmio_res);
346
347 ida_simple_remove(&dfl_device_ida, ddev->id);
348 kfree(ddev->irqs);
349 kfree(ddev);
350}
351
352static struct dfl_device *
353dfl_dev_add(struct dfl_feature_platform_data *pdata,
354 struct dfl_feature *feature)
355{
356 struct platform_device *pdev = pdata->dev;
357 struct resource *parent_res;
358 struct dfl_device *ddev;
359 int id, i, ret;
360
361 ddev = kzalloc(sizeof(*ddev), GFP_KERNEL);
362 if (!ddev)
363 return ERR_PTR(-ENOMEM);
364
365 id = ida_simple_get(&dfl_device_ida, 0, 0, GFP_KERNEL);
366 if (id < 0) {
367 dev_err(&pdev->dev, "unable to get id\n");
368 kfree(ddev);
369 return ERR_PTR(id);
370 }
371
372 /* freeing resources by put_device() after device_initialize() */
373 device_initialize(&ddev->dev);
374 ddev->dev.parent = &pdev->dev;
375 ddev->dev.bus = &dfl_bus_type;
376 ddev->dev.release = release_dfl_dev;
377 ddev->id = id;
378 ret = dev_set_name(&ddev->dev, "dfl_dev.%d", id);
379 if (ret)
380 goto put_dev;
381
382 ddev->type = feature_dev_id_type(pdev);
383 ddev->feature_id = feature->id;
384 ddev->cdev = pdata->dfl_cdev;
385
386 /* add mmio resource */
387 parent_res = &pdev->resource[feature->resource_index];
388 ddev->mmio_res.flags = IORESOURCE_MEM;
389 ddev->mmio_res.start = parent_res->start;
390 ddev->mmio_res.end = parent_res->end;
391 ddev->mmio_res.name = dev_name(&ddev->dev);
392 ret = insert_resource(parent_res, &ddev->mmio_res);
393 if (ret) {
394 dev_err(&pdev->dev, "%s failed to claim resource: %pR\n",
395 dev_name(&ddev->dev), &ddev->mmio_res);
396 goto put_dev;
397 }
398
399 /* then add irq resource */
400 if (feature->nr_irqs) {
401 ddev->irqs = kcalloc(feature->nr_irqs,
402 sizeof(*ddev->irqs), GFP_KERNEL);
403 if (!ddev->irqs) {
404 ret = -ENOMEM;
405 goto put_dev;
406 }
407
408 for (i = 0; i < feature->nr_irqs; i++)
409 ddev->irqs[i] = feature->irq_ctx[i].irq;
410
411 ddev->num_irqs = feature->nr_irqs;
412 }
413
414 ret = device_add(&ddev->dev);
415 if (ret)
416 goto put_dev;
417
418 dev_dbg(&pdev->dev, "add dfl_dev: %s\n", dev_name(&ddev->dev));
419 return ddev;
420
421put_dev:
422 /* calls release_dfl_dev() which does the clean up */
423 put_device(&ddev->dev);
424 return ERR_PTR(ret);
425}
426
427static void dfl_devs_remove(struct dfl_feature_platform_data *pdata)
428{
429 struct dfl_feature *feature;
430
431 dfl_fpga_dev_for_each_feature(pdata, feature) {
432 if (feature->ddev) {
433 device_unregister(&feature->ddev->dev);
434 feature->ddev = NULL;
435 }
436 }
437}
438
439static int dfl_devs_add(struct dfl_feature_platform_data *pdata)
440{
441 struct dfl_feature *feature;
442 struct dfl_device *ddev;
443 int ret;
444
445 dfl_fpga_dev_for_each_feature(pdata, feature) {
446 if (feature->ioaddr)
447 continue;
448
449 if (feature->ddev) {
450 ret = -EEXIST;
451 goto err;
452 }
453
454 ddev = dfl_dev_add(pdata, feature);
455 if (IS_ERR(ddev)) {
456 ret = PTR_ERR(ddev);
457 goto err;
458 }
459
460 feature->ddev = ddev;
461 }
462
463 return 0;
464
465err:
466 dfl_devs_remove(pdata);
467 return ret;
468}
469
470int __dfl_driver_register(struct dfl_driver *dfl_drv, struct module *owner)
471{
472 if (!dfl_drv || !dfl_drv->probe || !dfl_drv->id_table)
473 return -EINVAL;
474
475 dfl_drv->drv.owner = owner;
476 dfl_drv->drv.bus = &dfl_bus_type;
477
478 return driver_register(&dfl_drv->drv);
479}
480EXPORT_SYMBOL(__dfl_driver_register);
481
482void dfl_driver_unregister(struct dfl_driver *dfl_drv)
483{
484 driver_unregister(&dfl_drv->drv);
485}
486EXPORT_SYMBOL(dfl_driver_unregister);
487
488#define is_header_feature(feature) ((feature)->id == FEATURE_ID_FIU_HEADER)
489
490/**
491 * dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
492 * @pdev: feature device.
493 */
494void dfl_fpga_dev_feature_uinit(struct platform_device *pdev)
495{
496 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
497 struct dfl_feature *feature;
498
499 dfl_devs_remove(pdata);
500
501 dfl_fpga_dev_for_each_feature(pdata, feature) {
502 if (feature->ops) {
503 if (feature->ops->uinit)
504 feature->ops->uinit(pdev, feature);
505 feature->ops = NULL;
506 }
507 }
508}
509EXPORT_SYMBOL_GPL(dfl_fpga_dev_feature_uinit);
510
511static int dfl_feature_instance_init(struct platform_device *pdev,
512 struct dfl_feature_platform_data *pdata,
513 struct dfl_feature *feature,
514 struct dfl_feature_driver *drv)
515{
516 void __iomem *base;
517 int ret = 0;
518
519 if (!is_header_feature(feature)) {
520 base = devm_platform_ioremap_resource(pdev,
521 feature->resource_index);
522 if (IS_ERR(base)) {
523 dev_err(&pdev->dev,
524 "ioremap failed for feature 0x%x!\n",
525 feature->id);
526 return PTR_ERR(base);
527 }
528
529 feature->ioaddr = base;
530 }
531
532 if (drv->ops->init) {
533 ret = drv->ops->init(pdev, feature);
534 if (ret)
535 return ret;
536 }
537
538 feature->ops = drv->ops;
539
540 return ret;
541}
542
543static bool dfl_feature_drv_match(struct dfl_feature *feature,
544 struct dfl_feature_driver *driver)
545{
546 const struct dfl_feature_id *ids = driver->id_table;
547
548 if (ids) {
549 while (ids->id) {
550 if (ids->id == feature->id)
551 return true;
552 ids++;
553 }
554 }
555 return false;
556}
557
558/**
559 * dfl_fpga_dev_feature_init - init for sub features of dfl feature device
560 * @pdev: feature device.
561 * @feature_drvs: drvs for sub features.
562 *
563 * This function will match sub features with given feature drvs list and
564 * use matched drv to init related sub feature.
565 *
566 * Return: 0 on success, negative error code otherwise.
567 */
568int dfl_fpga_dev_feature_init(struct platform_device *pdev,
569 struct dfl_feature_driver *feature_drvs)
570{
571 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
572 struct dfl_feature_driver *drv = feature_drvs;
573 struct dfl_feature *feature;
574 int ret;
575
576 while (drv->ops) {
577 dfl_fpga_dev_for_each_feature(pdata, feature) {
578 if (dfl_feature_drv_match(feature, drv)) {
579 ret = dfl_feature_instance_init(pdev, pdata,
580 feature, drv);
581 if (ret)
582 goto exit;
583 }
584 }
585 drv++;
586 }
587
588 ret = dfl_devs_add(pdata);
589 if (ret)
590 goto exit;
591
592 return 0;
593exit:
594 dfl_fpga_dev_feature_uinit(pdev);
595 return ret;
596}
597EXPORT_SYMBOL_GPL(dfl_fpga_dev_feature_init);
598
599static void dfl_chardev_uinit(void)
600{
601 int i;
602
603 for (i = 0; i < DFL_FPGA_DEVT_MAX; i++)
604 if (MAJOR(dfl_chrdevs[i].devt)) {
605 unregister_chrdev_region(dfl_chrdevs[i].devt,
606 MINORMASK + 1);
607 dfl_chrdevs[i].devt = MKDEV(0, 0);
608 }
609}
610
611static int dfl_chardev_init(void)
612{
613 int i, ret;
614
615 for (i = 0; i < DFL_FPGA_DEVT_MAX; i++) {
616 ret = alloc_chrdev_region(&dfl_chrdevs[i].devt, 0,
617 MINORMASK + 1, dfl_chrdevs[i].name);
618 if (ret)
619 goto exit;
620 }
621
622 return 0;
623
624exit:
625 dfl_chardev_uinit();
626 return ret;
627}
628
629static dev_t dfl_get_devt(enum dfl_fpga_devt_type type, int id)
630{
631 if (type >= DFL_FPGA_DEVT_MAX)
632 return 0;
633
634 return MKDEV(MAJOR(dfl_chrdevs[type].devt), id);
635}
636
637/**
638 * dfl_fpga_dev_ops_register - register cdev ops for feature dev
639 *
640 * @pdev: feature dev.
641 * @fops: file operations for feature dev's cdev.
642 * @owner: owning module/driver.
643 *
644 * Return: 0 on success, negative error code otherwise.
645 */
646int dfl_fpga_dev_ops_register(struct platform_device *pdev,
647 const struct file_operations *fops,
648 struct module *owner)
649{
650 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
651
652 cdev_init(&pdata->cdev, fops);
653 pdata->cdev.owner = owner;
654
655 /*
656 * set parent to the feature device so that its refcount is
657 * decreased after the last refcount of cdev is gone, that
658 * makes sure the feature device is valid during device
659 * file's life-cycle.
660 */
661 pdata->cdev.kobj.parent = &pdev->dev.kobj;
662
663 return cdev_add(&pdata->cdev, pdev->dev.devt, 1);
664}
665EXPORT_SYMBOL_GPL(dfl_fpga_dev_ops_register);
666
667/**
668 * dfl_fpga_dev_ops_unregister - unregister cdev ops for feature dev
669 * @pdev: feature dev.
670 */
671void dfl_fpga_dev_ops_unregister(struct platform_device *pdev)
672{
673 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
674
675 cdev_del(&pdata->cdev);
676}
677EXPORT_SYMBOL_GPL(dfl_fpga_dev_ops_unregister);
678
679/**
680 * struct build_feature_devs_info - info collected during feature dev build.
681 *
682 * @dev: device to enumerate.
683 * @cdev: the container device for all feature devices.
684 * @nr_irqs: number of irqs for all feature devices.
685 * @irq_table: Linux IRQ numbers for all irqs, indexed by local irq index of
686 * this device.
687 * @feature_dev: current feature device.
688 * @ioaddr: header register region address of current FIU in enumeration.
689 * @start: register resource start of current FIU.
690 * @len: max register resource length of current FIU.
691 * @sub_features: a sub features linked list for feature device in enumeration.
692 * @feature_num: number of sub features for feature device in enumeration.
693 */
694struct build_feature_devs_info {
695 struct device *dev;
696 struct dfl_fpga_cdev *cdev;
697 unsigned int nr_irqs;
698 int *irq_table;
699
700 struct platform_device *feature_dev;
701 void __iomem *ioaddr;
702 resource_size_t start;
703 resource_size_t len;
704 struct list_head sub_features;
705 int feature_num;
706};
707
708/**
709 * struct dfl_feature_info - sub feature info collected during feature dev build
710 *
711 * @fid: id of this sub feature.
712 * @mmio_res: mmio resource of this sub feature.
713 * @ioaddr: mapped base address of mmio resource.
714 * @node: node in sub_features linked list.
715 * @irq_base: start of irq index in this sub feature.
716 * @nr_irqs: number of irqs of this sub feature.
717 */
718struct dfl_feature_info {
719 u16 fid;
720 struct resource mmio_res;
721 void __iomem *ioaddr;
722 struct list_head node;
723 unsigned int irq_base;
724 unsigned int nr_irqs;
725};
726
727static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev,
728 struct platform_device *port)
729{
730 struct dfl_feature_platform_data *pdata = dev_get_platdata(&port->dev);
731
732 mutex_lock(&cdev->lock);
733 list_add(&pdata->node, &cdev->port_dev_list);
734 get_device(&pdata->dev->dev);
735 mutex_unlock(&cdev->lock);
736}
737
738/*
739 * register current feature device, it is called when we need to switch to
740 * another feature parsing or we have parsed all features on given device
741 * feature list.
742 */
743static int build_info_commit_dev(struct build_feature_devs_info *binfo)
744{
745 struct platform_device *fdev = binfo->feature_dev;
746 struct dfl_feature_platform_data *pdata;
747 struct dfl_feature_info *finfo, *p;
748 enum dfl_id_type type;
749 int ret, index = 0, res_idx = 0;
750
751 type = feature_dev_id_type(fdev);
752 if (WARN_ON_ONCE(type >= DFL_ID_MAX))
753 return -EINVAL;
754
755 /*
756 * we do not need to care for the memory which is associated with
757 * the platform device. After calling platform_device_unregister(),
758 * it will be automatically freed by device's release() callback,
759 * platform_device_release().
760 */
761 pdata = kzalloc(struct_size(pdata, features, binfo->feature_num), GFP_KERNEL);
762 if (!pdata)
763 return -ENOMEM;
764
765 pdata->dev = fdev;
766 pdata->num = binfo->feature_num;
767 pdata->dfl_cdev = binfo->cdev;
768 pdata->id = FEATURE_DEV_ID_UNUSED;
769 mutex_init(&pdata->lock);
770 lockdep_set_class_and_name(&pdata->lock, &dfl_pdata_keys[type],
771 dfl_pdata_key_strings[type]);
772
773 /*
774 * the count should be initialized to 0 to make sure
775 *__fpga_port_enable() following __fpga_port_disable()
776 * works properly for port device.
777 * and it should always be 0 for fme device.
778 */
779 WARN_ON(pdata->disable_count);
780
781 fdev->dev.platform_data = pdata;
782
783 /* each sub feature has one MMIO resource */
784 fdev->num_resources = binfo->feature_num;
785 fdev->resource = kcalloc(binfo->feature_num, sizeof(*fdev->resource),
786 GFP_KERNEL);
787 if (!fdev->resource)
788 return -ENOMEM;
789
790 /* fill features and resource information for feature dev */
791 list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
792 struct dfl_feature *feature = &pdata->features[index++];
793 struct dfl_feature_irq_ctx *ctx;
794 unsigned int i;
795
796 /* save resource information for each feature */
797 feature->dev = fdev;
798 feature->id = finfo->fid;
799
800 /*
801 * the FIU header feature has some fundamental functions (sriov
802 * set, port enable/disable) needed for the dfl bus device and
803 * other sub features. So its mmio resource should be mapped by
804 * DFL bus device. And we should not assign it to feature
805 * devices (dfl-fme/afu) again.
806 */
807 if (is_header_feature(feature)) {
808 feature->resource_index = -1;
809 feature->ioaddr =
810 devm_ioremap_resource(binfo->dev,
811 &finfo->mmio_res);
812 if (IS_ERR(feature->ioaddr))
813 return PTR_ERR(feature->ioaddr);
814 } else {
815 feature->resource_index = res_idx;
816 fdev->resource[res_idx++] = finfo->mmio_res;
817 }
818
819 if (finfo->nr_irqs) {
820 ctx = devm_kcalloc(binfo->dev, finfo->nr_irqs,
821 sizeof(*ctx), GFP_KERNEL);
822 if (!ctx)
823 return -ENOMEM;
824
825 for (i = 0; i < finfo->nr_irqs; i++)
826 ctx[i].irq =
827 binfo->irq_table[finfo->irq_base + i];
828
829 feature->irq_ctx = ctx;
830 feature->nr_irqs = finfo->nr_irqs;
831 }
832
833 list_del(&finfo->node);
834 kfree(finfo);
835 }
836
837 ret = platform_device_add(binfo->feature_dev);
838 if (!ret) {
839 if (type == PORT_ID)
840 dfl_fpga_cdev_add_port_dev(binfo->cdev,
841 binfo->feature_dev);
842 else
843 binfo->cdev->fme_dev =
844 get_device(&binfo->feature_dev->dev);
845 /*
846 * reset it to avoid build_info_free() freeing their resource.
847 *
848 * The resource of successfully registered feature devices
849 * will be freed by platform_device_unregister(). See the
850 * comments in build_info_create_dev().
851 */
852 binfo->feature_dev = NULL;
853 }
854
855 return ret;
856}
857
858static int
859build_info_create_dev(struct build_feature_devs_info *binfo,
860 enum dfl_id_type type)
861{
862 struct platform_device *fdev;
863
864 if (type >= DFL_ID_MAX)
865 return -EINVAL;
866
867 /*
868 * we use -ENODEV as the initialization indicator which indicates
869 * whether the id need to be reclaimed
870 */
871 fdev = platform_device_alloc(dfl_devs[type].name, -ENODEV);
872 if (!fdev)
873 return -ENOMEM;
874
875 binfo->feature_dev = fdev;
876 binfo->feature_num = 0;
877
878 INIT_LIST_HEAD(&binfo->sub_features);
879
880 fdev->id = dfl_id_alloc(type, &fdev->dev);
881 if (fdev->id < 0)
882 return fdev->id;
883
884 fdev->dev.parent = &binfo->cdev->region->dev;
885 fdev->dev.devt = dfl_get_devt(dfl_devs[type].devt_type, fdev->id);
886
887 return 0;
888}
889
890static void build_info_free(struct build_feature_devs_info *binfo)
891{
892 struct dfl_feature_info *finfo, *p;
893
894 /*
895 * it is a valid id, free it. See comments in
896 * build_info_create_dev()
897 */
898 if (binfo->feature_dev && binfo->feature_dev->id >= 0) {
899 dfl_id_free(feature_dev_id_type(binfo->feature_dev),
900 binfo->feature_dev->id);
901
902 list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
903 list_del(&finfo->node);
904 kfree(finfo);
905 }
906 }
907
908 platform_device_put(binfo->feature_dev);
909
910 devm_kfree(binfo->dev, binfo);
911}
912
913static inline u32 feature_size(void __iomem *start)
914{
915 u64 v = readq(start + DFH);
916 u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
917 /* workaround for private features with invalid size, use 4K instead */
918 return ofst ? ofst : 4096;
919}
920
921static u16 feature_id(void __iomem *start)
922{
923 u64 v = readq(start + DFH);
924 u16 id = FIELD_GET(DFH_ID, v);
925 u8 type = FIELD_GET(DFH_TYPE, v);
926
927 if (type == DFH_TYPE_FIU)
928 return FEATURE_ID_FIU_HEADER;
929 else if (type == DFH_TYPE_PRIVATE)
930 return id;
931 else if (type == DFH_TYPE_AFU)
932 return FEATURE_ID_AFU;
933
934 WARN_ON(1);
935 return 0;
936}
937
938static int parse_feature_irqs(struct build_feature_devs_info *binfo,
939 resource_size_t ofst, u16 fid,
940 unsigned int *irq_base, unsigned int *nr_irqs)
941{
942 void __iomem *base = binfo->ioaddr + ofst;
943 unsigned int i, ibase, inr = 0;
944 int virq;
945 u64 v;
946
947 /*
948 * Ideally DFL framework should only read info from DFL header, but
949 * current version DFL only provides mmio resources information for
950 * each feature in DFL Header, no field for interrupt resources.
951 * Interrupt resource information is provided by specific mmio
952 * registers of each private feature which supports interrupt. So in
953 * order to parse and assign irq resources, DFL framework has to look
954 * into specific capability registers of these private features.
955 *
956 * Once future DFL version supports generic interrupt resource
957 * information in common DFL headers, the generic interrupt parsing
958 * code will be added. But in order to be compatible to old version
959 * DFL, the driver may still fall back to these quirks.
960 */
961 switch (fid) {
962 case PORT_FEATURE_ID_UINT:
963 v = readq(base + PORT_UINT_CAP);
964 ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
965 inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
966 break;
967 case PORT_FEATURE_ID_ERROR:
968 v = readq(base + PORT_ERROR_CAP);
969 ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
970 inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
971 break;
972 case FME_FEATURE_ID_GLOBAL_ERR:
973 v = readq(base + FME_ERROR_CAP);
974 ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
975 inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
976 break;
977 }
978
979 if (!inr) {
980 *irq_base = 0;
981 *nr_irqs = 0;
982 return 0;
983 }
984
985 dev_dbg(binfo->dev, "feature: 0x%x, irq_base: %u, nr_irqs: %u\n",
986 fid, ibase, inr);
987
988 if (ibase + inr > binfo->nr_irqs) {
989 dev_err(binfo->dev,
990 "Invalid interrupt number in feature 0x%x\n", fid);
991 return -EINVAL;
992 }
993
994 for (i = 0; i < inr; i++) {
995 virq = binfo->irq_table[ibase + i];
996 if (virq < 0 || virq > NR_IRQS) {
997 dev_err(binfo->dev,
998 "Invalid irq table entry for feature 0x%x\n",
999 fid);
1000 return -EINVAL;
1001 }
1002 }
1003
1004 *irq_base = ibase;
1005 *nr_irqs = inr;
1006
1007 return 0;
1008}
1009
1010/*
1011 * when create sub feature instances, for private features, it doesn't need
1012 * to provide resource size and feature id as they could be read from DFH
1013 * register. For afu sub feature, its register region only contains user
1014 * defined registers, so never trust any information from it, just use the
1015 * resource size information provided by its parent FIU.
1016 */
1017static int
1018create_feature_instance(struct build_feature_devs_info *binfo,
1019 resource_size_t ofst, resource_size_t size, u16 fid)
1020{
1021 unsigned int irq_base, nr_irqs;
1022 struct dfl_feature_info *finfo;
1023 int ret;
1024
1025 /* read feature size and id if inputs are invalid */
1026 size = size ? size : feature_size(binfo->ioaddr + ofst);
1027 fid = fid ? fid : feature_id(binfo->ioaddr + ofst);
1028
1029 if (binfo->len - ofst < size)
1030 return -EINVAL;
1031
1032 ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs);
1033 if (ret)
1034 return ret;
1035
1036 finfo = kzalloc(sizeof(*finfo), GFP_KERNEL);
1037 if (!finfo)
1038 return -ENOMEM;
1039
1040 finfo->fid = fid;
1041 finfo->mmio_res.start = binfo->start + ofst;
1042 finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
1043 finfo->mmio_res.flags = IORESOURCE_MEM;
1044 finfo->irq_base = irq_base;
1045 finfo->nr_irqs = nr_irqs;
1046
1047 list_add_tail(&finfo->node, &binfo->sub_features);
1048 binfo->feature_num++;
1049
1050 return 0;
1051}
1052
1053static int parse_feature_port_afu(struct build_feature_devs_info *binfo,
1054 resource_size_t ofst)
1055{
1056 u64 v = readq(binfo->ioaddr + PORT_HDR_CAP);
1057 u32 size = FIELD_GET(PORT_CAP_MMIO_SIZE, v) << 10;
1058
1059 WARN_ON(!size);
1060
1061 return create_feature_instance(binfo, ofst, size, FEATURE_ID_AFU);
1062}
1063
1064#define is_feature_dev_detected(binfo) (!!(binfo)->feature_dev)
1065
1066static int parse_feature_afu(struct build_feature_devs_info *binfo,
1067 resource_size_t ofst)
1068{
1069 if (!is_feature_dev_detected(binfo)) {
1070 dev_err(binfo->dev, "this AFU does not belong to any FIU.\n");
1071 return -EINVAL;
1072 }
1073
1074 switch (feature_dev_id_type(binfo->feature_dev)) {
1075 case PORT_ID:
1076 return parse_feature_port_afu(binfo, ofst);
1077 default:
1078 dev_info(binfo->dev, "AFU belonging to FIU %s is not supported yet.\n",
1079 binfo->feature_dev->name);
1080 }
1081
1082 return 0;
1083}
1084
1085static int build_info_prepare(struct build_feature_devs_info *binfo,
1086 resource_size_t start, resource_size_t len)
1087{
1088 struct device *dev = binfo->dev;
1089 void __iomem *ioaddr;
1090
1091 if (!devm_request_mem_region(dev, start, len, dev_name(dev))) {
1092 dev_err(dev, "request region fail, start:%pa, len:%pa\n",
1093 &start, &len);
1094 return -EBUSY;
1095 }
1096
1097 ioaddr = devm_ioremap(dev, start, len);
1098 if (!ioaddr) {
1099 dev_err(dev, "ioremap region fail, start:%pa, len:%pa\n",
1100 &start, &len);
1101 return -ENOMEM;
1102 }
1103
1104 binfo->start = start;
1105 binfo->len = len;
1106 binfo->ioaddr = ioaddr;
1107
1108 return 0;
1109}
1110
1111static void build_info_complete(struct build_feature_devs_info *binfo)
1112{
1113 devm_iounmap(binfo->dev, binfo->ioaddr);
1114 devm_release_mem_region(binfo->dev, binfo->start, binfo->len);
1115}
1116
1117static int parse_feature_fiu(struct build_feature_devs_info *binfo,
1118 resource_size_t ofst)
1119{
1120 int ret = 0;
1121 u32 offset;
1122 u16 id;
1123 u64 v;
1124
1125 if (is_feature_dev_detected(binfo)) {
1126 build_info_complete(binfo);
1127
1128 ret = build_info_commit_dev(binfo);
1129 if (ret)
1130 return ret;
1131
1132 ret = build_info_prepare(binfo, binfo->start + ofst,
1133 binfo->len - ofst);
1134 if (ret)
1135 return ret;
1136 }
1137
1138 v = readq(binfo->ioaddr + DFH);
1139 id = FIELD_GET(DFH_ID, v);
1140
1141 /* create platform device for dfl feature dev */
1142 ret = build_info_create_dev(binfo, dfh_id_to_type(id));
1143 if (ret)
1144 return ret;
1145
1146 ret = create_feature_instance(binfo, 0, 0, 0);
1147 if (ret)
1148 return ret;
1149 /*
1150 * find and parse FIU's child AFU via its NEXT_AFU register.
1151 * please note that only Port has valid NEXT_AFU pointer per spec.
1152 */
1153 v = readq(binfo->ioaddr + NEXT_AFU);
1154
1155 offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v);
1156 if (offset)
1157 return parse_feature_afu(binfo, offset);
1158
1159 dev_dbg(binfo->dev, "No AFUs detected on FIU %d\n", id);
1160
1161 return ret;
1162}
1163
1164static int parse_feature_private(struct build_feature_devs_info *binfo,
1165 resource_size_t ofst)
1166{
1167 if (!is_feature_dev_detected(binfo)) {
1168 dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n",
1169 feature_id(binfo->ioaddr + ofst));
1170 return -EINVAL;
1171 }
1172
1173 return create_feature_instance(binfo, ofst, 0, 0);
1174}
1175
1176/**
1177 * parse_feature - parse a feature on given device feature list
1178 *
1179 * @binfo: build feature devices information.
1180 * @ofst: offset to current FIU header
1181 */
1182static int parse_feature(struct build_feature_devs_info *binfo,
1183 resource_size_t ofst)
1184{
1185 u64 v;
1186 u32 type;
1187
1188 v = readq(binfo->ioaddr + ofst + DFH);
1189 type = FIELD_GET(DFH_TYPE, v);
1190
1191 switch (type) {
1192 case DFH_TYPE_AFU:
1193 return parse_feature_afu(binfo, ofst);
1194 case DFH_TYPE_PRIVATE:
1195 return parse_feature_private(binfo, ofst);
1196 case DFH_TYPE_FIU:
1197 return parse_feature_fiu(binfo, ofst);
1198 default:
1199 dev_info(binfo->dev,
1200 "Feature Type %x is not supported.\n", type);
1201 }
1202
1203 return 0;
1204}
1205
1206static int parse_feature_list(struct build_feature_devs_info *binfo,
1207 resource_size_t start, resource_size_t len)
1208{
1209 resource_size_t end = start + len;
1210 int ret = 0;
1211 u32 ofst = 0;
1212 u64 v;
1213
1214 ret = build_info_prepare(binfo, start, len);
1215 if (ret)
1216 return ret;
1217
1218 /* walk through the device feature list via DFH's next DFH pointer. */
1219 for (; start < end; start += ofst) {
1220 if (end - start < DFH_SIZE) {
1221 dev_err(binfo->dev, "The region is too small to contain a feature.\n");
1222 return -EINVAL;
1223 }
1224
1225 ret = parse_feature(binfo, start - binfo->start);
1226 if (ret)
1227 return ret;
1228
1229 v = readq(binfo->ioaddr + start - binfo->start + DFH);
1230 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
1231
1232 /* stop parsing if EOL(End of List) is set or offset is 0 */
1233 if ((v & DFH_EOL) || !ofst)
1234 break;
1235 }
1236
1237 /* commit current feature device when reach the end of list */
1238 build_info_complete(binfo);
1239
1240 if (is_feature_dev_detected(binfo))
1241 ret = build_info_commit_dev(binfo);
1242
1243 return ret;
1244}
1245
1246struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev)
1247{
1248 struct dfl_fpga_enum_info *info;
1249
1250 get_device(dev);
1251
1252 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1253 if (!info) {
1254 put_device(dev);
1255 return NULL;
1256 }
1257
1258 info->dev = dev;
1259 INIT_LIST_HEAD(&info->dfls);
1260
1261 return info;
1262}
1263EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_alloc);
1264
1265void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info)
1266{
1267 struct dfl_fpga_enum_dfl *tmp, *dfl;
1268 struct device *dev;
1269
1270 if (!info)
1271 return;
1272
1273 dev = info->dev;
1274
1275 /* remove all device feature lists in the list. */
1276 list_for_each_entry_safe(dfl, tmp, &info->dfls, node) {
1277 list_del(&dfl->node);
1278 devm_kfree(dev, dfl);
1279 }
1280
1281 /* remove irq table */
1282 if (info->irq_table)
1283 devm_kfree(dev, info->irq_table);
1284
1285 devm_kfree(dev, info);
1286 put_device(dev);
1287}
1288EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_free);
1289
1290/**
1291 * dfl_fpga_enum_info_add_dfl - add info of a device feature list to enum info
1292 *
1293 * @info: ptr to dfl_fpga_enum_info
1294 * @start: mmio resource address of the device feature list.
1295 * @len: mmio resource length of the device feature list.
1296 *
1297 * One FPGA device may have one or more Device Feature Lists (DFLs), use this
1298 * function to add information of each DFL to common data structure for next
1299 * step enumeration.
1300 *
1301 * Return: 0 on success, negative error code otherwise.
1302 */
1303int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
1304 resource_size_t start, resource_size_t len)
1305{
1306 struct dfl_fpga_enum_dfl *dfl;
1307
1308 dfl = devm_kzalloc(info->dev, sizeof(*dfl), GFP_KERNEL);
1309 if (!dfl)
1310 return -ENOMEM;
1311
1312 dfl->start = start;
1313 dfl->len = len;
1314
1315 list_add_tail(&dfl->node, &info->dfls);
1316
1317 return 0;
1318}
1319EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_add_dfl);
1320
1321/**
1322 * dfl_fpga_enum_info_add_irq - add irq table to enum info
1323 *
1324 * @info: ptr to dfl_fpga_enum_info
1325 * @nr_irqs: number of irqs of the DFL fpga device to be enumerated.
1326 * @irq_table: Linux IRQ numbers for all irqs, indexed by local irq index of
1327 * this device.
1328 *
1329 * One FPGA device may have several interrupts. This function adds irq
1330 * information of the DFL fpga device to enum info for next step enumeration.
1331 * This function should be called before dfl_fpga_feature_devs_enumerate().
1332 * As we only support one irq domain for all DFLs in the same enum info, adding
1333 * irq table a second time for the same enum info will return error.
1334 *
1335 * If we need to enumerate DFLs which belong to different irq domains, we
1336 * should fill more enum info and enumerate them one by one.
1337 *
1338 * Return: 0 on success, negative error code otherwise.
1339 */
1340int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
1341 unsigned int nr_irqs, int *irq_table)
1342{
1343 if (!nr_irqs || !irq_table)
1344 return -EINVAL;
1345
1346 if (info->irq_table)
1347 return -EEXIST;
1348
1349 info->irq_table = devm_kmemdup(info->dev, irq_table,
1350 sizeof(int) * nr_irqs, GFP_KERNEL);
1351 if (!info->irq_table)
1352 return -ENOMEM;
1353
1354 info->nr_irqs = nr_irqs;
1355
1356 return 0;
1357}
1358EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_add_irq);
1359
1360static int remove_feature_dev(struct device *dev, void *data)
1361{
1362 struct platform_device *pdev = to_platform_device(dev);
1363 enum dfl_id_type type = feature_dev_id_type(pdev);
1364 int id = pdev->id;
1365
1366 platform_device_unregister(pdev);
1367
1368 dfl_id_free(type, id);
1369
1370 return 0;
1371}
1372
1373static void remove_feature_devs(struct dfl_fpga_cdev *cdev)
1374{
1375 device_for_each_child(&cdev->region->dev, NULL, remove_feature_dev);
1376}
1377
1378/**
1379 * dfl_fpga_feature_devs_enumerate - enumerate feature devices
1380 * @info: information for enumeration.
1381 *
1382 * This function creates a container device (base FPGA region), enumerates
1383 * feature devices based on the enumeration info and creates platform devices
1384 * under the container device.
1385 *
1386 * Return: dfl_fpga_cdev struct on success, -errno on failure
1387 */
1388struct dfl_fpga_cdev *
1389dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
1390{
1391 struct build_feature_devs_info *binfo;
1392 struct dfl_fpga_enum_dfl *dfl;
1393 struct dfl_fpga_cdev *cdev;
1394 int ret = 0;
1395
1396 if (!info->dev)
1397 return ERR_PTR(-ENODEV);
1398
1399 cdev = devm_kzalloc(info->dev, sizeof(*cdev), GFP_KERNEL);
1400 if (!cdev)
1401 return ERR_PTR(-ENOMEM);
1402
1403 cdev->region = devm_fpga_region_create(info->dev, NULL, NULL);
1404 if (!cdev->region) {
1405 ret = -ENOMEM;
1406 goto free_cdev_exit;
1407 }
1408
1409 cdev->parent = info->dev;
1410 mutex_init(&cdev->lock);
1411 INIT_LIST_HEAD(&cdev->port_dev_list);
1412
1413 ret = fpga_region_register(cdev->region);
1414 if (ret)
1415 goto free_cdev_exit;
1416
1417 /* create and init build info for enumeration */
1418 binfo = devm_kzalloc(info->dev, sizeof(*binfo), GFP_KERNEL);
1419 if (!binfo) {
1420 ret = -ENOMEM;
1421 goto unregister_region_exit;
1422 }
1423
1424 binfo->dev = info->dev;
1425 binfo->cdev = cdev;
1426
1427 binfo->nr_irqs = info->nr_irqs;
1428 if (info->nr_irqs)
1429 binfo->irq_table = info->irq_table;
1430
1431 /*
1432 * start enumeration for all feature devices based on Device Feature
1433 * Lists.
1434 */
1435 list_for_each_entry(dfl, &info->dfls, node) {
1436 ret = parse_feature_list(binfo, dfl->start, dfl->len);
1437 if (ret) {
1438 remove_feature_devs(cdev);
1439 build_info_free(binfo);
1440 goto unregister_region_exit;
1441 }
1442 }
1443
1444 build_info_free(binfo);
1445
1446 return cdev;
1447
1448unregister_region_exit:
1449 fpga_region_unregister(cdev->region);
1450free_cdev_exit:
1451 devm_kfree(info->dev, cdev);
1452 return ERR_PTR(ret);
1453}
1454EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_enumerate);
1455
1456/**
1457 * dfl_fpga_feature_devs_remove - remove all feature devices
1458 * @cdev: fpga container device.
1459 *
1460 * Remove the container device and all feature devices under given container
1461 * devices.
1462 */
1463void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev)
1464{
1465 struct dfl_feature_platform_data *pdata, *ptmp;
1466
1467 mutex_lock(&cdev->lock);
1468 if (cdev->fme_dev)
1469 put_device(cdev->fme_dev);
1470
1471 list_for_each_entry_safe(pdata, ptmp, &cdev->port_dev_list, node) {
1472 struct platform_device *port_dev = pdata->dev;
1473
1474 /* remove released ports */
1475 if (!device_is_registered(&port_dev->dev)) {
1476 dfl_id_free(feature_dev_id_type(port_dev),
1477 port_dev->id);
1478 platform_device_put(port_dev);
1479 }
1480
1481 list_del(&pdata->node);
1482 put_device(&port_dev->dev);
1483 }
1484 mutex_unlock(&cdev->lock);
1485
1486 remove_feature_devs(cdev);
1487
1488 fpga_region_unregister(cdev->region);
1489 devm_kfree(cdev->parent, cdev);
1490}
1491EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_remove);
1492
1493/**
1494 * __dfl_fpga_cdev_find_port - find a port under given container device
1495 *
1496 * @cdev: container device
1497 * @data: data passed to match function
1498 * @match: match function used to find specific port from the port device list
1499 *
1500 * Find a port device under container device. This function needs to be
1501 * invoked with lock held.
1502 *
1503 * Return: pointer to port's platform device if successful, NULL otherwise.
1504 *
1505 * NOTE: you will need to drop the device reference with put_device() after use.
1506 */
1507struct platform_device *
1508__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
1509 int (*match)(struct platform_device *, void *))
1510{
1511 struct dfl_feature_platform_data *pdata;
1512 struct platform_device *port_dev;
1513
1514 list_for_each_entry(pdata, &cdev->port_dev_list, node) {
1515 port_dev = pdata->dev;
1516
1517 if (match(port_dev, data) && get_device(&port_dev->dev))
1518 return port_dev;
1519 }
1520
1521 return NULL;
1522}
1523EXPORT_SYMBOL_GPL(__dfl_fpga_cdev_find_port);
1524
1525static int __init dfl_fpga_init(void)
1526{
1527 int ret;
1528
1529 ret = bus_register(&dfl_bus_type);
1530 if (ret)
1531 return ret;
1532
1533 dfl_ids_init();
1534
1535 ret = dfl_chardev_init();
1536 if (ret) {
1537 dfl_ids_destroy();
1538 bus_unregister(&dfl_bus_type);
1539 }
1540
1541 return ret;
1542}
1543
1544/**
1545 * dfl_fpga_cdev_release_port - release a port platform device
1546 *
1547 * @cdev: parent container device.
1548 * @port_id: id of the port platform device.
1549 *
1550 * This function allows user to release a port platform device. This is a
1551 * mandatory step before turn a port from PF into VF for SRIOV support.
1552 *
1553 * Return: 0 on success, negative error code otherwise.
1554 */
1555int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id)
1556{
1557 struct dfl_feature_platform_data *pdata;
1558 struct platform_device *port_pdev;
1559 int ret = -ENODEV;
1560
1561 mutex_lock(&cdev->lock);
1562 port_pdev = __dfl_fpga_cdev_find_port(cdev, &port_id,
1563 dfl_fpga_check_port_id);
1564 if (!port_pdev)
1565 goto unlock_exit;
1566
1567 if (!device_is_registered(&port_pdev->dev)) {
1568 ret = -EBUSY;
1569 goto put_dev_exit;
1570 }
1571
1572 pdata = dev_get_platdata(&port_pdev->dev);
1573
1574 mutex_lock(&pdata->lock);
1575 ret = dfl_feature_dev_use_begin(pdata, true);
1576 mutex_unlock(&pdata->lock);
1577 if (ret)
1578 goto put_dev_exit;
1579
1580 platform_device_del(port_pdev);
1581 cdev->released_port_num++;
1582put_dev_exit:
1583 put_device(&port_pdev->dev);
1584unlock_exit:
1585 mutex_unlock(&cdev->lock);
1586 return ret;
1587}
1588EXPORT_SYMBOL_GPL(dfl_fpga_cdev_release_port);
1589
1590/**
1591 * dfl_fpga_cdev_assign_port - assign a port platform device back
1592 *
1593 * @cdev: parent container device.
1594 * @port_id: id of the port platform device.
1595 *
1596 * This function allows user to assign a port platform device back. This is
1597 * a mandatory step after disable SRIOV support.
1598 *
1599 * Return: 0 on success, negative error code otherwise.
1600 */
1601int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id)
1602{
1603 struct dfl_feature_platform_data *pdata;
1604 struct platform_device *port_pdev;
1605 int ret = -ENODEV;
1606
1607 mutex_lock(&cdev->lock);
1608 port_pdev = __dfl_fpga_cdev_find_port(cdev, &port_id,
1609 dfl_fpga_check_port_id);
1610 if (!port_pdev)
1611 goto unlock_exit;
1612
1613 if (device_is_registered(&port_pdev->dev)) {
1614 ret = -EBUSY;
1615 goto put_dev_exit;
1616 }
1617
1618 ret = platform_device_add(port_pdev);
1619 if (ret)
1620 goto put_dev_exit;
1621
1622 pdata = dev_get_platdata(&port_pdev->dev);
1623
1624 mutex_lock(&pdata->lock);
1625 dfl_feature_dev_use_end(pdata);
1626 mutex_unlock(&pdata->lock);
1627
1628 cdev->released_port_num--;
1629put_dev_exit:
1630 put_device(&port_pdev->dev);
1631unlock_exit:
1632 mutex_unlock(&cdev->lock);
1633 return ret;
1634}
1635EXPORT_SYMBOL_GPL(dfl_fpga_cdev_assign_port);
1636
1637static void config_port_access_mode(struct device *fme_dev, int port_id,
1638 bool is_vf)
1639{
1640 void __iomem *base;
1641 u64 v;
1642
1643 base = dfl_get_feature_ioaddr_by_id(fme_dev, FME_FEATURE_ID_HEADER);
1644
1645 v = readq(base + FME_HDR_PORT_OFST(port_id));
1646
1647 v &= ~FME_PORT_OFST_ACC_CTRL;
1648 v |= FIELD_PREP(FME_PORT_OFST_ACC_CTRL,
1649 is_vf ? FME_PORT_OFST_ACC_VF : FME_PORT_OFST_ACC_PF);
1650
1651 writeq(v, base + FME_HDR_PORT_OFST(port_id));
1652}
1653
1654#define config_port_vf_mode(dev, id) config_port_access_mode(dev, id, true)
1655#define config_port_pf_mode(dev, id) config_port_access_mode(dev, id, false)
1656
1657/**
1658 * dfl_fpga_cdev_config_ports_pf - configure ports to PF access mode
1659 *
1660 * @cdev: parent container device.
1661 *
1662 * This function is needed in sriov configuration routine. It could be used to
1663 * configure the all released ports from VF access mode to PF.
1664 */
1665void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev)
1666{
1667 struct dfl_feature_platform_data *pdata;
1668
1669 mutex_lock(&cdev->lock);
1670 list_for_each_entry(pdata, &cdev->port_dev_list, node) {
1671 if (device_is_registered(&pdata->dev->dev))
1672 continue;
1673
1674 config_port_pf_mode(cdev->fme_dev, pdata->id);
1675 }
1676 mutex_unlock(&cdev->lock);
1677}
1678EXPORT_SYMBOL_GPL(dfl_fpga_cdev_config_ports_pf);
1679
1680/**
1681 * dfl_fpga_cdev_config_ports_vf - configure ports to VF access mode
1682 *
1683 * @cdev: parent container device.
1684 * @num_vfs: VF device number.
1685 *
1686 * This function is needed in sriov configuration routine. It could be used to
1687 * configure the released ports from PF access mode to VF.
1688 *
1689 * Return: 0 on success, negative error code otherwise.
1690 */
1691int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
1692{
1693 struct dfl_feature_platform_data *pdata;
1694 int ret = 0;
1695
1696 mutex_lock(&cdev->lock);
1697 /*
1698 * can't turn multiple ports into 1 VF device, only 1 port for 1 VF
1699 * device, so if released port number doesn't match VF device number,
1700 * then reject the request with -EINVAL error code.
1701 */
1702 if (cdev->released_port_num != num_vfs) {
1703 ret = -EINVAL;
1704 goto done;
1705 }
1706
1707 list_for_each_entry(pdata, &cdev->port_dev_list, node) {
1708 if (device_is_registered(&pdata->dev->dev))
1709 continue;
1710
1711 config_port_vf_mode(cdev->fme_dev, pdata->id);
1712 }
1713done:
1714 mutex_unlock(&cdev->lock);
1715 return ret;
1716}
1717EXPORT_SYMBOL_GPL(dfl_fpga_cdev_config_ports_vf);
1718
1719static irqreturn_t dfl_irq_handler(int irq, void *arg)
1720{
1721 struct eventfd_ctx *trigger = arg;
1722
1723 eventfd_signal(trigger, 1);
1724 return IRQ_HANDLED;
1725}
1726
1727static int do_set_irq_trigger(struct dfl_feature *feature, unsigned int idx,
1728 int fd)
1729{
1730 struct platform_device *pdev = feature->dev;
1731 struct eventfd_ctx *trigger;
1732 int irq, ret;
1733
1734 irq = feature->irq_ctx[idx].irq;
1735
1736 if (feature->irq_ctx[idx].trigger) {
1737 free_irq(irq, feature->irq_ctx[idx].trigger);
1738 kfree(feature->irq_ctx[idx].name);
1739 eventfd_ctx_put(feature->irq_ctx[idx].trigger);
1740 feature->irq_ctx[idx].trigger = NULL;
1741 }
1742
1743 if (fd < 0)
1744 return 0;
1745
1746 feature->irq_ctx[idx].name =
1747 kasprintf(GFP_KERNEL, "fpga-irq[%u](%s-%x)", idx,
1748 dev_name(&pdev->dev), feature->id);
1749 if (!feature->irq_ctx[idx].name)
1750 return -ENOMEM;
1751
1752 trigger = eventfd_ctx_fdget(fd);
1753 if (IS_ERR(trigger)) {
1754 ret = PTR_ERR(trigger);
1755 goto free_name;
1756 }
1757
1758 ret = request_irq(irq, dfl_irq_handler, 0,
1759 feature->irq_ctx[idx].name, trigger);
1760 if (!ret) {
1761 feature->irq_ctx[idx].trigger = trigger;
1762 return ret;
1763 }
1764
1765 eventfd_ctx_put(trigger);
1766free_name:
1767 kfree(feature->irq_ctx[idx].name);
1768
1769 return ret;
1770}
1771
1772/**
1773 * dfl_fpga_set_irq_triggers - set eventfd triggers for dfl feature interrupts
1774 *
1775 * @feature: dfl sub feature.
1776 * @start: start of irq index in this dfl sub feature.
1777 * @count: number of irqs.
1778 * @fds: eventfds to bind with irqs. unbind related irq if fds[n] is negative.
1779 * unbind "count" specified number of irqs if fds ptr is NULL.
1780 *
1781 * Bind given eventfds with irqs in this dfl sub feature. Unbind related irq if
1782 * fds[n] is negative. Unbind "count" specified number of irqs if fds ptr is
1783 * NULL.
1784 *
1785 * Return: 0 on success, negative error code otherwise.
1786 */
1787int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
1788 unsigned int count, int32_t *fds)
1789{
1790 unsigned int i;
1791 int ret = 0;
1792
1793 /* overflow */
1794 if (unlikely(start + count < start))
1795 return -EINVAL;
1796
1797 /* exceeds nr_irqs */
1798 if (start + count > feature->nr_irqs)
1799 return -EINVAL;
1800
1801 for (i = 0; i < count; i++) {
1802 int fd = fds ? fds[i] : -1;
1803
1804 ret = do_set_irq_trigger(feature, start + i, fd);
1805 if (ret) {
1806 while (i--)
1807 do_set_irq_trigger(feature, start + i, -1);
1808 break;
1809 }
1810 }
1811
1812 return ret;
1813}
1814EXPORT_SYMBOL_GPL(dfl_fpga_set_irq_triggers);
1815
1816/**
1817 * dfl_feature_ioctl_get_num_irqs - dfl feature _GET_IRQ_NUM ioctl interface.
1818 * @pdev: the feature device which has the sub feature
1819 * @feature: the dfl sub feature
1820 * @arg: ioctl argument
1821 *
1822 * Return: 0 on success, negative error code otherwise.
1823 */
1824long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
1825 struct dfl_feature *feature,
1826 unsigned long arg)
1827{
1828 return put_user(feature->nr_irqs, (__u32 __user *)arg);
1829}
1830EXPORT_SYMBOL_GPL(dfl_feature_ioctl_get_num_irqs);
1831
1832/**
1833 * dfl_feature_ioctl_set_irq - dfl feature _SET_IRQ ioctl interface.
1834 * @pdev: the feature device which has the sub feature
1835 * @feature: the dfl sub feature
1836 * @arg: ioctl argument
1837 *
1838 * Return: 0 on success, negative error code otherwise.
1839 */
1840long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
1841 struct dfl_feature *feature,
1842 unsigned long arg)
1843{
1844 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
1845 struct dfl_fpga_irq_set hdr;
1846 s32 *fds;
1847 long ret;
1848
1849 if (!feature->nr_irqs)
1850 return -ENOENT;
1851
1852 if (copy_from_user(&hdr, (void __user *)arg, sizeof(hdr)))
1853 return -EFAULT;
1854
1855 if (!hdr.count || (hdr.start + hdr.count > feature->nr_irqs) ||
1856 (hdr.start + hdr.count < hdr.start))
1857 return -EINVAL;
1858
1859 fds = memdup_user((void __user *)(arg + sizeof(hdr)),
1860 hdr.count * sizeof(s32));
1861 if (IS_ERR(fds))
1862 return PTR_ERR(fds);
1863
1864 mutex_lock(&pdata->lock);
1865 ret = dfl_fpga_set_irq_triggers(feature, hdr.start, hdr.count, fds);
1866 mutex_unlock(&pdata->lock);
1867
1868 kfree(fds);
1869 return ret;
1870}
1871EXPORT_SYMBOL_GPL(dfl_feature_ioctl_set_irq);
1872
1873static void __exit dfl_fpga_exit(void)
1874{
1875 dfl_chardev_uinit();
1876 dfl_ids_destroy();
1877 bus_unregister(&dfl_bus_type);
1878}
1879
1880module_init(dfl_fpga_init);
1881module_exit(dfl_fpga_exit);
1882
1883MODULE_DESCRIPTION("FPGA Device Feature List (DFL) Support");
1884MODULE_AUTHOR("Intel Corporation");
1885MODULE_LICENSE("GPL v2");