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1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/fpu/internal.h>
72#include <asm/setup.h>
73#include <asm/uv/uv.h>
74#include <linux/mc146818rtc.h>
75#include <asm/i8259.h>
76#include <asm/realmode.h>
77#include <asm/misc.h>
78
79/* Number of siblings per CPU package */
80int smp_num_siblings = 1;
81EXPORT_SYMBOL(smp_num_siblings);
82
83/* Last level cache ID of each logical CPU */
84DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85
86/* representing HT siblings of each logical CPU */
87DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89
90/* representing HT and core siblings of each logical CPU */
91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95
96/* Per CPU bogomips and other parameters */
97DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98EXPORT_PER_CPU_SYMBOL(cpu_info);
99
100/* Logical package management. We might want to allocate that dynamically */
101static int *physical_to_logical_pkg __read_mostly;
102static unsigned long *physical_package_map __read_mostly;;
103static unsigned long *logical_package_map __read_mostly;
104static unsigned int max_physical_pkg_id __read_mostly;
105unsigned int __max_logical_packages __read_mostly;
106EXPORT_SYMBOL(__max_logical_packages);
107
108static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
109{
110 unsigned long flags;
111
112 spin_lock_irqsave(&rtc_lock, flags);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock, flags);
115 local_flush_tlb();
116 pr_debug("1.\n");
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
118 start_eip >> 4;
119 pr_debug("2.\n");
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
121 start_eip & 0xf;
122 pr_debug("3.\n");
123}
124
125static inline void smpboot_restore_warm_reset_vector(void)
126{
127 unsigned long flags;
128
129 /*
130 * Install writable page 0 entry to set BIOS data area.
131 */
132 local_flush_tlb();
133
134 /*
135 * Paranoid: Set warm reset code and vector here back
136 * to default values.
137 */
138 spin_lock_irqsave(&rtc_lock, flags);
139 CMOS_WRITE(0, 0xf);
140 spin_unlock_irqrestore(&rtc_lock, flags);
141
142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
143}
144
145/*
146 * Report back to the Boot Processor during boot time or to the caller processor
147 * during CPU online.
148 */
149static void smp_callin(void)
150{
151 int cpuid, phys_id;
152
153 /*
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
158 */
159 cpuid = smp_processor_id();
160
161 /*
162 * (This works even if the APIC is not enabled.)
163 */
164 phys_id = read_apic_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * Get our bogomips.
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
185 */
186 calibrate_delay();
187 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
188 pr_debug("Stack at about %p\n", &cpuid);
189
190 /*
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
193 */
194 set_cpu_sibling_map(raw_smp_processor_id());
195 wmb();
196
197 notify_cpu_starting(cpuid);
198
199 /*
200 * Allow the master to continue.
201 */
202 cpumask_set_cpu(cpuid, cpu_callin_mask);
203}
204
205static int cpu0_logical_apicid;
206static int enable_start_cpu0;
207/*
208 * Activate a secondary processor.
209 */
210static void notrace start_secondary(void *unused)
211{
212 /*
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
216 */
217 cpu_init();
218 x86_cpuinit.early_percpu_clock_init();
219 preempt_disable();
220 smp_callin();
221
222 enable_start_cpu0 = 0;
223
224#ifdef CONFIG_X86_32
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir);
227 __flush_tlb_all();
228#endif
229
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
231 barrier();
232 /*
233 * Check TSC synchronization with the BP:
234 */
235 check_tsc_sync_target();
236
237 /*
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
242 */
243 lock_vector_lock();
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform.nmi_init();
249
250 /* enable local interrupts */
251 local_irq_enable();
252
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
255
256 x86_cpuinit.setup_percpu_clockev();
257
258 wmb();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
260}
261
262int topology_update_package_map(unsigned int apicid, unsigned int cpu)
263{
264 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
265
266 /* Called from early boot ? */
267 if (!physical_package_map)
268 return 0;
269
270 if (pkg >= max_physical_pkg_id)
271 return -EINVAL;
272
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg, physical_package_map))
275 goto found;
276
277 new = find_first_zero_bit(logical_package_map, __max_logical_packages);
278 if (new >= __max_logical_packages) {
279 physical_to_logical_pkg[pkg] = -1;
280 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
281 apicid, pkg);
282 return -ENOSPC;
283 }
284 set_bit(new, logical_package_map);
285 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
286 apicid, pkg, new);
287 physical_to_logical_pkg[pkg] = new;
288
289found:
290 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
291 return 0;
292}
293
294/**
295 * topology_phys_to_logical_pkg - Map a physical package id to a logical
296 *
297 * Returns logical package id or -1 if not found
298 */
299int topology_phys_to_logical_pkg(unsigned int phys_pkg)
300{
301 if (phys_pkg >= max_physical_pkg_id)
302 return -1;
303 return physical_to_logical_pkg[phys_pkg];
304}
305EXPORT_SYMBOL(topology_phys_to_logical_pkg);
306
307static void __init smp_init_package_map(void)
308{
309 unsigned int ncpus, cpu;
310 size_t size;
311
312 /*
313 * Today neither Intel nor AMD support heterogenous systems. That
314 * might change in the future....
315 *
316 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
317 * computation, this won't actually work since some Intel BIOSes
318 * report inconsistent HT data when they disable HT.
319 *
320 * In particular, they reduce the APIC-IDs to only include the cores,
321 * but leave the CPUID topology to say there are (2) siblings.
322 * This means we don't know how many threads there will be until
323 * after the APIC enumeration.
324 *
325 * By not including this we'll sometimes over-estimate the number of
326 * logical packages by the amount of !present siblings, but this is
327 * still better than MAX_LOCAL_APIC.
328 *
329 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
330 * on the command line leading to a similar issue as the HT disable
331 * problem because the hyperthreads are usually enumerated after the
332 * primary cores.
333 */
334 ncpus = boot_cpu_data.x86_max_cores;
335 if (!ncpus) {
336 pr_warn("x86_max_cores == zero !?!?");
337 ncpus = 1;
338 }
339
340 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
341
342 /*
343 * Possibly larger than what we need as the number of apic ids per
344 * package can be smaller than the actual used apic ids.
345 */
346 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
347 size = max_physical_pkg_id * sizeof(unsigned int);
348 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
349 memset(physical_to_logical_pkg, 0xff, size);
350 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
351 physical_package_map = kzalloc(size, GFP_KERNEL);
352 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long);
353 logical_package_map = kzalloc(size, GFP_KERNEL);
354
355 pr_info("Max logical packages: %u\n", __max_logical_packages);
356
357 for_each_present_cpu(cpu) {
358 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
359
360 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
361 continue;
362 if (!topology_update_package_map(apicid, cpu))
363 continue;
364 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
365 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
366 set_cpu_possible(cpu, false);
367 set_cpu_present(cpu, false);
368 }
369}
370
371void __init smp_store_boot_cpu_info(void)
372{
373 int id = 0; /* CPU 0 */
374 struct cpuinfo_x86 *c = &cpu_data(id);
375
376 *c = boot_cpu_data;
377 c->cpu_index = id;
378 smp_init_package_map();
379}
380
381/*
382 * The bootstrap kernel entry code has set these up. Save them for
383 * a given CPU
384 */
385void smp_store_cpu_info(int id)
386{
387 struct cpuinfo_x86 *c = &cpu_data(id);
388
389 *c = boot_cpu_data;
390 c->cpu_index = id;
391 /*
392 * During boot time, CPU0 has this setup already. Save the info when
393 * bringing up AP or offlined CPU0.
394 */
395 identify_secondary_cpu(c);
396}
397
398static bool
399topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
400{
401 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
402
403 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
404}
405
406static bool
407topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
408{
409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
410
411 return !WARN_ONCE(!topology_same_node(c, o),
412 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
413 "[node: %d != %d]. Ignoring dependency.\n",
414 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
415}
416
417#define link_mask(mfunc, c1, c2) \
418do { \
419 cpumask_set_cpu((c1), mfunc(c2)); \
420 cpumask_set_cpu((c2), mfunc(c1)); \
421} while (0)
422
423static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
424{
425 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427
428 if (c->phys_proc_id == o->phys_proc_id &&
429 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
430 c->cpu_core_id == o->cpu_core_id)
431 return topology_sane(c, o, "smt");
432
433 } else if (c->phys_proc_id == o->phys_proc_id &&
434 c->cpu_core_id == o->cpu_core_id) {
435 return topology_sane(c, o, "smt");
436 }
437
438 return false;
439}
440
441static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
442{
443 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
444
445 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
447 return topology_sane(c, o, "llc");
448
449 return false;
450}
451
452/*
453 * Unlike the other levels, we do not enforce keeping a
454 * multicore group inside a NUMA node. If this happens, we will
455 * discard the MC level of the topology later.
456 */
457static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
458{
459 if (c->phys_proc_id == o->phys_proc_id)
460 return true;
461 return false;
462}
463
464static struct sched_domain_topology_level numa_inside_package_topology[] = {
465#ifdef CONFIG_SCHED_SMT
466 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
467#endif
468#ifdef CONFIG_SCHED_MC
469 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
470#endif
471 { NULL, },
472};
473/*
474 * set_sched_topology() sets the topology internal to a CPU. The
475 * NUMA topologies are layered on top of it to build the full
476 * system topology.
477 *
478 * If NUMA nodes are observed to occur within a CPU package, this
479 * function should be called. It forces the sched domain code to
480 * only use the SMT level for the CPU portion of the topology.
481 * This essentially falls back to relying on NUMA information
482 * from the SRAT table to describe the entire system topology
483 * (except for hyperthreads).
484 */
485static void primarily_use_numa_for_topology(void)
486{
487 set_sched_topology(numa_inside_package_topology);
488}
489
490void set_cpu_sibling_map(int cpu)
491{
492 bool has_smt = smp_num_siblings > 1;
493 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
494 struct cpuinfo_x86 *c = &cpu_data(cpu);
495 struct cpuinfo_x86 *o;
496 int i;
497
498 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
499
500 if (!has_mp) {
501 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
502 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
503 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
504 c->booted_cores = 1;
505 return;
506 }
507
508 for_each_cpu(i, cpu_sibling_setup_mask) {
509 o = &cpu_data(i);
510
511 if ((i == cpu) || (has_smt && match_smt(c, o)))
512 link_mask(topology_sibling_cpumask, cpu, i);
513
514 if ((i == cpu) || (has_mp && match_llc(c, o)))
515 link_mask(cpu_llc_shared_mask, cpu, i);
516
517 }
518
519 /*
520 * This needs a separate iteration over the cpus because we rely on all
521 * topology_sibling_cpumask links to be set-up.
522 */
523 for_each_cpu(i, cpu_sibling_setup_mask) {
524 o = &cpu_data(i);
525
526 if ((i == cpu) || (has_mp && match_die(c, o))) {
527 link_mask(topology_core_cpumask, cpu, i);
528
529 /*
530 * Does this new cpu bringup a new core?
531 */
532 if (cpumask_weight(
533 topology_sibling_cpumask(cpu)) == 1) {
534 /*
535 * for each core in package, increment
536 * the booted_cores for this new cpu
537 */
538 if (cpumask_first(
539 topology_sibling_cpumask(i)) == i)
540 c->booted_cores++;
541 /*
542 * increment the core count for all
543 * the other cpus in this package
544 */
545 if (i != cpu)
546 cpu_data(i).booted_cores++;
547 } else if (i != cpu && !c->booted_cores)
548 c->booted_cores = cpu_data(i).booted_cores;
549 }
550 if (match_die(c, o) && !topology_same_node(c, o))
551 primarily_use_numa_for_topology();
552 }
553}
554
555/* maps the cpu to the sched domain representing multi-core */
556const struct cpumask *cpu_coregroup_mask(int cpu)
557{
558 return cpu_llc_shared_mask(cpu);
559}
560
561static void impress_friends(void)
562{
563 int cpu;
564 unsigned long bogosum = 0;
565 /*
566 * Allow the user to impress friends.
567 */
568 pr_debug("Before bogomips\n");
569 for_each_possible_cpu(cpu)
570 if (cpumask_test_cpu(cpu, cpu_callout_mask))
571 bogosum += cpu_data(cpu).loops_per_jiffy;
572 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
573 num_online_cpus(),
574 bogosum/(500000/HZ),
575 (bogosum/(5000/HZ))%100);
576
577 pr_debug("Before bogocount - setting activated=1\n");
578}
579
580void __inquire_remote_apic(int apicid)
581{
582 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
583 const char * const names[] = { "ID", "VERSION", "SPIV" };
584 int timeout;
585 u32 status;
586
587 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
588
589 for (i = 0; i < ARRAY_SIZE(regs); i++) {
590 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
591
592 /*
593 * Wait for idle.
594 */
595 status = safe_apic_wait_icr_idle();
596 if (status)
597 pr_cont("a previous APIC delivery may have failed\n");
598
599 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
600
601 timeout = 0;
602 do {
603 udelay(100);
604 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
605 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
606
607 switch (status) {
608 case APIC_ICR_RR_VALID:
609 status = apic_read(APIC_RRR);
610 pr_cont("%08x\n", status);
611 break;
612 default:
613 pr_cont("failed\n");
614 }
615 }
616}
617
618/*
619 * The Multiprocessor Specification 1.4 (1997) example code suggests
620 * that there should be a 10ms delay between the BSP asserting INIT
621 * and de-asserting INIT, when starting a remote processor.
622 * But that slows boot and resume on modern processors, which include
623 * many cores and don't require that delay.
624 *
625 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
626 * Modern processor families are quirked to remove the delay entirely.
627 */
628#define UDELAY_10MS_DEFAULT 10000
629
630static unsigned int init_udelay = UINT_MAX;
631
632static int __init cpu_init_udelay(char *str)
633{
634 get_option(&str, &init_udelay);
635
636 return 0;
637}
638early_param("cpu_init_udelay", cpu_init_udelay);
639
640static void __init smp_quirk_init_udelay(void)
641{
642 /* if cmdline changed it from default, leave it alone */
643 if (init_udelay != UINT_MAX)
644 return;
645
646 /* if modern processor, use no delay */
647 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
648 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
649 init_udelay = 0;
650 return;
651 }
652 /* else, use legacy delay */
653 init_udelay = UDELAY_10MS_DEFAULT;
654}
655
656/*
657 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
658 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
659 * won't ... remember to clear down the APIC, etc later.
660 */
661int
662wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
663{
664 unsigned long send_status, accept_status = 0;
665 int maxlvt;
666
667 /* Target chip */
668 /* Boot on the stack */
669 /* Kick the second */
670 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
671
672 pr_debug("Waiting for send to finish...\n");
673 send_status = safe_apic_wait_icr_idle();
674
675 /*
676 * Give the other CPU some time to accept the IPI.
677 */
678 udelay(200);
679 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
680 maxlvt = lapic_get_maxlvt();
681 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
682 apic_write(APIC_ESR, 0);
683 accept_status = (apic_read(APIC_ESR) & 0xEF);
684 }
685 pr_debug("NMI sent\n");
686
687 if (send_status)
688 pr_err("APIC never delivered???\n");
689 if (accept_status)
690 pr_err("APIC delivery error (%lx)\n", accept_status);
691
692 return (send_status | accept_status);
693}
694
695static int
696wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
697{
698 unsigned long send_status = 0, accept_status = 0;
699 int maxlvt, num_starts, j;
700
701 maxlvt = lapic_get_maxlvt();
702
703 /*
704 * Be paranoid about clearing APIC errors.
705 */
706 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
707 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
708 apic_write(APIC_ESR, 0);
709 apic_read(APIC_ESR);
710 }
711
712 pr_debug("Asserting INIT\n");
713
714 /*
715 * Turn INIT on target chip
716 */
717 /*
718 * Send IPI
719 */
720 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
721 phys_apicid);
722
723 pr_debug("Waiting for send to finish...\n");
724 send_status = safe_apic_wait_icr_idle();
725
726 udelay(init_udelay);
727
728 pr_debug("Deasserting INIT\n");
729
730 /* Target chip */
731 /* Send IPI */
732 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
733
734 pr_debug("Waiting for send to finish...\n");
735 send_status = safe_apic_wait_icr_idle();
736
737 mb();
738
739 /*
740 * Should we send STARTUP IPIs ?
741 *
742 * Determine this based on the APIC version.
743 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
744 */
745 if (APIC_INTEGRATED(apic_version[phys_apicid]))
746 num_starts = 2;
747 else
748 num_starts = 0;
749
750 /*
751 * Run STARTUP IPI loop.
752 */
753 pr_debug("#startup loops: %d\n", num_starts);
754
755 for (j = 1; j <= num_starts; j++) {
756 pr_debug("Sending STARTUP #%d\n", j);
757 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
758 apic_write(APIC_ESR, 0);
759 apic_read(APIC_ESR);
760 pr_debug("After apic_write\n");
761
762 /*
763 * STARTUP IPI
764 */
765
766 /* Target chip */
767 /* Boot on the stack */
768 /* Kick the second */
769 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
770 phys_apicid);
771
772 /*
773 * Give the other CPU some time to accept the IPI.
774 */
775 if (init_udelay == 0)
776 udelay(10);
777 else
778 udelay(300);
779
780 pr_debug("Startup point 1\n");
781
782 pr_debug("Waiting for send to finish...\n");
783 send_status = safe_apic_wait_icr_idle();
784
785 /*
786 * Give the other CPU some time to accept the IPI.
787 */
788 if (init_udelay == 0)
789 udelay(10);
790 else
791 udelay(200);
792
793 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
794 apic_write(APIC_ESR, 0);
795 accept_status = (apic_read(APIC_ESR) & 0xEF);
796 if (send_status || accept_status)
797 break;
798 }
799 pr_debug("After Startup\n");
800
801 if (send_status)
802 pr_err("APIC never delivered???\n");
803 if (accept_status)
804 pr_err("APIC delivery error (%lx)\n", accept_status);
805
806 return (send_status | accept_status);
807}
808
809void smp_announce(void)
810{
811 int num_nodes = num_online_nodes();
812
813 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
814 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
815}
816
817/* reduce the number of lines printed when booting a large cpu count system */
818static void announce_cpu(int cpu, int apicid)
819{
820 static int current_node = -1;
821 int node = early_cpu_to_node(cpu);
822 static int width, node_width;
823
824 if (!width)
825 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
826
827 if (!node_width)
828 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
829
830 if (cpu == 1)
831 printk(KERN_INFO "x86: Booting SMP configuration:\n");
832
833 if (system_state == SYSTEM_BOOTING) {
834 if (node != current_node) {
835 if (current_node > (-1))
836 pr_cont("\n");
837 current_node = node;
838
839 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
840 node_width - num_digits(node), " ", node);
841 }
842
843 /* Add padding for the BSP */
844 if (cpu == 1)
845 pr_cont("%*s", width + 1, " ");
846
847 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
848
849 } else
850 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
851 node, cpu, apicid);
852}
853
854static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
855{
856 int cpu;
857
858 cpu = smp_processor_id();
859 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
860 return NMI_HANDLED;
861
862 return NMI_DONE;
863}
864
865/*
866 * Wake up AP by INIT, INIT, STARTUP sequence.
867 *
868 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
869 * boot-strap code which is not a desired behavior for waking up BSP. To
870 * void the boot-strap code, wake up CPU0 by NMI instead.
871 *
872 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
873 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
874 * We'll change this code in the future to wake up hard offlined CPU0 if
875 * real platform and request are available.
876 */
877static int
878wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
879 int *cpu0_nmi_registered)
880{
881 int id;
882 int boot_error;
883
884 preempt_disable();
885
886 /*
887 * Wake up AP by INIT, INIT, STARTUP sequence.
888 */
889 if (cpu) {
890 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
891 goto out;
892 }
893
894 /*
895 * Wake up BSP by nmi.
896 *
897 * Register a NMI handler to help wake up CPU0.
898 */
899 boot_error = register_nmi_handler(NMI_LOCAL,
900 wakeup_cpu0_nmi, 0, "wake_cpu0");
901
902 if (!boot_error) {
903 enable_start_cpu0 = 1;
904 *cpu0_nmi_registered = 1;
905 if (apic->dest_logical == APIC_DEST_LOGICAL)
906 id = cpu0_logical_apicid;
907 else
908 id = apicid;
909 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
910 }
911
912out:
913 preempt_enable();
914
915 return boot_error;
916}
917
918void common_cpu_up(unsigned int cpu, struct task_struct *idle)
919{
920 /* Just in case we booted with a single CPU. */
921 alternatives_enable_smp();
922
923 per_cpu(current_task, cpu) = idle;
924
925#ifdef CONFIG_X86_32
926 /* Stack for startup_32 can be just as for start_secondary onwards */
927 irq_ctx_init(cpu);
928 per_cpu(cpu_current_top_of_stack, cpu) =
929 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
930#else
931 clear_tsk_thread_flag(idle, TIF_FORK);
932 initial_gs = per_cpu_offset(cpu);
933#endif
934}
935
936/*
937 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
938 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
939 * Returns zero if CPU booted OK, else error code from
940 * ->wakeup_secondary_cpu.
941 */
942static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
943{
944 volatile u32 *trampoline_status =
945 (volatile u32 *) __va(real_mode_header->trampoline_status);
946 /* start_ip had better be page-aligned! */
947 unsigned long start_ip = real_mode_header->trampoline_start;
948
949 unsigned long boot_error = 0;
950 int cpu0_nmi_registered = 0;
951 unsigned long timeout;
952
953 idle->thread.sp = (unsigned long) (((struct pt_regs *)
954 (THREAD_SIZE + task_stack_page(idle))) - 1);
955
956 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
957 initial_code = (unsigned long)start_secondary;
958 stack_start = idle->thread.sp;
959
960 /*
961 * Enable the espfix hack for this CPU
962 */
963#ifdef CONFIG_X86_ESPFIX64
964 init_espfix_ap(cpu);
965#endif
966
967 /* So we see what's up */
968 announce_cpu(cpu, apicid);
969
970 /*
971 * This grunge runs the startup process for
972 * the targeted processor.
973 */
974
975 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
976
977 pr_debug("Setting warm reset code and vector.\n");
978
979 smpboot_setup_warm_reset_vector(start_ip);
980 /*
981 * Be paranoid about clearing APIC errors.
982 */
983 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
984 apic_write(APIC_ESR, 0);
985 apic_read(APIC_ESR);
986 }
987 }
988
989 /*
990 * AP might wait on cpu_callout_mask in cpu_init() with
991 * cpu_initialized_mask set if previous attempt to online
992 * it timed-out. Clear cpu_initialized_mask so that after
993 * INIT/SIPI it could start with a clean state.
994 */
995 cpumask_clear_cpu(cpu, cpu_initialized_mask);
996 smp_mb();
997
998 /*
999 * Wake up a CPU in difference cases:
1000 * - Use the method in the APIC driver if it's defined
1001 * Otherwise,
1002 * - Use an INIT boot APIC message for APs or NMI for BSP.
1003 */
1004 if (apic->wakeup_secondary_cpu)
1005 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1006 else
1007 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1008 &cpu0_nmi_registered);
1009
1010 if (!boot_error) {
1011 /*
1012 * Wait 10s total for first sign of life from AP
1013 */
1014 boot_error = -1;
1015 timeout = jiffies + 10*HZ;
1016 while (time_before(jiffies, timeout)) {
1017 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1018 /*
1019 * Tell AP to proceed with initialization
1020 */
1021 cpumask_set_cpu(cpu, cpu_callout_mask);
1022 boot_error = 0;
1023 break;
1024 }
1025 schedule();
1026 }
1027 }
1028
1029 if (!boot_error) {
1030 /*
1031 * Wait till AP completes initial initialization
1032 */
1033 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1034 /*
1035 * Allow other tasks to run while we wait for the
1036 * AP to come online. This also gives a chance
1037 * for the MTRR work(triggered by the AP coming online)
1038 * to be completed in the stop machine context.
1039 */
1040 schedule();
1041 }
1042 }
1043
1044 /* mark "stuck" area as not stuck */
1045 *trampoline_status = 0;
1046
1047 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1048 /*
1049 * Cleanup possible dangling ends...
1050 */
1051 smpboot_restore_warm_reset_vector();
1052 }
1053 /*
1054 * Clean up the nmi handler. Do this after the callin and callout sync
1055 * to avoid impact of possible long unregister time.
1056 */
1057 if (cpu0_nmi_registered)
1058 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1059
1060 return boot_error;
1061}
1062
1063int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1064{
1065 int apicid = apic->cpu_present_to_apicid(cpu);
1066 unsigned long flags;
1067 int err;
1068
1069 WARN_ON(irqs_disabled());
1070
1071 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1072
1073 if (apicid == BAD_APICID ||
1074 !physid_isset(apicid, phys_cpu_present_map) ||
1075 !apic->apic_id_valid(apicid)) {
1076 pr_err("%s: bad cpu %d\n", __func__, cpu);
1077 return -EINVAL;
1078 }
1079
1080 /*
1081 * Already booted CPU?
1082 */
1083 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1084 pr_debug("do_boot_cpu %d Already started\n", cpu);
1085 return -ENOSYS;
1086 }
1087
1088 /*
1089 * Save current MTRR state in case it was changed since early boot
1090 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1091 */
1092 mtrr_save_state();
1093
1094 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1095 err = cpu_check_up_prepare(cpu);
1096 if (err && err != -EBUSY)
1097 return err;
1098
1099 /* the FPU context is blank, nobody can own it */
1100 __cpu_disable_lazy_restore(cpu);
1101
1102 common_cpu_up(cpu, tidle);
1103
1104 /*
1105 * We have to walk the irq descriptors to setup the vector
1106 * space for the cpu which comes online. Prevent irq
1107 * alloc/free across the bringup.
1108 */
1109 irq_lock_sparse();
1110
1111 err = do_boot_cpu(apicid, cpu, tidle);
1112
1113 if (err) {
1114 irq_unlock_sparse();
1115 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1116 return -EIO;
1117 }
1118
1119 /*
1120 * Check TSC synchronization with the AP (keep irqs disabled
1121 * while doing so):
1122 */
1123 local_irq_save(flags);
1124 check_tsc_sync_source(cpu);
1125 local_irq_restore(flags);
1126
1127 while (!cpu_online(cpu)) {
1128 cpu_relax();
1129 touch_nmi_watchdog();
1130 }
1131
1132 irq_unlock_sparse();
1133
1134 return 0;
1135}
1136
1137/**
1138 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1139 */
1140void arch_disable_smp_support(void)
1141{
1142 disable_ioapic_support();
1143}
1144
1145/*
1146 * Fall back to non SMP mode after errors.
1147 *
1148 * RED-PEN audit/test this more. I bet there is more state messed up here.
1149 */
1150static __init void disable_smp(void)
1151{
1152 pr_info("SMP disabled\n");
1153
1154 disable_ioapic_support();
1155
1156 init_cpu_present(cpumask_of(0));
1157 init_cpu_possible(cpumask_of(0));
1158
1159 if (smp_found_config)
1160 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1161 else
1162 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1163 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1164 cpumask_set_cpu(0, topology_core_cpumask(0));
1165}
1166
1167enum {
1168 SMP_OK,
1169 SMP_NO_CONFIG,
1170 SMP_NO_APIC,
1171 SMP_FORCE_UP,
1172};
1173
1174/*
1175 * Various sanity checks.
1176 */
1177static int __init smp_sanity_check(unsigned max_cpus)
1178{
1179 preempt_disable();
1180
1181#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1182 if (def_to_bigsmp && nr_cpu_ids > 8) {
1183 unsigned int cpu;
1184 unsigned nr;
1185
1186 pr_warn("More than 8 CPUs detected - skipping them\n"
1187 "Use CONFIG_X86_BIGSMP\n");
1188
1189 nr = 0;
1190 for_each_present_cpu(cpu) {
1191 if (nr >= 8)
1192 set_cpu_present(cpu, false);
1193 nr++;
1194 }
1195
1196 nr = 0;
1197 for_each_possible_cpu(cpu) {
1198 if (nr >= 8)
1199 set_cpu_possible(cpu, false);
1200 nr++;
1201 }
1202
1203 nr_cpu_ids = 8;
1204 }
1205#endif
1206
1207 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1208 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1209 hard_smp_processor_id());
1210
1211 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1212 }
1213
1214 /*
1215 * If we couldn't find an SMP configuration at boot time,
1216 * get out of here now!
1217 */
1218 if (!smp_found_config && !acpi_lapic) {
1219 preempt_enable();
1220 pr_notice("SMP motherboard not detected\n");
1221 return SMP_NO_CONFIG;
1222 }
1223
1224 /*
1225 * Should not be necessary because the MP table should list the boot
1226 * CPU too, but we do it for the sake of robustness anyway.
1227 */
1228 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1229 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1230 boot_cpu_physical_apicid);
1231 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1232 }
1233 preempt_enable();
1234
1235 /*
1236 * If we couldn't find a local APIC, then get out of here now!
1237 */
1238 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1239 !cpu_has_apic) {
1240 if (!disable_apic) {
1241 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1242 boot_cpu_physical_apicid);
1243 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1244 }
1245 return SMP_NO_APIC;
1246 }
1247
1248 /*
1249 * If SMP should be disabled, then really disable it!
1250 */
1251 if (!max_cpus) {
1252 pr_info("SMP mode deactivated\n");
1253 return SMP_FORCE_UP;
1254 }
1255
1256 return SMP_OK;
1257}
1258
1259static void __init smp_cpu_index_default(void)
1260{
1261 int i;
1262 struct cpuinfo_x86 *c;
1263
1264 for_each_possible_cpu(i) {
1265 c = &cpu_data(i);
1266 /* mark all to hotplug */
1267 c->cpu_index = nr_cpu_ids;
1268 }
1269}
1270
1271/*
1272 * Prepare for SMP bootup. The MP table or ACPI has been read
1273 * earlier. Just do some sanity checking here and enable APIC mode.
1274 */
1275void __init native_smp_prepare_cpus(unsigned int max_cpus)
1276{
1277 unsigned int i;
1278
1279 smp_cpu_index_default();
1280
1281 /*
1282 * Setup boot CPU information
1283 */
1284 smp_store_boot_cpu_info(); /* Final full version of the data */
1285 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1286 mb();
1287
1288 current_thread_info()->cpu = 0; /* needed? */
1289 for_each_possible_cpu(i) {
1290 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1291 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1292 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1293 }
1294 set_cpu_sibling_map(0);
1295
1296 switch (smp_sanity_check(max_cpus)) {
1297 case SMP_NO_CONFIG:
1298 disable_smp();
1299 if (APIC_init_uniprocessor())
1300 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1301 return;
1302 case SMP_NO_APIC:
1303 disable_smp();
1304 return;
1305 case SMP_FORCE_UP:
1306 disable_smp();
1307 apic_bsp_setup(false);
1308 return;
1309 case SMP_OK:
1310 break;
1311 }
1312
1313 default_setup_apic_routing();
1314
1315 if (read_apic_id() != boot_cpu_physical_apicid) {
1316 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1317 read_apic_id(), boot_cpu_physical_apicid);
1318 /* Or can we switch back to PIC here? */
1319 }
1320
1321 cpu0_logical_apicid = apic_bsp_setup(false);
1322
1323 pr_info("CPU%d: ", 0);
1324 print_cpu_info(&cpu_data(0));
1325
1326 if (is_uv_system())
1327 uv_system_init();
1328
1329 set_mtrr_aps_delayed_init();
1330
1331 smp_quirk_init_udelay();
1332}
1333
1334void arch_enable_nonboot_cpus_begin(void)
1335{
1336 set_mtrr_aps_delayed_init();
1337}
1338
1339void arch_enable_nonboot_cpus_end(void)
1340{
1341 mtrr_aps_init();
1342}
1343
1344/*
1345 * Early setup to make printk work.
1346 */
1347void __init native_smp_prepare_boot_cpu(void)
1348{
1349 int me = smp_processor_id();
1350 switch_to_new_gdt(me);
1351 /* already set me in cpu_online_mask in boot_cpu_init() */
1352 cpumask_set_cpu(me, cpu_callout_mask);
1353 cpu_set_state_online(me);
1354}
1355
1356void __init native_smp_cpus_done(unsigned int max_cpus)
1357{
1358 pr_debug("Boot done\n");
1359
1360 nmi_selftest();
1361 impress_friends();
1362 setup_ioapic_dest();
1363 mtrr_aps_init();
1364}
1365
1366static int __initdata setup_possible_cpus = -1;
1367static int __init _setup_possible_cpus(char *str)
1368{
1369 get_option(&str, &setup_possible_cpus);
1370 return 0;
1371}
1372early_param("possible_cpus", _setup_possible_cpus);
1373
1374
1375/*
1376 * cpu_possible_mask should be static, it cannot change as cpu's
1377 * are onlined, or offlined. The reason is per-cpu data-structures
1378 * are allocated by some modules at init time, and dont expect to
1379 * do this dynamically on cpu arrival/departure.
1380 * cpu_present_mask on the other hand can change dynamically.
1381 * In case when cpu_hotplug is not compiled, then we resort to current
1382 * behaviour, which is cpu_possible == cpu_present.
1383 * - Ashok Raj
1384 *
1385 * Three ways to find out the number of additional hotplug CPUs:
1386 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1387 * - The user can overwrite it with possible_cpus=NUM
1388 * - Otherwise don't reserve additional CPUs.
1389 * We do this because additional CPUs waste a lot of memory.
1390 * -AK
1391 */
1392__init void prefill_possible_map(void)
1393{
1394 int i, possible;
1395
1396 /* no processor from mptable or madt */
1397 if (!num_processors)
1398 num_processors = 1;
1399
1400 i = setup_max_cpus ?: 1;
1401 if (setup_possible_cpus == -1) {
1402 possible = num_processors;
1403#ifdef CONFIG_HOTPLUG_CPU
1404 if (setup_max_cpus)
1405 possible += disabled_cpus;
1406#else
1407 if (possible > i)
1408 possible = i;
1409#endif
1410 } else
1411 possible = setup_possible_cpus;
1412
1413 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1414
1415 /* nr_cpu_ids could be reduced via nr_cpus= */
1416 if (possible > nr_cpu_ids) {
1417 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1418 possible, nr_cpu_ids);
1419 possible = nr_cpu_ids;
1420 }
1421
1422#ifdef CONFIG_HOTPLUG_CPU
1423 if (!setup_max_cpus)
1424#endif
1425 if (possible > i) {
1426 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1427 possible, setup_max_cpus);
1428 possible = i;
1429 }
1430
1431 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1432 possible, max_t(int, possible - num_processors, 0));
1433
1434 for (i = 0; i < possible; i++)
1435 set_cpu_possible(i, true);
1436 for (; i < NR_CPUS; i++)
1437 set_cpu_possible(i, false);
1438
1439 nr_cpu_ids = possible;
1440}
1441
1442#ifdef CONFIG_HOTPLUG_CPU
1443
1444static void remove_siblinginfo(int cpu)
1445{
1446 int sibling;
1447 struct cpuinfo_x86 *c = &cpu_data(cpu);
1448
1449 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1450 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1451 /*/
1452 * last thread sibling in this cpu core going down
1453 */
1454 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1455 cpu_data(sibling).booted_cores--;
1456 }
1457
1458 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1459 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1460 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1461 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1462 cpumask_clear(cpu_llc_shared_mask(cpu));
1463 cpumask_clear(topology_sibling_cpumask(cpu));
1464 cpumask_clear(topology_core_cpumask(cpu));
1465 c->phys_proc_id = 0;
1466 c->cpu_core_id = 0;
1467 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1468}
1469
1470static void remove_cpu_from_maps(int cpu)
1471{
1472 set_cpu_online(cpu, false);
1473 cpumask_clear_cpu(cpu, cpu_callout_mask);
1474 cpumask_clear_cpu(cpu, cpu_callin_mask);
1475 /* was set by cpu_init() */
1476 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1477 numa_remove_cpu(cpu);
1478}
1479
1480void cpu_disable_common(void)
1481{
1482 int cpu = smp_processor_id();
1483
1484 remove_siblinginfo(cpu);
1485
1486 /* It's now safe to remove this processor from the online map */
1487 lock_vector_lock();
1488 remove_cpu_from_maps(cpu);
1489 unlock_vector_lock();
1490 fixup_irqs();
1491}
1492
1493int native_cpu_disable(void)
1494{
1495 int ret;
1496
1497 ret = check_irq_vectors_for_cpu_disable();
1498 if (ret)
1499 return ret;
1500
1501 clear_local_APIC();
1502 cpu_disable_common();
1503
1504 return 0;
1505}
1506
1507int common_cpu_die(unsigned int cpu)
1508{
1509 int ret = 0;
1510
1511 /* We don't do anything here: idle task is faking death itself. */
1512
1513 /* They ack this in play_dead() by setting CPU_DEAD */
1514 if (cpu_wait_death(cpu, 5)) {
1515 if (system_state == SYSTEM_RUNNING)
1516 pr_info("CPU %u is now offline\n", cpu);
1517 } else {
1518 pr_err("CPU %u didn't die...\n", cpu);
1519 ret = -1;
1520 }
1521
1522 return ret;
1523}
1524
1525void native_cpu_die(unsigned int cpu)
1526{
1527 common_cpu_die(cpu);
1528}
1529
1530void play_dead_common(void)
1531{
1532 idle_task_exit();
1533 reset_lazy_tlbstate();
1534 amd_e400_remove_cpu(raw_smp_processor_id());
1535
1536 /* Ack it */
1537 (void)cpu_report_death();
1538
1539 /*
1540 * With physical CPU hotplug, we should halt the cpu
1541 */
1542 local_irq_disable();
1543}
1544
1545static bool wakeup_cpu0(void)
1546{
1547 if (smp_processor_id() == 0 && enable_start_cpu0)
1548 return true;
1549
1550 return false;
1551}
1552
1553/*
1554 * We need to flush the caches before going to sleep, lest we have
1555 * dirty data in our caches when we come back up.
1556 */
1557static inline void mwait_play_dead(void)
1558{
1559 unsigned int eax, ebx, ecx, edx;
1560 unsigned int highest_cstate = 0;
1561 unsigned int highest_subcstate = 0;
1562 void *mwait_ptr;
1563 int i;
1564
1565 if (!this_cpu_has(X86_FEATURE_MWAIT))
1566 return;
1567 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1568 return;
1569 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1570 return;
1571
1572 eax = CPUID_MWAIT_LEAF;
1573 ecx = 0;
1574 native_cpuid(&eax, &ebx, &ecx, &edx);
1575
1576 /*
1577 * eax will be 0 if EDX enumeration is not valid.
1578 * Initialized below to cstate, sub_cstate value when EDX is valid.
1579 */
1580 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1581 eax = 0;
1582 } else {
1583 edx >>= MWAIT_SUBSTATE_SIZE;
1584 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1585 if (edx & MWAIT_SUBSTATE_MASK) {
1586 highest_cstate = i;
1587 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1588 }
1589 }
1590 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1591 (highest_subcstate - 1);
1592 }
1593
1594 /*
1595 * This should be a memory location in a cache line which is
1596 * unlikely to be touched by other processors. The actual
1597 * content is immaterial as it is not actually modified in any way.
1598 */
1599 mwait_ptr = ¤t_thread_info()->flags;
1600
1601 wbinvd();
1602
1603 while (1) {
1604 /*
1605 * The CLFLUSH is a workaround for erratum AAI65 for
1606 * the Xeon 7400 series. It's not clear it is actually
1607 * needed, but it should be harmless in either case.
1608 * The WBINVD is insufficient due to the spurious-wakeup
1609 * case where we return around the loop.
1610 */
1611 mb();
1612 clflush(mwait_ptr);
1613 mb();
1614 __monitor(mwait_ptr, 0, 0);
1615 mb();
1616 __mwait(eax, 0);
1617 /*
1618 * If NMI wants to wake up CPU0, start CPU0.
1619 */
1620 if (wakeup_cpu0())
1621 start_cpu0();
1622 }
1623}
1624
1625static inline void hlt_play_dead(void)
1626{
1627 if (__this_cpu_read(cpu_info.x86) >= 4)
1628 wbinvd();
1629
1630 while (1) {
1631 native_halt();
1632 /*
1633 * If NMI wants to wake up CPU0, start CPU0.
1634 */
1635 if (wakeup_cpu0())
1636 start_cpu0();
1637 }
1638}
1639
1640void native_play_dead(void)
1641{
1642 play_dead_common();
1643 tboot_shutdown(TB_SHUTDOWN_WFS);
1644
1645 mwait_play_dead(); /* Only returns on failure */
1646 if (cpuidle_play_dead())
1647 hlt_play_dead();
1648}
1649
1650#else /* ... !CONFIG_HOTPLUG_CPU */
1651int native_cpu_disable(void)
1652{
1653 return -ENOSYS;
1654}
1655
1656void native_cpu_die(unsigned int cpu)
1657{
1658 /* We said "no" in __cpu_disable */
1659 BUG();
1660}
1661
1662void native_play_dead(void)
1663{
1664 BUG();
1665}
1666
1667#endif
1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/numa.h>
57#include <linux/pgtable.h>
58#include <linux/overflow.h>
59#include <linux/syscore_ops.h>
60
61#include <asm/acpi.h>
62#include <asm/desc.h>
63#include <asm/nmi.h>
64#include <asm/irq.h>
65#include <asm/realmode.h>
66#include <asm/cpu.h>
67#include <asm/numa.h>
68#include <asm/tlbflush.h>
69#include <asm/mtrr.h>
70#include <asm/mwait.h>
71#include <asm/apic.h>
72#include <asm/io_apic.h>
73#include <asm/fpu/internal.h>
74#include <asm/setup.h>
75#include <asm/uv/uv.h>
76#include <linux/mc146818rtc.h>
77#include <asm/i8259.h>
78#include <asm/misc.h>
79#include <asm/qspinlock.h>
80#include <asm/intel-family.h>
81#include <asm/cpu_device_id.h>
82#include <asm/spec-ctrl.h>
83#include <asm/hw_irq.h>
84#include <asm/stackprotector.h>
85
86#ifdef CONFIG_ACPI_CPPC_LIB
87#include <acpi/cppc_acpi.h>
88#endif
89
90/* representing HT siblings of each logical CPU */
91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
92EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
93
94/* representing HT and core siblings of each logical CPU */
95DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
96EXPORT_PER_CPU_SYMBOL(cpu_core_map);
97
98/* representing HT, core, and die siblings of each logical CPU */
99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
100EXPORT_PER_CPU_SYMBOL(cpu_die_map);
101
102DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
103
104/* Per CPU bogomips and other parameters */
105DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106EXPORT_PER_CPU_SYMBOL(cpu_info);
107
108/* Logical package management. We might want to allocate that dynamically */
109unsigned int __max_logical_packages __read_mostly;
110EXPORT_SYMBOL(__max_logical_packages);
111static unsigned int logical_packages __read_mostly;
112static unsigned int logical_die __read_mostly;
113
114/* Maximum number of SMT threads on any online core */
115int __read_mostly __max_smt_threads = 1;
116
117/* Flag to indicate if a complete sched domain rebuild is required */
118bool x86_topology_update;
119
120int arch_update_cpu_topology(void)
121{
122 int retval = x86_topology_update;
123
124 x86_topology_update = false;
125 return retval;
126}
127
128static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
129{
130 unsigned long flags;
131
132 spin_lock_irqsave(&rtc_lock, flags);
133 CMOS_WRITE(0xa, 0xf);
134 spin_unlock_irqrestore(&rtc_lock, flags);
135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
136 start_eip >> 4;
137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
138 start_eip & 0xf;
139}
140
141static inline void smpboot_restore_warm_reset_vector(void)
142{
143 unsigned long flags;
144
145 /*
146 * Paranoid: Set warm reset code and vector here back
147 * to default values.
148 */
149 spin_lock_irqsave(&rtc_lock, flags);
150 CMOS_WRITE(0, 0xf);
151 spin_unlock_irqrestore(&rtc_lock, flags);
152
153 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
154}
155
156static void init_freq_invariance(bool secondary, bool cppc_ready);
157
158/*
159 * Report back to the Boot Processor during boot time or to the caller processor
160 * during CPU online.
161 */
162static void smp_callin(void)
163{
164 int cpuid;
165
166 /*
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
171 */
172 cpuid = smp_processor_id();
173
174 /*
175 * the boot CPU has finished the init stage and is spinning
176 * on callin_map until we finish. We are free to set up this
177 * CPU, first the APIC. (this is probably redundant on most
178 * boards)
179 */
180 apic_ap_setup();
181
182 /*
183 * Save our processor parameters. Note: this information
184 * is needed for clock calibration.
185 */
186 smp_store_cpu_info(cpuid);
187
188 /*
189 * The topology information must be up to date before
190 * calibrate_delay() and notify_cpu_starting().
191 */
192 set_cpu_sibling_map(raw_smp_processor_id());
193
194 init_freq_invariance(true, false);
195
196 /*
197 * Get our bogomips.
198 * Update loops_per_jiffy in cpu_data. Previous call to
199 * smp_store_cpu_info() stored a value that is close but not as
200 * accurate as the value just calculated.
201 */
202 calibrate_delay();
203 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
204 pr_debug("Stack at about %p\n", &cpuid);
205
206 wmb();
207
208 notify_cpu_starting(cpuid);
209
210 /*
211 * Allow the master to continue.
212 */
213 cpumask_set_cpu(cpuid, cpu_callin_mask);
214}
215
216static int cpu0_logical_apicid;
217static int enable_start_cpu0;
218/*
219 * Activate a secondary processor.
220 */
221static void notrace start_secondary(void *unused)
222{
223 /*
224 * Don't put *anything* except direct CPU state initialization
225 * before cpu_init(), SMP booting is too fragile that we want to
226 * limit the things done here to the most necessary things.
227 */
228 cr4_init();
229
230#ifdef CONFIG_X86_32
231 /* switch away from the initial page table */
232 load_cr3(swapper_pg_dir);
233 __flush_tlb_all();
234#endif
235 cpu_init_secondary();
236 rcu_cpu_starting(raw_smp_processor_id());
237 x86_cpuinit.early_percpu_clock_init();
238 smp_callin();
239
240 enable_start_cpu0 = 0;
241
242 /* otherwise gcc will move up smp_processor_id before the cpu_init */
243 barrier();
244 /*
245 * Check TSC synchronization with the boot CPU:
246 */
247 check_tsc_sync_target();
248
249 speculative_store_bypass_ht_init();
250
251 /*
252 * Lock vector_lock, set CPU online and bring the vector
253 * allocator online. Online must be set with vector_lock held
254 * to prevent a concurrent irq setup/teardown from seeing a
255 * half valid vector space.
256 */
257 lock_vector_lock();
258 set_cpu_online(smp_processor_id(), true);
259 lapic_online();
260 unlock_vector_lock();
261 cpu_set_state_online(smp_processor_id());
262 x86_platform.nmi_init();
263
264 /* enable local interrupts */
265 local_irq_enable();
266
267 x86_cpuinit.setup_percpu_clockev();
268
269 wmb();
270 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
271}
272
273/**
274 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
275 * @cpu: CPU to check
276 */
277bool topology_is_primary_thread(unsigned int cpu)
278{
279 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
280}
281
282/**
283 * topology_smt_supported - Check whether SMT is supported by the CPUs
284 */
285bool topology_smt_supported(void)
286{
287 return smp_num_siblings > 1;
288}
289
290/**
291 * topology_phys_to_logical_pkg - Map a physical package id to a logical
292 *
293 * Returns logical package id or -1 if not found
294 */
295int topology_phys_to_logical_pkg(unsigned int phys_pkg)
296{
297 int cpu;
298
299 for_each_possible_cpu(cpu) {
300 struct cpuinfo_x86 *c = &cpu_data(cpu);
301
302 if (c->initialized && c->phys_proc_id == phys_pkg)
303 return c->logical_proc_id;
304 }
305 return -1;
306}
307EXPORT_SYMBOL(topology_phys_to_logical_pkg);
308/**
309 * topology_phys_to_logical_die - Map a physical die id to logical
310 *
311 * Returns logical die id or -1 if not found
312 */
313int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
314{
315 int cpu;
316 int proc_id = cpu_data(cur_cpu).phys_proc_id;
317
318 for_each_possible_cpu(cpu) {
319 struct cpuinfo_x86 *c = &cpu_data(cpu);
320
321 if (c->initialized && c->cpu_die_id == die_id &&
322 c->phys_proc_id == proc_id)
323 return c->logical_die_id;
324 }
325 return -1;
326}
327EXPORT_SYMBOL(topology_phys_to_logical_die);
328
329/**
330 * topology_update_package_map - Update the physical to logical package map
331 * @pkg: The physical package id as retrieved via CPUID
332 * @cpu: The cpu for which this is updated
333 */
334int topology_update_package_map(unsigned int pkg, unsigned int cpu)
335{
336 int new;
337
338 /* Already available somewhere? */
339 new = topology_phys_to_logical_pkg(pkg);
340 if (new >= 0)
341 goto found;
342
343 new = logical_packages++;
344 if (new != pkg) {
345 pr_info("CPU %u Converting physical %u to logical package %u\n",
346 cpu, pkg, new);
347 }
348found:
349 cpu_data(cpu).logical_proc_id = new;
350 return 0;
351}
352/**
353 * topology_update_die_map - Update the physical to logical die map
354 * @die: The die id as retrieved via CPUID
355 * @cpu: The cpu for which this is updated
356 */
357int topology_update_die_map(unsigned int die, unsigned int cpu)
358{
359 int new;
360
361 /* Already available somewhere? */
362 new = topology_phys_to_logical_die(die, cpu);
363 if (new >= 0)
364 goto found;
365
366 new = logical_die++;
367 if (new != die) {
368 pr_info("CPU %u Converting physical %u to logical die %u\n",
369 cpu, die, new);
370 }
371found:
372 cpu_data(cpu).logical_die_id = new;
373 return 0;
374}
375
376void __init smp_store_boot_cpu_info(void)
377{
378 int id = 0; /* CPU 0 */
379 struct cpuinfo_x86 *c = &cpu_data(id);
380
381 *c = boot_cpu_data;
382 c->cpu_index = id;
383 topology_update_package_map(c->phys_proc_id, id);
384 topology_update_die_map(c->cpu_die_id, id);
385 c->initialized = true;
386}
387
388/*
389 * The bootstrap kernel entry code has set these up. Save them for
390 * a given CPU
391 */
392void smp_store_cpu_info(int id)
393{
394 struct cpuinfo_x86 *c = &cpu_data(id);
395
396 /* Copy boot_cpu_data only on the first bringup */
397 if (!c->initialized)
398 *c = boot_cpu_data;
399 c->cpu_index = id;
400 /*
401 * During boot time, CPU0 has this setup already. Save the info when
402 * bringing up AP or offlined CPU0.
403 */
404 identify_secondary_cpu(c);
405 c->initialized = true;
406}
407
408static bool
409topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
410{
411 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
412
413 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
414}
415
416static bool
417topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
418{
419 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
420
421 return !WARN_ONCE(!topology_same_node(c, o),
422 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
423 "[node: %d != %d]. Ignoring dependency.\n",
424 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
425}
426
427#define link_mask(mfunc, c1, c2) \
428do { \
429 cpumask_set_cpu((c1), mfunc(c2)); \
430 cpumask_set_cpu((c2), mfunc(c1)); \
431} while (0)
432
433static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
434{
435 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
436 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
437
438 if (c->phys_proc_id == o->phys_proc_id &&
439 c->cpu_die_id == o->cpu_die_id &&
440 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
441 if (c->cpu_core_id == o->cpu_core_id)
442 return topology_sane(c, o, "smt");
443
444 if ((c->cu_id != 0xff) &&
445 (o->cu_id != 0xff) &&
446 (c->cu_id == o->cu_id))
447 return topology_sane(c, o, "smt");
448 }
449
450 } else if (c->phys_proc_id == o->phys_proc_id &&
451 c->cpu_die_id == o->cpu_die_id &&
452 c->cpu_core_id == o->cpu_core_id) {
453 return topology_sane(c, o, "smt");
454 }
455
456 return false;
457}
458
459static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
460{
461 if (c->phys_proc_id == o->phys_proc_id &&
462 c->cpu_die_id == o->cpu_die_id)
463 return true;
464 return false;
465}
466
467/*
468 * Unlike the other levels, we do not enforce keeping a
469 * multicore group inside a NUMA node. If this happens, we will
470 * discard the MC level of the topology later.
471 */
472static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
473{
474 if (c->phys_proc_id == o->phys_proc_id)
475 return true;
476 return false;
477}
478
479/*
480 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
481 *
482 * Any Intel CPU that has multiple nodes per package and does not
483 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
484 *
485 * When in SNC mode, these CPUs enumerate an LLC that is shared
486 * by multiple NUMA nodes. The LLC is shared for off-package data
487 * access but private to the NUMA node (half of the package) for
488 * on-package access. CPUID (the source of the information about
489 * the LLC) can only enumerate the cache as shared or unshared,
490 * but not this particular configuration.
491 */
492
493static const struct x86_cpu_id intel_cod_cpu[] = {
494 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
495 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
496 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
497 {}
498};
499
500static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
501{
502 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
503 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
504 bool intel_snc = id && id->driver_data;
505
506 /* Do not match if we do not have a valid APICID for cpu: */
507 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
508 return false;
509
510 /* Do not match if LLC id does not match: */
511 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
512 return false;
513
514 /*
515 * Allow the SNC topology without warning. Return of false
516 * means 'c' does not share the LLC of 'o'. This will be
517 * reflected to userspace.
518 */
519 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
520 return false;
521
522 return topology_sane(c, o, "llc");
523}
524
525
526#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
527static inline int x86_sched_itmt_flags(void)
528{
529 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
530}
531
532#ifdef CONFIG_SCHED_MC
533static int x86_core_flags(void)
534{
535 return cpu_core_flags() | x86_sched_itmt_flags();
536}
537#endif
538#ifdef CONFIG_SCHED_SMT
539static int x86_smt_flags(void)
540{
541 return cpu_smt_flags() | x86_sched_itmt_flags();
542}
543#endif
544#endif
545
546static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
547#ifdef CONFIG_SCHED_SMT
548 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
549#endif
550#ifdef CONFIG_SCHED_MC
551 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
552#endif
553 { NULL, },
554};
555
556static struct sched_domain_topology_level x86_topology[] = {
557#ifdef CONFIG_SCHED_SMT
558 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
559#endif
560#ifdef CONFIG_SCHED_MC
561 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
562#endif
563 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
564 { NULL, },
565};
566
567/*
568 * Set if a package/die has multiple NUMA nodes inside.
569 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
570 * Sub-NUMA Clustering have this.
571 */
572static bool x86_has_numa_in_package;
573
574void set_cpu_sibling_map(int cpu)
575{
576 bool has_smt = smp_num_siblings > 1;
577 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
578 struct cpuinfo_x86 *c = &cpu_data(cpu);
579 struct cpuinfo_x86 *o;
580 int i, threads;
581
582 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
583
584 if (!has_mp) {
585 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
586 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
587 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
588 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
589 c->booted_cores = 1;
590 return;
591 }
592
593 for_each_cpu(i, cpu_sibling_setup_mask) {
594 o = &cpu_data(i);
595
596 if (match_pkg(c, o) && !topology_same_node(c, o))
597 x86_has_numa_in_package = true;
598
599 if ((i == cpu) || (has_smt && match_smt(c, o)))
600 link_mask(topology_sibling_cpumask, cpu, i);
601
602 if ((i == cpu) || (has_mp && match_llc(c, o)))
603 link_mask(cpu_llc_shared_mask, cpu, i);
604
605 if ((i == cpu) || (has_mp && match_die(c, o)))
606 link_mask(topology_die_cpumask, cpu, i);
607 }
608
609 threads = cpumask_weight(topology_sibling_cpumask(cpu));
610 if (threads > __max_smt_threads)
611 __max_smt_threads = threads;
612
613 /*
614 * This needs a separate iteration over the cpus because we rely on all
615 * topology_sibling_cpumask links to be set-up.
616 */
617 for_each_cpu(i, cpu_sibling_setup_mask) {
618 o = &cpu_data(i);
619
620 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
621 link_mask(topology_core_cpumask, cpu, i);
622
623 /*
624 * Does this new cpu bringup a new core?
625 */
626 if (threads == 1) {
627 /*
628 * for each core in package, increment
629 * the booted_cores for this new cpu
630 */
631 if (cpumask_first(
632 topology_sibling_cpumask(i)) == i)
633 c->booted_cores++;
634 /*
635 * increment the core count for all
636 * the other cpus in this package
637 */
638 if (i != cpu)
639 cpu_data(i).booted_cores++;
640 } else if (i != cpu && !c->booted_cores)
641 c->booted_cores = cpu_data(i).booted_cores;
642 }
643 }
644}
645
646/* maps the cpu to the sched domain representing multi-core */
647const struct cpumask *cpu_coregroup_mask(int cpu)
648{
649 return cpu_llc_shared_mask(cpu);
650}
651
652static void impress_friends(void)
653{
654 int cpu;
655 unsigned long bogosum = 0;
656 /*
657 * Allow the user to impress friends.
658 */
659 pr_debug("Before bogomips\n");
660 for_each_possible_cpu(cpu)
661 if (cpumask_test_cpu(cpu, cpu_callout_mask))
662 bogosum += cpu_data(cpu).loops_per_jiffy;
663 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
664 num_online_cpus(),
665 bogosum/(500000/HZ),
666 (bogosum/(5000/HZ))%100);
667
668 pr_debug("Before bogocount - setting activated=1\n");
669}
670
671void __inquire_remote_apic(int apicid)
672{
673 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
674 const char * const names[] = { "ID", "VERSION", "SPIV" };
675 int timeout;
676 u32 status;
677
678 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
679
680 for (i = 0; i < ARRAY_SIZE(regs); i++) {
681 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
682
683 /*
684 * Wait for idle.
685 */
686 status = safe_apic_wait_icr_idle();
687 if (status)
688 pr_cont("a previous APIC delivery may have failed\n");
689
690 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
691
692 timeout = 0;
693 do {
694 udelay(100);
695 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
696 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
697
698 switch (status) {
699 case APIC_ICR_RR_VALID:
700 status = apic_read(APIC_RRR);
701 pr_cont("%08x\n", status);
702 break;
703 default:
704 pr_cont("failed\n");
705 }
706 }
707}
708
709/*
710 * The Multiprocessor Specification 1.4 (1997) example code suggests
711 * that there should be a 10ms delay between the BSP asserting INIT
712 * and de-asserting INIT, when starting a remote processor.
713 * But that slows boot and resume on modern processors, which include
714 * many cores and don't require that delay.
715 *
716 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
717 * Modern processor families are quirked to remove the delay entirely.
718 */
719#define UDELAY_10MS_DEFAULT 10000
720
721static unsigned int init_udelay = UINT_MAX;
722
723static int __init cpu_init_udelay(char *str)
724{
725 get_option(&str, &init_udelay);
726
727 return 0;
728}
729early_param("cpu_init_udelay", cpu_init_udelay);
730
731static void __init smp_quirk_init_udelay(void)
732{
733 /* if cmdline changed it from default, leave it alone */
734 if (init_udelay != UINT_MAX)
735 return;
736
737 /* if modern processor, use no delay */
738 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
739 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
740 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
741 init_udelay = 0;
742 return;
743 }
744 /* else, use legacy delay */
745 init_udelay = UDELAY_10MS_DEFAULT;
746}
747
748/*
749 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
750 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
751 * won't ... remember to clear down the APIC, etc later.
752 */
753int
754wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
755{
756 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
757 unsigned long send_status, accept_status = 0;
758 int maxlvt;
759
760 /* Target chip */
761 /* Boot on the stack */
762 /* Kick the second */
763 apic_icr_write(APIC_DM_NMI | dm, apicid);
764
765 pr_debug("Waiting for send to finish...\n");
766 send_status = safe_apic_wait_icr_idle();
767
768 /*
769 * Give the other CPU some time to accept the IPI.
770 */
771 udelay(200);
772 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
773 maxlvt = lapic_get_maxlvt();
774 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
775 apic_write(APIC_ESR, 0);
776 accept_status = (apic_read(APIC_ESR) & 0xEF);
777 }
778 pr_debug("NMI sent\n");
779
780 if (send_status)
781 pr_err("APIC never delivered???\n");
782 if (accept_status)
783 pr_err("APIC delivery error (%lx)\n", accept_status);
784
785 return (send_status | accept_status);
786}
787
788static int
789wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
790{
791 unsigned long send_status = 0, accept_status = 0;
792 int maxlvt, num_starts, j;
793
794 maxlvt = lapic_get_maxlvt();
795
796 /*
797 * Be paranoid about clearing APIC errors.
798 */
799 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
800 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
801 apic_write(APIC_ESR, 0);
802 apic_read(APIC_ESR);
803 }
804
805 pr_debug("Asserting INIT\n");
806
807 /*
808 * Turn INIT on target chip
809 */
810 /*
811 * Send IPI
812 */
813 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
814 phys_apicid);
815
816 pr_debug("Waiting for send to finish...\n");
817 send_status = safe_apic_wait_icr_idle();
818
819 udelay(init_udelay);
820
821 pr_debug("Deasserting INIT\n");
822
823 /* Target chip */
824 /* Send IPI */
825 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
826
827 pr_debug("Waiting for send to finish...\n");
828 send_status = safe_apic_wait_icr_idle();
829
830 mb();
831
832 /*
833 * Should we send STARTUP IPIs ?
834 *
835 * Determine this based on the APIC version.
836 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
837 */
838 if (APIC_INTEGRATED(boot_cpu_apic_version))
839 num_starts = 2;
840 else
841 num_starts = 0;
842
843 /*
844 * Run STARTUP IPI loop.
845 */
846 pr_debug("#startup loops: %d\n", num_starts);
847
848 for (j = 1; j <= num_starts; j++) {
849 pr_debug("Sending STARTUP #%d\n", j);
850 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
851 apic_write(APIC_ESR, 0);
852 apic_read(APIC_ESR);
853 pr_debug("After apic_write\n");
854
855 /*
856 * STARTUP IPI
857 */
858
859 /* Target chip */
860 /* Boot on the stack */
861 /* Kick the second */
862 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
863 phys_apicid);
864
865 /*
866 * Give the other CPU some time to accept the IPI.
867 */
868 if (init_udelay == 0)
869 udelay(10);
870 else
871 udelay(300);
872
873 pr_debug("Startup point 1\n");
874
875 pr_debug("Waiting for send to finish...\n");
876 send_status = safe_apic_wait_icr_idle();
877
878 /*
879 * Give the other CPU some time to accept the IPI.
880 */
881 if (init_udelay == 0)
882 udelay(10);
883 else
884 udelay(200);
885
886 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
887 apic_write(APIC_ESR, 0);
888 accept_status = (apic_read(APIC_ESR) & 0xEF);
889 if (send_status || accept_status)
890 break;
891 }
892 pr_debug("After Startup\n");
893
894 if (send_status)
895 pr_err("APIC never delivered???\n");
896 if (accept_status)
897 pr_err("APIC delivery error (%lx)\n", accept_status);
898
899 return (send_status | accept_status);
900}
901
902/* reduce the number of lines printed when booting a large cpu count system */
903static void announce_cpu(int cpu, int apicid)
904{
905 static int current_node = NUMA_NO_NODE;
906 int node = early_cpu_to_node(cpu);
907 static int width, node_width;
908
909 if (!width)
910 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
911
912 if (!node_width)
913 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
914
915 if (cpu == 1)
916 printk(KERN_INFO "x86: Booting SMP configuration:\n");
917
918 if (system_state < SYSTEM_RUNNING) {
919 if (node != current_node) {
920 if (current_node > (-1))
921 pr_cont("\n");
922 current_node = node;
923
924 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
925 node_width - num_digits(node), " ", node);
926 }
927
928 /* Add padding for the BSP */
929 if (cpu == 1)
930 pr_cont("%*s", width + 1, " ");
931
932 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
933
934 } else
935 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
936 node, cpu, apicid);
937}
938
939static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
940{
941 int cpu;
942
943 cpu = smp_processor_id();
944 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
945 return NMI_HANDLED;
946
947 return NMI_DONE;
948}
949
950/*
951 * Wake up AP by INIT, INIT, STARTUP sequence.
952 *
953 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
954 * boot-strap code which is not a desired behavior for waking up BSP. To
955 * void the boot-strap code, wake up CPU0 by NMI instead.
956 *
957 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
958 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
959 * We'll change this code in the future to wake up hard offlined CPU0 if
960 * real platform and request are available.
961 */
962static int
963wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
964 int *cpu0_nmi_registered)
965{
966 int id;
967 int boot_error;
968
969 preempt_disable();
970
971 /*
972 * Wake up AP by INIT, INIT, STARTUP sequence.
973 */
974 if (cpu) {
975 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
976 goto out;
977 }
978
979 /*
980 * Wake up BSP by nmi.
981 *
982 * Register a NMI handler to help wake up CPU0.
983 */
984 boot_error = register_nmi_handler(NMI_LOCAL,
985 wakeup_cpu0_nmi, 0, "wake_cpu0");
986
987 if (!boot_error) {
988 enable_start_cpu0 = 1;
989 *cpu0_nmi_registered = 1;
990 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
991 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
992 }
993
994out:
995 preempt_enable();
996
997 return boot_error;
998}
999
1000int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1001{
1002 int ret;
1003
1004 /* Just in case we booted with a single CPU. */
1005 alternatives_enable_smp();
1006
1007 per_cpu(current_task, cpu) = idle;
1008 cpu_init_stack_canary(cpu, idle);
1009
1010 /* Initialize the interrupt stack(s) */
1011 ret = irq_init_percpu_irqstack(cpu);
1012 if (ret)
1013 return ret;
1014
1015#ifdef CONFIG_X86_32
1016 /* Stack for startup_32 can be just as for start_secondary onwards */
1017 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1018#else
1019 initial_gs = per_cpu_offset(cpu);
1020#endif
1021 return 0;
1022}
1023
1024/*
1025 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1026 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1027 * Returns zero if CPU booted OK, else error code from
1028 * ->wakeup_secondary_cpu.
1029 */
1030static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1031 int *cpu0_nmi_registered)
1032{
1033 /* start_ip had better be page-aligned! */
1034 unsigned long start_ip = real_mode_header->trampoline_start;
1035
1036 unsigned long boot_error = 0;
1037 unsigned long timeout;
1038
1039 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1040 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1041 initial_code = (unsigned long)start_secondary;
1042 initial_stack = idle->thread.sp;
1043
1044 /* Enable the espfix hack for this CPU */
1045 init_espfix_ap(cpu);
1046
1047 /* So we see what's up */
1048 announce_cpu(cpu, apicid);
1049
1050 /*
1051 * This grunge runs the startup process for
1052 * the targeted processor.
1053 */
1054
1055 if (x86_platform.legacy.warm_reset) {
1056
1057 pr_debug("Setting warm reset code and vector.\n");
1058
1059 smpboot_setup_warm_reset_vector(start_ip);
1060 /*
1061 * Be paranoid about clearing APIC errors.
1062 */
1063 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1064 apic_write(APIC_ESR, 0);
1065 apic_read(APIC_ESR);
1066 }
1067 }
1068
1069 /*
1070 * AP might wait on cpu_callout_mask in cpu_init() with
1071 * cpu_initialized_mask set if previous attempt to online
1072 * it timed-out. Clear cpu_initialized_mask so that after
1073 * INIT/SIPI it could start with a clean state.
1074 */
1075 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1076 smp_mb();
1077
1078 /*
1079 * Wake up a CPU in difference cases:
1080 * - Use the method in the APIC driver if it's defined
1081 * Otherwise,
1082 * - Use an INIT boot APIC message for APs or NMI for BSP.
1083 */
1084 if (apic->wakeup_secondary_cpu)
1085 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1086 else
1087 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1088 cpu0_nmi_registered);
1089
1090 if (!boot_error) {
1091 /*
1092 * Wait 10s total for first sign of life from AP
1093 */
1094 boot_error = -1;
1095 timeout = jiffies + 10*HZ;
1096 while (time_before(jiffies, timeout)) {
1097 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1098 /*
1099 * Tell AP to proceed with initialization
1100 */
1101 cpumask_set_cpu(cpu, cpu_callout_mask);
1102 boot_error = 0;
1103 break;
1104 }
1105 schedule();
1106 }
1107 }
1108
1109 if (!boot_error) {
1110 /*
1111 * Wait till AP completes initial initialization
1112 */
1113 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1114 /*
1115 * Allow other tasks to run while we wait for the
1116 * AP to come online. This also gives a chance
1117 * for the MTRR work(triggered by the AP coming online)
1118 * to be completed in the stop machine context.
1119 */
1120 schedule();
1121 }
1122 }
1123
1124 if (x86_platform.legacy.warm_reset) {
1125 /*
1126 * Cleanup possible dangling ends...
1127 */
1128 smpboot_restore_warm_reset_vector();
1129 }
1130
1131 return boot_error;
1132}
1133
1134int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1135{
1136 int apicid = apic->cpu_present_to_apicid(cpu);
1137 int cpu0_nmi_registered = 0;
1138 unsigned long flags;
1139 int err, ret = 0;
1140
1141 lockdep_assert_irqs_enabled();
1142
1143 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1144
1145 if (apicid == BAD_APICID ||
1146 !physid_isset(apicid, phys_cpu_present_map) ||
1147 !apic->apic_id_valid(apicid)) {
1148 pr_err("%s: bad cpu %d\n", __func__, cpu);
1149 return -EINVAL;
1150 }
1151
1152 /*
1153 * Already booted CPU?
1154 */
1155 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1156 pr_debug("do_boot_cpu %d Already started\n", cpu);
1157 return -ENOSYS;
1158 }
1159
1160 /*
1161 * Save current MTRR state in case it was changed since early boot
1162 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1163 */
1164 mtrr_save_state();
1165
1166 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1167 err = cpu_check_up_prepare(cpu);
1168 if (err && err != -EBUSY)
1169 return err;
1170
1171 /* the FPU context is blank, nobody can own it */
1172 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1173
1174 err = common_cpu_up(cpu, tidle);
1175 if (err)
1176 return err;
1177
1178 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1179 if (err) {
1180 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1181 ret = -EIO;
1182 goto unreg_nmi;
1183 }
1184
1185 /*
1186 * Check TSC synchronization with the AP (keep irqs disabled
1187 * while doing so):
1188 */
1189 local_irq_save(flags);
1190 check_tsc_sync_source(cpu);
1191 local_irq_restore(flags);
1192
1193 while (!cpu_online(cpu)) {
1194 cpu_relax();
1195 touch_nmi_watchdog();
1196 }
1197
1198unreg_nmi:
1199 /*
1200 * Clean up the nmi handler. Do this after the callin and callout sync
1201 * to avoid impact of possible long unregister time.
1202 */
1203 if (cpu0_nmi_registered)
1204 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1205
1206 return ret;
1207}
1208
1209/**
1210 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1211 */
1212void arch_disable_smp_support(void)
1213{
1214 disable_ioapic_support();
1215}
1216
1217/*
1218 * Fall back to non SMP mode after errors.
1219 *
1220 * RED-PEN audit/test this more. I bet there is more state messed up here.
1221 */
1222static __init void disable_smp(void)
1223{
1224 pr_info("SMP disabled\n");
1225
1226 disable_ioapic_support();
1227
1228 init_cpu_present(cpumask_of(0));
1229 init_cpu_possible(cpumask_of(0));
1230
1231 if (smp_found_config)
1232 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1233 else
1234 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1235 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1236 cpumask_set_cpu(0, topology_core_cpumask(0));
1237 cpumask_set_cpu(0, topology_die_cpumask(0));
1238}
1239
1240/*
1241 * Various sanity checks.
1242 */
1243static void __init smp_sanity_check(void)
1244{
1245 preempt_disable();
1246
1247#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1248 if (def_to_bigsmp && nr_cpu_ids > 8) {
1249 unsigned int cpu;
1250 unsigned nr;
1251
1252 pr_warn("More than 8 CPUs detected - skipping them\n"
1253 "Use CONFIG_X86_BIGSMP\n");
1254
1255 nr = 0;
1256 for_each_present_cpu(cpu) {
1257 if (nr >= 8)
1258 set_cpu_present(cpu, false);
1259 nr++;
1260 }
1261
1262 nr = 0;
1263 for_each_possible_cpu(cpu) {
1264 if (nr >= 8)
1265 set_cpu_possible(cpu, false);
1266 nr++;
1267 }
1268
1269 nr_cpu_ids = 8;
1270 }
1271#endif
1272
1273 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1274 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1275 hard_smp_processor_id());
1276
1277 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1278 }
1279
1280 /*
1281 * Should not be necessary because the MP table should list the boot
1282 * CPU too, but we do it for the sake of robustness anyway.
1283 */
1284 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1285 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1286 boot_cpu_physical_apicid);
1287 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1288 }
1289 preempt_enable();
1290}
1291
1292static void __init smp_cpu_index_default(void)
1293{
1294 int i;
1295 struct cpuinfo_x86 *c;
1296
1297 for_each_possible_cpu(i) {
1298 c = &cpu_data(i);
1299 /* mark all to hotplug */
1300 c->cpu_index = nr_cpu_ids;
1301 }
1302}
1303
1304static void __init smp_get_logical_apicid(void)
1305{
1306 if (x2apic_mode)
1307 cpu0_logical_apicid = apic_read(APIC_LDR);
1308 else
1309 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1310}
1311
1312/*
1313 * Prepare for SMP bootup.
1314 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1315 * for common interface support.
1316 */
1317void __init native_smp_prepare_cpus(unsigned int max_cpus)
1318{
1319 unsigned int i;
1320
1321 smp_cpu_index_default();
1322
1323 /*
1324 * Setup boot CPU information
1325 */
1326 smp_store_boot_cpu_info(); /* Final full version of the data */
1327 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1328 mb();
1329
1330 for_each_possible_cpu(i) {
1331 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1332 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1333 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1334 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1335 }
1336
1337 /*
1338 * Set 'default' x86 topology, this matches default_topology() in that
1339 * it has NUMA nodes as a topology level. See also
1340 * native_smp_cpus_done().
1341 *
1342 * Must be done before set_cpus_sibling_map() is ran.
1343 */
1344 set_sched_topology(x86_topology);
1345
1346 set_cpu_sibling_map(0);
1347 init_freq_invariance(false, false);
1348 smp_sanity_check();
1349
1350 switch (apic_intr_mode) {
1351 case APIC_PIC:
1352 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1353 disable_smp();
1354 return;
1355 case APIC_SYMMETRIC_IO_NO_ROUTING:
1356 disable_smp();
1357 /* Setup local timer */
1358 x86_init.timers.setup_percpu_clockev();
1359 return;
1360 case APIC_VIRTUAL_WIRE:
1361 case APIC_SYMMETRIC_IO:
1362 break;
1363 }
1364
1365 /* Setup local timer */
1366 x86_init.timers.setup_percpu_clockev();
1367
1368 smp_get_logical_apicid();
1369
1370 pr_info("CPU0: ");
1371 print_cpu_info(&cpu_data(0));
1372
1373 uv_system_init();
1374
1375 set_mtrr_aps_delayed_init();
1376
1377 smp_quirk_init_udelay();
1378
1379 speculative_store_bypass_ht_init();
1380}
1381
1382void arch_thaw_secondary_cpus_begin(void)
1383{
1384 set_mtrr_aps_delayed_init();
1385}
1386
1387void arch_thaw_secondary_cpus_end(void)
1388{
1389 mtrr_aps_init();
1390}
1391
1392/*
1393 * Early setup to make printk work.
1394 */
1395void __init native_smp_prepare_boot_cpu(void)
1396{
1397 int me = smp_processor_id();
1398 switch_to_new_gdt(me);
1399 /* already set me in cpu_online_mask in boot_cpu_init() */
1400 cpumask_set_cpu(me, cpu_callout_mask);
1401 cpu_set_state_online(me);
1402 native_pv_lock_init();
1403}
1404
1405void __init calculate_max_logical_packages(void)
1406{
1407 int ncpus;
1408
1409 /*
1410 * Today neither Intel nor AMD support heterogeneous systems so
1411 * extrapolate the boot cpu's data to all packages.
1412 */
1413 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1414 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1415 pr_info("Max logical packages: %u\n", __max_logical_packages);
1416}
1417
1418void __init native_smp_cpus_done(unsigned int max_cpus)
1419{
1420 pr_debug("Boot done\n");
1421
1422 calculate_max_logical_packages();
1423
1424 if (x86_has_numa_in_package)
1425 set_sched_topology(x86_numa_in_package_topology);
1426
1427 nmi_selftest();
1428 impress_friends();
1429 mtrr_aps_init();
1430}
1431
1432static int __initdata setup_possible_cpus = -1;
1433static int __init _setup_possible_cpus(char *str)
1434{
1435 get_option(&str, &setup_possible_cpus);
1436 return 0;
1437}
1438early_param("possible_cpus", _setup_possible_cpus);
1439
1440
1441/*
1442 * cpu_possible_mask should be static, it cannot change as cpu's
1443 * are onlined, or offlined. The reason is per-cpu data-structures
1444 * are allocated by some modules at init time, and don't expect to
1445 * do this dynamically on cpu arrival/departure.
1446 * cpu_present_mask on the other hand can change dynamically.
1447 * In case when cpu_hotplug is not compiled, then we resort to current
1448 * behaviour, which is cpu_possible == cpu_present.
1449 * - Ashok Raj
1450 *
1451 * Three ways to find out the number of additional hotplug CPUs:
1452 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1453 * - The user can overwrite it with possible_cpus=NUM
1454 * - Otherwise don't reserve additional CPUs.
1455 * We do this because additional CPUs waste a lot of memory.
1456 * -AK
1457 */
1458__init void prefill_possible_map(void)
1459{
1460 int i, possible;
1461
1462 /* No boot processor was found in mptable or ACPI MADT */
1463 if (!num_processors) {
1464 if (boot_cpu_has(X86_FEATURE_APIC)) {
1465 int apicid = boot_cpu_physical_apicid;
1466 int cpu = hard_smp_processor_id();
1467
1468 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1469
1470 /* Make sure boot cpu is enumerated */
1471 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1472 apic->apic_id_valid(apicid))
1473 generic_processor_info(apicid, boot_cpu_apic_version);
1474 }
1475
1476 if (!num_processors)
1477 num_processors = 1;
1478 }
1479
1480 i = setup_max_cpus ?: 1;
1481 if (setup_possible_cpus == -1) {
1482 possible = num_processors;
1483#ifdef CONFIG_HOTPLUG_CPU
1484 if (setup_max_cpus)
1485 possible += disabled_cpus;
1486#else
1487 if (possible > i)
1488 possible = i;
1489#endif
1490 } else
1491 possible = setup_possible_cpus;
1492
1493 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1494
1495 /* nr_cpu_ids could be reduced via nr_cpus= */
1496 if (possible > nr_cpu_ids) {
1497 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1498 possible, nr_cpu_ids);
1499 possible = nr_cpu_ids;
1500 }
1501
1502#ifdef CONFIG_HOTPLUG_CPU
1503 if (!setup_max_cpus)
1504#endif
1505 if (possible > i) {
1506 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1507 possible, setup_max_cpus);
1508 possible = i;
1509 }
1510
1511 nr_cpu_ids = possible;
1512
1513 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1514 possible, max_t(int, possible - num_processors, 0));
1515
1516 reset_cpu_possible_mask();
1517
1518 for (i = 0; i < possible; i++)
1519 set_cpu_possible(i, true);
1520}
1521
1522#ifdef CONFIG_HOTPLUG_CPU
1523
1524/* Recompute SMT state for all CPUs on offline */
1525static void recompute_smt_state(void)
1526{
1527 int max_threads, cpu;
1528
1529 max_threads = 0;
1530 for_each_online_cpu (cpu) {
1531 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1532
1533 if (threads > max_threads)
1534 max_threads = threads;
1535 }
1536 __max_smt_threads = max_threads;
1537}
1538
1539static void remove_siblinginfo(int cpu)
1540{
1541 int sibling;
1542 struct cpuinfo_x86 *c = &cpu_data(cpu);
1543
1544 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1545 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1546 /*/
1547 * last thread sibling in this cpu core going down
1548 */
1549 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1550 cpu_data(sibling).booted_cores--;
1551 }
1552
1553 for_each_cpu(sibling, topology_die_cpumask(cpu))
1554 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1555 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1556 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1557 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1558 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1559 cpumask_clear(cpu_llc_shared_mask(cpu));
1560 cpumask_clear(topology_sibling_cpumask(cpu));
1561 cpumask_clear(topology_core_cpumask(cpu));
1562 cpumask_clear(topology_die_cpumask(cpu));
1563 c->cpu_core_id = 0;
1564 c->booted_cores = 0;
1565 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1566 recompute_smt_state();
1567}
1568
1569static void remove_cpu_from_maps(int cpu)
1570{
1571 set_cpu_online(cpu, false);
1572 cpumask_clear_cpu(cpu, cpu_callout_mask);
1573 cpumask_clear_cpu(cpu, cpu_callin_mask);
1574 /* was set by cpu_init() */
1575 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1576 numa_remove_cpu(cpu);
1577}
1578
1579void cpu_disable_common(void)
1580{
1581 int cpu = smp_processor_id();
1582
1583 remove_siblinginfo(cpu);
1584
1585 /* It's now safe to remove this processor from the online map */
1586 lock_vector_lock();
1587 remove_cpu_from_maps(cpu);
1588 unlock_vector_lock();
1589 fixup_irqs();
1590 lapic_offline();
1591}
1592
1593int native_cpu_disable(void)
1594{
1595 int ret;
1596
1597 ret = lapic_can_unplug_cpu();
1598 if (ret)
1599 return ret;
1600
1601 cpu_disable_common();
1602
1603 /*
1604 * Disable the local APIC. Otherwise IPI broadcasts will reach
1605 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1606 * messages.
1607 *
1608 * Disabling the APIC must happen after cpu_disable_common()
1609 * which invokes fixup_irqs().
1610 *
1611 * Disabling the APIC preserves already set bits in IRR, but
1612 * an interrupt arriving after disabling the local APIC does not
1613 * set the corresponding IRR bit.
1614 *
1615 * fixup_irqs() scans IRR for set bits so it can raise a not
1616 * yet handled interrupt on the new destination CPU via an IPI
1617 * but obviously it can't do so for IRR bits which are not set.
1618 * IOW, interrupts arriving after disabling the local APIC will
1619 * be lost.
1620 */
1621 apic_soft_disable();
1622
1623 return 0;
1624}
1625
1626int common_cpu_die(unsigned int cpu)
1627{
1628 int ret = 0;
1629
1630 /* We don't do anything here: idle task is faking death itself. */
1631
1632 /* They ack this in play_dead() by setting CPU_DEAD */
1633 if (cpu_wait_death(cpu, 5)) {
1634 if (system_state == SYSTEM_RUNNING)
1635 pr_info("CPU %u is now offline\n", cpu);
1636 } else {
1637 pr_err("CPU %u didn't die...\n", cpu);
1638 ret = -1;
1639 }
1640
1641 return ret;
1642}
1643
1644void native_cpu_die(unsigned int cpu)
1645{
1646 common_cpu_die(cpu);
1647}
1648
1649void play_dead_common(void)
1650{
1651 idle_task_exit();
1652
1653 /* Ack it */
1654 (void)cpu_report_death();
1655
1656 /*
1657 * With physical CPU hotplug, we should halt the cpu
1658 */
1659 local_irq_disable();
1660}
1661
1662/**
1663 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1664 *
1665 * If NMI wants to wake up CPU0, start CPU0.
1666 */
1667void cond_wakeup_cpu0(void)
1668{
1669 if (smp_processor_id() == 0 && enable_start_cpu0)
1670 start_cpu0();
1671}
1672EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
1673
1674/*
1675 * We need to flush the caches before going to sleep, lest we have
1676 * dirty data in our caches when we come back up.
1677 */
1678static inline void mwait_play_dead(void)
1679{
1680 unsigned int eax, ebx, ecx, edx;
1681 unsigned int highest_cstate = 0;
1682 unsigned int highest_subcstate = 0;
1683 void *mwait_ptr;
1684 int i;
1685
1686 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1687 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1688 return;
1689 if (!this_cpu_has(X86_FEATURE_MWAIT))
1690 return;
1691 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1692 return;
1693 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1694 return;
1695
1696 eax = CPUID_MWAIT_LEAF;
1697 ecx = 0;
1698 native_cpuid(&eax, &ebx, &ecx, &edx);
1699
1700 /*
1701 * eax will be 0 if EDX enumeration is not valid.
1702 * Initialized below to cstate, sub_cstate value when EDX is valid.
1703 */
1704 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1705 eax = 0;
1706 } else {
1707 edx >>= MWAIT_SUBSTATE_SIZE;
1708 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1709 if (edx & MWAIT_SUBSTATE_MASK) {
1710 highest_cstate = i;
1711 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1712 }
1713 }
1714 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1715 (highest_subcstate - 1);
1716 }
1717
1718 /*
1719 * This should be a memory location in a cache line which is
1720 * unlikely to be touched by other processors. The actual
1721 * content is immaterial as it is not actually modified in any way.
1722 */
1723 mwait_ptr = ¤t_thread_info()->flags;
1724
1725 wbinvd();
1726
1727 while (1) {
1728 /*
1729 * The CLFLUSH is a workaround for erratum AAI65 for
1730 * the Xeon 7400 series. It's not clear it is actually
1731 * needed, but it should be harmless in either case.
1732 * The WBINVD is insufficient due to the spurious-wakeup
1733 * case where we return around the loop.
1734 */
1735 mb();
1736 clflush(mwait_ptr);
1737 mb();
1738 __monitor(mwait_ptr, 0, 0);
1739 mb();
1740 __mwait(eax, 0);
1741
1742 cond_wakeup_cpu0();
1743 }
1744}
1745
1746void hlt_play_dead(void)
1747{
1748 if (__this_cpu_read(cpu_info.x86) >= 4)
1749 wbinvd();
1750
1751 while (1) {
1752 native_halt();
1753
1754 cond_wakeup_cpu0();
1755 }
1756}
1757
1758void native_play_dead(void)
1759{
1760 play_dead_common();
1761 tboot_shutdown(TB_SHUTDOWN_WFS);
1762
1763 mwait_play_dead(); /* Only returns on failure */
1764 if (cpuidle_play_dead())
1765 hlt_play_dead();
1766}
1767
1768#else /* ... !CONFIG_HOTPLUG_CPU */
1769int native_cpu_disable(void)
1770{
1771 return -ENOSYS;
1772}
1773
1774void native_cpu_die(unsigned int cpu)
1775{
1776 /* We said "no" in __cpu_disable */
1777 BUG();
1778}
1779
1780void native_play_dead(void)
1781{
1782 BUG();
1783}
1784
1785#endif
1786
1787#ifdef CONFIG_X86_64
1788/*
1789 * APERF/MPERF frequency ratio computation.
1790 *
1791 * The scheduler wants to do frequency invariant accounting and needs a <1
1792 * ratio to account for the 'current' frequency, corresponding to
1793 * freq_curr / freq_max.
1794 *
1795 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1796 * our P-state setting is little more than a request/hint, we need to observe
1797 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1798 * interval after discarding idle time. This is given by:
1799 *
1800 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1801 *
1802 * where freq_base is the max non-turbo P-state.
1803 *
1804 * The freq_max term has to be set to a somewhat arbitrary value, because we
1805 * can't know which turbo states will be available at a given point in time:
1806 * it all depends on the thermal headroom of the entire package. We set it to
1807 * the turbo level with 4 cores active.
1808 *
1809 * Benchmarks show that's a good compromise between the 1C turbo ratio
1810 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1811 * which would ignore the entire turbo range (a conspicuous part, making
1812 * freq_curr/freq_max always maxed out).
1813 *
1814 * An exception to the heuristic above is the Atom uarch, where we choose the
1815 * highest turbo level for freq_max since Atom's are generally oriented towards
1816 * power efficiency.
1817 *
1818 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1819 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1820 */
1821
1822DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1823
1824static DEFINE_PER_CPU(u64, arch_prev_aperf);
1825static DEFINE_PER_CPU(u64, arch_prev_mperf);
1826static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1827static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1828
1829void arch_set_max_freq_ratio(bool turbo_disabled)
1830{
1831 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1832 arch_turbo_freq_ratio;
1833}
1834EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio);
1835
1836static bool turbo_disabled(void)
1837{
1838 u64 misc_en;
1839 int err;
1840
1841 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1842 if (err)
1843 return false;
1844
1845 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1846}
1847
1848static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1849{
1850 int err;
1851
1852 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1853 if (err)
1854 return false;
1855
1856 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1857 if (err)
1858 return false;
1859
1860 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1861 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1862
1863 return true;
1864}
1865
1866#define X86_MATCH(model) \
1867 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1868 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1869
1870static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1871 X86_MATCH(XEON_PHI_KNL),
1872 X86_MATCH(XEON_PHI_KNM),
1873 {}
1874};
1875
1876static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1877 X86_MATCH(SKYLAKE_X),
1878 {}
1879};
1880
1881static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1882 X86_MATCH(ATOM_GOLDMONT),
1883 X86_MATCH(ATOM_GOLDMONT_D),
1884 X86_MATCH(ATOM_GOLDMONT_PLUS),
1885 {}
1886};
1887
1888static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1889 int num_delta_fratio)
1890{
1891 int fratio, delta_fratio, found;
1892 int err, i;
1893 u64 msr;
1894
1895 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1896 if (err)
1897 return false;
1898
1899 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1900
1901 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1902 if (err)
1903 return false;
1904
1905 fratio = (msr >> 8) & 0xFF;
1906 i = 16;
1907 found = 0;
1908 do {
1909 if (found >= num_delta_fratio) {
1910 *turbo_freq = fratio;
1911 return true;
1912 }
1913
1914 delta_fratio = (msr >> (i + 5)) & 0x7;
1915
1916 if (delta_fratio) {
1917 found += 1;
1918 fratio -= delta_fratio;
1919 }
1920
1921 i += 8;
1922 } while (i < 64);
1923
1924 return true;
1925}
1926
1927static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1928{
1929 u64 ratios, counts;
1930 u32 group_size;
1931 int err, i;
1932
1933 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1934 if (err)
1935 return false;
1936
1937 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1938
1939 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1940 if (err)
1941 return false;
1942
1943 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1944 if (err)
1945 return false;
1946
1947 for (i = 0; i < 64; i += 8) {
1948 group_size = (counts >> i) & 0xFF;
1949 if (group_size >= size) {
1950 *turbo_freq = (ratios >> i) & 0xFF;
1951 return true;
1952 }
1953 }
1954
1955 return false;
1956}
1957
1958static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1959{
1960 u64 msr;
1961 int err;
1962
1963 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1964 if (err)
1965 return false;
1966
1967 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1968 if (err)
1969 return false;
1970
1971 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1972 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1973
1974 /* The CPU may have less than 4 cores */
1975 if (!*turbo_freq)
1976 *turbo_freq = msr & 0xFF; /* 1C turbo */
1977
1978 return true;
1979}
1980
1981static bool intel_set_max_freq_ratio(void)
1982{
1983 u64 base_freq, turbo_freq;
1984 u64 turbo_ratio;
1985
1986 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1987 goto out;
1988
1989 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1990 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1991 goto out;
1992
1993 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1994 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1995 goto out;
1996
1997 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
1998 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
1999 goto out;
2000
2001 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2002 goto out;
2003
2004 return false;
2005
2006out:
2007 /*
2008 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2009 * but then fill all MSR's with zeroes.
2010 * Some CPUs have turbo boost but don't declare any turbo ratio
2011 * in MSR_TURBO_RATIO_LIMIT.
2012 */
2013 if (!base_freq || !turbo_freq) {
2014 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2015 return false;
2016 }
2017
2018 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2019 if (!turbo_ratio) {
2020 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2021 return false;
2022 }
2023
2024 arch_turbo_freq_ratio = turbo_ratio;
2025 arch_set_max_freq_ratio(turbo_disabled());
2026
2027 return true;
2028}
2029
2030#ifdef CONFIG_ACPI_CPPC_LIB
2031static bool amd_set_max_freq_ratio(void)
2032{
2033 struct cppc_perf_caps perf_caps;
2034 u64 highest_perf, nominal_perf;
2035 u64 perf_ratio;
2036 int rc;
2037
2038 rc = cppc_get_perf_caps(0, &perf_caps);
2039 if (rc) {
2040 pr_debug("Could not retrieve perf counters (%d)\n", rc);
2041 return false;
2042 }
2043
2044 highest_perf = amd_get_highest_perf();
2045 nominal_perf = perf_caps.nominal_perf;
2046
2047 if (!highest_perf || !nominal_perf) {
2048 pr_debug("Could not retrieve highest or nominal performance\n");
2049 return false;
2050 }
2051
2052 perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
2053 /* midpoint between max_boost and max_P */
2054 perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
2055 if (!perf_ratio) {
2056 pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
2057 return false;
2058 }
2059
2060 arch_turbo_freq_ratio = perf_ratio;
2061 arch_set_max_freq_ratio(false);
2062
2063 return true;
2064}
2065#else
2066static bool amd_set_max_freq_ratio(void)
2067{
2068 return false;
2069}
2070#endif
2071
2072static void init_counter_refs(void)
2073{
2074 u64 aperf, mperf;
2075
2076 rdmsrl(MSR_IA32_APERF, aperf);
2077 rdmsrl(MSR_IA32_MPERF, mperf);
2078
2079 this_cpu_write(arch_prev_aperf, aperf);
2080 this_cpu_write(arch_prev_mperf, mperf);
2081}
2082
2083#ifdef CONFIG_PM_SLEEP
2084static struct syscore_ops freq_invariance_syscore_ops = {
2085 .resume = init_counter_refs,
2086};
2087
2088static void register_freq_invariance_syscore_ops(void)
2089{
2090 /* Bail out if registered already. */
2091 if (freq_invariance_syscore_ops.node.prev)
2092 return;
2093
2094 register_syscore_ops(&freq_invariance_syscore_ops);
2095}
2096#else
2097static inline void register_freq_invariance_syscore_ops(void) {}
2098#endif
2099
2100static void init_freq_invariance(bool secondary, bool cppc_ready)
2101{
2102 bool ret = false;
2103
2104 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2105 return;
2106
2107 if (secondary) {
2108 if (static_branch_likely(&arch_scale_freq_key)) {
2109 init_counter_refs();
2110 }
2111 return;
2112 }
2113
2114 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2115 ret = intel_set_max_freq_ratio();
2116 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
2117 if (!cppc_ready) {
2118 return;
2119 }
2120 ret = amd_set_max_freq_ratio();
2121 }
2122
2123 if (ret) {
2124 init_counter_refs();
2125 static_branch_enable(&arch_scale_freq_key);
2126 register_freq_invariance_syscore_ops();
2127 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio);
2128 } else {
2129 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2130 }
2131}
2132
2133#ifdef CONFIG_ACPI_CPPC_LIB
2134static DEFINE_MUTEX(freq_invariance_lock);
2135
2136void init_freq_invariance_cppc(void)
2137{
2138 static bool secondary;
2139
2140 mutex_lock(&freq_invariance_lock);
2141
2142 init_freq_invariance(secondary, true);
2143 secondary = true;
2144
2145 mutex_unlock(&freq_invariance_lock);
2146}
2147#endif
2148
2149static void disable_freq_invariance_workfn(struct work_struct *work)
2150{
2151 static_branch_disable(&arch_scale_freq_key);
2152}
2153
2154static DECLARE_WORK(disable_freq_invariance_work,
2155 disable_freq_invariance_workfn);
2156
2157DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2158
2159void arch_scale_freq_tick(void)
2160{
2161 u64 freq_scale = SCHED_CAPACITY_SCALE;
2162 u64 aperf, mperf;
2163 u64 acnt, mcnt;
2164
2165 if (!arch_scale_freq_invariant())
2166 return;
2167
2168 rdmsrl(MSR_IA32_APERF, aperf);
2169 rdmsrl(MSR_IA32_MPERF, mperf);
2170
2171 acnt = aperf - this_cpu_read(arch_prev_aperf);
2172 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2173
2174 this_cpu_write(arch_prev_aperf, aperf);
2175 this_cpu_write(arch_prev_mperf, mperf);
2176
2177 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2178 goto error;
2179
2180 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2181 goto error;
2182
2183 freq_scale = div64_u64(acnt, mcnt);
2184 if (!freq_scale)
2185 goto error;
2186
2187 if (freq_scale > SCHED_CAPACITY_SCALE)
2188 freq_scale = SCHED_CAPACITY_SCALE;
2189
2190 this_cpu_write(arch_freq_scale, freq_scale);
2191 return;
2192
2193error:
2194 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2195 schedule_work(&disable_freq_invariance_work);
2196}
2197#else
2198static inline void init_freq_invariance(bool secondary, bool cppc_ready)
2199{
2200}
2201#endif /* CONFIG_X86_64 */