1/*
  2 * Based on arch/arm/mm/proc.S
  3 *
  4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5 * Copyright (C) 2012 ARM Ltd.
  6 * Author: Catalin Marinas <catalin.marinas@arm.com>
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 *
 12 * This program is distributed in the hope that it will be useful,
 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 *
 17 * You should have received a copy of the GNU General Public License
 18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 19 */
 20
 21#include <linux/init.h>
 22#include <linux/linkage.h>
 
 23#include <asm/assembler.h>
 24#include <asm/asm-offsets.h>
 
 25#include <asm/hwcap.h>
 26#include <asm/pgtable-hwdef.h>
 27#include <asm/pgtable.h>
 28#include <asm/cpufeature.h>
 29#include <asm/alternative.h>
 30
 31#include "proc-macros.S"
 32
 33#ifdef CONFIG_ARM64_64K_PAGES
 34#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
 35#elif defined(CONFIG_ARM64_16K_PAGES)
 36#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
 37#else /* CONFIG_ARM64_4K_PAGES */
 38#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
 39#endif
 40
 
 
 
 
 
 
 41#define TCR_SMP_FLAGS	TCR_SHARED
 42
 43/* PTWs cacheable, inner/outer WBWA */
 44#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
 45
 46#define MAIR(attr, mt)	((attr) << ((mt) * 8))
 
 
 
 
 47
 
 
 
 48/*
 49 *	cpu_do_idle()
 50 *
 51 *	Idle the processor (wait for interrupt).
 52 */
 53ENTRY(cpu_do_idle)
 54	dsb	sy				// WFI may enter a low-power mode
 55	wfi
 56	ret
 57ENDPROC(cpu_do_idle)
 
 
 
 
 
 
 
 
 58
 59#ifdef CONFIG_CPU_PM
 60/**
 61 * cpu_do_suspend - save CPU registers context
 62 *
 63 * x0: virtual address of context pointer
 
 
 64 */
 65ENTRY(cpu_do_suspend)
 66	mrs	x2, tpidr_el0
 67	mrs	x3, tpidrro_el0
 68	mrs	x4, contextidr_el1
 69	mrs	x5, mair_el1
 70	mrs	x6, cpacr_el1
 71	mrs	x7, ttbr1_el1
 72	mrs	x8, tcr_el1
 73	mrs	x9, vbar_el1
 74	mrs	x10, mdscr_el1
 75	mrs	x11, oslsr_el1
 76	mrs	x12, sctlr_el1
 
 77	stp	x2, x3, [x0]
 78	stp	x4, x5, [x0, #16]
 79	stp	x6, x7, [x0, #32]
 80	stp	x8, x9, [x0, #48]
 81	stp	x10, x11, [x0, #64]
 82	str	x12, [x0, #80]
 
 
 
 
 
 83	ret
 84ENDPROC(cpu_do_suspend)
 85
 86/**
 87 * cpu_do_resume - restore CPU register context
 88 *
 89 * x0: Physical address of context pointer
 90 * x1: ttbr0_el1 to be restored
 91 *
 92 * Returns:
 93 *	sctlr_el1 value in x0
 94 */
 95ENTRY(cpu_do_resume)
 96	/*
 97	 * Invalidate local tlb entries before turning on MMU
 98	 */
 99	tlbi	vmalle1
100	ldp	x2, x3, [x0]
101	ldp	x4, x5, [x0, #16]
102	ldp	x6, x7, [x0, #32]
103	ldp	x8, x9, [x0, #48]
104	ldp	x10, x11, [x0, #64]
105	ldr	x12, [x0, #80]
 
 
 
 
 
 
 
106	msr	tpidr_el0, x2
107	msr	tpidrro_el0, x3
108	msr	contextidr_el1, x4
109	msr	mair_el1, x5
110	msr	cpacr_el1, x6
111	msr	ttbr0_el1, x1
112	msr	ttbr1_el1, x7
113	tcr_set_idmap_t0sz x8, x7
 
 
114	msr	tcr_el1, x8
115	msr	vbar_el1, x9
 
 
 
 
 
 
 
 
116	msr	mdscr_el1, x10
 
 
 
 
117	/*
118	 * Restore oslsr_el1 by writing oslar_el1
119	 */
 
120	ubfx	x11, x11, #1, #1
121	msr	oslar_el1, x11
122	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
123	mov	x0, x12
124	dsb	nsh		// Make sure local tlb invalidation completed
 
 
 
 
 
125	isb
126	ret
127ENDPROC(cpu_do_resume)
 
128#endif
129
130/*
131 *	cpu_do_switch_mm(pgd_phys, tsk)
132 *
133 *	Set the translation table base pointer to be pgd_phys.
134 *
135 *	- pgd_phys - physical address of new TTB
136 */
137ENTRY(cpu_do_switch_mm)
138	mmid	x1, x1				// get mm->context.id
139	bfi	x0, x1, #48, #16		// set the ASID
140	msr	ttbr0_el1, x0			// set TTBR0
141	isb
142alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
143	ret
144	nop
145	nop
146	nop
147alternative_else
148	ic	iallu
149	dsb	nsh
150	isb
151	ret
152alternative_endif
153ENDPROC(cpu_do_switch_mm)
154
155	.pushsection ".idmap.text", "ax"
156/*
157 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
158 *
159 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
160 * called by anything else. It can only be executed from a TTBR0 mapping.
161 */
162ENTRY(idmap_cpu_replace_ttbr1)
163	mrs	x2, daif
164	msr	daifset, #0xf
 
165
166	adrp	x1, empty_zero_page
167	msr	ttbr1_el1, x1
168	isb
169
170	tlbi	vmalle1
171	dsb	nsh
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
172	isb
173
174	msr	ttbr1_el1, x0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
175	isb
176
177	msr	daif, x2
 
 
 
178
 
 
179	ret
180ENDPROC(idmap_cpu_replace_ttbr1)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
181	.popsection
 
182
183/*
184 *	__cpu_setup
185 *
186 *	Initialise the processor for turning the MMU on.  Return in x0 the
187 *	value of the SCTLR_EL1 register.
 
 
188 */
189ENTRY(__cpu_setup)
 
190	tlbi	vmalle1				// Invalidate local TLB
191	dsb	nsh
192
193	mov	x0, #3 << 20
194	msr	cpacr_el1, x0			// Enable FP/ASIMD
195	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
196	msr	mdscr_el1, x0			// access to the DCC from EL0
197	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
 
 
 
 
198	/*
199	 * Memory region attributes for LPAE:
200	 *
201	 *   n = AttrIndx[2:0]
202	 *			n	MAIR
203	 *   DEVICE_nGnRnE	000	00000000
204	 *   DEVICE_nGnRE	001	00000100
205	 *   DEVICE_GRE		010	00001100
206	 *   NORMAL_NC		011	01000100
207	 *   NORMAL		100	11111111
208	 *   NORMAL_WT		101	10111011
209	 */
210	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
211		     MAIR(0x04, MT_DEVICE_nGnRE) | \
212		     MAIR(0x0c, MT_DEVICE_GRE) | \
213		     MAIR(0x44, MT_NORMAL_NC) | \
214		     MAIR(0xff, MT_NORMAL) | \
215		     MAIR(0xbb, MT_NORMAL_WT)
216	msr	mair_el1, x5
 
217	/*
218	 * Prepare SCTLR
 
219	 */
220	adr	x5, crval
221	ldp	w5, w6, [x5]
222	mrs	x0, sctlr_el1
223	bic	x0, x0, x5			// clear bits
224	orr	x0, x0, x6			// set bits
 
 
 
 
 
 
 
 
225	/*
226	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
227	 * both user and kernel.
 
 
228	 */
229	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
230			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
231	tcr_set_idmap_t0sz	x10, x9
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
232
233	/*
234	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
235	 * TCR_EL1.
236	 */
237	mrs	x9, ID_AA64MMFR0_EL1
238	bfi	x10, x9, #32, #3
239#ifdef CONFIG_ARM64_HW_AFDBM
240	/*
241	 * Hardware update of the Access and Dirty bits.
 
 
242	 */
243	mrs	x9, ID_AA64MMFR1_EL1
244	and	x9, x9, #0xf
245	cbz	x9, 2f
246	cmp	x9, #2
247	b.lt	1f
248	orr	x10, x10, #TCR_HD		// hardware Dirty flag update
2491:	orr	x10, x10, #TCR_HA		// hardware Access flag update
2502:
251#endif	/* CONFIG_ARM64_HW_AFDBM */
252	msr	tcr_el1, x10
253	ret					// return to head.S
254ENDPROC(__cpu_setup)
255
256	/*
257	 * We set the desired value explicitly, including those of the
258	 * reserved bits. The values of bits EE & E0E were set early in
259	 * el2_setup, which are left untouched below.
260	 *
261	 *                 n n            T
262	 *       U E      WT T UD     US IHBS
263	 *       CE0      XWHW CZ     ME TEEA S
264	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
265	 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
266	 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
267	 */
268	.type	crval, #object
269crval:
270	.word	0xfcffffff			// clear
271	.word	0x34d5d91d			// set
 
 

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Based on arch/arm/mm/proc.S
  4 *
  5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
  6 * Copyright (C) 2012 ARM Ltd.
  7 * Author: Catalin Marinas <catalin.marinas@arm.com>
 
 
 
 
 
 
 
 
 
 
 
 
  8 */
  9
 10#include <linux/init.h>
 11#include <linux/linkage.h>
 12#include <linux/pgtable.h>
 13#include <asm/assembler.h>
 14#include <asm/asm-offsets.h>
 15#include <asm/asm_pointer_auth.h>
 16#include <asm/hwcap.h>
 17#include <asm/pgtable-hwdef.h>
 
 18#include <asm/cpufeature.h>
 19#include <asm/alternative.h>
 20#include <asm/smp.h>
 21#include <asm/sysreg.h>
 22
 23#ifdef CONFIG_ARM64_64K_PAGES
 24#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
 25#elif defined(CONFIG_ARM64_16K_PAGES)
 26#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
 27#else /* CONFIG_ARM64_4K_PAGES */
 28#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
 29#endif
 30
 31#ifdef CONFIG_RANDOMIZE_BASE
 32#define TCR_KASLR_FLAGS	TCR_NFD1
 33#else
 34#define TCR_KASLR_FLAGS	0
 35#endif
 36
 37#define TCR_SMP_FLAGS	TCR_SHARED
 38
 39/* PTWs cacheable, inner/outer WBWA */
 40#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
 41
 42#ifdef CONFIG_KASAN_SW_TAGS
 43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
 44#else
 45#define TCR_KASAN_SW_FLAGS 0
 46#endif
 47
 48#ifdef CONFIG_KASAN_HW_TAGS
 49#define TCR_MTE_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1
 50#else
 51/*
 52 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
 53 * TBI being enabled at EL1.
 
 54 */
 55#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
 56#endif
 57
 58/*
 59 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
 60 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
 61 */
 62#define MAIR_EL1_SET							\
 63	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
 64	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
 65	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
 66	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
 67	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
 68
 69#ifdef CONFIG_CPU_PM
 70/**
 71 * cpu_do_suspend - save CPU registers context
 72 *
 73 * x0: virtual address of context pointer
 74 *
 75 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
 76 */
 77SYM_FUNC_START(cpu_do_suspend)
 78	mrs	x2, tpidr_el0
 79	mrs	x3, tpidrro_el0
 80	mrs	x4, contextidr_el1
 81	mrs	x5, osdlr_el1
 82	mrs	x6, cpacr_el1
 83	mrs	x7, tcr_el1
 84	mrs	x8, vbar_el1
 85	mrs	x9, mdscr_el1
 86	mrs	x10, oslsr_el1
 87	mrs	x11, sctlr_el1
 88	get_this_cpu_offset x12
 89	mrs	x13, sp_el0
 90	stp	x2, x3, [x0]
 91	stp	x4, x5, [x0, #16]
 92	stp	x6, x7, [x0, #32]
 93	stp	x8, x9, [x0, #48]
 94	stp	x10, x11, [x0, #64]
 95	stp	x12, x13, [x0, #80]
 96	/*
 97	 * Save x18 as it may be used as a platform register, e.g. by shadow
 98	 * call stack.
 99	 */
100	str	x18, [x0, #96]
101	ret
102SYM_FUNC_END(cpu_do_suspend)
103
104/**
105 * cpu_do_resume - restore CPU register context
106 *
107 * x0: Address of context pointer
 
 
 
 
108 */
109	.pushsection ".idmap.text", "awx"
110SYM_FUNC_START(cpu_do_resume)
 
 
 
111	ldp	x2, x3, [x0]
112	ldp	x4, x5, [x0, #16]
113	ldp	x6, x8, [x0, #32]
114	ldp	x9, x10, [x0, #48]
115	ldp	x11, x12, [x0, #64]
116	ldp	x13, x14, [x0, #80]
117	/*
118	 * Restore x18, as it may be used as a platform register, and clear
119	 * the buffer to minimize the risk of exposure when used for shadow
120	 * call stack.
121	 */
122	ldr	x18, [x0, #96]
123	str	xzr, [x0, #96]
124	msr	tpidr_el0, x2
125	msr	tpidrro_el0, x3
126	msr	contextidr_el1, x4
 
127	msr	cpacr_el1, x6
128
129	/* Don't change t0sz here, mask those bits when restoring */
130	mrs	x7, tcr_el1
131	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
132
133	msr	tcr_el1, x8
134	msr	vbar_el1, x9
135
136	/*
137	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
138	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
139	 * exception. Mask them until local_daif_restore() in cpu_suspend()
140	 * resets them.
141	 */
142	disable_daif
143	msr	mdscr_el1, x10
144
145	msr	sctlr_el1, x12
146	set_this_cpu_offset x13
147	msr	sp_el0, x14
148	/*
149	 * Restore oslsr_el1 by writing oslar_el1
150	 */
151	msr	osdlr_el1, x5
152	ubfx	x11, x11, #1, #1
153	msr	oslar_el1, x11
154	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
155	reset_amuserenr_el0 x0			// Disable AMU access from EL0
156
157alternative_if ARM64_HAS_RAS_EXTN
158	msr_s	SYS_DISR_EL1, xzr
159alternative_else_nop_endif
160
161	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
162	isb
163	ret
164SYM_FUNC_END(cpu_do_resume)
165	.popsection
166#endif
167
168	.pushsection ".idmap.text", "awx"
169
170.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
171	adrp	\tmp1, reserved_pg_dir
172	phys_to_ttbr \tmp2, \tmp1
173	offset_ttbr1 \tmp2, \tmp1
174	msr	ttbr1_el1, \tmp2
 
 
 
 
175	isb
176	tlbi	vmalle1
 
 
 
 
 
 
177	dsb	nsh
178	isb
179.endm
 
 
180
 
181/*
182 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
183 *
184 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
185 * called by anything else. It can only be executed from a TTBR0 mapping.
186 */
187SYM_FUNC_START(idmap_cpu_replace_ttbr1)
188	save_and_disable_daif flags=x2
189
190	__idmap_cpu_set_reserved_ttbr1 x1, x3
191
192	offset_ttbr1 x0, x3
193	msr	ttbr1_el1, x0
194	isb
195
196	restore_daif x2
197
198	ret
199SYM_FUNC_END(idmap_cpu_replace_ttbr1)
200	.popsection
201
202#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
203	.pushsection ".idmap.text", "awx"
204
205	.macro	__idmap_kpti_get_pgtable_ent, type
206	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
207	dmb	sy				// lines are written back before
208	ldr	\type, [cur_\()\type\()p]	// loading the entry
209	tbz	\type, #0, skip_\()\type	// Skip invalid and
210	tbnz	\type, #11, skip_\()\type	// non-global entries
211	.endm
212
213	.macro __idmap_kpti_put_pgtable_ent_ng, type
214	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
215	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
216	dmb	sy				// that it is visible to all
217	dc	civac, cur_\()\type\()p		// CPUs.
218	.endm
219
220/*
221 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
222 *
223 * Called exactly once from stop_machine context by each CPU found during boot.
224 */
225__idmap_kpti_flag:
226	.long	1
227SYM_FUNC_START(idmap_kpti_install_ng_mappings)
228	cpu		.req	w0
229	num_cpus	.req	w1
230	swapper_pa	.req	x2
231	swapper_ttb	.req	x3
232	flag_ptr	.req	x4
233	cur_pgdp	.req	x5
234	end_pgdp	.req	x6
235	pgd		.req	x7
236	cur_pudp	.req	x8
237	end_pudp	.req	x9
238	pud		.req	x10
239	cur_pmdp	.req	x11
240	end_pmdp	.req	x12
241	pmd		.req	x13
242	cur_ptep	.req	x14
243	end_ptep	.req	x15
244	pte		.req	x16
245
246	mrs	swapper_ttb, ttbr1_el1
247	restore_ttbr1	swapper_ttb
248	adr	flag_ptr, __idmap_kpti_flag
249
250	cbnz	cpu, __idmap_kpti_secondary
251
252	/* We're the boot CPU. Wait for the others to catch up */
253	sevl
2541:	wfe
255	ldaxr	w17, [flag_ptr]
256	eor	w17, w17, num_cpus
257	cbnz	w17, 1b
258
259	/* We need to walk swapper, so turn off the MMU. */
260	pre_disable_mmu_workaround
261	mrs	x17, sctlr_el1
262	bic	x17, x17, #SCTLR_ELx_M
263	msr	sctlr_el1, x17
264	isb
265
266	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
267	/* PGD */
268	mov	cur_pgdp, swapper_pa
269	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
270do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
271	tbnz	pgd, #1, walk_puds
272next_pgd:
273	__idmap_kpti_put_pgtable_ent_ng	pgd
274skip_pgd:
275	add	cur_pgdp, cur_pgdp, #8
276	cmp	cur_pgdp, end_pgdp
277	b.ne	do_pgd
278
279	/* Publish the updated tables and nuke all the TLBs */
280	dsb	sy
281	tlbi	vmalle1is
282	dsb	ish
283	isb
284
285	/* We're done: fire up the MMU again */
286	mrs	x17, sctlr_el1
287	orr	x17, x17, #SCTLR_ELx_M
288	set_sctlr_el1	x17
289
290	/* Set the flag to zero to indicate that we're all done */
291	str	wzr, [flag_ptr]
292	ret
293
294	/* PUD */
295walk_puds:
296	.if CONFIG_PGTABLE_LEVELS > 3
297	pte_to_phys	cur_pudp, pgd
298	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
299do_pud:	__idmap_kpti_get_pgtable_ent	pud
300	tbnz	pud, #1, walk_pmds
301next_pud:
302	__idmap_kpti_put_pgtable_ent_ng	pud
303skip_pud:
304	add	cur_pudp, cur_pudp, 8
305	cmp	cur_pudp, end_pudp
306	b.ne	do_pud
307	b	next_pgd
308	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
309	mov	pud, pgd
310	b	walk_pmds
311next_pud:
312	b	next_pgd
313	.endif
314
315	/* PMD */
316walk_pmds:
317	.if CONFIG_PGTABLE_LEVELS > 2
318	pte_to_phys	cur_pmdp, pud
319	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
320do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
321	tbnz	pmd, #1, walk_ptes
322next_pmd:
323	__idmap_kpti_put_pgtable_ent_ng	pmd
324skip_pmd:
325	add	cur_pmdp, cur_pmdp, #8
326	cmp	cur_pmdp, end_pmdp
327	b.ne	do_pmd
328	b	next_pud
329	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
330	mov	pmd, pud
331	b	walk_ptes
332next_pmd:
333	b	next_pud
334	.endif
335
336	/* PTE */
337walk_ptes:
338	pte_to_phys	cur_ptep, pmd
339	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
340do_pte:	__idmap_kpti_get_pgtable_ent	pte
341	__idmap_kpti_put_pgtable_ent_ng	pte
342skip_pte:
343	add	cur_ptep, cur_ptep, #8
344	cmp	cur_ptep, end_ptep
345	b.ne	do_pte
346	b	next_pmd
347
348	.unreq	cpu
349	.unreq	num_cpus
350	.unreq	swapper_pa
351	.unreq	cur_pgdp
352	.unreq	end_pgdp
353	.unreq	pgd
354	.unreq	cur_pudp
355	.unreq	end_pudp
356	.unreq	pud
357	.unreq	cur_pmdp
358	.unreq	end_pmdp
359	.unreq	pmd
360	.unreq	cur_ptep
361	.unreq	end_ptep
362	.unreq	pte
363
364	/* Secondary CPUs end up here */
365__idmap_kpti_secondary:
366	/* Uninstall swapper before surgery begins */
367	__idmap_cpu_set_reserved_ttbr1 x16, x17
368
369	/* Increment the flag to let the boot CPU we're ready */
3701:	ldxr	w16, [flag_ptr]
371	add	w16, w16, #1
372	stxr	w17, w16, [flag_ptr]
373	cbnz	w17, 1b
374
375	/* Wait for the boot CPU to finish messing around with swapper */
376	sevl
3771:	wfe
378	ldxr	w16, [flag_ptr]
379	cbnz	w16, 1b
380
381	/* All done, act like nothing happened */
382	offset_ttbr1 swapper_ttb, x16
383	msr	ttbr1_el1, swapper_ttb
384	isb
385	ret
386
387	.unreq	swapper_ttb
388	.unreq	flag_ptr
389SYM_FUNC_END(idmap_kpti_install_ng_mappings)
390	.popsection
391#endif
392
393/*
394 *	__cpu_setup
395 *
396 *	Initialise the processor for turning the MMU on.
397 *
398 * Output:
399 *	Return in x0 the value of the SCTLR_EL1 register.
400 */
401	.pushsection ".idmap.text", "awx"
402SYM_FUNC_START(__cpu_setup)
403	tlbi	vmalle1				// Invalidate local TLB
404	dsb	nsh
405
406	mov	x1, #3 << 20
407	msr	cpacr_el1, x1			// Enable FP/ASIMD
408	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
409	msr	mdscr_el1, x1			// access to the DCC from EL0
410	isb					// Unmask debug exceptions now,
411	enable_dbg				// since this is per-cpu
412	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
413	reset_amuserenr_el0 x1			// Disable AMU access from EL0
414
415	/*
416	 * Default values for VMSA control registers. These will be adjusted
417	 * below depending on detected CPU features.
 
 
 
 
 
 
 
 
418	 */
419	mair	.req	x17
420	tcr	.req	x16
421	mov_q	mair, MAIR_EL1_SET
422	mov_q	tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
423			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
424			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
425
426#ifdef CONFIG_ARM64_MTE
427	/*
428	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
429	 * (ID_AA64PFR1_EL1[11:8] > 1).
430	 */
431	mrs	x10, ID_AA64PFR1_EL1
432	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
433	cmp	x10, #ID_AA64PFR1_MTE
434	b.lt	1f
435
436	/* Normal Tagged memory type at the corresponding MAIR index */
437	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
438	bfi	mair, x10, #(8 *  MT_NORMAL_TAGGED), #8
439
440	/* initialize GCR_EL1: all non-zero tags excluded by default */
441	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
442	msr_s	SYS_GCR_EL1, x10
443
444	/*
445	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
446	 * RGSR_EL1.SEED must be non-zero for IRG to produce
447	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
448	 * must initialize it.
449	 */
450	mrs	x10, CNTVCT_EL0
451	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK
452	csinc	x10, x10, xzr, ne
453	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
454	msr_s	SYS_RGSR_EL1, x10
455
456	/* clear any pending tag check faults in TFSR*_EL1 */
457	msr_s	SYS_TFSR_EL1, xzr
458	msr_s	SYS_TFSRE0_EL1, xzr
459
460	/* set the TCR_EL1 bits */
461	mov_q	x10, TCR_MTE_FLAGS
462	orr	tcr, tcr, x10
4631:
464#endif
465	tcr_clear_errata_bits tcr, x9, x5
466
467#ifdef CONFIG_ARM64_VA_BITS_52
468	ldr_l		x9, vabits_actual
469	sub		x9, xzr, x9
470	add		x9, x9, #64
471	tcr_set_t1sz	tcr, x9
472#else
473	ldr_l		x9, idmap_t0sz
474#endif
475	tcr_set_t0sz	tcr, x9
476
477	/*
478	 * Set the IPS bits in TCR_EL1.
 
479	 */
480	tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
 
481#ifdef CONFIG_ARM64_HW_AFDBM
482	/*
483	 * Enable hardware update of the Access Flags bit.
484	 * Hardware dirty bit management is enabled later,
485	 * via capabilities.
486	 */
487	mrs	x9, ID_AA64MMFR1_EL1
488	and	x9, x9, #0xf
489	cbz	x9, 1f
490	orr	tcr, tcr, #TCR_HA		// hardware Access flag update
4911:
 
 
 
492#endif	/* CONFIG_ARM64_HW_AFDBM */
493	msr	mair_el1, mair
494	msr	tcr_el1, tcr
 
 
495	/*
496	 * Prepare SCTLR
 
 
 
 
 
 
 
 
 
497	 */
498	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
499	ret					// return to head.S
500
501	.unreq	mair
502	.unreq	tcr
503SYM_FUNC_END(__cpu_setup)