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1/*
2 * AMD CS5535/CS5536 GPIO driver
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/spinlock.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/cs5535.h>
18#include <asm/msr.h>
19
20#define DRV_NAME "cs5535-gpio"
21
22/*
23 * Some GPIO pins
24 * 31-29,23 : reserved (always mask out)
25 * 28 : Power Button
26 * 26 : PME#
27 * 22-16 : LPC
28 * 14,15 : SMBus
29 * 9,8 : UART1
30 * 7 : PCI INTB
31 * 3,4 : UART2/DDC
32 * 2 : IDE_IRQ0
33 * 1 : AC_BEEP
34 * 0 : PCI INTA
35 *
36 * If a mask was not specified, allow all except
37 * reserved and Power Button
38 */
39#define GPIO_DEFAULT_MASK 0x0F7FFFFF
40
41static ulong mask = GPIO_DEFAULT_MASK;
42module_param_named(mask, mask, ulong, 0444);
43MODULE_PARM_DESC(mask, "GPIO channel mask.");
44
45/*
46 * FIXME: convert this singleton driver to use the state container
47 * design pattern, see Documentation/driver-model/design-patterns.txt
48 */
49static struct cs5535_gpio_chip {
50 struct gpio_chip chip;
51 resource_size_t base;
52
53 struct platform_device *pdev;
54 spinlock_t lock;
55} cs5535_gpio_chip;
56
57/*
58 * The CS5535/CS5536 GPIOs support a number of extra features not defined
59 * by the gpio_chip API, so these are exported. For a full list of the
60 * registers, see include/linux/cs5535.h.
61 */
62
63static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
64 unsigned int reg)
65{
66 unsigned long addr = chip->base + 0x80 + reg;
67
68 /*
69 * According to the CS5536 errata (#36), after suspend
70 * a write to the high bank GPIO register will clear all
71 * non-selected bits; the recommended workaround is a
72 * read-modify-write operation.
73 *
74 * Don't apply this errata to the edge status GPIOs, as writing
75 * to their lower bits will clear them.
76 */
77 if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
78 if (val & 0xffff)
79 val |= (inl(addr) & 0xffff); /* ignore the high bits */
80 else
81 val |= (inl(addr) ^ (val >> 16));
82 }
83 outl(val, addr);
84}
85
86static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
87 unsigned int reg)
88{
89 if (offset < 16)
90 /* low bank register */
91 outl(1 << offset, chip->base + reg);
92 else
93 /* high bank register */
94 errata_outl(chip, 1 << (offset - 16), reg);
95}
96
97void cs5535_gpio_set(unsigned offset, unsigned int reg)
98{
99 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
100 unsigned long flags;
101
102 spin_lock_irqsave(&chip->lock, flags);
103 __cs5535_gpio_set(chip, offset, reg);
104 spin_unlock_irqrestore(&chip->lock, flags);
105}
106EXPORT_SYMBOL_GPL(cs5535_gpio_set);
107
108static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
109 unsigned int reg)
110{
111 if (offset < 16)
112 /* low bank register */
113 outl(1 << (offset + 16), chip->base + reg);
114 else
115 /* high bank register */
116 errata_outl(chip, 1 << offset, reg);
117}
118
119void cs5535_gpio_clear(unsigned offset, unsigned int reg)
120{
121 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
122 unsigned long flags;
123
124 spin_lock_irqsave(&chip->lock, flags);
125 __cs5535_gpio_clear(chip, offset, reg);
126 spin_unlock_irqrestore(&chip->lock, flags);
127}
128EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
129
130int cs5535_gpio_isset(unsigned offset, unsigned int reg)
131{
132 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
133 unsigned long flags;
134 long val;
135
136 spin_lock_irqsave(&chip->lock, flags);
137 if (offset < 16)
138 /* low bank register */
139 val = inl(chip->base + reg);
140 else {
141 /* high bank register */
142 val = inl(chip->base + 0x80 + reg);
143 offset -= 16;
144 }
145 spin_unlock_irqrestore(&chip->lock, flags);
146
147 return (val & (1 << offset)) ? 1 : 0;
148}
149EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
150
151int cs5535_gpio_set_irq(unsigned group, unsigned irq)
152{
153 uint32_t lo, hi;
154
155 if (group > 7 || irq > 15)
156 return -EINVAL;
157
158 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
159
160 lo &= ~(0xF << (group * 4));
161 lo |= (irq & 0xF) << (group * 4);
162
163 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
164 return 0;
165}
166EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
167
168void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
169{
170 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
171 uint32_t shift = (offset % 8) * 4;
172 unsigned long flags;
173 uint32_t val;
174
175 if (offset >= 24)
176 offset = GPIO_MAP_W;
177 else if (offset >= 16)
178 offset = GPIO_MAP_Z;
179 else if (offset >= 8)
180 offset = GPIO_MAP_Y;
181 else
182 offset = GPIO_MAP_X;
183
184 spin_lock_irqsave(&chip->lock, flags);
185 val = inl(chip->base + offset);
186
187 /* Clear whatever was there before */
188 val &= ~(0xF << shift);
189
190 /* Set the new value */
191 val |= ((pair & 7) << shift);
192
193 /* Set the PME bit if this is a PME event */
194 if (pme)
195 val |= (1 << (shift + 3));
196
197 outl(val, chip->base + offset);
198 spin_unlock_irqrestore(&chip->lock, flags);
199}
200EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
201
202/*
203 * Generic gpio_chip API support.
204 */
205
206static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
207{
208 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
209 unsigned long flags;
210
211 spin_lock_irqsave(&chip->lock, flags);
212
213 /* check if this pin is available */
214 if ((mask & (1 << offset)) == 0) {
215 dev_info(&chip->pdev->dev,
216 "pin %u is not available (check mask)\n", offset);
217 spin_unlock_irqrestore(&chip->lock, flags);
218 return -EINVAL;
219 }
220
221 /* disable output aux 1 & 2 on this pin */
222 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
223 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
224
225 /* disable input aux 1 on this pin */
226 __cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
227
228 spin_unlock_irqrestore(&chip->lock, flags);
229
230 return 0;
231}
232
233static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
234{
235 return cs5535_gpio_isset(offset, GPIO_READ_BACK);
236}
237
238static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
239{
240 if (val)
241 cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
242 else
243 cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
244}
245
246static int chip_direction_input(struct gpio_chip *c, unsigned offset)
247{
248 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
249 unsigned long flags;
250
251 spin_lock_irqsave(&chip->lock, flags);
252 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
253 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
254 spin_unlock_irqrestore(&chip->lock, flags);
255
256 return 0;
257}
258
259static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
260{
261 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
262 unsigned long flags;
263
264 spin_lock_irqsave(&chip->lock, flags);
265
266 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
267 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
268 if (val)
269 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
270 else
271 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
272
273 spin_unlock_irqrestore(&chip->lock, flags);
274
275 return 0;
276}
277
278static const char * const cs5535_gpio_names[] = {
279 "GPIO0", "GPIO1", "GPIO2", "GPIO3",
280 "GPIO4", "GPIO5", "GPIO6", "GPIO7",
281 "GPIO8", "GPIO9", "GPIO10", "GPIO11",
282 "GPIO12", "GPIO13", "GPIO14", "GPIO15",
283 "GPIO16", "GPIO17", "GPIO18", "GPIO19",
284 "GPIO20", "GPIO21", "GPIO22", NULL,
285 "GPIO24", "GPIO25", "GPIO26", "GPIO27",
286 "GPIO28", NULL, NULL, NULL,
287};
288
289static struct cs5535_gpio_chip cs5535_gpio_chip = {
290 .chip = {
291 .owner = THIS_MODULE,
292 .label = DRV_NAME,
293
294 .base = 0,
295 .ngpio = 32,
296 .names = cs5535_gpio_names,
297 .request = chip_gpio_request,
298
299 .get = chip_gpio_get,
300 .set = chip_gpio_set,
301
302 .direction_input = chip_direction_input,
303 .direction_output = chip_direction_output,
304 },
305};
306
307static int cs5535_gpio_probe(struct platform_device *pdev)
308{
309 struct resource *res;
310 int err = -EIO;
311 ulong mask_orig = mask;
312
313 /* There are two ways to get the GPIO base address; one is by
314 * fetching it from MSR_LBAR_GPIO, the other is by reading the
315 * PCI BAR info. The latter method is easier (especially across
316 * different architectures), so we'll stick with that for now. If
317 * it turns out to be unreliable in the face of crappy BIOSes, we
318 * can always go back to using MSRs.. */
319
320 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
321 if (!res) {
322 dev_err(&pdev->dev, "can't fetch device resource info\n");
323 return err;
324 }
325
326 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
327 pdev->name)) {
328 dev_err(&pdev->dev, "can't request region\n");
329 return err;
330 }
331
332 /* set up the driver-specific struct */
333 cs5535_gpio_chip.base = res->start;
334 cs5535_gpio_chip.pdev = pdev;
335 spin_lock_init(&cs5535_gpio_chip.lock);
336
337 dev_info(&pdev->dev, "reserved resource region %pR\n", res);
338
339 /* mask out reserved pins */
340 mask &= 0x1F7FFFFF;
341
342 /* do not allow pin 28, Power Button, as there's special handling
343 * in the PMC needed. (note 12, p. 48) */
344 mask &= ~(1 << 28);
345
346 if (mask_orig != mask)
347 dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
348 mask_orig, mask);
349
350 /* finally, register with the generic GPIO API */
351 err = devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
352 &cs5535_gpio_chip);
353 if (err)
354 return err;
355
356 return 0;
357}
358
359static struct platform_driver cs5535_gpio_driver = {
360 .driver = {
361 .name = DRV_NAME,
362 },
363 .probe = cs5535_gpio_probe,
364};
365
366module_platform_driver(cs5535_gpio_driver);
367
368MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
369MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
370MODULE_LICENSE("GPL");
371MODULE_ALIAS("platform:" DRV_NAME);
1/*
2 * AMD CS5535/CS5536 GPIO driver
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/spinlock.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/cs5535.h>
18#include <asm/msr.h>
19
20#define DRV_NAME "cs5535-gpio"
21
22/*
23 * Some GPIO pins
24 * 31-29,23 : reserved (always mask out)
25 * 28 : Power Button
26 * 26 : PME#
27 * 22-16 : LPC
28 * 14,15 : SMBus
29 * 9,8 : UART1
30 * 7 : PCI INTB
31 * 3,4 : UART2/DDC
32 * 2 : IDE_IRQ0
33 * 1 : AC_BEEP
34 * 0 : PCI INTA
35 *
36 * If a mask was not specified, allow all except
37 * reserved and Power Button
38 */
39#define GPIO_DEFAULT_MASK 0x0F7FFFFF
40
41static ulong mask = GPIO_DEFAULT_MASK;
42module_param_named(mask, mask, ulong, 0444);
43MODULE_PARM_DESC(mask, "GPIO channel mask.");
44
45/*
46 * FIXME: convert this singleton driver to use the state container
47 * design pattern, see Documentation/driver-model/design-patterns.txt
48 */
49static struct cs5535_gpio_chip {
50 struct gpio_chip chip;
51 resource_size_t base;
52
53 struct platform_device *pdev;
54 spinlock_t lock;
55} cs5535_gpio_chip;
56
57/*
58 * The CS5535/CS5536 GPIOs support a number of extra features not defined
59 * by the gpio_chip API, so these are exported. For a full list of the
60 * registers, see include/linux/cs5535.h.
61 */
62
63static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
64 unsigned int reg)
65{
66 unsigned long addr = chip->base + 0x80 + reg;
67
68 /*
69 * According to the CS5536 errata (#36), after suspend
70 * a write to the high bank GPIO register will clear all
71 * non-selected bits; the recommended workaround is a
72 * read-modify-write operation.
73 *
74 * Don't apply this errata to the edge status GPIOs, as writing
75 * to their lower bits will clear them.
76 */
77 if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
78 if (val & 0xffff)
79 val |= (inl(addr) & 0xffff); /* ignore the high bits */
80 else
81 val |= (inl(addr) ^ (val >> 16));
82 }
83 outl(val, addr);
84}
85
86static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
87 unsigned int reg)
88{
89 if (offset < 16)
90 /* low bank register */
91 outl(1 << offset, chip->base + reg);
92 else
93 /* high bank register */
94 errata_outl(chip, 1 << (offset - 16), reg);
95}
96
97void cs5535_gpio_set(unsigned offset, unsigned int reg)
98{
99 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
100 unsigned long flags;
101
102 spin_lock_irqsave(&chip->lock, flags);
103 __cs5535_gpio_set(chip, offset, reg);
104 spin_unlock_irqrestore(&chip->lock, flags);
105}
106EXPORT_SYMBOL_GPL(cs5535_gpio_set);
107
108static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
109 unsigned int reg)
110{
111 if (offset < 16)
112 /* low bank register */
113 outl(1 << (offset + 16), chip->base + reg);
114 else
115 /* high bank register */
116 errata_outl(chip, 1 << offset, reg);
117}
118
119void cs5535_gpio_clear(unsigned offset, unsigned int reg)
120{
121 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
122 unsigned long flags;
123
124 spin_lock_irqsave(&chip->lock, flags);
125 __cs5535_gpio_clear(chip, offset, reg);
126 spin_unlock_irqrestore(&chip->lock, flags);
127}
128EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
129
130int cs5535_gpio_isset(unsigned offset, unsigned int reg)
131{
132 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
133 unsigned long flags;
134 long val;
135
136 spin_lock_irqsave(&chip->lock, flags);
137 if (offset < 16)
138 /* low bank register */
139 val = inl(chip->base + reg);
140 else {
141 /* high bank register */
142 val = inl(chip->base + 0x80 + reg);
143 offset -= 16;
144 }
145 spin_unlock_irqrestore(&chip->lock, flags);
146
147 return (val & (1 << offset)) ? 1 : 0;
148}
149EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
150
151int cs5535_gpio_set_irq(unsigned group, unsigned irq)
152{
153 uint32_t lo, hi;
154
155 if (group > 7 || irq > 15)
156 return -EINVAL;
157
158 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
159
160 lo &= ~(0xF << (group * 4));
161 lo |= (irq & 0xF) << (group * 4);
162
163 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
164 return 0;
165}
166EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
167
168void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
169{
170 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
171 uint32_t shift = (offset % 8) * 4;
172 unsigned long flags;
173 uint32_t val;
174
175 if (offset >= 24)
176 offset = GPIO_MAP_W;
177 else if (offset >= 16)
178 offset = GPIO_MAP_Z;
179 else if (offset >= 8)
180 offset = GPIO_MAP_Y;
181 else
182 offset = GPIO_MAP_X;
183
184 spin_lock_irqsave(&chip->lock, flags);
185 val = inl(chip->base + offset);
186
187 /* Clear whatever was there before */
188 val &= ~(0xF << shift);
189
190 /* Set the new value */
191 val |= ((pair & 7) << shift);
192
193 /* Set the PME bit if this is a PME event */
194 if (pme)
195 val |= (1 << (shift + 3));
196
197 outl(val, chip->base + offset);
198 spin_unlock_irqrestore(&chip->lock, flags);
199}
200EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
201
202/*
203 * Generic gpio_chip API support.
204 */
205
206static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
207{
208 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
209 unsigned long flags;
210
211 spin_lock_irqsave(&chip->lock, flags);
212
213 /* check if this pin is available */
214 if ((mask & (1 << offset)) == 0) {
215 dev_info(&chip->pdev->dev,
216 "pin %u is not available (check mask)\n", offset);
217 spin_unlock_irqrestore(&chip->lock, flags);
218 return -EINVAL;
219 }
220
221 /* disable output aux 1 & 2 on this pin */
222 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
223 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
224
225 /* disable input aux 1 on this pin */
226 __cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
227
228 spin_unlock_irqrestore(&chip->lock, flags);
229
230 return 0;
231}
232
233static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
234{
235 return cs5535_gpio_isset(offset, GPIO_READ_BACK);
236}
237
238static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
239{
240 if (val)
241 cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
242 else
243 cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
244}
245
246static int chip_direction_input(struct gpio_chip *c, unsigned offset)
247{
248 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
249 unsigned long flags;
250
251 spin_lock_irqsave(&chip->lock, flags);
252 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
253 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
254 spin_unlock_irqrestore(&chip->lock, flags);
255
256 return 0;
257}
258
259static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
260{
261 struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
262 unsigned long flags;
263
264 spin_lock_irqsave(&chip->lock, flags);
265
266 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
267 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
268 if (val)
269 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
270 else
271 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
272
273 spin_unlock_irqrestore(&chip->lock, flags);
274
275 return 0;
276}
277
278static const char * const cs5535_gpio_names[] = {
279 "GPIO0", "GPIO1", "GPIO2", "GPIO3",
280 "GPIO4", "GPIO5", "GPIO6", "GPIO7",
281 "GPIO8", "GPIO9", "GPIO10", "GPIO11",
282 "GPIO12", "GPIO13", "GPIO14", "GPIO15",
283 "GPIO16", "GPIO17", "GPIO18", "GPIO19",
284 "GPIO20", "GPIO21", "GPIO22", NULL,
285 "GPIO24", "GPIO25", "GPIO26", "GPIO27",
286 "GPIO28", NULL, NULL, NULL,
287};
288
289static struct cs5535_gpio_chip cs5535_gpio_chip = {
290 .chip = {
291 .owner = THIS_MODULE,
292 .label = DRV_NAME,
293
294 .base = 0,
295 .ngpio = 32,
296 .names = cs5535_gpio_names,
297 .request = chip_gpio_request,
298
299 .get = chip_gpio_get,
300 .set = chip_gpio_set,
301
302 .direction_input = chip_direction_input,
303 .direction_output = chip_direction_output,
304 },
305};
306
307static int cs5535_gpio_probe(struct platform_device *pdev)
308{
309 struct resource *res;
310 int err = -EIO;
311 ulong mask_orig = mask;
312
313 /* There are two ways to get the GPIO base address; one is by
314 * fetching it from MSR_LBAR_GPIO, the other is by reading the
315 * PCI BAR info. The latter method is easier (especially across
316 * different architectures), so we'll stick with that for now. If
317 * it turns out to be unreliable in the face of crappy BIOSes, we
318 * can always go back to using MSRs.. */
319
320 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
321 if (!res) {
322 dev_err(&pdev->dev, "can't fetch device resource info\n");
323 return err;
324 }
325
326 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
327 pdev->name)) {
328 dev_err(&pdev->dev, "can't request region\n");
329 return err;
330 }
331
332 /* set up the driver-specific struct */
333 cs5535_gpio_chip.base = res->start;
334 cs5535_gpio_chip.pdev = pdev;
335 spin_lock_init(&cs5535_gpio_chip.lock);
336
337 dev_info(&pdev->dev, "reserved resource region %pR\n", res);
338
339 /* mask out reserved pins */
340 mask &= 0x1F7FFFFF;
341
342 /* do not allow pin 28, Power Button, as there's special handling
343 * in the PMC needed. (note 12, p. 48) */
344 mask &= ~(1 << 28);
345
346 if (mask_orig != mask)
347 dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
348 mask_orig, mask);
349
350 /* finally, register with the generic GPIO API */
351 err = devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
352 &cs5535_gpio_chip);
353 if (err)
354 return err;
355
356 return 0;
357}
358
359static struct platform_driver cs5535_gpio_driver = {
360 .driver = {
361 .name = DRV_NAME,
362 },
363 .probe = cs5535_gpio_probe,
364};
365
366module_platform_driver(cs5535_gpio_driver);
367
368MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
369MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
370MODULE_LICENSE("GPL");
371MODULE_ALIAS("platform:" DRV_NAME);