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1/*
2 * Copyright (C) 2012-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23
24#define BCM_GPIO_PASSWD 0x00a5a501
25#define GPIO_PER_BANK 32
26#define GPIO_MAX_BANK_NUM 8
27
28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
38#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
43
44#define GPIO_GPPWR_OFFSET 0x00000520
45
46#define GPIO_GPCTR0_DBR_SHIFT 5
47#define GPIO_GPCTR0_DBR_MASK 0x000001e0
48
49#define GPIO_GPCTR0_ITR_SHIFT 3
50#define GPIO_GPCTR0_ITR_MASK 0x00000018
51#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
52#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
53#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
54
55#define GPIO_GPCTR0_IOTR_MASK 0x00000001
56#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
57#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
58
59#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
60
61#define LOCK_CODE 0xffffffff
62#define UNLOCK_CODE 0x00000000
63
64struct bcm_kona_gpio {
65 void __iomem *reg_base;
66 int num_bank;
67 spinlock_t lock;
68 struct gpio_chip gpio_chip;
69 struct irq_domain *irq_domain;
70 struct bcm_kona_gpio_bank *banks;
71 struct platform_device *pdev;
72};
73
74struct bcm_kona_gpio_bank {
75 int id;
76 int irq;
77 /* Used in the interrupt handler */
78 struct bcm_kona_gpio *kona_gpio;
79};
80
81static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
82 int bank_id, u32 lockcode)
83{
84 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
85 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
86}
87
88static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
89 unsigned gpio)
90{
91 u32 val;
92 unsigned long flags;
93 int bank_id = GPIO_BANK(gpio);
94
95 spin_lock_irqsave(&kona_gpio->lock, flags);
96
97 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
98 val |= BIT(gpio);
99 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
100
101 spin_unlock_irqrestore(&kona_gpio->lock, flags);
102}
103
104static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
105 unsigned gpio)
106{
107 u32 val;
108 unsigned long flags;
109 int bank_id = GPIO_BANK(gpio);
110
111 spin_lock_irqsave(&kona_gpio->lock, flags);
112
113 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
114 val &= ~BIT(gpio);
115 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
116
117 spin_unlock_irqrestore(&kona_gpio->lock, flags);
118}
119
120static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
121{
122 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
123 void __iomem *reg_base = kona_gpio->reg_base;
124 u32 val;
125
126 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
127 return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
128}
129
130static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
131{
132 struct bcm_kona_gpio *kona_gpio;
133 void __iomem *reg_base;
134 int bank_id = GPIO_BANK(gpio);
135 int bit = GPIO_BIT(gpio);
136 u32 val, reg_offset;
137 unsigned long flags;
138
139 kona_gpio = gpiochip_get_data(chip);
140 reg_base = kona_gpio->reg_base;
141 spin_lock_irqsave(&kona_gpio->lock, flags);
142
143 /* this function only applies to output pin */
144 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
145 goto out;
146
147 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
148
149 val = readl(reg_base + reg_offset);
150 val |= BIT(bit);
151 writel(val, reg_base + reg_offset);
152
153out:
154 spin_unlock_irqrestore(&kona_gpio->lock, flags);
155}
156
157static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
158{
159 struct bcm_kona_gpio *kona_gpio;
160 void __iomem *reg_base;
161 int bank_id = GPIO_BANK(gpio);
162 int bit = GPIO_BIT(gpio);
163 u32 val, reg_offset;
164 unsigned long flags;
165
166 kona_gpio = gpiochip_get_data(chip);
167 reg_base = kona_gpio->reg_base;
168 spin_lock_irqsave(&kona_gpio->lock, flags);
169
170 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
171 reg_offset = GPIO_IN_STATUS(bank_id);
172 else
173 reg_offset = GPIO_OUT_STATUS(bank_id);
174
175 /* read the GPIO bank status */
176 val = readl(reg_base + reg_offset);
177
178 spin_unlock_irqrestore(&kona_gpio->lock, flags);
179
180 /* return the specified bit status */
181 return !!(val & BIT(bit));
182}
183
184static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
185{
186 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
187
188 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
189 return 0;
190}
191
192static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
193{
194 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
195
196 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
197}
198
199static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
200{
201 struct bcm_kona_gpio *kona_gpio;
202 void __iomem *reg_base;
203 u32 val;
204 unsigned long flags;
205
206 kona_gpio = gpiochip_get_data(chip);
207 reg_base = kona_gpio->reg_base;
208 spin_lock_irqsave(&kona_gpio->lock, flags);
209
210 val = readl(reg_base + GPIO_CONTROL(gpio));
211 val &= ~GPIO_GPCTR0_IOTR_MASK;
212 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
213 writel(val, reg_base + GPIO_CONTROL(gpio));
214
215 spin_unlock_irqrestore(&kona_gpio->lock, flags);
216
217 return 0;
218}
219
220static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
221 unsigned gpio, int value)
222{
223 struct bcm_kona_gpio *kona_gpio;
224 void __iomem *reg_base;
225 int bank_id = GPIO_BANK(gpio);
226 int bit = GPIO_BIT(gpio);
227 u32 val, reg_offset;
228 unsigned long flags;
229
230 kona_gpio = gpiochip_get_data(chip);
231 reg_base = kona_gpio->reg_base;
232 spin_lock_irqsave(&kona_gpio->lock, flags);
233
234 val = readl(reg_base + GPIO_CONTROL(gpio));
235 val &= ~GPIO_GPCTR0_IOTR_MASK;
236 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
237 writel(val, reg_base + GPIO_CONTROL(gpio));
238 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
239
240 val = readl(reg_base + reg_offset);
241 val |= BIT(bit);
242 writel(val, reg_base + reg_offset);
243
244 spin_unlock_irqrestore(&kona_gpio->lock, flags);
245
246 return 0;
247}
248
249static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
250{
251 struct bcm_kona_gpio *kona_gpio;
252
253 kona_gpio = gpiochip_get_data(chip);
254 if (gpio >= kona_gpio->gpio_chip.ngpio)
255 return -ENXIO;
256 return irq_create_mapping(kona_gpio->irq_domain, gpio);
257}
258
259static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
260 unsigned debounce)
261{
262 struct bcm_kona_gpio *kona_gpio;
263 void __iomem *reg_base;
264 u32 val, res;
265 unsigned long flags;
266
267 kona_gpio = gpiochip_get_data(chip);
268 reg_base = kona_gpio->reg_base;
269 /* debounce must be 1-128ms (or 0) */
270 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
271 dev_err(chip->parent, "Debounce value %u not in range\n",
272 debounce);
273 return -EINVAL;
274 }
275
276 /* calculate debounce bit value */
277 if (debounce != 0) {
278 /* Convert to ms */
279 debounce /= 1000;
280 /* find the MSB */
281 res = fls(debounce) - 1;
282 /* Check if MSB-1 is set (round up or down) */
283 if (res > 0 && (debounce & BIT(res - 1)))
284 res++;
285 }
286
287 /* spin lock for read-modify-write of the GPIO register */
288 spin_lock_irqsave(&kona_gpio->lock, flags);
289
290 val = readl(reg_base + GPIO_CONTROL(gpio));
291 val &= ~GPIO_GPCTR0_DBR_MASK;
292
293 if (debounce == 0) {
294 /* disable debounce */
295 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
296 } else {
297 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
298 (res << GPIO_GPCTR0_DBR_SHIFT);
299 }
300
301 writel(val, reg_base + GPIO_CONTROL(gpio));
302
303 spin_unlock_irqrestore(&kona_gpio->lock, flags);
304
305 return 0;
306}
307
308static struct gpio_chip template_chip = {
309 .label = "bcm-kona-gpio",
310 .owner = THIS_MODULE,
311 .request = bcm_kona_gpio_request,
312 .free = bcm_kona_gpio_free,
313 .get_direction = bcm_kona_gpio_get_dir,
314 .direction_input = bcm_kona_gpio_direction_input,
315 .get = bcm_kona_gpio_get,
316 .direction_output = bcm_kona_gpio_direction_output,
317 .set = bcm_kona_gpio_set,
318 .set_debounce = bcm_kona_gpio_set_debounce,
319 .to_irq = bcm_kona_gpio_to_irq,
320 .base = 0,
321};
322
323static void bcm_kona_gpio_irq_ack(struct irq_data *d)
324{
325 struct bcm_kona_gpio *kona_gpio;
326 void __iomem *reg_base;
327 unsigned gpio = d->hwirq;
328 int bank_id = GPIO_BANK(gpio);
329 int bit = GPIO_BIT(gpio);
330 u32 val;
331 unsigned long flags;
332
333 kona_gpio = irq_data_get_irq_chip_data(d);
334 reg_base = kona_gpio->reg_base;
335 spin_lock_irqsave(&kona_gpio->lock, flags);
336
337 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
338 val |= BIT(bit);
339 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
340
341 spin_unlock_irqrestore(&kona_gpio->lock, flags);
342}
343
344static void bcm_kona_gpio_irq_mask(struct irq_data *d)
345{
346 struct bcm_kona_gpio *kona_gpio;
347 void __iomem *reg_base;
348 unsigned gpio = d->hwirq;
349 int bank_id = GPIO_BANK(gpio);
350 int bit = GPIO_BIT(gpio);
351 u32 val;
352 unsigned long flags;
353
354 kona_gpio = irq_data_get_irq_chip_data(d);
355 reg_base = kona_gpio->reg_base;
356 spin_lock_irqsave(&kona_gpio->lock, flags);
357
358 val = readl(reg_base + GPIO_INT_MASK(bank_id));
359 val |= BIT(bit);
360 writel(val, reg_base + GPIO_INT_MASK(bank_id));
361
362 spin_unlock_irqrestore(&kona_gpio->lock, flags);
363}
364
365static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
366{
367 struct bcm_kona_gpio *kona_gpio;
368 void __iomem *reg_base;
369 unsigned gpio = d->hwirq;
370 int bank_id = GPIO_BANK(gpio);
371 int bit = GPIO_BIT(gpio);
372 u32 val;
373 unsigned long flags;
374
375 kona_gpio = irq_data_get_irq_chip_data(d);
376 reg_base = kona_gpio->reg_base;
377 spin_lock_irqsave(&kona_gpio->lock, flags);
378
379 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
380 val |= BIT(bit);
381 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
382
383 spin_unlock_irqrestore(&kona_gpio->lock, flags);
384}
385
386static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
387{
388 struct bcm_kona_gpio *kona_gpio;
389 void __iomem *reg_base;
390 unsigned gpio = d->hwirq;
391 u32 lvl_type;
392 u32 val;
393 unsigned long flags;
394
395 kona_gpio = irq_data_get_irq_chip_data(d);
396 reg_base = kona_gpio->reg_base;
397 switch (type & IRQ_TYPE_SENSE_MASK) {
398 case IRQ_TYPE_EDGE_RISING:
399 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
400 break;
401
402 case IRQ_TYPE_EDGE_FALLING:
403 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
404 break;
405
406 case IRQ_TYPE_EDGE_BOTH:
407 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
408 break;
409
410 case IRQ_TYPE_LEVEL_HIGH:
411 case IRQ_TYPE_LEVEL_LOW:
412 /* BCM GPIO doesn't support level triggering */
413 default:
414 dev_err(kona_gpio->gpio_chip.parent,
415 "Invalid BCM GPIO irq type 0x%x\n", type);
416 return -EINVAL;
417 }
418
419 spin_lock_irqsave(&kona_gpio->lock, flags);
420
421 val = readl(reg_base + GPIO_CONTROL(gpio));
422 val &= ~GPIO_GPCTR0_ITR_MASK;
423 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
424 writel(val, reg_base + GPIO_CONTROL(gpio));
425
426 spin_unlock_irqrestore(&kona_gpio->lock, flags);
427
428 return 0;
429}
430
431static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
432{
433 void __iomem *reg_base;
434 int bit, bank_id;
435 unsigned long sta;
436 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
437 struct irq_chip *chip = irq_desc_get_chip(desc);
438
439 chained_irq_enter(chip, desc);
440
441 /*
442 * For bank interrupts, we can't use chip_data to store the kona_gpio
443 * pointer, since GIC needs it for its own purposes. Therefore, we get
444 * our pointer from the bank structure.
445 */
446 reg_base = bank->kona_gpio->reg_base;
447 bank_id = bank->id;
448
449 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
450 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
451 for_each_set_bit(bit, &sta, 32) {
452 int hwirq = GPIO_PER_BANK * bank_id + bit;
453 int child_irq =
454 irq_find_mapping(bank->kona_gpio->irq_domain,
455 hwirq);
456 /*
457 * Clear interrupt before handler is called so we don't
458 * miss any interrupt occurred during executing them.
459 */
460 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
461 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
462 /* Invoke interrupt handler */
463 generic_handle_irq(child_irq);
464 }
465 }
466
467 chained_irq_exit(chip, desc);
468}
469
470static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
471{
472 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
473
474 if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
475 dev_err(kona_gpio->gpio_chip.parent,
476 "unable to lock HW IRQ %lu for IRQ\n",
477 d->hwirq);
478 return -EINVAL;
479 }
480 return 0;
481}
482
483static void bcm_kona_gpio_irq_relres(struct irq_data *d)
484{
485 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
486
487 gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
488}
489
490static struct irq_chip bcm_gpio_irq_chip = {
491 .name = "bcm-kona-gpio",
492 .irq_ack = bcm_kona_gpio_irq_ack,
493 .irq_mask = bcm_kona_gpio_irq_mask,
494 .irq_unmask = bcm_kona_gpio_irq_unmask,
495 .irq_set_type = bcm_kona_gpio_irq_set_type,
496 .irq_request_resources = bcm_kona_gpio_irq_reqres,
497 .irq_release_resources = bcm_kona_gpio_irq_relres,
498};
499
500static struct of_device_id const bcm_kona_gpio_of_match[] = {
501 { .compatible = "brcm,kona-gpio" },
502 {}
503};
504
505MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
506
507/*
508 * This lock class tells lockdep that GPIO irqs are in a different
509 * category than their parents, so it won't report false recursion.
510 */
511static struct lock_class_key gpio_lock_class;
512
513static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
514 irq_hw_number_t hwirq)
515{
516 int ret;
517
518 ret = irq_set_chip_data(irq, d->host_data);
519 if (ret < 0)
520 return ret;
521 irq_set_lockdep_class(irq, &gpio_lock_class);
522 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
523 irq_set_noprobe(irq);
524
525 return 0;
526}
527
528static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
529{
530 irq_set_chip_and_handler(irq, NULL, NULL);
531 irq_set_chip_data(irq, NULL);
532}
533
534static const struct irq_domain_ops bcm_kona_irq_ops = {
535 .map = bcm_kona_gpio_irq_map,
536 .unmap = bcm_kona_gpio_irq_unmap,
537 .xlate = irq_domain_xlate_twocell,
538};
539
540static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
541{
542 void __iomem *reg_base;
543 int i;
544
545 reg_base = kona_gpio->reg_base;
546 /* disable interrupts and clear status */
547 for (i = 0; i < kona_gpio->num_bank; i++) {
548 /* Unlock the entire bank first */
549 bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
550 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
551 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
552 /* Now re-lock the bank */
553 bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
554 }
555}
556
557static int bcm_kona_gpio_probe(struct platform_device *pdev)
558{
559 struct device *dev = &pdev->dev;
560 const struct of_device_id *match;
561 struct resource *res;
562 struct bcm_kona_gpio_bank *bank;
563 struct bcm_kona_gpio *kona_gpio;
564 struct gpio_chip *chip;
565 int ret;
566 int i;
567
568 match = of_match_device(bcm_kona_gpio_of_match, dev);
569 if (!match) {
570 dev_err(dev, "Failed to find gpio controller\n");
571 return -ENODEV;
572 }
573
574 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
575 if (!kona_gpio)
576 return -ENOMEM;
577
578 kona_gpio->gpio_chip = template_chip;
579 chip = &kona_gpio->gpio_chip;
580 kona_gpio->num_bank = of_irq_count(dev->of_node);
581 if (kona_gpio->num_bank == 0) {
582 dev_err(dev, "Couldn't determine # GPIO banks\n");
583 return -ENOENT;
584 }
585 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
586 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
587 GPIO_MAX_BANK_NUM);
588 return -ENXIO;
589 }
590 kona_gpio->banks = devm_kzalloc(dev,
591 kona_gpio->num_bank *
592 sizeof(*kona_gpio->banks), GFP_KERNEL);
593 if (!kona_gpio->banks)
594 return -ENOMEM;
595
596 kona_gpio->pdev = pdev;
597 platform_set_drvdata(pdev, kona_gpio);
598 chip->of_node = dev->of_node;
599 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
600
601 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
602 chip->ngpio,
603 &bcm_kona_irq_ops,
604 kona_gpio);
605 if (!kona_gpio->irq_domain) {
606 dev_err(dev, "Couldn't allocate IRQ domain\n");
607 return -ENXIO;
608 }
609
610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
612 if (IS_ERR(kona_gpio->reg_base)) {
613 ret = -ENXIO;
614 goto err_irq_domain;
615 }
616
617 for (i = 0; i < kona_gpio->num_bank; i++) {
618 bank = &kona_gpio->banks[i];
619 bank->id = i;
620 bank->irq = platform_get_irq(pdev, i);
621 bank->kona_gpio = kona_gpio;
622 if (bank->irq < 0) {
623 dev_err(dev, "Couldn't get IRQ for bank %d", i);
624 ret = -ENOENT;
625 goto err_irq_domain;
626 }
627 }
628
629 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
630
631 bcm_kona_gpio_reset(kona_gpio);
632
633 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
634 if (ret < 0) {
635 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
636 goto err_irq_domain;
637 }
638 for (i = 0; i < kona_gpio->num_bank; i++) {
639 bank = &kona_gpio->banks[i];
640 irq_set_chained_handler_and_data(bank->irq,
641 bcm_kona_gpio_irq_handler,
642 bank);
643 }
644
645 spin_lock_init(&kona_gpio->lock);
646
647 return 0;
648
649err_irq_domain:
650 irq_domain_remove(kona_gpio->irq_domain);
651
652 return ret;
653}
654
655static struct platform_driver bcm_kona_gpio_driver = {
656 .driver = {
657 .name = "bcm-kona-gpio",
658 .of_match_table = bcm_kona_gpio_of_match,
659 },
660 .probe = bcm_kona_gpio_probe,
661};
662
663module_platform_driver(bcm_kona_gpio_driver);
664
665MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
666MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
667MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2012-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23
24#define BCM_GPIO_PASSWD 0x00a5a501
25#define GPIO_PER_BANK 32
26#define GPIO_MAX_BANK_NUM 8
27
28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
38#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
43
44#define GPIO_GPPWR_OFFSET 0x00000520
45
46#define GPIO_GPCTR0_DBR_SHIFT 5
47#define GPIO_GPCTR0_DBR_MASK 0x000001e0
48
49#define GPIO_GPCTR0_ITR_SHIFT 3
50#define GPIO_GPCTR0_ITR_MASK 0x00000018
51#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
52#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
53#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
54
55#define GPIO_GPCTR0_IOTR_MASK 0x00000001
56#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
57#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
58
59#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
60
61#define LOCK_CODE 0xffffffff
62#define UNLOCK_CODE 0x00000000
63
64struct bcm_kona_gpio {
65 void __iomem *reg_base;
66 int num_bank;
67 spinlock_t lock;
68 struct gpio_chip gpio_chip;
69 struct irq_domain *irq_domain;
70 struct bcm_kona_gpio_bank *banks;
71 struct platform_device *pdev;
72};
73
74struct bcm_kona_gpio_bank {
75 int id;
76 int irq;
77 /* Used in the interrupt handler */
78 struct bcm_kona_gpio *kona_gpio;
79};
80
81static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
82 int bank_id, u32 lockcode)
83{
84 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
85 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
86}
87
88static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
89 unsigned gpio)
90{
91 u32 val;
92 unsigned long flags;
93 int bank_id = GPIO_BANK(gpio);
94
95 spin_lock_irqsave(&kona_gpio->lock, flags);
96
97 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
98 val |= BIT(gpio);
99 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
100
101 spin_unlock_irqrestore(&kona_gpio->lock, flags);
102}
103
104static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
105 unsigned gpio)
106{
107 u32 val;
108 unsigned long flags;
109 int bank_id = GPIO_BANK(gpio);
110
111 spin_lock_irqsave(&kona_gpio->lock, flags);
112
113 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
114 val &= ~BIT(gpio);
115 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
116
117 spin_unlock_irqrestore(&kona_gpio->lock, flags);
118}
119
120static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
121{
122 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
123 void __iomem *reg_base = kona_gpio->reg_base;
124 u32 val;
125
126 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
127 return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
128}
129
130static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
131{
132 struct bcm_kona_gpio *kona_gpio;
133 void __iomem *reg_base;
134 int bank_id = GPIO_BANK(gpio);
135 int bit = GPIO_BIT(gpio);
136 u32 val, reg_offset;
137 unsigned long flags;
138
139 kona_gpio = gpiochip_get_data(chip);
140 reg_base = kona_gpio->reg_base;
141 spin_lock_irqsave(&kona_gpio->lock, flags);
142
143 /* this function only applies to output pin */
144 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
145 goto out;
146
147 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
148
149 val = readl(reg_base + reg_offset);
150 val |= BIT(bit);
151 writel(val, reg_base + reg_offset);
152
153out:
154 spin_unlock_irqrestore(&kona_gpio->lock, flags);
155}
156
157static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
158{
159 struct bcm_kona_gpio *kona_gpio;
160 void __iomem *reg_base;
161 int bank_id = GPIO_BANK(gpio);
162 int bit = GPIO_BIT(gpio);
163 u32 val, reg_offset;
164 unsigned long flags;
165
166 kona_gpio = gpiochip_get_data(chip);
167 reg_base = kona_gpio->reg_base;
168 spin_lock_irqsave(&kona_gpio->lock, flags);
169
170 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
171 reg_offset = GPIO_IN_STATUS(bank_id);
172 else
173 reg_offset = GPIO_OUT_STATUS(bank_id);
174
175 /* read the GPIO bank status */
176 val = readl(reg_base + reg_offset);
177
178 spin_unlock_irqrestore(&kona_gpio->lock, flags);
179
180 /* return the specified bit status */
181 return !!(val & BIT(bit));
182}
183
184static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
185{
186 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
187
188 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
189 return 0;
190}
191
192static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
193{
194 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
195
196 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
197}
198
199static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
200{
201 struct bcm_kona_gpio *kona_gpio;
202 void __iomem *reg_base;
203 u32 val;
204 unsigned long flags;
205
206 kona_gpio = gpiochip_get_data(chip);
207 reg_base = kona_gpio->reg_base;
208 spin_lock_irqsave(&kona_gpio->lock, flags);
209
210 val = readl(reg_base + GPIO_CONTROL(gpio));
211 val &= ~GPIO_GPCTR0_IOTR_MASK;
212 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
213 writel(val, reg_base + GPIO_CONTROL(gpio));
214
215 spin_unlock_irqrestore(&kona_gpio->lock, flags);
216
217 return 0;
218}
219
220static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
221 unsigned gpio, int value)
222{
223 struct bcm_kona_gpio *kona_gpio;
224 void __iomem *reg_base;
225 int bank_id = GPIO_BANK(gpio);
226 int bit = GPIO_BIT(gpio);
227 u32 val, reg_offset;
228 unsigned long flags;
229
230 kona_gpio = gpiochip_get_data(chip);
231 reg_base = kona_gpio->reg_base;
232 spin_lock_irqsave(&kona_gpio->lock, flags);
233
234 val = readl(reg_base + GPIO_CONTROL(gpio));
235 val &= ~GPIO_GPCTR0_IOTR_MASK;
236 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
237 writel(val, reg_base + GPIO_CONTROL(gpio));
238 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
239
240 val = readl(reg_base + reg_offset);
241 val |= BIT(bit);
242 writel(val, reg_base + reg_offset);
243
244 spin_unlock_irqrestore(&kona_gpio->lock, flags);
245
246 return 0;
247}
248
249static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
250{
251 struct bcm_kona_gpio *kona_gpio;
252
253 kona_gpio = gpiochip_get_data(chip);
254 if (gpio >= kona_gpio->gpio_chip.ngpio)
255 return -ENXIO;
256 return irq_create_mapping(kona_gpio->irq_domain, gpio);
257}
258
259static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
260 unsigned debounce)
261{
262 struct bcm_kona_gpio *kona_gpio;
263 void __iomem *reg_base;
264 u32 val, res;
265 unsigned long flags;
266
267 kona_gpio = gpiochip_get_data(chip);
268 reg_base = kona_gpio->reg_base;
269 /* debounce must be 1-128ms (or 0) */
270 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
271 dev_err(chip->parent, "Debounce value %u not in range\n",
272 debounce);
273 return -EINVAL;
274 }
275
276 /* calculate debounce bit value */
277 if (debounce != 0) {
278 /* Convert to ms */
279 debounce /= 1000;
280 /* find the MSB */
281 res = fls(debounce) - 1;
282 /* Check if MSB-1 is set (round up or down) */
283 if (res > 0 && (debounce & BIT(res - 1)))
284 res++;
285 }
286
287 /* spin lock for read-modify-write of the GPIO register */
288 spin_lock_irqsave(&kona_gpio->lock, flags);
289
290 val = readl(reg_base + GPIO_CONTROL(gpio));
291 val &= ~GPIO_GPCTR0_DBR_MASK;
292
293 if (debounce == 0) {
294 /* disable debounce */
295 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
296 } else {
297 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
298 (res << GPIO_GPCTR0_DBR_SHIFT);
299 }
300
301 writel(val, reg_base + GPIO_CONTROL(gpio));
302
303 spin_unlock_irqrestore(&kona_gpio->lock, flags);
304
305 return 0;
306}
307
308static struct gpio_chip template_chip = {
309 .label = "bcm-kona-gpio",
310 .owner = THIS_MODULE,
311 .request = bcm_kona_gpio_request,
312 .free = bcm_kona_gpio_free,
313 .get_direction = bcm_kona_gpio_get_dir,
314 .direction_input = bcm_kona_gpio_direction_input,
315 .get = bcm_kona_gpio_get,
316 .direction_output = bcm_kona_gpio_direction_output,
317 .set = bcm_kona_gpio_set,
318 .set_debounce = bcm_kona_gpio_set_debounce,
319 .to_irq = bcm_kona_gpio_to_irq,
320 .base = 0,
321};
322
323static void bcm_kona_gpio_irq_ack(struct irq_data *d)
324{
325 struct bcm_kona_gpio *kona_gpio;
326 void __iomem *reg_base;
327 unsigned gpio = d->hwirq;
328 int bank_id = GPIO_BANK(gpio);
329 int bit = GPIO_BIT(gpio);
330 u32 val;
331 unsigned long flags;
332
333 kona_gpio = irq_data_get_irq_chip_data(d);
334 reg_base = kona_gpio->reg_base;
335 spin_lock_irqsave(&kona_gpio->lock, flags);
336
337 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
338 val |= BIT(bit);
339 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
340
341 spin_unlock_irqrestore(&kona_gpio->lock, flags);
342}
343
344static void bcm_kona_gpio_irq_mask(struct irq_data *d)
345{
346 struct bcm_kona_gpio *kona_gpio;
347 void __iomem *reg_base;
348 unsigned gpio = d->hwirq;
349 int bank_id = GPIO_BANK(gpio);
350 int bit = GPIO_BIT(gpio);
351 u32 val;
352 unsigned long flags;
353
354 kona_gpio = irq_data_get_irq_chip_data(d);
355 reg_base = kona_gpio->reg_base;
356 spin_lock_irqsave(&kona_gpio->lock, flags);
357
358 val = readl(reg_base + GPIO_INT_MASK(bank_id));
359 val |= BIT(bit);
360 writel(val, reg_base + GPIO_INT_MASK(bank_id));
361
362 spin_unlock_irqrestore(&kona_gpio->lock, flags);
363}
364
365static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
366{
367 struct bcm_kona_gpio *kona_gpio;
368 void __iomem *reg_base;
369 unsigned gpio = d->hwirq;
370 int bank_id = GPIO_BANK(gpio);
371 int bit = GPIO_BIT(gpio);
372 u32 val;
373 unsigned long flags;
374
375 kona_gpio = irq_data_get_irq_chip_data(d);
376 reg_base = kona_gpio->reg_base;
377 spin_lock_irqsave(&kona_gpio->lock, flags);
378
379 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
380 val |= BIT(bit);
381 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
382
383 spin_unlock_irqrestore(&kona_gpio->lock, flags);
384}
385
386static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
387{
388 struct bcm_kona_gpio *kona_gpio;
389 void __iomem *reg_base;
390 unsigned gpio = d->hwirq;
391 u32 lvl_type;
392 u32 val;
393 unsigned long flags;
394
395 kona_gpio = irq_data_get_irq_chip_data(d);
396 reg_base = kona_gpio->reg_base;
397 switch (type & IRQ_TYPE_SENSE_MASK) {
398 case IRQ_TYPE_EDGE_RISING:
399 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
400 break;
401
402 case IRQ_TYPE_EDGE_FALLING:
403 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
404 break;
405
406 case IRQ_TYPE_EDGE_BOTH:
407 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
408 break;
409
410 case IRQ_TYPE_LEVEL_HIGH:
411 case IRQ_TYPE_LEVEL_LOW:
412 /* BCM GPIO doesn't support level triggering */
413 default:
414 dev_err(kona_gpio->gpio_chip.parent,
415 "Invalid BCM GPIO irq type 0x%x\n", type);
416 return -EINVAL;
417 }
418
419 spin_lock_irqsave(&kona_gpio->lock, flags);
420
421 val = readl(reg_base + GPIO_CONTROL(gpio));
422 val &= ~GPIO_GPCTR0_ITR_MASK;
423 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
424 writel(val, reg_base + GPIO_CONTROL(gpio));
425
426 spin_unlock_irqrestore(&kona_gpio->lock, flags);
427
428 return 0;
429}
430
431static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
432{
433 void __iomem *reg_base;
434 int bit, bank_id;
435 unsigned long sta;
436 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
437 struct irq_chip *chip = irq_desc_get_chip(desc);
438
439 chained_irq_enter(chip, desc);
440
441 /*
442 * For bank interrupts, we can't use chip_data to store the kona_gpio
443 * pointer, since GIC needs it for its own purposes. Therefore, we get
444 * our pointer from the bank structure.
445 */
446 reg_base = bank->kona_gpio->reg_base;
447 bank_id = bank->id;
448
449 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
450 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
451 for_each_set_bit(bit, &sta, 32) {
452 int hwirq = GPIO_PER_BANK * bank_id + bit;
453 int child_irq =
454 irq_find_mapping(bank->kona_gpio->irq_domain,
455 hwirq);
456 /*
457 * Clear interrupt before handler is called so we don't
458 * miss any interrupt occurred during executing them.
459 */
460 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
461 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
462 /* Invoke interrupt handler */
463 generic_handle_irq(child_irq);
464 }
465 }
466
467 chained_irq_exit(chip, desc);
468}
469
470static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
471{
472 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
473
474 if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
475 dev_err(kona_gpio->gpio_chip.parent,
476 "unable to lock HW IRQ %lu for IRQ\n",
477 d->hwirq);
478 return -EINVAL;
479 }
480 return 0;
481}
482
483static void bcm_kona_gpio_irq_relres(struct irq_data *d)
484{
485 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
486
487 gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
488}
489
490static struct irq_chip bcm_gpio_irq_chip = {
491 .name = "bcm-kona-gpio",
492 .irq_ack = bcm_kona_gpio_irq_ack,
493 .irq_mask = bcm_kona_gpio_irq_mask,
494 .irq_unmask = bcm_kona_gpio_irq_unmask,
495 .irq_set_type = bcm_kona_gpio_irq_set_type,
496 .irq_request_resources = bcm_kona_gpio_irq_reqres,
497 .irq_release_resources = bcm_kona_gpio_irq_relres,
498};
499
500static struct of_device_id const bcm_kona_gpio_of_match[] = {
501 { .compatible = "brcm,kona-gpio" },
502 {}
503};
504
505MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
506
507/*
508 * This lock class tells lockdep that GPIO irqs are in a different
509 * category than their parents, so it won't report false recursion.
510 */
511static struct lock_class_key gpio_lock_class;
512
513static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
514 irq_hw_number_t hwirq)
515{
516 int ret;
517
518 ret = irq_set_chip_data(irq, d->host_data);
519 if (ret < 0)
520 return ret;
521 irq_set_lockdep_class(irq, &gpio_lock_class);
522 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
523 irq_set_noprobe(irq);
524
525 return 0;
526}
527
528static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
529{
530 irq_set_chip_and_handler(irq, NULL, NULL);
531 irq_set_chip_data(irq, NULL);
532}
533
534static const struct irq_domain_ops bcm_kona_irq_ops = {
535 .map = bcm_kona_gpio_irq_map,
536 .unmap = bcm_kona_gpio_irq_unmap,
537 .xlate = irq_domain_xlate_twocell,
538};
539
540static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
541{
542 void __iomem *reg_base;
543 int i;
544
545 reg_base = kona_gpio->reg_base;
546 /* disable interrupts and clear status */
547 for (i = 0; i < kona_gpio->num_bank; i++) {
548 /* Unlock the entire bank first */
549 bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
550 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
551 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
552 /* Now re-lock the bank */
553 bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
554 }
555}
556
557static int bcm_kona_gpio_probe(struct platform_device *pdev)
558{
559 struct device *dev = &pdev->dev;
560 const struct of_device_id *match;
561 struct resource *res;
562 struct bcm_kona_gpio_bank *bank;
563 struct bcm_kona_gpio *kona_gpio;
564 struct gpio_chip *chip;
565 int ret;
566 int i;
567
568 match = of_match_device(bcm_kona_gpio_of_match, dev);
569 if (!match) {
570 dev_err(dev, "Failed to find gpio controller\n");
571 return -ENODEV;
572 }
573
574 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
575 if (!kona_gpio)
576 return -ENOMEM;
577
578 kona_gpio->gpio_chip = template_chip;
579 chip = &kona_gpio->gpio_chip;
580 kona_gpio->num_bank = of_irq_count(dev->of_node);
581 if (kona_gpio->num_bank == 0) {
582 dev_err(dev, "Couldn't determine # GPIO banks\n");
583 return -ENOENT;
584 }
585 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
586 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
587 GPIO_MAX_BANK_NUM);
588 return -ENXIO;
589 }
590 kona_gpio->banks = devm_kzalloc(dev,
591 kona_gpio->num_bank *
592 sizeof(*kona_gpio->banks), GFP_KERNEL);
593 if (!kona_gpio->banks)
594 return -ENOMEM;
595
596 kona_gpio->pdev = pdev;
597 platform_set_drvdata(pdev, kona_gpio);
598 chip->of_node = dev->of_node;
599 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
600
601 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
602 chip->ngpio,
603 &bcm_kona_irq_ops,
604 kona_gpio);
605 if (!kona_gpio->irq_domain) {
606 dev_err(dev, "Couldn't allocate IRQ domain\n");
607 return -ENXIO;
608 }
609
610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
612 if (IS_ERR(kona_gpio->reg_base)) {
613 ret = -ENXIO;
614 goto err_irq_domain;
615 }
616
617 for (i = 0; i < kona_gpio->num_bank; i++) {
618 bank = &kona_gpio->banks[i];
619 bank->id = i;
620 bank->irq = platform_get_irq(pdev, i);
621 bank->kona_gpio = kona_gpio;
622 if (bank->irq < 0) {
623 dev_err(dev, "Couldn't get IRQ for bank %d", i);
624 ret = -ENOENT;
625 goto err_irq_domain;
626 }
627 }
628
629 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
630
631 bcm_kona_gpio_reset(kona_gpio);
632
633 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
634 if (ret < 0) {
635 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
636 goto err_irq_domain;
637 }
638 for (i = 0; i < kona_gpio->num_bank; i++) {
639 bank = &kona_gpio->banks[i];
640 irq_set_chained_handler_and_data(bank->irq,
641 bcm_kona_gpio_irq_handler,
642 bank);
643 }
644
645 spin_lock_init(&kona_gpio->lock);
646
647 return 0;
648
649err_irq_domain:
650 irq_domain_remove(kona_gpio->irq_domain);
651
652 return ret;
653}
654
655static struct platform_driver bcm_kona_gpio_driver = {
656 .driver = {
657 .name = "bcm-kona-gpio",
658 .of_match_table = bcm_kona_gpio_of_match,
659 },
660 .probe = bcm_kona_gpio_probe,
661};
662
663module_platform_driver(bcm_kona_gpio_driver);
664
665MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
666MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
667MODULE_LICENSE("GPL v2");