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1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <linux/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/module.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
45#ifdef CONFIG_KVM_GUEST
46#include <linux/kvm_para.h>
47#else
48#define kvm_para_available() (0)
49#endif
50
51MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
52MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
53MODULE_LICENSE("GPL");
54MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
55 "{Intel,82901AB-ICH0},"
56 "{Intel,82801BA-ICH2},"
57 "{Intel,82801CA-ICH3},"
58 "{Intel,82801DB-ICH4},"
59 "{Intel,ICH5},"
60 "{Intel,ICH6},"
61 "{Intel,ICH7},"
62 "{Intel,6300ESB},"
63 "{Intel,ESB2},"
64 "{Intel,MX440},"
65 "{SiS,SI7012},"
66 "{NVidia,nForce Audio},"
67 "{NVidia,nForce2 Audio},"
68 "{NVidia,nForce3 Audio},"
69 "{NVidia,MCP04},"
70 "{NVidia,MCP501},"
71 "{NVidia,CK804},"
72 "{NVidia,CK8},"
73 "{NVidia,CK8S},"
74 "{AMD,AMD768},"
75 "{AMD,AMD8111},"
76 "{ALI,M5455}}");
77
78static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
79static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
80static int ac97_clock;
81static char *ac97_quirk;
82static bool buggy_semaphore;
83static int buggy_irq = -1; /* auto-check */
84static bool xbox;
85static int spdif_aclink = -1;
86static int inside_vm = -1;
87
88module_param(index, int, 0444);
89MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
90module_param(id, charp, 0444);
91MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
92module_param(ac97_clock, int, 0444);
93MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
94module_param(ac97_quirk, charp, 0444);
95MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
96module_param(buggy_semaphore, bool, 0444);
97MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
98module_param(buggy_irq, bint, 0444);
99MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
100module_param(xbox, bool, 0444);
101MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
102module_param(spdif_aclink, int, 0444);
103MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
104module_param(inside_vm, bint, 0444);
105MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
106
107/* just for backward compatibility */
108static bool enable;
109module_param(enable, bool, 0444);
110static int joystick;
111module_param(joystick, int, 0444);
112
113/*
114 * Direct registers
115 */
116enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
117
118#define ICHREG(x) ICH_REG_##x
119
120#define DEFINE_REGSET(name,base) \
121enum { \
122 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
123 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
124 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
125 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
126 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
127 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
128 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
129};
130
131/* busmaster blocks */
132DEFINE_REGSET(OFF, 0); /* offset */
133DEFINE_REGSET(PI, 0x00); /* PCM in */
134DEFINE_REGSET(PO, 0x10); /* PCM out */
135DEFINE_REGSET(MC, 0x20); /* Mic in */
136
137/* ICH4 busmaster blocks */
138DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
139DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
140DEFINE_REGSET(SP, 0x60); /* SPDIF out */
141
142/* values for each busmaster block */
143
144/* LVI */
145#define ICH_REG_LVI_MASK 0x1f
146
147/* SR */
148#define ICH_FIFOE 0x10 /* FIFO error */
149#define ICH_BCIS 0x08 /* buffer completion interrupt status */
150#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
151#define ICH_CELV 0x02 /* current equals last valid */
152#define ICH_DCH 0x01 /* DMA controller halted */
153
154/* PIV */
155#define ICH_REG_PIV_MASK 0x1f /* mask */
156
157/* CR */
158#define ICH_IOCE 0x10 /* interrupt on completion enable */
159#define ICH_FEIE 0x08 /* fifo error interrupt enable */
160#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
161#define ICH_RESETREGS 0x02 /* reset busmaster registers */
162#define ICH_STARTBM 0x01 /* start busmaster operation */
163
164
165/* global block */
166#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
167#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
168#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
169#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
170#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
171#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
172#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
173#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
174#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
175#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
176#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
177#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
178#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
179#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
180#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
181#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
182#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
183#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
184#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
185#define ICH_ACLINK 0x00000008 /* AClink shut off */
186#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
187#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
188#define ICH_GIE 0x00000001 /* GPI interrupt enable */
189#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
190#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
191#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
192#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
193#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
194#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
195#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
196#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
197#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
198#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
199#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
200#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
201#define ICH_MD3 0x00020000 /* modem power down semaphore */
202#define ICH_AD3 0x00010000 /* audio power down semaphore */
203#define ICH_RCS 0x00008000 /* read completion status */
204#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
205#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
206#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
207#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
208#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
209#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
210#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
211#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
212#define ICH_POINT 0x00000040 /* playback interrupt */
213#define ICH_PIINT 0x00000020 /* capture interrupt */
214#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
215#define ICH_MOINT 0x00000004 /* modem playback interrupt */
216#define ICH_MIINT 0x00000002 /* modem capture interrupt */
217#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
218#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
219#define ICH_CAS 0x01 /* codec access semaphore */
220#define ICH_REG_SDM 0x80
221#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
222#define ICH_DI2L_SHIFT 6
223#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
224#define ICH_DI1L_SHIFT 4
225#define ICH_SE 0x00000008 /* steer enable */
226#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
227
228#define ICH_MAX_FRAGS 32 /* max hw frags */
229
230
231/*
232 * registers for Ali5455
233 */
234
235/* ALi 5455 busmaster blocks */
236DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
237DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
238DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
239DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
240DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
241DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
242DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
243DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
244DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
245DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
246DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
247
248enum {
249 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
250 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
251 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
252 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
253 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
254 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
255 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
256 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
257 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
258 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
259 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
260 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
261 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
262 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
263 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
264 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
265 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
266 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
267 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
268 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
269 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
270};
271
272#define ALI_CAS_SEM_BUSY 0x80000000
273#define ALI_CPR_ADDR_SECONDARY 0x100
274#define ALI_CPR_ADDR_READ 0x80
275#define ALI_CSPSR_CODEC_READY 0x08
276#define ALI_CSPSR_READ_OK 0x02
277#define ALI_CSPSR_WRITE_OK 0x01
278
279/* interrupts for the whole chip by interrupt status register finish */
280
281#define ALI_INT_MICIN2 (1<<26)
282#define ALI_INT_PCMIN2 (1<<25)
283#define ALI_INT_I2SIN (1<<24)
284#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
285#define ALI_INT_SPDIFIN (1<<22)
286#define ALI_INT_LFEOUT (1<<21)
287#define ALI_INT_CENTEROUT (1<<20)
288#define ALI_INT_CODECSPDIFOUT (1<<19)
289#define ALI_INT_MICIN (1<<18)
290#define ALI_INT_PCMOUT (1<<17)
291#define ALI_INT_PCMIN (1<<16)
292#define ALI_INT_CPRAIS (1<<7) /* command port available */
293#define ALI_INT_SPRAIS (1<<5) /* status port available */
294#define ALI_INT_GPIO (1<<1)
295#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
296 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
297
298#define ICH_ALI_SC_RESET (1<<31) /* master reset */
299#define ICH_ALI_SC_AC97_DBL (1<<30)
300#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
301#define ICH_ALI_SC_IN_BITS (3<<18)
302#define ICH_ALI_SC_OUT_BITS (3<<16)
303#define ICH_ALI_SC_6CH_CFG (3<<14)
304#define ICH_ALI_SC_PCM_4 (1<<8)
305#define ICH_ALI_SC_PCM_6 (2<<8)
306#define ICH_ALI_SC_PCM_246_MASK (3<<8)
307
308#define ICH_ALI_SS_SEC_ID (3<<5)
309#define ICH_ALI_SS_PRI_ID (3<<3)
310
311#define ICH_ALI_IF_AC97SP (1<<21)
312#define ICH_ALI_IF_MC (1<<20)
313#define ICH_ALI_IF_PI (1<<19)
314#define ICH_ALI_IF_MC2 (1<<18)
315#define ICH_ALI_IF_PI2 (1<<17)
316#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
317#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
318#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
319#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
320#define ICH_ALI_IF_PO_SPDF (1<<3)
321#define ICH_ALI_IF_PO (1<<1)
322
323/*
324 *
325 */
326
327enum {
328 ICHD_PCMIN,
329 ICHD_PCMOUT,
330 ICHD_MIC,
331 ICHD_MIC2,
332 ICHD_PCM2IN,
333 ICHD_SPBAR,
334 ICHD_LAST = ICHD_SPBAR
335};
336enum {
337 NVD_PCMIN,
338 NVD_PCMOUT,
339 NVD_MIC,
340 NVD_SPBAR,
341 NVD_LAST = NVD_SPBAR
342};
343enum {
344 ALID_PCMIN,
345 ALID_PCMOUT,
346 ALID_MIC,
347 ALID_AC97SPDIFOUT,
348 ALID_SPDIFIN,
349 ALID_SPDIFOUT,
350 ALID_LAST = ALID_SPDIFOUT
351};
352
353#define get_ichdev(substream) (substream->runtime->private_data)
354
355struct ichdev {
356 unsigned int ichd; /* ich device number */
357 unsigned long reg_offset; /* offset to bmaddr */
358 u32 *bdbar; /* CPU address (32bit) */
359 unsigned int bdbar_addr; /* PCI bus address (32bit) */
360 struct snd_pcm_substream *substream;
361 unsigned int physbuf; /* physical address (32bit) */
362 unsigned int size;
363 unsigned int fragsize;
364 unsigned int fragsize1;
365 unsigned int position;
366 unsigned int pos_shift;
367 unsigned int last_pos;
368 int frags;
369 int lvi;
370 int lvi_frag;
371 int civ;
372 int ack;
373 int ack_reload;
374 unsigned int ack_bit;
375 unsigned int roff_sr;
376 unsigned int roff_picb;
377 unsigned int int_sta_mask; /* interrupt status mask */
378 unsigned int ali_slot; /* ALI DMA slot */
379 struct ac97_pcm *pcm;
380 int pcm_open_flag;
381 unsigned int page_attr_changed: 1;
382 unsigned int suspended: 1;
383};
384
385struct intel8x0 {
386 unsigned int device_type;
387
388 int irq;
389
390 void __iomem *addr;
391 void __iomem *bmaddr;
392
393 struct pci_dev *pci;
394 struct snd_card *card;
395
396 int pcm_devs;
397 struct snd_pcm *pcm[6];
398 struct ichdev ichd[6];
399
400 unsigned multi4: 1,
401 multi6: 1,
402 multi8 :1,
403 dra: 1,
404 smp20bit: 1;
405 unsigned in_ac97_init: 1,
406 in_sdin_init: 1;
407 unsigned in_measurement: 1; /* during ac97 clock measurement */
408 unsigned fix_nocache: 1; /* workaround for 440MX */
409 unsigned buggy_irq: 1; /* workaround for buggy mobos */
410 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
411 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
412 unsigned inside_vm: 1; /* enable VM optimization */
413
414 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
415 unsigned int sdm_saved; /* SDM reg value */
416
417 struct snd_ac97_bus *ac97_bus;
418 struct snd_ac97 *ac97[3];
419 unsigned int ac97_sdin[3];
420 unsigned int max_codecs, ncodecs;
421 unsigned int *codec_bit;
422 unsigned int codec_isr_bits;
423 unsigned int codec_ready_bits;
424
425 spinlock_t reg_lock;
426
427 u32 bdbars_count;
428 struct snd_dma_buffer bdbars;
429 u32 int_sta_reg; /* interrupt status register */
430 u32 int_sta_mask; /* interrupt status mask */
431};
432
433static const struct pci_device_id snd_intel8x0_ids[] = {
434 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
435 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
436 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
437 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
438 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
439 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
440 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
441 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
442 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
443 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
444 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
445 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
446 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
447 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
448 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
449 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
450 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
451 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
452 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
453 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
454 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
455 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
456 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
457 { 0, }
458};
459
460MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
461
462/*
463 * Lowlevel I/O - busmaster
464 */
465
466static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
467{
468 return ioread8(chip->bmaddr + offset);
469}
470
471static inline u16 igetword(struct intel8x0 *chip, u32 offset)
472{
473 return ioread16(chip->bmaddr + offset);
474}
475
476static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
477{
478 return ioread32(chip->bmaddr + offset);
479}
480
481static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
482{
483 iowrite8(val, chip->bmaddr + offset);
484}
485
486static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
487{
488 iowrite16(val, chip->bmaddr + offset);
489}
490
491static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
492{
493 iowrite32(val, chip->bmaddr + offset);
494}
495
496/*
497 * Lowlevel I/O - AC'97 registers
498 */
499
500static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
501{
502 return ioread16(chip->addr + offset);
503}
504
505static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
506{
507 iowrite16(val, chip->addr + offset);
508}
509
510/*
511 * Basic I/O
512 */
513
514/*
515 * access to AC97 codec via normal i/o (for ICH and SIS7012)
516 */
517
518static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
519{
520 int time;
521
522 if (codec > 2)
523 return -EIO;
524 if (chip->in_sdin_init) {
525 /* we don't know the ready bit assignment at the moment */
526 /* so we check any */
527 codec = chip->codec_isr_bits;
528 } else {
529 codec = chip->codec_bit[chip->ac97_sdin[codec]];
530 }
531
532 /* codec ready ? */
533 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
534 return -EIO;
535
536 if (chip->buggy_semaphore)
537 return 0; /* just ignore ... */
538
539 /* Anyone holding a semaphore for 1 msec should be shot... */
540 time = 100;
541 do {
542 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
543 return 0;
544 udelay(10);
545 } while (time--);
546
547 /* access to some forbidden (non existent) ac97 registers will not
548 * reset the semaphore. So even if you don't get the semaphore, still
549 * continue the access. We don't need the semaphore anyway. */
550 dev_err(chip->card->dev,
551 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
552 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
553 iagetword(chip, 0); /* clear semaphore flag */
554 /* I don't care about the semaphore */
555 return -EBUSY;
556}
557
558static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
559 unsigned short reg,
560 unsigned short val)
561{
562 struct intel8x0 *chip = ac97->private_data;
563
564 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
565 if (! chip->in_ac97_init)
566 dev_err(chip->card->dev,
567 "codec_write %d: semaphore is not ready for register 0x%x\n",
568 ac97->num, reg);
569 }
570 iaputword(chip, reg + ac97->num * 0x80, val);
571}
572
573static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
574 unsigned short reg)
575{
576 struct intel8x0 *chip = ac97->private_data;
577 unsigned short res;
578 unsigned int tmp;
579
580 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
581 if (! chip->in_ac97_init)
582 dev_err(chip->card->dev,
583 "codec_read %d: semaphore is not ready for register 0x%x\n",
584 ac97->num, reg);
585 res = 0xffff;
586 } else {
587 res = iagetword(chip, reg + ac97->num * 0x80);
588 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
589 /* reset RCS and preserve other R/WC bits */
590 iputdword(chip, ICHREG(GLOB_STA), tmp &
591 ~(chip->codec_ready_bits | ICH_GSCI));
592 if (! chip->in_ac97_init)
593 dev_err(chip->card->dev,
594 "codec_read %d: read timeout for register 0x%x\n",
595 ac97->num, reg);
596 res = 0xffff;
597 }
598 }
599 return res;
600}
601
602static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
603 unsigned int codec)
604{
605 unsigned int tmp;
606
607 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
608 iagetword(chip, codec * 0x80);
609 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
610 /* reset RCS and preserve other R/WC bits */
611 iputdword(chip, ICHREG(GLOB_STA), tmp &
612 ~(chip->codec_ready_bits | ICH_GSCI));
613 }
614 }
615}
616
617/*
618 * access to AC97 for Ali5455
619 */
620static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
621{
622 int count = 0;
623 for (count = 0; count < 0x7f; count++) {
624 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
625 if (val & mask)
626 return 0;
627 }
628 if (! chip->in_ac97_init)
629 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
630 return -EBUSY;
631}
632
633static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
634{
635 int time = 100;
636 if (chip->buggy_semaphore)
637 return 0; /* just ignore ... */
638 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
639 udelay(1);
640 if (! time && ! chip->in_ac97_init)
641 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
642 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
643}
644
645static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
646{
647 struct intel8x0 *chip = ac97->private_data;
648 unsigned short data = 0xffff;
649
650 if (snd_intel8x0_ali_codec_semaphore(chip))
651 goto __err;
652 reg |= ALI_CPR_ADDR_READ;
653 if (ac97->num)
654 reg |= ALI_CPR_ADDR_SECONDARY;
655 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
656 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
657 goto __err;
658 data = igetword(chip, ICHREG(ALI_SPR));
659 __err:
660 return data;
661}
662
663static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
664 unsigned short val)
665{
666 struct intel8x0 *chip = ac97->private_data;
667
668 if (snd_intel8x0_ali_codec_semaphore(chip))
669 return;
670 iputword(chip, ICHREG(ALI_CPR), val);
671 if (ac97->num)
672 reg |= ALI_CPR_ADDR_SECONDARY;
673 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
674 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
675}
676
677
678/*
679 * DMA I/O
680 */
681static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
682{
683 int idx;
684 u32 *bdbar = ichdev->bdbar;
685 unsigned long port = ichdev->reg_offset;
686
687 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
688 if (ichdev->size == ichdev->fragsize) {
689 ichdev->ack_reload = ichdev->ack = 2;
690 ichdev->fragsize1 = ichdev->fragsize >> 1;
691 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
692 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
693 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
694 ichdev->fragsize1 >> ichdev->pos_shift);
695 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
696 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
697 ichdev->fragsize1 >> ichdev->pos_shift);
698 }
699 ichdev->frags = 2;
700 } else {
701 ichdev->ack_reload = ichdev->ack = 1;
702 ichdev->fragsize1 = ichdev->fragsize;
703 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
704 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
705 (((idx >> 1) * ichdev->fragsize) %
706 ichdev->size));
707 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
708 ichdev->fragsize >> ichdev->pos_shift);
709#if 0
710 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
711 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
712#endif
713 }
714 ichdev->frags = ichdev->size / ichdev->fragsize;
715 }
716 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
717 ichdev->civ = 0;
718 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
719 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
720 ichdev->position = 0;
721#if 0
722 dev_dbg(chip->card->dev,
723 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
724 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
725 ichdev->fragsize1);
726#endif
727 /* clear interrupts */
728 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
729}
730
731#ifdef __i386__
732/*
733 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
734 * which aborts PCI busmaster for audio transfer. A workaround is to set
735 * the pages as non-cached. For details, see the errata in
736 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
737 */
738static void fill_nocache(void *buf, int size, int nocache)
739{
740 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
741 if (nocache)
742 set_pages_uc(virt_to_page(buf), size);
743 else
744 set_pages_wb(virt_to_page(buf), size);
745}
746#else
747#define fill_nocache(buf, size, nocache) do { ; } while (0)
748#endif
749
750/*
751 * Interrupt handler
752 */
753
754static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
755{
756 unsigned long port = ichdev->reg_offset;
757 unsigned long flags;
758 int status, civ, i, step;
759 int ack = 0;
760
761 spin_lock_irqsave(&chip->reg_lock, flags);
762 status = igetbyte(chip, port + ichdev->roff_sr);
763 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
764 if (!(status & ICH_BCIS)) {
765 step = 0;
766 } else if (civ == ichdev->civ) {
767 // snd_printd("civ same %d\n", civ);
768 step = 1;
769 ichdev->civ++;
770 ichdev->civ &= ICH_REG_LVI_MASK;
771 } else {
772 step = civ - ichdev->civ;
773 if (step < 0)
774 step += ICH_REG_LVI_MASK + 1;
775 // if (step != 1)
776 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
777 ichdev->civ = civ;
778 }
779
780 ichdev->position += step * ichdev->fragsize1;
781 if (! chip->in_measurement)
782 ichdev->position %= ichdev->size;
783 ichdev->lvi += step;
784 ichdev->lvi &= ICH_REG_LVI_MASK;
785 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
786 for (i = 0; i < step; i++) {
787 ichdev->lvi_frag++;
788 ichdev->lvi_frag %= ichdev->frags;
789 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
790#if 0
791 dev_dbg(chip->card->dev,
792 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
793 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
794 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
795 inl(port + 4), inb(port + ICH_REG_OFF_CR));
796#endif
797 if (--ichdev->ack == 0) {
798 ichdev->ack = ichdev->ack_reload;
799 ack = 1;
800 }
801 }
802 spin_unlock_irqrestore(&chip->reg_lock, flags);
803 if (ack && ichdev->substream) {
804 snd_pcm_period_elapsed(ichdev->substream);
805 }
806 iputbyte(chip, port + ichdev->roff_sr,
807 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
808}
809
810static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
811{
812 struct intel8x0 *chip = dev_id;
813 struct ichdev *ichdev;
814 unsigned int status;
815 unsigned int i;
816
817 status = igetdword(chip, chip->int_sta_reg);
818 if (status == 0xffffffff) /* we are not yet resumed */
819 return IRQ_NONE;
820
821 if ((status & chip->int_sta_mask) == 0) {
822 if (status) {
823 /* ack */
824 iputdword(chip, chip->int_sta_reg, status);
825 if (! chip->buggy_irq)
826 status = 0;
827 }
828 return IRQ_RETVAL(status);
829 }
830
831 for (i = 0; i < chip->bdbars_count; i++) {
832 ichdev = &chip->ichd[i];
833 if (status & ichdev->int_sta_mask)
834 snd_intel8x0_update(chip, ichdev);
835 }
836
837 /* ack them */
838 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
839
840 return IRQ_HANDLED;
841}
842
843/*
844 * PCM part
845 */
846
847static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
848{
849 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
850 struct ichdev *ichdev = get_ichdev(substream);
851 unsigned char val = 0;
852 unsigned long port = ichdev->reg_offset;
853
854 switch (cmd) {
855 case SNDRV_PCM_TRIGGER_RESUME:
856 ichdev->suspended = 0;
857 /* fallthru */
858 case SNDRV_PCM_TRIGGER_START:
859 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
860 val = ICH_IOCE | ICH_STARTBM;
861 ichdev->last_pos = ichdev->position;
862 break;
863 case SNDRV_PCM_TRIGGER_SUSPEND:
864 ichdev->suspended = 1;
865 /* fallthru */
866 case SNDRV_PCM_TRIGGER_STOP:
867 val = 0;
868 break;
869 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
870 val = ICH_IOCE;
871 break;
872 default:
873 return -EINVAL;
874 }
875 iputbyte(chip, port + ICH_REG_OFF_CR, val);
876 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
877 /* wait until DMA stopped */
878 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
879 /* reset whole DMA things */
880 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
881 }
882 return 0;
883}
884
885static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
886{
887 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
888 struct ichdev *ichdev = get_ichdev(substream);
889 unsigned long port = ichdev->reg_offset;
890 static int fiforeg[] = {
891 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
892 };
893 unsigned int val, fifo;
894
895 val = igetdword(chip, ICHREG(ALI_DMACR));
896 switch (cmd) {
897 case SNDRV_PCM_TRIGGER_RESUME:
898 ichdev->suspended = 0;
899 /* fallthru */
900 case SNDRV_PCM_TRIGGER_START:
901 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
902 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
903 /* clear FIFO for synchronization of channels */
904 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
905 fifo &= ~(0xff << (ichdev->ali_slot % 4));
906 fifo |= 0x83 << (ichdev->ali_slot % 4);
907 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
908 }
909 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
910 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
911 /* start DMA */
912 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
913 break;
914 case SNDRV_PCM_TRIGGER_SUSPEND:
915 ichdev->suspended = 1;
916 /* fallthru */
917 case SNDRV_PCM_TRIGGER_STOP:
918 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
919 /* pause */
920 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
921 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
922 while (igetbyte(chip, port + ICH_REG_OFF_CR))
923 ;
924 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
925 break;
926 /* reset whole DMA things */
927 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
928 /* clear interrupts */
929 iputbyte(chip, port + ICH_REG_OFF_SR,
930 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
931 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
932 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
933 break;
934 default:
935 return -EINVAL;
936 }
937 return 0;
938}
939
940static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
941 struct snd_pcm_hw_params *hw_params)
942{
943 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
944 struct ichdev *ichdev = get_ichdev(substream);
945 struct snd_pcm_runtime *runtime = substream->runtime;
946 int dbl = params_rate(hw_params) > 48000;
947 int err;
948
949 if (chip->fix_nocache && ichdev->page_attr_changed) {
950 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
951 ichdev->page_attr_changed = 0;
952 }
953 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
954 if (err < 0)
955 return err;
956 if (chip->fix_nocache) {
957 if (runtime->dma_area && ! ichdev->page_attr_changed) {
958 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
959 ichdev->page_attr_changed = 1;
960 }
961 }
962 if (ichdev->pcm_open_flag) {
963 snd_ac97_pcm_close(ichdev->pcm);
964 ichdev->pcm_open_flag = 0;
965 }
966 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
967 params_channels(hw_params),
968 ichdev->pcm->r[dbl].slots);
969 if (err >= 0) {
970 ichdev->pcm_open_flag = 1;
971 /* Force SPDIF setting */
972 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
973 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
974 params_rate(hw_params));
975 }
976 return err;
977}
978
979static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
980{
981 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
982 struct ichdev *ichdev = get_ichdev(substream);
983
984 if (ichdev->pcm_open_flag) {
985 snd_ac97_pcm_close(ichdev->pcm);
986 ichdev->pcm_open_flag = 0;
987 }
988 if (chip->fix_nocache && ichdev->page_attr_changed) {
989 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
990 ichdev->page_attr_changed = 0;
991 }
992 return snd_pcm_lib_free_pages(substream);
993}
994
995static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
996 struct snd_pcm_runtime *runtime)
997{
998 unsigned int cnt;
999 int dbl = runtime->rate > 48000;
1000
1001 spin_lock_irq(&chip->reg_lock);
1002 switch (chip->device_type) {
1003 case DEVICE_ALI:
1004 cnt = igetdword(chip, ICHREG(ALI_SCR));
1005 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1006 if (runtime->channels == 4 || dbl)
1007 cnt |= ICH_ALI_SC_PCM_4;
1008 else if (runtime->channels == 6)
1009 cnt |= ICH_ALI_SC_PCM_6;
1010 iputdword(chip, ICHREG(ALI_SCR), cnt);
1011 break;
1012 case DEVICE_SIS:
1013 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1014 cnt &= ~ICH_SIS_PCM_246_MASK;
1015 if (runtime->channels == 4 || dbl)
1016 cnt |= ICH_SIS_PCM_4;
1017 else if (runtime->channels == 6)
1018 cnt |= ICH_SIS_PCM_6;
1019 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1020 break;
1021 default:
1022 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1023 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1024 if (runtime->channels == 4 || dbl)
1025 cnt |= ICH_PCM_4;
1026 else if (runtime->channels == 6)
1027 cnt |= ICH_PCM_6;
1028 else if (runtime->channels == 8)
1029 cnt |= ICH_PCM_8;
1030 if (chip->device_type == DEVICE_NFORCE) {
1031 /* reset to 2ch once to keep the 6 channel data in alignment,
1032 * to start from Front Left always
1033 */
1034 if (cnt & ICH_PCM_246_MASK) {
1035 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1036 spin_unlock_irq(&chip->reg_lock);
1037 msleep(50); /* grrr... */
1038 spin_lock_irq(&chip->reg_lock);
1039 }
1040 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1041 if (runtime->sample_bits > 16)
1042 cnt |= ICH_PCM_20BIT;
1043 }
1044 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1045 break;
1046 }
1047 spin_unlock_irq(&chip->reg_lock);
1048}
1049
1050static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1051{
1052 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1053 struct snd_pcm_runtime *runtime = substream->runtime;
1054 struct ichdev *ichdev = get_ichdev(substream);
1055
1056 ichdev->physbuf = runtime->dma_addr;
1057 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1058 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1059 if (ichdev->ichd == ICHD_PCMOUT) {
1060 snd_intel8x0_setup_pcm_out(chip, runtime);
1061 if (chip->device_type == DEVICE_INTEL_ICH4)
1062 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1063 }
1064 snd_intel8x0_setup_periods(chip, ichdev);
1065 return 0;
1066}
1067
1068static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1069{
1070 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1071 struct ichdev *ichdev = get_ichdev(substream);
1072 size_t ptr1, ptr;
1073 int civ, timeout = 10;
1074 unsigned int position;
1075
1076 spin_lock(&chip->reg_lock);
1077 do {
1078 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1079 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1080 position = ichdev->position;
1081 if (ptr1 == 0) {
1082 udelay(10);
1083 continue;
1084 }
1085 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1086 continue;
1087
1088 /* IO read operation is very expensive inside virtual machine
1089 * as it is emulated. The probability that subsequent PICB read
1090 * will return different result is high enough to loop till
1091 * timeout here.
1092 * Same CIV is strict enough condition to be sure that PICB
1093 * is valid inside VM on emulated card. */
1094 if (chip->inside_vm)
1095 break;
1096 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1097 break;
1098 } while (timeout--);
1099 ptr = ichdev->last_pos;
1100 if (ptr1 != 0) {
1101 ptr1 <<= ichdev->pos_shift;
1102 ptr = ichdev->fragsize1 - ptr1;
1103 ptr += position;
1104 if (ptr < ichdev->last_pos) {
1105 unsigned int pos_base, last_base;
1106 pos_base = position / ichdev->fragsize1;
1107 last_base = ichdev->last_pos / ichdev->fragsize1;
1108 /* another sanity check; ptr1 can go back to full
1109 * before the base position is updated
1110 */
1111 if (pos_base == last_base)
1112 ptr = ichdev->last_pos;
1113 }
1114 }
1115 ichdev->last_pos = ptr;
1116 spin_unlock(&chip->reg_lock);
1117 if (ptr >= ichdev->size)
1118 return 0;
1119 return bytes_to_frames(substream->runtime, ptr);
1120}
1121
1122static struct snd_pcm_hardware snd_intel8x0_stream =
1123{
1124 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1125 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1126 SNDRV_PCM_INFO_MMAP_VALID |
1127 SNDRV_PCM_INFO_PAUSE |
1128 SNDRV_PCM_INFO_RESUME),
1129 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1130 .rates = SNDRV_PCM_RATE_48000,
1131 .rate_min = 48000,
1132 .rate_max = 48000,
1133 .channels_min = 2,
1134 .channels_max = 2,
1135 .buffer_bytes_max = 128 * 1024,
1136 .period_bytes_min = 32,
1137 .period_bytes_max = 128 * 1024,
1138 .periods_min = 1,
1139 .periods_max = 1024,
1140 .fifo_size = 0,
1141};
1142
1143static unsigned int channels4[] = {
1144 2, 4,
1145};
1146
1147static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1148 .count = ARRAY_SIZE(channels4),
1149 .list = channels4,
1150 .mask = 0,
1151};
1152
1153static unsigned int channels6[] = {
1154 2, 4, 6,
1155};
1156
1157static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1158 .count = ARRAY_SIZE(channels6),
1159 .list = channels6,
1160 .mask = 0,
1161};
1162
1163static unsigned int channels8[] = {
1164 2, 4, 6, 8,
1165};
1166
1167static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1168 .count = ARRAY_SIZE(channels8),
1169 .list = channels8,
1170 .mask = 0,
1171};
1172
1173static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1174{
1175 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1176 struct snd_pcm_runtime *runtime = substream->runtime;
1177 int err;
1178
1179 ichdev->substream = substream;
1180 runtime->hw = snd_intel8x0_stream;
1181 runtime->hw.rates = ichdev->pcm->rates;
1182 snd_pcm_limit_hw_rates(runtime);
1183 if (chip->device_type == DEVICE_SIS) {
1184 runtime->hw.buffer_bytes_max = 64*1024;
1185 runtime->hw.period_bytes_max = 64*1024;
1186 }
1187 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1188 return err;
1189 runtime->private_data = ichdev;
1190 return 0;
1191}
1192
1193static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1194{
1195 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1196 struct snd_pcm_runtime *runtime = substream->runtime;
1197 int err;
1198
1199 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1200 if (err < 0)
1201 return err;
1202
1203 if (chip->multi8) {
1204 runtime->hw.channels_max = 8;
1205 snd_pcm_hw_constraint_list(runtime, 0,
1206 SNDRV_PCM_HW_PARAM_CHANNELS,
1207 &hw_constraints_channels8);
1208 } else if (chip->multi6) {
1209 runtime->hw.channels_max = 6;
1210 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1211 &hw_constraints_channels6);
1212 } else if (chip->multi4) {
1213 runtime->hw.channels_max = 4;
1214 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1215 &hw_constraints_channels4);
1216 }
1217 if (chip->dra) {
1218 snd_ac97_pcm_double_rate_rules(runtime);
1219 }
1220 if (chip->smp20bit) {
1221 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1222 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1223 }
1224 return 0;
1225}
1226
1227static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1228{
1229 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1230
1231 chip->ichd[ICHD_PCMOUT].substream = NULL;
1232 return 0;
1233}
1234
1235static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1236{
1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238
1239 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1240}
1241
1242static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1243{
1244 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1245
1246 chip->ichd[ICHD_PCMIN].substream = NULL;
1247 return 0;
1248}
1249
1250static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1251{
1252 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253
1254 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1255}
1256
1257static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1258{
1259 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1260
1261 chip->ichd[ICHD_MIC].substream = NULL;
1262 return 0;
1263}
1264
1265static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1266{
1267 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1268
1269 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1270}
1271
1272static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1273{
1274 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1275
1276 chip->ichd[ICHD_MIC2].substream = NULL;
1277 return 0;
1278}
1279
1280static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1281{
1282 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1283
1284 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1285}
1286
1287static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1288{
1289 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290
1291 chip->ichd[ICHD_PCM2IN].substream = NULL;
1292 return 0;
1293}
1294
1295static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1296{
1297 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1298 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1299
1300 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1301}
1302
1303static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1304{
1305 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1306 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1307
1308 chip->ichd[idx].substream = NULL;
1309 return 0;
1310}
1311
1312static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1313{
1314 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1315 unsigned int val;
1316
1317 spin_lock_irq(&chip->reg_lock);
1318 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1319 val |= ICH_ALI_IF_AC97SP;
1320 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1321 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1322 spin_unlock_irq(&chip->reg_lock);
1323
1324 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1325}
1326
1327static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1328{
1329 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1330 unsigned int val;
1331
1332 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1333 spin_lock_irq(&chip->reg_lock);
1334 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1335 val &= ~ICH_ALI_IF_AC97SP;
1336 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1337 spin_unlock_irq(&chip->reg_lock);
1338
1339 return 0;
1340}
1341
1342#if 0 // NYI
1343static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1344{
1345 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1346
1347 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1348}
1349
1350static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1351{
1352 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1353
1354 chip->ichd[ALID_SPDIFIN].substream = NULL;
1355 return 0;
1356}
1357
1358static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1359{
1360 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1361
1362 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1363}
1364
1365static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1366{
1367 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1368
1369 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1370 return 0;
1371}
1372#endif
1373
1374static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1375 .open = snd_intel8x0_playback_open,
1376 .close = snd_intel8x0_playback_close,
1377 .ioctl = snd_pcm_lib_ioctl,
1378 .hw_params = snd_intel8x0_hw_params,
1379 .hw_free = snd_intel8x0_hw_free,
1380 .prepare = snd_intel8x0_pcm_prepare,
1381 .trigger = snd_intel8x0_pcm_trigger,
1382 .pointer = snd_intel8x0_pcm_pointer,
1383};
1384
1385static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1386 .open = snd_intel8x0_capture_open,
1387 .close = snd_intel8x0_capture_close,
1388 .ioctl = snd_pcm_lib_ioctl,
1389 .hw_params = snd_intel8x0_hw_params,
1390 .hw_free = snd_intel8x0_hw_free,
1391 .prepare = snd_intel8x0_pcm_prepare,
1392 .trigger = snd_intel8x0_pcm_trigger,
1393 .pointer = snd_intel8x0_pcm_pointer,
1394};
1395
1396static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1397 .open = snd_intel8x0_mic_open,
1398 .close = snd_intel8x0_mic_close,
1399 .ioctl = snd_pcm_lib_ioctl,
1400 .hw_params = snd_intel8x0_hw_params,
1401 .hw_free = snd_intel8x0_hw_free,
1402 .prepare = snd_intel8x0_pcm_prepare,
1403 .trigger = snd_intel8x0_pcm_trigger,
1404 .pointer = snd_intel8x0_pcm_pointer,
1405};
1406
1407static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1408 .open = snd_intel8x0_mic2_open,
1409 .close = snd_intel8x0_mic2_close,
1410 .ioctl = snd_pcm_lib_ioctl,
1411 .hw_params = snd_intel8x0_hw_params,
1412 .hw_free = snd_intel8x0_hw_free,
1413 .prepare = snd_intel8x0_pcm_prepare,
1414 .trigger = snd_intel8x0_pcm_trigger,
1415 .pointer = snd_intel8x0_pcm_pointer,
1416};
1417
1418static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1419 .open = snd_intel8x0_capture2_open,
1420 .close = snd_intel8x0_capture2_close,
1421 .ioctl = snd_pcm_lib_ioctl,
1422 .hw_params = snd_intel8x0_hw_params,
1423 .hw_free = snd_intel8x0_hw_free,
1424 .prepare = snd_intel8x0_pcm_prepare,
1425 .trigger = snd_intel8x0_pcm_trigger,
1426 .pointer = snd_intel8x0_pcm_pointer,
1427};
1428
1429static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1430 .open = snd_intel8x0_spdif_open,
1431 .close = snd_intel8x0_spdif_close,
1432 .ioctl = snd_pcm_lib_ioctl,
1433 .hw_params = snd_intel8x0_hw_params,
1434 .hw_free = snd_intel8x0_hw_free,
1435 .prepare = snd_intel8x0_pcm_prepare,
1436 .trigger = snd_intel8x0_pcm_trigger,
1437 .pointer = snd_intel8x0_pcm_pointer,
1438};
1439
1440static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1441 .open = snd_intel8x0_playback_open,
1442 .close = snd_intel8x0_playback_close,
1443 .ioctl = snd_pcm_lib_ioctl,
1444 .hw_params = snd_intel8x0_hw_params,
1445 .hw_free = snd_intel8x0_hw_free,
1446 .prepare = snd_intel8x0_pcm_prepare,
1447 .trigger = snd_intel8x0_ali_trigger,
1448 .pointer = snd_intel8x0_pcm_pointer,
1449};
1450
1451static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1452 .open = snd_intel8x0_capture_open,
1453 .close = snd_intel8x0_capture_close,
1454 .ioctl = snd_pcm_lib_ioctl,
1455 .hw_params = snd_intel8x0_hw_params,
1456 .hw_free = snd_intel8x0_hw_free,
1457 .prepare = snd_intel8x0_pcm_prepare,
1458 .trigger = snd_intel8x0_ali_trigger,
1459 .pointer = snd_intel8x0_pcm_pointer,
1460};
1461
1462static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1463 .open = snd_intel8x0_mic_open,
1464 .close = snd_intel8x0_mic_close,
1465 .ioctl = snd_pcm_lib_ioctl,
1466 .hw_params = snd_intel8x0_hw_params,
1467 .hw_free = snd_intel8x0_hw_free,
1468 .prepare = snd_intel8x0_pcm_prepare,
1469 .trigger = snd_intel8x0_ali_trigger,
1470 .pointer = snd_intel8x0_pcm_pointer,
1471};
1472
1473static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1474 .open = snd_intel8x0_ali_ac97spdifout_open,
1475 .close = snd_intel8x0_ali_ac97spdifout_close,
1476 .ioctl = snd_pcm_lib_ioctl,
1477 .hw_params = snd_intel8x0_hw_params,
1478 .hw_free = snd_intel8x0_hw_free,
1479 .prepare = snd_intel8x0_pcm_prepare,
1480 .trigger = snd_intel8x0_ali_trigger,
1481 .pointer = snd_intel8x0_pcm_pointer,
1482};
1483
1484#if 0 // NYI
1485static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1486 .open = snd_intel8x0_ali_spdifin_open,
1487 .close = snd_intel8x0_ali_spdifin_close,
1488 .ioctl = snd_pcm_lib_ioctl,
1489 .hw_params = snd_intel8x0_hw_params,
1490 .hw_free = snd_intel8x0_hw_free,
1491 .prepare = snd_intel8x0_pcm_prepare,
1492 .trigger = snd_intel8x0_pcm_trigger,
1493 .pointer = snd_intel8x0_pcm_pointer,
1494};
1495
1496static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1497 .open = snd_intel8x0_ali_spdifout_open,
1498 .close = snd_intel8x0_ali_spdifout_close,
1499 .ioctl = snd_pcm_lib_ioctl,
1500 .hw_params = snd_intel8x0_hw_params,
1501 .hw_free = snd_intel8x0_hw_free,
1502 .prepare = snd_intel8x0_pcm_prepare,
1503 .trigger = snd_intel8x0_pcm_trigger,
1504 .pointer = snd_intel8x0_pcm_pointer,
1505};
1506#endif // NYI
1507
1508struct ich_pcm_table {
1509 char *suffix;
1510 struct snd_pcm_ops *playback_ops;
1511 struct snd_pcm_ops *capture_ops;
1512 size_t prealloc_size;
1513 size_t prealloc_max_size;
1514 int ac97_idx;
1515};
1516
1517static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1518 struct ich_pcm_table *rec)
1519{
1520 struct snd_pcm *pcm;
1521 int err;
1522 char name[32];
1523
1524 if (rec->suffix)
1525 sprintf(name, "Intel ICH - %s", rec->suffix);
1526 else
1527 strcpy(name, "Intel ICH");
1528 err = snd_pcm_new(chip->card, name, device,
1529 rec->playback_ops ? 1 : 0,
1530 rec->capture_ops ? 1 : 0, &pcm);
1531 if (err < 0)
1532 return err;
1533
1534 if (rec->playback_ops)
1535 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1536 if (rec->capture_ops)
1537 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1538
1539 pcm->private_data = chip;
1540 pcm->info_flags = 0;
1541 if (rec->suffix)
1542 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1543 else
1544 strcpy(pcm->name, chip->card->shortname);
1545 chip->pcm[device] = pcm;
1546
1547 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1548 snd_dma_pci_data(chip->pci),
1549 rec->prealloc_size, rec->prealloc_max_size);
1550
1551 if (rec->playback_ops &&
1552 rec->playback_ops->open == snd_intel8x0_playback_open) {
1553 struct snd_pcm_chmap *chmap;
1554 int chs = 2;
1555 if (chip->multi8)
1556 chs = 8;
1557 else if (chip->multi6)
1558 chs = 6;
1559 else if (chip->multi4)
1560 chs = 4;
1561 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1562 snd_pcm_alt_chmaps, chs, 0,
1563 &chmap);
1564 if (err < 0)
1565 return err;
1566 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1567 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1568 }
1569
1570 return 0;
1571}
1572
1573static struct ich_pcm_table intel_pcms[] = {
1574 {
1575 .playback_ops = &snd_intel8x0_playback_ops,
1576 .capture_ops = &snd_intel8x0_capture_ops,
1577 .prealloc_size = 64 * 1024,
1578 .prealloc_max_size = 128 * 1024,
1579 },
1580 {
1581 .suffix = "MIC ADC",
1582 .capture_ops = &snd_intel8x0_capture_mic_ops,
1583 .prealloc_size = 0,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = ICHD_MIC,
1586 },
1587 {
1588 .suffix = "MIC2 ADC",
1589 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1590 .prealloc_size = 0,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = ICHD_MIC2,
1593 },
1594 {
1595 .suffix = "ADC2",
1596 .capture_ops = &snd_intel8x0_capture2_ops,
1597 .prealloc_size = 0,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ICHD_PCM2IN,
1600 },
1601 {
1602 .suffix = "IEC958",
1603 .playback_ops = &snd_intel8x0_spdif_ops,
1604 .prealloc_size = 64 * 1024,
1605 .prealloc_max_size = 128 * 1024,
1606 .ac97_idx = ICHD_SPBAR,
1607 },
1608};
1609
1610static struct ich_pcm_table nforce_pcms[] = {
1611 {
1612 .playback_ops = &snd_intel8x0_playback_ops,
1613 .capture_ops = &snd_intel8x0_capture_ops,
1614 .prealloc_size = 64 * 1024,
1615 .prealloc_max_size = 128 * 1024,
1616 },
1617 {
1618 .suffix = "MIC ADC",
1619 .capture_ops = &snd_intel8x0_capture_mic_ops,
1620 .prealloc_size = 0,
1621 .prealloc_max_size = 128 * 1024,
1622 .ac97_idx = NVD_MIC,
1623 },
1624 {
1625 .suffix = "IEC958",
1626 .playback_ops = &snd_intel8x0_spdif_ops,
1627 .prealloc_size = 64 * 1024,
1628 .prealloc_max_size = 128 * 1024,
1629 .ac97_idx = NVD_SPBAR,
1630 },
1631};
1632
1633static struct ich_pcm_table ali_pcms[] = {
1634 {
1635 .playback_ops = &snd_intel8x0_ali_playback_ops,
1636 .capture_ops = &snd_intel8x0_ali_capture_ops,
1637 .prealloc_size = 64 * 1024,
1638 .prealloc_max_size = 128 * 1024,
1639 },
1640 {
1641 .suffix = "MIC ADC",
1642 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1643 .prealloc_size = 0,
1644 .prealloc_max_size = 128 * 1024,
1645 .ac97_idx = ALID_MIC,
1646 },
1647 {
1648 .suffix = "IEC958",
1649 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1650 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1651 .prealloc_size = 64 * 1024,
1652 .prealloc_max_size = 128 * 1024,
1653 .ac97_idx = ALID_AC97SPDIFOUT,
1654 },
1655#if 0 // NYI
1656 {
1657 .suffix = "HW IEC958",
1658 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1659 .prealloc_size = 64 * 1024,
1660 .prealloc_max_size = 128 * 1024,
1661 },
1662#endif
1663};
1664
1665static int snd_intel8x0_pcm(struct intel8x0 *chip)
1666{
1667 int i, tblsize, device, err;
1668 struct ich_pcm_table *tbl, *rec;
1669
1670 switch (chip->device_type) {
1671 case DEVICE_INTEL_ICH4:
1672 tbl = intel_pcms;
1673 tblsize = ARRAY_SIZE(intel_pcms);
1674 if (spdif_aclink)
1675 tblsize--;
1676 break;
1677 case DEVICE_NFORCE:
1678 tbl = nforce_pcms;
1679 tblsize = ARRAY_SIZE(nforce_pcms);
1680 if (spdif_aclink)
1681 tblsize--;
1682 break;
1683 case DEVICE_ALI:
1684 tbl = ali_pcms;
1685 tblsize = ARRAY_SIZE(ali_pcms);
1686 break;
1687 default:
1688 tbl = intel_pcms;
1689 tblsize = 2;
1690 break;
1691 }
1692
1693 device = 0;
1694 for (i = 0; i < tblsize; i++) {
1695 rec = tbl + i;
1696 if (i > 0 && rec->ac97_idx) {
1697 /* activate PCM only when associated AC'97 codec */
1698 if (! chip->ichd[rec->ac97_idx].pcm)
1699 continue;
1700 }
1701 err = snd_intel8x0_pcm1(chip, device, rec);
1702 if (err < 0)
1703 return err;
1704 device++;
1705 }
1706
1707 chip->pcm_devs = device;
1708 return 0;
1709}
1710
1711
1712/*
1713 * Mixer part
1714 */
1715
1716static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1717{
1718 struct intel8x0 *chip = bus->private_data;
1719 chip->ac97_bus = NULL;
1720}
1721
1722static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1723{
1724 struct intel8x0 *chip = ac97->private_data;
1725 chip->ac97[ac97->num] = NULL;
1726}
1727
1728static struct ac97_pcm ac97_pcm_defs[] = {
1729 /* front PCM */
1730 {
1731 .exclusive = 1,
1732 .r = { {
1733 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1734 (1 << AC97_SLOT_PCM_RIGHT) |
1735 (1 << AC97_SLOT_PCM_CENTER) |
1736 (1 << AC97_SLOT_PCM_SLEFT) |
1737 (1 << AC97_SLOT_PCM_SRIGHT) |
1738 (1 << AC97_SLOT_LFE)
1739 },
1740 {
1741 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1742 (1 << AC97_SLOT_PCM_RIGHT) |
1743 (1 << AC97_SLOT_PCM_LEFT_0) |
1744 (1 << AC97_SLOT_PCM_RIGHT_0)
1745 }
1746 }
1747 },
1748 /* PCM IN #1 */
1749 {
1750 .stream = 1,
1751 .exclusive = 1,
1752 .r = { {
1753 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1754 (1 << AC97_SLOT_PCM_RIGHT)
1755 }
1756 }
1757 },
1758 /* MIC IN #1 */
1759 {
1760 .stream = 1,
1761 .exclusive = 1,
1762 .r = { {
1763 .slots = (1 << AC97_SLOT_MIC)
1764 }
1765 }
1766 },
1767 /* S/PDIF PCM */
1768 {
1769 .exclusive = 1,
1770 .spdif = 1,
1771 .r = { {
1772 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1773 (1 << AC97_SLOT_SPDIF_RIGHT2)
1774 }
1775 }
1776 },
1777 /* PCM IN #2 */
1778 {
1779 .stream = 1,
1780 .exclusive = 1,
1781 .r = { {
1782 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1783 (1 << AC97_SLOT_PCM_RIGHT)
1784 }
1785 }
1786 },
1787 /* MIC IN #2 */
1788 {
1789 .stream = 1,
1790 .exclusive = 1,
1791 .r = { {
1792 .slots = (1 << AC97_SLOT_MIC)
1793 }
1794 }
1795 },
1796};
1797
1798static const struct ac97_quirk ac97_quirks[] = {
1799 {
1800 .subvendor = 0x0e11,
1801 .subdevice = 0x000e,
1802 .name = "Compaq Deskpro EN", /* AD1885 */
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x0e11,
1807 .subdevice = 0x008a,
1808 .name = "Compaq Evo W4000", /* AD1885 */
1809 .type = AC97_TUNE_HP_ONLY
1810 },
1811 {
1812 .subvendor = 0x0e11,
1813 .subdevice = 0x00b8,
1814 .name = "Compaq Evo D510C",
1815 .type = AC97_TUNE_HP_ONLY
1816 },
1817 {
1818 .subvendor = 0x0e11,
1819 .subdevice = 0x0860,
1820 .name = "HP/Compaq nx7010",
1821 .type = AC97_TUNE_MUTE_LED
1822 },
1823 {
1824 .subvendor = 0x1014,
1825 .subdevice = 0x0534,
1826 .name = "ThinkPad X31",
1827 .type = AC97_TUNE_INV_EAPD
1828 },
1829 {
1830 .subvendor = 0x1014,
1831 .subdevice = 0x1f00,
1832 .name = "MS-9128",
1833 .type = AC97_TUNE_ALC_JACK
1834 },
1835 {
1836 .subvendor = 0x1014,
1837 .subdevice = 0x0267,
1838 .name = "IBM NetVista A30p", /* AD1981B */
1839 .type = AC97_TUNE_HP_ONLY
1840 },
1841 {
1842 .subvendor = 0x1025,
1843 .subdevice = 0x0082,
1844 .name = "Acer Travelmate 2310",
1845 .type = AC97_TUNE_HP_ONLY
1846 },
1847 {
1848 .subvendor = 0x1025,
1849 .subdevice = 0x0083,
1850 .name = "Acer Aspire 3003LCi",
1851 .type = AC97_TUNE_HP_ONLY
1852 },
1853 {
1854 .subvendor = 0x1028,
1855 .subdevice = 0x00d8,
1856 .name = "Dell Precision 530", /* AD1885 */
1857 .type = AC97_TUNE_HP_ONLY
1858 },
1859 {
1860 .subvendor = 0x1028,
1861 .subdevice = 0x010d,
1862 .name = "Dell", /* which model? AD1885 */
1863 .type = AC97_TUNE_HP_ONLY
1864 },
1865 {
1866 .subvendor = 0x1028,
1867 .subdevice = 0x0126,
1868 .name = "Dell Optiplex GX260", /* AD1981A */
1869 .type = AC97_TUNE_HP_ONLY
1870 },
1871 {
1872 .subvendor = 0x1028,
1873 .subdevice = 0x012c,
1874 .name = "Dell Precision 650", /* AD1981A */
1875 .type = AC97_TUNE_HP_ONLY
1876 },
1877 {
1878 .subvendor = 0x1028,
1879 .subdevice = 0x012d,
1880 .name = "Dell Precision 450", /* AD1981B*/
1881 .type = AC97_TUNE_HP_ONLY
1882 },
1883 {
1884 .subvendor = 0x1028,
1885 .subdevice = 0x0147,
1886 .name = "Dell", /* which model? AD1981B*/
1887 .type = AC97_TUNE_HP_ONLY
1888 },
1889 {
1890 .subvendor = 0x1028,
1891 .subdevice = 0x0151,
1892 .name = "Dell Optiplex GX270", /* AD1981B */
1893 .type = AC97_TUNE_HP_ONLY
1894 },
1895 {
1896 .subvendor = 0x1028,
1897 .subdevice = 0x014e,
1898 .name = "Dell D800", /* STAC9750/51 */
1899 .type = AC97_TUNE_HP_ONLY
1900 },
1901 {
1902 .subvendor = 0x1028,
1903 .subdevice = 0x0163,
1904 .name = "Dell Unknown", /* STAC9750/51 */
1905 .type = AC97_TUNE_HP_ONLY
1906 },
1907 {
1908 .subvendor = 0x1028,
1909 .subdevice = 0x016a,
1910 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1911 .type = AC97_TUNE_HP_ONLY
1912 },
1913 {
1914 .subvendor = 0x1028,
1915 .subdevice = 0x0182,
1916 .name = "Dell Latitude D610", /* STAC9750/51 */
1917 .type = AC97_TUNE_HP_ONLY
1918 },
1919 {
1920 .subvendor = 0x1028,
1921 .subdevice = 0x0186,
1922 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1923 .type = AC97_TUNE_HP_MUTE_LED
1924 },
1925 {
1926 .subvendor = 0x1028,
1927 .subdevice = 0x0188,
1928 .name = "Dell Inspiron 6000",
1929 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1930 },
1931 {
1932 .subvendor = 0x1028,
1933 .subdevice = 0x0189,
1934 .name = "Dell Inspiron 9300",
1935 .type = AC97_TUNE_HP_MUTE_LED
1936 },
1937 {
1938 .subvendor = 0x1028,
1939 .subdevice = 0x0191,
1940 .name = "Dell Inspiron 8600",
1941 .type = AC97_TUNE_HP_ONLY
1942 },
1943 {
1944 .subvendor = 0x103c,
1945 .subdevice = 0x006d,
1946 .name = "HP zv5000",
1947 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1948 },
1949 { /* FIXME: which codec? */
1950 .subvendor = 0x103c,
1951 .subdevice = 0x00c3,
1952 .name = "HP xw6000",
1953 .type = AC97_TUNE_HP_ONLY
1954 },
1955 {
1956 .subvendor = 0x103c,
1957 .subdevice = 0x088c,
1958 .name = "HP nc8000",
1959 .type = AC97_TUNE_HP_MUTE_LED
1960 },
1961 {
1962 .subvendor = 0x103c,
1963 .subdevice = 0x0890,
1964 .name = "HP nc6000",
1965 .type = AC97_TUNE_MUTE_LED
1966 },
1967 {
1968 .subvendor = 0x103c,
1969 .subdevice = 0x129d,
1970 .name = "HP xw8000",
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
1974 .subvendor = 0x103c,
1975 .subdevice = 0x0938,
1976 .name = "HP nc4200",
1977 .type = AC97_TUNE_HP_MUTE_LED
1978 },
1979 {
1980 .subvendor = 0x103c,
1981 .subdevice = 0x099c,
1982 .name = "HP nx6110/nc6120",
1983 .type = AC97_TUNE_HP_MUTE_LED
1984 },
1985 {
1986 .subvendor = 0x103c,
1987 .subdevice = 0x0944,
1988 .name = "HP nc6220",
1989 .type = AC97_TUNE_HP_MUTE_LED
1990 },
1991 {
1992 .subvendor = 0x103c,
1993 .subdevice = 0x0934,
1994 .name = "HP nc8220",
1995 .type = AC97_TUNE_HP_MUTE_LED
1996 },
1997 {
1998 .subvendor = 0x103c,
1999 .subdevice = 0x12f1,
2000 .name = "HP xw8200", /* AD1981B*/
2001 .type = AC97_TUNE_HP_ONLY
2002 },
2003 {
2004 .subvendor = 0x103c,
2005 .subdevice = 0x12f2,
2006 .name = "HP xw6200",
2007 .type = AC97_TUNE_HP_ONLY
2008 },
2009 {
2010 .subvendor = 0x103c,
2011 .subdevice = 0x3008,
2012 .name = "HP xw4200", /* AD1981B*/
2013 .type = AC97_TUNE_HP_ONLY
2014 },
2015 {
2016 .subvendor = 0x104d,
2017 .subdevice = 0x8144,
2018 .name = "Sony",
2019 .type = AC97_TUNE_INV_EAPD
2020 },
2021 {
2022 .subvendor = 0x104d,
2023 .subdevice = 0x8197,
2024 .name = "Sony S1XP",
2025 .type = AC97_TUNE_INV_EAPD
2026 },
2027 {
2028 .subvendor = 0x104d,
2029 .subdevice = 0x81c0,
2030 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2031 .type = AC97_TUNE_INV_EAPD
2032 },
2033 {
2034 .subvendor = 0x104d,
2035 .subdevice = 0x81c5,
2036 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2037 .type = AC97_TUNE_INV_EAPD
2038 },
2039 {
2040 .subvendor = 0x1043,
2041 .subdevice = 0x80f3,
2042 .name = "ASUS ICH5/AD1985",
2043 .type = AC97_TUNE_AD_SHARING
2044 },
2045 {
2046 .subvendor = 0x10cf,
2047 .subdevice = 0x11c3,
2048 .name = "Fujitsu-Siemens E4010",
2049 .type = AC97_TUNE_HP_ONLY
2050 },
2051 {
2052 .subvendor = 0x10cf,
2053 .subdevice = 0x1225,
2054 .name = "Fujitsu-Siemens T3010",
2055 .type = AC97_TUNE_HP_ONLY
2056 },
2057 {
2058 .subvendor = 0x10cf,
2059 .subdevice = 0x1253,
2060 .name = "Fujitsu S6210", /* STAC9750/51 */
2061 .type = AC97_TUNE_HP_ONLY
2062 },
2063 {
2064 .subvendor = 0x10cf,
2065 .subdevice = 0x127d,
2066 .name = "Fujitsu Lifebook P7010",
2067 .type = AC97_TUNE_HP_ONLY
2068 },
2069 {
2070 .subvendor = 0x10cf,
2071 .subdevice = 0x127e,
2072 .name = "Fujitsu Lifebook C1211D",
2073 .type = AC97_TUNE_HP_ONLY
2074 },
2075 {
2076 .subvendor = 0x10cf,
2077 .subdevice = 0x12ec,
2078 .name = "Fujitsu-Siemens 4010",
2079 .type = AC97_TUNE_HP_ONLY
2080 },
2081 {
2082 .subvendor = 0x10cf,
2083 .subdevice = 0x12f2,
2084 .name = "Fujitsu-Siemens Celsius H320",
2085 .type = AC97_TUNE_SWAP_HP
2086 },
2087 {
2088 .subvendor = 0x10f1,
2089 .subdevice = 0x2665,
2090 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2091 .type = AC97_TUNE_HP_ONLY
2092 },
2093 {
2094 .subvendor = 0x10f1,
2095 .subdevice = 0x2885,
2096 .name = "AMD64 Mobo", /* ALC650 */
2097 .type = AC97_TUNE_HP_ONLY
2098 },
2099 {
2100 .subvendor = 0x10f1,
2101 .subdevice = 0x2895,
2102 .name = "Tyan Thunder K8WE",
2103 .type = AC97_TUNE_HP_ONLY
2104 },
2105 {
2106 .subvendor = 0x10f7,
2107 .subdevice = 0x834c,
2108 .name = "Panasonic CF-R4",
2109 .type = AC97_TUNE_HP_ONLY,
2110 },
2111 {
2112 .subvendor = 0x110a,
2113 .subdevice = 0x0056,
2114 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2115 .type = AC97_TUNE_HP_ONLY
2116 },
2117 {
2118 .subvendor = 0x11d4,
2119 .subdevice = 0x5375,
2120 .name = "ADI AD1985 (discrete)",
2121 .type = AC97_TUNE_HP_ONLY
2122 },
2123 {
2124 .subvendor = 0x1462,
2125 .subdevice = 0x5470,
2126 .name = "MSI P4 ATX 645 Ultra",
2127 .type = AC97_TUNE_HP_ONLY
2128 },
2129 {
2130 .subvendor = 0x161f,
2131 .subdevice = 0x202f,
2132 .name = "Gateway M520",
2133 .type = AC97_TUNE_INV_EAPD
2134 },
2135 {
2136 .subvendor = 0x161f,
2137 .subdevice = 0x203a,
2138 .name = "Gateway 4525GZ", /* AD1981B */
2139 .type = AC97_TUNE_INV_EAPD
2140 },
2141 {
2142 .subvendor = 0x1734,
2143 .subdevice = 0x0088,
2144 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2145 .type = AC97_TUNE_HP_ONLY
2146 },
2147 {
2148 .subvendor = 0x8086,
2149 .subdevice = 0x2000,
2150 .mask = 0xfff0,
2151 .name = "Intel ICH5/AD1985",
2152 .type = AC97_TUNE_AD_SHARING
2153 },
2154 {
2155 .subvendor = 0x8086,
2156 .subdevice = 0x4000,
2157 .mask = 0xfff0,
2158 .name = "Intel ICH5/AD1985",
2159 .type = AC97_TUNE_AD_SHARING
2160 },
2161 {
2162 .subvendor = 0x8086,
2163 .subdevice = 0x4856,
2164 .name = "Intel D845WN (82801BA)",
2165 .type = AC97_TUNE_SWAP_HP
2166 },
2167 {
2168 .subvendor = 0x8086,
2169 .subdevice = 0x4d44,
2170 .name = "Intel D850EMV2", /* AD1885 */
2171 .type = AC97_TUNE_HP_ONLY
2172 },
2173 {
2174 .subvendor = 0x8086,
2175 .subdevice = 0x4d56,
2176 .name = "Intel ICH/AD1885",
2177 .type = AC97_TUNE_HP_ONLY
2178 },
2179 {
2180 .subvendor = 0x8086,
2181 .subdevice = 0x6000,
2182 .mask = 0xfff0,
2183 .name = "Intel ICH5/AD1985",
2184 .type = AC97_TUNE_AD_SHARING
2185 },
2186 {
2187 .subvendor = 0x8086,
2188 .subdevice = 0xe000,
2189 .mask = 0xfff0,
2190 .name = "Intel ICH5/AD1985",
2191 .type = AC97_TUNE_AD_SHARING
2192 },
2193#if 0 /* FIXME: this seems wrong on most boards */
2194 {
2195 .subvendor = 0x8086,
2196 .subdevice = 0xa000,
2197 .mask = 0xfff0,
2198 .name = "Intel ICH5/AD1985",
2199 .type = AC97_TUNE_HP_ONLY
2200 },
2201#endif
2202 { } /* terminator */
2203};
2204
2205static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2206 const char *quirk_override)
2207{
2208 struct snd_ac97_bus *pbus;
2209 struct snd_ac97_template ac97;
2210 int err;
2211 unsigned int i, codecs;
2212 unsigned int glob_sta = 0;
2213 struct snd_ac97_bus_ops *ops;
2214 static struct snd_ac97_bus_ops standard_bus_ops = {
2215 .write = snd_intel8x0_codec_write,
2216 .read = snd_intel8x0_codec_read,
2217 };
2218 static struct snd_ac97_bus_ops ali_bus_ops = {
2219 .write = snd_intel8x0_ali_codec_write,
2220 .read = snd_intel8x0_ali_codec_read,
2221 };
2222
2223 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2224 if (!spdif_aclink) {
2225 switch (chip->device_type) {
2226 case DEVICE_NFORCE:
2227 chip->spdif_idx = NVD_SPBAR;
2228 break;
2229 case DEVICE_ALI:
2230 chip->spdif_idx = ALID_AC97SPDIFOUT;
2231 break;
2232 case DEVICE_INTEL_ICH4:
2233 chip->spdif_idx = ICHD_SPBAR;
2234 break;
2235 }
2236 }
2237
2238 chip->in_ac97_init = 1;
2239
2240 memset(&ac97, 0, sizeof(ac97));
2241 ac97.private_data = chip;
2242 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2243 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2244 if (chip->xbox)
2245 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2246 if (chip->device_type != DEVICE_ALI) {
2247 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2248 ops = &standard_bus_ops;
2249 chip->in_sdin_init = 1;
2250 codecs = 0;
2251 for (i = 0; i < chip->max_codecs; i++) {
2252 if (! (glob_sta & chip->codec_bit[i]))
2253 continue;
2254 if (chip->device_type == DEVICE_INTEL_ICH4) {
2255 snd_intel8x0_codec_read_test(chip, codecs);
2256 chip->ac97_sdin[codecs] =
2257 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2258 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2259 chip->ac97_sdin[codecs] = 0;
2260 } else
2261 chip->ac97_sdin[codecs] = i;
2262 codecs++;
2263 }
2264 chip->in_sdin_init = 0;
2265 if (! codecs)
2266 codecs = 1;
2267 } else {
2268 ops = &ali_bus_ops;
2269 codecs = 1;
2270 /* detect the secondary codec */
2271 for (i = 0; i < 100; i++) {
2272 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2273 if (reg & 0x40) {
2274 codecs = 2;
2275 break;
2276 }
2277 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2278 udelay(1);
2279 }
2280 }
2281 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2282 goto __err;
2283 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2284 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2285 pbus->clock = ac97_clock;
2286 /* FIXME: my test board doesn't work well with VRA... */
2287 if (chip->device_type == DEVICE_ALI)
2288 pbus->no_vra = 1;
2289 else
2290 pbus->dra = 1;
2291 chip->ac97_bus = pbus;
2292 chip->ncodecs = codecs;
2293
2294 ac97.pci = chip->pci;
2295 for (i = 0; i < codecs; i++) {
2296 ac97.num = i;
2297 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2298 if (err != -EACCES)
2299 dev_err(chip->card->dev,
2300 "Unable to initialize codec #%d\n", i);
2301 if (i == 0)
2302 goto __err;
2303 }
2304 }
2305 /* tune up the primary codec */
2306 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2307 /* enable separate SDINs for ICH4 */
2308 if (chip->device_type == DEVICE_INTEL_ICH4)
2309 pbus->isdin = 1;
2310 /* find the available PCM streams */
2311 i = ARRAY_SIZE(ac97_pcm_defs);
2312 if (chip->device_type != DEVICE_INTEL_ICH4)
2313 i -= 2; /* do not allocate PCM2IN and MIC2 */
2314 if (chip->spdif_idx < 0)
2315 i--; /* do not allocate S/PDIF */
2316 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2317 if (err < 0)
2318 goto __err;
2319 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2320 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2321 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2322 if (chip->spdif_idx >= 0)
2323 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2324 if (chip->device_type == DEVICE_INTEL_ICH4) {
2325 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2326 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2327 }
2328 /* enable separate SDINs for ICH4 */
2329 if (chip->device_type == DEVICE_INTEL_ICH4) {
2330 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2331 u8 tmp = igetbyte(chip, ICHREG(SDM));
2332 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2333 if (pcm) {
2334 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2335 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2336 for (i = 1; i < 4; i++) {
2337 if (pcm->r[0].codec[i]) {
2338 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2339 break;
2340 }
2341 }
2342 } else {
2343 tmp &= ~ICH_SE; /* steer disable */
2344 }
2345 iputbyte(chip, ICHREG(SDM), tmp);
2346 }
2347 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2348 chip->multi4 = 1;
2349 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2350 chip->multi6 = 1;
2351 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2352 chip->multi8 = 1;
2353 }
2354 }
2355 if (pbus->pcms[0].r[1].rslots[0]) {
2356 chip->dra = 1;
2357 }
2358 if (chip->device_type == DEVICE_INTEL_ICH4) {
2359 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2360 chip->smp20bit = 1;
2361 }
2362 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2363 /* 48kHz only */
2364 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2365 }
2366 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2367 /* use slot 10/11 for SPDIF */
2368 u32 val;
2369 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2370 val |= ICH_PCM_SPDIF_1011;
2371 iputdword(chip, ICHREG(GLOB_CNT), val);
2372 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2373 }
2374 chip->in_ac97_init = 0;
2375 return 0;
2376
2377 __err:
2378 /* clear the cold-reset bit for the next chance */
2379 if (chip->device_type != DEVICE_ALI)
2380 iputdword(chip, ICHREG(GLOB_CNT),
2381 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2382 return err;
2383}
2384
2385
2386/*
2387 *
2388 */
2389
2390static void do_ali_reset(struct intel8x0 *chip)
2391{
2392 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2393 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2394 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2395 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2396 iputdword(chip, ICHREG(ALI_INTERFACECR),
2397 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2398 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2399 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2400}
2401
2402#ifdef CONFIG_SND_AC97_POWER_SAVE
2403static struct snd_pci_quirk ich_chip_reset_mode[] = {
2404 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2405 { } /* end */
2406};
2407
2408static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2409{
2410 unsigned int cnt;
2411 /* ACLink on, 2 channels */
2412
2413 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2414 return -EIO;
2415
2416 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2417 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2418
2419 /* do cold reset - the full ac97 powerdown may leave the controller
2420 * in a warm state but actually it cannot communicate with the codec.
2421 */
2422 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2423 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2424 udelay(10);
2425 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2426 msleep(1);
2427 return 0;
2428}
2429#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2430 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2431#else
2432#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2433#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2434#endif
2435
2436static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2437{
2438 unsigned long end_time;
2439 unsigned int cnt;
2440 /* ACLink on, 2 channels */
2441 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2442 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2443 /* finish cold or do warm reset */
2444 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2445 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2446 end_time = (jiffies + (HZ / 4)) + 1;
2447 do {
2448 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2449 return 0;
2450 schedule_timeout_uninterruptible(1);
2451 } while (time_after_eq(end_time, jiffies));
2452 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2453 igetdword(chip, ICHREG(GLOB_CNT)));
2454 return -EIO;
2455}
2456
2457static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2458{
2459 unsigned long end_time;
2460 unsigned int status, nstatus;
2461 unsigned int cnt;
2462 int err;
2463
2464 /* put logic to right state */
2465 /* first clear status bits */
2466 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2467 if (chip->device_type == DEVICE_NFORCE)
2468 status |= ICH_NVSPINT;
2469 cnt = igetdword(chip, ICHREG(GLOB_STA));
2470 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2471
2472 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2473 err = snd_intel8x0_ich_chip_cold_reset(chip);
2474 else
2475 err = snd_intel8x0_ich_chip_reset(chip);
2476 if (err < 0)
2477 return err;
2478
2479 if (probing) {
2480 /* wait for any codec ready status.
2481 * Once it becomes ready it should remain ready
2482 * as long as we do not disable the ac97 link.
2483 */
2484 end_time = jiffies + HZ;
2485 do {
2486 status = igetdword(chip, ICHREG(GLOB_STA)) &
2487 chip->codec_isr_bits;
2488 if (status)
2489 break;
2490 schedule_timeout_uninterruptible(1);
2491 } while (time_after_eq(end_time, jiffies));
2492 if (! status) {
2493 /* no codec is found */
2494 dev_err(chip->card->dev,
2495 "codec_ready: codec is not ready [0x%x]\n",
2496 igetdword(chip, ICHREG(GLOB_STA)));
2497 return -EIO;
2498 }
2499
2500 /* wait for other codecs ready status. */
2501 end_time = jiffies + HZ / 4;
2502 while (status != chip->codec_isr_bits &&
2503 time_after_eq(end_time, jiffies)) {
2504 schedule_timeout_uninterruptible(1);
2505 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2506 chip->codec_isr_bits;
2507 }
2508
2509 } else {
2510 /* resume phase */
2511 int i;
2512 status = 0;
2513 for (i = 0; i < chip->ncodecs; i++)
2514 if (chip->ac97[i])
2515 status |= chip->codec_bit[chip->ac97_sdin[i]];
2516 /* wait until all the probed codecs are ready */
2517 end_time = jiffies + HZ;
2518 do {
2519 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2520 chip->codec_isr_bits;
2521 if (status == nstatus)
2522 break;
2523 schedule_timeout_uninterruptible(1);
2524 } while (time_after_eq(end_time, jiffies));
2525 }
2526
2527 if (chip->device_type == DEVICE_SIS) {
2528 /* unmute the output on SIS7012 */
2529 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2530 }
2531 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2532 /* enable SPDIF interrupt */
2533 unsigned int val;
2534 pci_read_config_dword(chip->pci, 0x4c, &val);
2535 val |= 0x1000000;
2536 pci_write_config_dword(chip->pci, 0x4c, val);
2537 }
2538 return 0;
2539}
2540
2541static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2542{
2543 u32 reg;
2544 int i = 0;
2545
2546 reg = igetdword(chip, ICHREG(ALI_SCR));
2547 if ((reg & 2) == 0) /* Cold required */
2548 reg |= 2;
2549 else
2550 reg |= 1; /* Warm */
2551 reg &= ~0x80000000; /* ACLink on */
2552 iputdword(chip, ICHREG(ALI_SCR), reg);
2553
2554 for (i = 0; i < HZ / 2; i++) {
2555 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2556 goto __ok;
2557 schedule_timeout_uninterruptible(1);
2558 }
2559 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2560 if (probing)
2561 return -EIO;
2562
2563 __ok:
2564 for (i = 0; i < HZ / 2; i++) {
2565 reg = igetdword(chip, ICHREG(ALI_RTSR));
2566 if (reg & 0x80) /* primary codec */
2567 break;
2568 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2569 schedule_timeout_uninterruptible(1);
2570 }
2571
2572 do_ali_reset(chip);
2573 return 0;
2574}
2575
2576static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2577{
2578 unsigned int i, timeout;
2579 int err;
2580
2581 if (chip->device_type != DEVICE_ALI) {
2582 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2583 return err;
2584 iagetword(chip, 0); /* clear semaphore flag */
2585 } else {
2586 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2587 return err;
2588 }
2589
2590 /* disable interrupts */
2591 for (i = 0; i < chip->bdbars_count; i++)
2592 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2593 /* reset channels */
2594 for (i = 0; i < chip->bdbars_count; i++)
2595 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2596 for (i = 0; i < chip->bdbars_count; i++) {
2597 timeout = 100000;
2598 while (--timeout != 0) {
2599 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2600 break;
2601 }
2602 if (timeout == 0)
2603 dev_err(chip->card->dev, "reset of registers failed?\n");
2604 }
2605 /* initialize Buffer Descriptor Lists */
2606 for (i = 0; i < chip->bdbars_count; i++)
2607 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2608 chip->ichd[i].bdbar_addr);
2609 return 0;
2610}
2611
2612static int snd_intel8x0_free(struct intel8x0 *chip)
2613{
2614 unsigned int i;
2615
2616 if (chip->irq < 0)
2617 goto __hw_end;
2618 /* disable interrupts */
2619 for (i = 0; i < chip->bdbars_count; i++)
2620 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2621 /* reset channels */
2622 for (i = 0; i < chip->bdbars_count; i++)
2623 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2624 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2625 /* stop the spdif interrupt */
2626 unsigned int val;
2627 pci_read_config_dword(chip->pci, 0x4c, &val);
2628 val &= ~0x1000000;
2629 pci_write_config_dword(chip->pci, 0x4c, val);
2630 }
2631 /* --- */
2632
2633 __hw_end:
2634 if (chip->irq >= 0)
2635 free_irq(chip->irq, chip);
2636 if (chip->bdbars.area) {
2637 if (chip->fix_nocache)
2638 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2639 snd_dma_free_pages(&chip->bdbars);
2640 }
2641 if (chip->addr)
2642 pci_iounmap(chip->pci, chip->addr);
2643 if (chip->bmaddr)
2644 pci_iounmap(chip->pci, chip->bmaddr);
2645 pci_release_regions(chip->pci);
2646 pci_disable_device(chip->pci);
2647 kfree(chip);
2648 return 0;
2649}
2650
2651#ifdef CONFIG_PM_SLEEP
2652/*
2653 * power management
2654 */
2655static int intel8x0_suspend(struct device *dev)
2656{
2657 struct snd_card *card = dev_get_drvdata(dev);
2658 struct intel8x0 *chip = card->private_data;
2659 int i;
2660
2661 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2662 for (i = 0; i < chip->pcm_devs; i++)
2663 snd_pcm_suspend_all(chip->pcm[i]);
2664 /* clear nocache */
2665 if (chip->fix_nocache) {
2666 for (i = 0; i < chip->bdbars_count; i++) {
2667 struct ichdev *ichdev = &chip->ichd[i];
2668 if (ichdev->substream && ichdev->page_attr_changed) {
2669 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2670 if (runtime->dma_area)
2671 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2672 }
2673 }
2674 }
2675 for (i = 0; i < chip->ncodecs; i++)
2676 snd_ac97_suspend(chip->ac97[i]);
2677 if (chip->device_type == DEVICE_INTEL_ICH4)
2678 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2679
2680 if (chip->irq >= 0) {
2681 free_irq(chip->irq, chip);
2682 chip->irq = -1;
2683 }
2684 return 0;
2685}
2686
2687static int intel8x0_resume(struct device *dev)
2688{
2689 struct pci_dev *pci = to_pci_dev(dev);
2690 struct snd_card *card = dev_get_drvdata(dev);
2691 struct intel8x0 *chip = card->private_data;
2692 int i;
2693
2694 snd_intel8x0_chip_init(chip, 0);
2695 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2696 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2697 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2698 pci->irq);
2699 snd_card_disconnect(card);
2700 return -EIO;
2701 }
2702 chip->irq = pci->irq;
2703 synchronize_irq(chip->irq);
2704
2705 /* re-initialize mixer stuff */
2706 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2707 /* enable separate SDINs for ICH4 */
2708 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2709 /* use slot 10/11 for SPDIF */
2710 iputdword(chip, ICHREG(GLOB_CNT),
2711 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2712 ICH_PCM_SPDIF_1011);
2713 }
2714
2715 /* refill nocache */
2716 if (chip->fix_nocache)
2717 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2718
2719 for (i = 0; i < chip->ncodecs; i++)
2720 snd_ac97_resume(chip->ac97[i]);
2721
2722 /* refill nocache */
2723 if (chip->fix_nocache) {
2724 for (i = 0; i < chip->bdbars_count; i++) {
2725 struct ichdev *ichdev = &chip->ichd[i];
2726 if (ichdev->substream && ichdev->page_attr_changed) {
2727 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2728 if (runtime->dma_area)
2729 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2730 }
2731 }
2732 }
2733
2734 /* resume status */
2735 for (i = 0; i < chip->bdbars_count; i++) {
2736 struct ichdev *ichdev = &chip->ichd[i];
2737 unsigned long port = ichdev->reg_offset;
2738 if (! ichdev->substream || ! ichdev->suspended)
2739 continue;
2740 if (ichdev->ichd == ICHD_PCMOUT)
2741 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2742 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2743 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2744 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2745 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2746 }
2747
2748 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2749 return 0;
2750}
2751
2752static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2753#define INTEL8X0_PM_OPS &intel8x0_pm
2754#else
2755#define INTEL8X0_PM_OPS NULL
2756#endif /* CONFIG_PM_SLEEP */
2757
2758#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2759
2760static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2761{
2762 struct snd_pcm_substream *subs;
2763 struct ichdev *ichdev;
2764 unsigned long port;
2765 unsigned long pos, pos1, t;
2766 int civ, timeout = 1000, attempt = 1;
2767 ktime_t start_time, stop_time;
2768
2769 if (chip->ac97_bus->clock != 48000)
2770 return; /* specified in module option */
2771
2772 __again:
2773 subs = chip->pcm[0]->streams[0].substream;
2774 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2775 dev_warn(chip->card->dev,
2776 "no playback buffer allocated - aborting measure ac97 clock\n");
2777 return;
2778 }
2779 ichdev = &chip->ichd[ICHD_PCMOUT];
2780 ichdev->physbuf = subs->dma_buffer.addr;
2781 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2782 ichdev->substream = NULL; /* don't process interrupts */
2783
2784 /* set rate */
2785 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2786 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2787 chip->ac97_bus->clock);
2788 return;
2789 }
2790 snd_intel8x0_setup_periods(chip, ichdev);
2791 port = ichdev->reg_offset;
2792 spin_lock_irq(&chip->reg_lock);
2793 chip->in_measurement = 1;
2794 /* trigger */
2795 if (chip->device_type != DEVICE_ALI)
2796 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2797 else {
2798 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2799 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2800 }
2801 start_time = ktime_get();
2802 spin_unlock_irq(&chip->reg_lock);
2803 msleep(50);
2804 spin_lock_irq(&chip->reg_lock);
2805 /* check the position */
2806 do {
2807 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2808 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2809 if (pos1 == 0) {
2810 udelay(10);
2811 continue;
2812 }
2813 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2814 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2815 break;
2816 } while (timeout--);
2817 if (pos1 == 0) { /* oops, this value is not reliable */
2818 pos = 0;
2819 } else {
2820 pos = ichdev->fragsize1;
2821 pos -= pos1 << ichdev->pos_shift;
2822 pos += ichdev->position;
2823 }
2824 chip->in_measurement = 0;
2825 stop_time = ktime_get();
2826 /* stop */
2827 if (chip->device_type == DEVICE_ALI) {
2828 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2829 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2830 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2831 ;
2832 } else {
2833 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2834 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2835 ;
2836 }
2837 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2838 spin_unlock_irq(&chip->reg_lock);
2839
2840 if (pos == 0) {
2841 dev_err(chip->card->dev,
2842 "measure - unreliable DMA position..\n");
2843 __retry:
2844 if (attempt < 3) {
2845 msleep(300);
2846 attempt++;
2847 goto __again;
2848 }
2849 goto __end;
2850 }
2851
2852 pos /= 4;
2853 t = ktime_us_delta(stop_time, start_time);
2854 dev_info(chip->card->dev,
2855 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2856 if (t == 0) {
2857 dev_err(chip->card->dev, "?? calculation error..\n");
2858 goto __retry;
2859 }
2860 pos *= 1000;
2861 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2862 if (pos < 40000 || pos >= 60000) {
2863 /* abnormal value. hw problem? */
2864 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2865 goto __retry;
2866 } else if (pos > 40500 && pos < 41500)
2867 /* first exception - 41000Hz reference clock */
2868 chip->ac97_bus->clock = 41000;
2869 else if (pos > 43600 && pos < 44600)
2870 /* second exception - 44100HZ reference clock */
2871 chip->ac97_bus->clock = 44100;
2872 else if (pos < 47500 || pos > 48500)
2873 /* not 48000Hz, tuning the clock.. */
2874 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2875 __end:
2876 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2877 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2878}
2879
2880static struct snd_pci_quirk intel8x0_clock_list[] = {
2881 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2882 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2883 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2884 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2885 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2886 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2887 { } /* terminator */
2888};
2889
2890static int intel8x0_in_clock_list(struct intel8x0 *chip)
2891{
2892 struct pci_dev *pci = chip->pci;
2893 const struct snd_pci_quirk *wl;
2894
2895 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2896 if (!wl)
2897 return 0;
2898 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2899 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2900 chip->ac97_bus->clock = wl->value;
2901 return 1;
2902}
2903
2904static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2905 struct snd_info_buffer *buffer)
2906{
2907 struct intel8x0 *chip = entry->private_data;
2908 unsigned int tmp;
2909
2910 snd_iprintf(buffer, "Intel8x0\n\n");
2911 if (chip->device_type == DEVICE_ALI)
2912 return;
2913 tmp = igetdword(chip, ICHREG(GLOB_STA));
2914 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2915 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2916 if (chip->device_type == DEVICE_INTEL_ICH4)
2917 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2918 snd_iprintf(buffer, "AC'97 codecs ready :");
2919 if (tmp & chip->codec_isr_bits) {
2920 int i;
2921 static const char *codecs[3] = {
2922 "primary", "secondary", "tertiary"
2923 };
2924 for (i = 0; i < chip->max_codecs; i++)
2925 if (tmp & chip->codec_bit[i])
2926 snd_iprintf(buffer, " %s", codecs[i]);
2927 } else
2928 snd_iprintf(buffer, " none");
2929 snd_iprintf(buffer, "\n");
2930 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2931 chip->device_type == DEVICE_SIS)
2932 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2933 chip->ac97_sdin[0],
2934 chip->ac97_sdin[1],
2935 chip->ac97_sdin[2]);
2936}
2937
2938static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2939{
2940 struct snd_info_entry *entry;
2941
2942 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2943 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2944}
2945
2946static int snd_intel8x0_dev_free(struct snd_device *device)
2947{
2948 struct intel8x0 *chip = device->device_data;
2949 return snd_intel8x0_free(chip);
2950}
2951
2952struct ich_reg_info {
2953 unsigned int int_sta_mask;
2954 unsigned int offset;
2955};
2956
2957static unsigned int ich_codec_bits[3] = {
2958 ICH_PCR, ICH_SCR, ICH_TCR
2959};
2960static unsigned int sis_codec_bits[3] = {
2961 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2962};
2963
2964static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2965{
2966 int result = inside_vm;
2967 char *msg = NULL;
2968
2969 /* check module parameter first (override detection) */
2970 if (result >= 0) {
2971 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2972 goto fini;
2973 }
2974
2975 /* detect KVM and Parallels virtual environments */
2976 result = kvm_para_available();
2977#ifdef X86_FEATURE_HYPERVISOR
2978 result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
2979#endif
2980 if (!result)
2981 goto fini;
2982
2983 /* check for known (emulated) devices */
2984 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2985 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2986 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2987 msg = "enable KVM";
2988 } else if (pci->subsystem_vendor == 0x1ab8) {
2989 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2990 msg = "enable Parallels VM";
2991 } else {
2992 msg = "disable (unknown or VT-d) VM";
2993 result = 0;
2994 }
2995
2996fini:
2997 if (msg != NULL)
2998 dev_info(&pci->dev, "%s optimization\n", msg);
2999
3000 return result;
3001}
3002
3003static int snd_intel8x0_create(struct snd_card *card,
3004 struct pci_dev *pci,
3005 unsigned long device_type,
3006 struct intel8x0 **r_intel8x0)
3007{
3008 struct intel8x0 *chip;
3009 int err;
3010 unsigned int i;
3011 unsigned int int_sta_masks;
3012 struct ichdev *ichdev;
3013 static struct snd_device_ops ops = {
3014 .dev_free = snd_intel8x0_dev_free,
3015 };
3016
3017 static unsigned int bdbars[] = {
3018 3, /* DEVICE_INTEL */
3019 6, /* DEVICE_INTEL_ICH4 */
3020 3, /* DEVICE_SIS */
3021 6, /* DEVICE_ALI */
3022 4, /* DEVICE_NFORCE */
3023 };
3024 static struct ich_reg_info intel_regs[6] = {
3025 { ICH_PIINT, 0 },
3026 { ICH_POINT, 0x10 },
3027 { ICH_MCINT, 0x20 },
3028 { ICH_M2INT, 0x40 },
3029 { ICH_P2INT, 0x50 },
3030 { ICH_SPINT, 0x60 },
3031 };
3032 static struct ich_reg_info nforce_regs[4] = {
3033 { ICH_PIINT, 0 },
3034 { ICH_POINT, 0x10 },
3035 { ICH_MCINT, 0x20 },
3036 { ICH_NVSPINT, 0x70 },
3037 };
3038 static struct ich_reg_info ali_regs[6] = {
3039 { ALI_INT_PCMIN, 0x40 },
3040 { ALI_INT_PCMOUT, 0x50 },
3041 { ALI_INT_MICIN, 0x60 },
3042 { ALI_INT_CODECSPDIFOUT, 0x70 },
3043 { ALI_INT_SPDIFIN, 0xa0 },
3044 { ALI_INT_SPDIFOUT, 0xb0 },
3045 };
3046 struct ich_reg_info *tbl;
3047
3048 *r_intel8x0 = NULL;
3049
3050 if ((err = pci_enable_device(pci)) < 0)
3051 return err;
3052
3053 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3054 if (chip == NULL) {
3055 pci_disable_device(pci);
3056 return -ENOMEM;
3057 }
3058 spin_lock_init(&chip->reg_lock);
3059 chip->device_type = device_type;
3060 chip->card = card;
3061 chip->pci = pci;
3062 chip->irq = -1;
3063
3064 /* module parameters */
3065 chip->buggy_irq = buggy_irq;
3066 chip->buggy_semaphore = buggy_semaphore;
3067 if (xbox)
3068 chip->xbox = 1;
3069
3070 chip->inside_vm = snd_intel8x0_inside_vm(pci);
3071
3072 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3073 pci->device == PCI_DEVICE_ID_INTEL_440MX)
3074 chip->fix_nocache = 1; /* enable workaround */
3075
3076 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3077 kfree(chip);
3078 pci_disable_device(pci);
3079 return err;
3080 }
3081
3082 if (device_type == DEVICE_ALI) {
3083 /* ALI5455 has no ac97 region */
3084 chip->bmaddr = pci_iomap(pci, 0, 0);
3085 goto port_inited;
3086 }
3087
3088 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3089 chip->addr = pci_iomap(pci, 2, 0);
3090 else
3091 chip->addr = pci_iomap(pci, 0, 0);
3092 if (!chip->addr) {
3093 dev_err(card->dev, "AC'97 space ioremap problem\n");
3094 snd_intel8x0_free(chip);
3095 return -EIO;
3096 }
3097 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3098 chip->bmaddr = pci_iomap(pci, 3, 0);
3099 else
3100 chip->bmaddr = pci_iomap(pci, 1, 0);
3101
3102 port_inited:
3103 if (!chip->bmaddr) {
3104 dev_err(card->dev, "Controller space ioremap problem\n");
3105 snd_intel8x0_free(chip);
3106 return -EIO;
3107 }
3108 chip->bdbars_count = bdbars[device_type];
3109
3110 /* initialize offsets */
3111 switch (device_type) {
3112 case DEVICE_NFORCE:
3113 tbl = nforce_regs;
3114 break;
3115 case DEVICE_ALI:
3116 tbl = ali_regs;
3117 break;
3118 default:
3119 tbl = intel_regs;
3120 break;
3121 }
3122 for (i = 0; i < chip->bdbars_count; i++) {
3123 ichdev = &chip->ichd[i];
3124 ichdev->ichd = i;
3125 ichdev->reg_offset = tbl[i].offset;
3126 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3127 if (device_type == DEVICE_SIS) {
3128 /* SiS 7012 swaps the registers */
3129 ichdev->roff_sr = ICH_REG_OFF_PICB;
3130 ichdev->roff_picb = ICH_REG_OFF_SR;
3131 } else {
3132 ichdev->roff_sr = ICH_REG_OFF_SR;
3133 ichdev->roff_picb = ICH_REG_OFF_PICB;
3134 }
3135 if (device_type == DEVICE_ALI)
3136 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3137 /* SIS7012 handles the pcm data in bytes, others are in samples */
3138 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3139 }
3140
3141 /* allocate buffer descriptor lists */
3142 /* the start of each lists must be aligned to 8 bytes */
3143 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3144 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3145 &chip->bdbars) < 0) {
3146 snd_intel8x0_free(chip);
3147 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3148 return -ENOMEM;
3149 }
3150 /* tables must be aligned to 8 bytes here, but the kernel pages
3151 are much bigger, so we don't care (on i386) */
3152 /* workaround for 440MX */
3153 if (chip->fix_nocache)
3154 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3155 int_sta_masks = 0;
3156 for (i = 0; i < chip->bdbars_count; i++) {
3157 ichdev = &chip->ichd[i];
3158 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3159 (i * ICH_MAX_FRAGS * 2);
3160 ichdev->bdbar_addr = chip->bdbars.addr +
3161 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3162 int_sta_masks |= ichdev->int_sta_mask;
3163 }
3164 chip->int_sta_reg = device_type == DEVICE_ALI ?
3165 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3166 chip->int_sta_mask = int_sta_masks;
3167
3168 pci_set_master(pci);
3169
3170 switch(chip->device_type) {
3171 case DEVICE_INTEL_ICH4:
3172 /* ICH4 can have three codecs */
3173 chip->max_codecs = 3;
3174 chip->codec_bit = ich_codec_bits;
3175 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3176 break;
3177 case DEVICE_SIS:
3178 /* recent SIS7012 can have three codecs */
3179 chip->max_codecs = 3;
3180 chip->codec_bit = sis_codec_bits;
3181 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3182 break;
3183 default:
3184 /* others up to two codecs */
3185 chip->max_codecs = 2;
3186 chip->codec_bit = ich_codec_bits;
3187 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3188 break;
3189 }
3190 for (i = 0; i < chip->max_codecs; i++)
3191 chip->codec_isr_bits |= chip->codec_bit[i];
3192
3193 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3194 snd_intel8x0_free(chip);
3195 return err;
3196 }
3197
3198 /* request irq after initializaing int_sta_mask, etc */
3199 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3200 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3201 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3202 snd_intel8x0_free(chip);
3203 return -EBUSY;
3204 }
3205 chip->irq = pci->irq;
3206
3207 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3208 snd_intel8x0_free(chip);
3209 return err;
3210 }
3211
3212 *r_intel8x0 = chip;
3213 return 0;
3214}
3215
3216static struct shortname_table {
3217 unsigned int id;
3218 const char *s;
3219} shortnames[] = {
3220 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3221 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3222 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3223 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3224 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3225 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3226 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3227 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3228 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3229 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3230 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3231 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3232 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3233 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3234 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3235 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3236 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3237 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3238 { 0x003a, "NVidia MCP04" },
3239 { 0x746d, "AMD AMD8111" },
3240 { 0x7445, "AMD AMD768" },
3241 { 0x5455, "ALi M5455" },
3242 { 0, NULL },
3243};
3244
3245static struct snd_pci_quirk spdif_aclink_defaults[] = {
3246 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3247 { } /* end */
3248};
3249
3250/* look up white/black list for SPDIF over ac-link */
3251static int check_default_spdif_aclink(struct pci_dev *pci)
3252{
3253 const struct snd_pci_quirk *w;
3254
3255 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3256 if (w) {
3257 if (w->value)
3258 dev_dbg(&pci->dev,
3259 "Using SPDIF over AC-Link for %s\n",
3260 snd_pci_quirk_name(w));
3261 else
3262 dev_dbg(&pci->dev,
3263 "Using integrated SPDIF DMA for %s\n",
3264 snd_pci_quirk_name(w));
3265 return w->value;
3266 }
3267 return 0;
3268}
3269
3270static int snd_intel8x0_probe(struct pci_dev *pci,
3271 const struct pci_device_id *pci_id)
3272{
3273 struct snd_card *card;
3274 struct intel8x0 *chip;
3275 int err;
3276 struct shortname_table *name;
3277
3278 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3279 if (err < 0)
3280 return err;
3281
3282 if (spdif_aclink < 0)
3283 spdif_aclink = check_default_spdif_aclink(pci);
3284
3285 strcpy(card->driver, "ICH");
3286 if (!spdif_aclink) {
3287 switch (pci_id->driver_data) {
3288 case DEVICE_NFORCE:
3289 strcpy(card->driver, "NFORCE");
3290 break;
3291 case DEVICE_INTEL_ICH4:
3292 strcpy(card->driver, "ICH4");
3293 }
3294 }
3295
3296 strcpy(card->shortname, "Intel ICH");
3297 for (name = shortnames; name->id; name++) {
3298 if (pci->device == name->id) {
3299 strcpy(card->shortname, name->s);
3300 break;
3301 }
3302 }
3303
3304 if (buggy_irq < 0) {
3305 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3306 * Needs to return IRQ_HANDLED for unknown irqs.
3307 */
3308 if (pci_id->driver_data == DEVICE_NFORCE)
3309 buggy_irq = 1;
3310 else
3311 buggy_irq = 0;
3312 }
3313
3314 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3315 &chip)) < 0) {
3316 snd_card_free(card);
3317 return err;
3318 }
3319 card->private_data = chip;
3320
3321 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3322 snd_card_free(card);
3323 return err;
3324 }
3325 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3326 snd_card_free(card);
3327 return err;
3328 }
3329
3330 snd_intel8x0_proc_init(chip);
3331
3332 snprintf(card->longname, sizeof(card->longname),
3333 "%s with %s at irq %i", card->shortname,
3334 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3335
3336 if (ac97_clock == 0 || ac97_clock == 1) {
3337 if (ac97_clock == 0) {
3338 if (intel8x0_in_clock_list(chip) == 0)
3339 intel8x0_measure_ac97_clock(chip);
3340 } else {
3341 intel8x0_measure_ac97_clock(chip);
3342 }
3343 }
3344
3345 if ((err = snd_card_register(card)) < 0) {
3346 snd_card_free(card);
3347 return err;
3348 }
3349 pci_set_drvdata(pci, card);
3350 return 0;
3351}
3352
3353static void snd_intel8x0_remove(struct pci_dev *pci)
3354{
3355 snd_card_free(pci_get_drvdata(pci));
3356}
3357
3358static struct pci_driver intel8x0_driver = {
3359 .name = KBUILD_MODNAME,
3360 .id_table = snd_intel8x0_ids,
3361 .probe = snd_intel8x0_probe,
3362 .remove = snd_intel8x0_remove,
3363 .driver = {
3364 .pm = INTEL8X0_PM_OPS,
3365 },
3366};
3367
3368module_pci_driver(intel8x0_driver);
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <linux/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/module.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#ifdef CONFIG_X86
44#include <asm/set_memory.h>
45#endif
46
47MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
48MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
49MODULE_LICENSE("GPL");
50MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{NVidia,nForce3 Audio},"
65 "{NVidia,MCP04},"
66 "{NVidia,MCP501},"
67 "{NVidia,CK804},"
68 "{NVidia,CK8},"
69 "{NVidia,CK8S},"
70 "{AMD,AMD768},"
71 "{AMD,AMD8111},"
72 "{ALI,M5455}}");
73
74static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
75static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
76static int ac97_clock;
77static char *ac97_quirk;
78static bool buggy_semaphore;
79static int buggy_irq = -1; /* auto-check */
80static bool xbox;
81static int spdif_aclink = -1;
82static int inside_vm = -1;
83
84module_param(index, int, 0444);
85MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
86module_param(id, charp, 0444);
87MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
88module_param(ac97_clock, int, 0444);
89MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
90module_param(ac97_quirk, charp, 0444);
91MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
92module_param(buggy_semaphore, bool, 0444);
93MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
94module_param(buggy_irq, bint, 0444);
95MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
96module_param(xbox, bool, 0444);
97MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
98module_param(spdif_aclink, int, 0444);
99MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
100module_param(inside_vm, bint, 0444);
101MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
102
103/* just for backward compatibility */
104static bool enable;
105module_param(enable, bool, 0444);
106static int joystick;
107module_param(joystick, int, 0444);
108
109/*
110 * Direct registers
111 */
112enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
113
114#define ICHREG(x) ICH_REG_##x
115
116#define DEFINE_REGSET(name,base) \
117enum { \
118 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
119 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
120 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
121 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
122 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
123 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
124 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
125};
126
127/* busmaster blocks */
128DEFINE_REGSET(OFF, 0); /* offset */
129DEFINE_REGSET(PI, 0x00); /* PCM in */
130DEFINE_REGSET(PO, 0x10); /* PCM out */
131DEFINE_REGSET(MC, 0x20); /* Mic in */
132
133/* ICH4 busmaster blocks */
134DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
135DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
136DEFINE_REGSET(SP, 0x60); /* SPDIF out */
137
138/* values for each busmaster block */
139
140/* LVI */
141#define ICH_REG_LVI_MASK 0x1f
142
143/* SR */
144#define ICH_FIFOE 0x10 /* FIFO error */
145#define ICH_BCIS 0x08 /* buffer completion interrupt status */
146#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
147#define ICH_CELV 0x02 /* current equals last valid */
148#define ICH_DCH 0x01 /* DMA controller halted */
149
150/* PIV */
151#define ICH_REG_PIV_MASK 0x1f /* mask */
152
153/* CR */
154#define ICH_IOCE 0x10 /* interrupt on completion enable */
155#define ICH_FEIE 0x08 /* fifo error interrupt enable */
156#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
157#define ICH_RESETREGS 0x02 /* reset busmaster registers */
158#define ICH_STARTBM 0x01 /* start busmaster operation */
159
160
161/* global block */
162#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
163#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
164#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
165#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
166#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
167#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
168#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
169#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
170#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
171#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
172#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
173#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
174#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
175#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
176#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
177#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
178#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
179#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
180#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
181#define ICH_ACLINK 0x00000008 /* AClink shut off */
182#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
183#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
184#define ICH_GIE 0x00000001 /* GPI interrupt enable */
185#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
186#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
187#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
188#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
189#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
190#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
191#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
192#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
193#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
194#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
195#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
196#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
197#define ICH_MD3 0x00020000 /* modem power down semaphore */
198#define ICH_AD3 0x00010000 /* audio power down semaphore */
199#define ICH_RCS 0x00008000 /* read completion status */
200#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
201#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
202#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
203#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
204#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
205#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
206#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
207#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
208#define ICH_POINT 0x00000040 /* playback interrupt */
209#define ICH_PIINT 0x00000020 /* capture interrupt */
210#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
211#define ICH_MOINT 0x00000004 /* modem playback interrupt */
212#define ICH_MIINT 0x00000002 /* modem capture interrupt */
213#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
214#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
215#define ICH_CAS 0x01 /* codec access semaphore */
216#define ICH_REG_SDM 0x80
217#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
218#define ICH_DI2L_SHIFT 6
219#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
220#define ICH_DI1L_SHIFT 4
221#define ICH_SE 0x00000008 /* steer enable */
222#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
223
224#define ICH_MAX_FRAGS 32 /* max hw frags */
225
226
227/*
228 * registers for Ali5455
229 */
230
231/* ALi 5455 busmaster blocks */
232DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
233DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
234DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
235DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
236DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
237DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
238DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
239DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
240DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
241DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
242DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
243
244enum {
245 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
246 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
247 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
248 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
249 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
250 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
251 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
252 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
253 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
254 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
255 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
256 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
257 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
258 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
259 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
260 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
261 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
262 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
263 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
264 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
265 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
266};
267
268#define ALI_CAS_SEM_BUSY 0x80000000
269#define ALI_CPR_ADDR_SECONDARY 0x100
270#define ALI_CPR_ADDR_READ 0x80
271#define ALI_CSPSR_CODEC_READY 0x08
272#define ALI_CSPSR_READ_OK 0x02
273#define ALI_CSPSR_WRITE_OK 0x01
274
275/* interrupts for the whole chip by interrupt status register finish */
276
277#define ALI_INT_MICIN2 (1<<26)
278#define ALI_INT_PCMIN2 (1<<25)
279#define ALI_INT_I2SIN (1<<24)
280#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
281#define ALI_INT_SPDIFIN (1<<22)
282#define ALI_INT_LFEOUT (1<<21)
283#define ALI_INT_CENTEROUT (1<<20)
284#define ALI_INT_CODECSPDIFOUT (1<<19)
285#define ALI_INT_MICIN (1<<18)
286#define ALI_INT_PCMOUT (1<<17)
287#define ALI_INT_PCMIN (1<<16)
288#define ALI_INT_CPRAIS (1<<7) /* command port available */
289#define ALI_INT_SPRAIS (1<<5) /* status port available */
290#define ALI_INT_GPIO (1<<1)
291#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
292 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
293
294#define ICH_ALI_SC_RESET (1<<31) /* master reset */
295#define ICH_ALI_SC_AC97_DBL (1<<30)
296#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
297#define ICH_ALI_SC_IN_BITS (3<<18)
298#define ICH_ALI_SC_OUT_BITS (3<<16)
299#define ICH_ALI_SC_6CH_CFG (3<<14)
300#define ICH_ALI_SC_PCM_4 (1<<8)
301#define ICH_ALI_SC_PCM_6 (2<<8)
302#define ICH_ALI_SC_PCM_246_MASK (3<<8)
303
304#define ICH_ALI_SS_SEC_ID (3<<5)
305#define ICH_ALI_SS_PRI_ID (3<<3)
306
307#define ICH_ALI_IF_AC97SP (1<<21)
308#define ICH_ALI_IF_MC (1<<20)
309#define ICH_ALI_IF_PI (1<<19)
310#define ICH_ALI_IF_MC2 (1<<18)
311#define ICH_ALI_IF_PI2 (1<<17)
312#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
313#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
314#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
315#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
316#define ICH_ALI_IF_PO_SPDF (1<<3)
317#define ICH_ALI_IF_PO (1<<1)
318
319/*
320 *
321 */
322
323enum {
324 ICHD_PCMIN,
325 ICHD_PCMOUT,
326 ICHD_MIC,
327 ICHD_MIC2,
328 ICHD_PCM2IN,
329 ICHD_SPBAR,
330 ICHD_LAST = ICHD_SPBAR
331};
332enum {
333 NVD_PCMIN,
334 NVD_PCMOUT,
335 NVD_MIC,
336 NVD_SPBAR,
337 NVD_LAST = NVD_SPBAR
338};
339enum {
340 ALID_PCMIN,
341 ALID_PCMOUT,
342 ALID_MIC,
343 ALID_AC97SPDIFOUT,
344 ALID_SPDIFIN,
345 ALID_SPDIFOUT,
346 ALID_LAST = ALID_SPDIFOUT
347};
348
349#define get_ichdev(substream) (substream->runtime->private_data)
350
351struct ichdev {
352 unsigned int ichd; /* ich device number */
353 unsigned long reg_offset; /* offset to bmaddr */
354 u32 *bdbar; /* CPU address (32bit) */
355 unsigned int bdbar_addr; /* PCI bus address (32bit) */
356 struct snd_pcm_substream *substream;
357 unsigned int physbuf; /* physical address (32bit) */
358 unsigned int size;
359 unsigned int fragsize;
360 unsigned int fragsize1;
361 unsigned int position;
362 unsigned int pos_shift;
363 unsigned int last_pos;
364 int frags;
365 int lvi;
366 int lvi_frag;
367 int civ;
368 int ack;
369 int ack_reload;
370 unsigned int ack_bit;
371 unsigned int roff_sr;
372 unsigned int roff_picb;
373 unsigned int int_sta_mask; /* interrupt status mask */
374 unsigned int ali_slot; /* ALI DMA slot */
375 struct ac97_pcm *pcm;
376 int pcm_open_flag;
377 unsigned int page_attr_changed: 1;
378 unsigned int suspended: 1;
379};
380
381struct intel8x0 {
382 unsigned int device_type;
383
384 int irq;
385
386 void __iomem *addr;
387 void __iomem *bmaddr;
388
389 struct pci_dev *pci;
390 struct snd_card *card;
391
392 int pcm_devs;
393 struct snd_pcm *pcm[6];
394 struct ichdev ichd[6];
395
396 unsigned multi4: 1,
397 multi6: 1,
398 multi8 :1,
399 dra: 1,
400 smp20bit: 1;
401 unsigned in_ac97_init: 1,
402 in_sdin_init: 1;
403 unsigned in_measurement: 1; /* during ac97 clock measurement */
404 unsigned fix_nocache: 1; /* workaround for 440MX */
405 unsigned buggy_irq: 1; /* workaround for buggy mobos */
406 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
407 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
408 unsigned inside_vm: 1; /* enable VM optimization */
409
410 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
411 unsigned int sdm_saved; /* SDM reg value */
412
413 struct snd_ac97_bus *ac97_bus;
414 struct snd_ac97 *ac97[3];
415 unsigned int ac97_sdin[3];
416 unsigned int max_codecs, ncodecs;
417 unsigned int *codec_bit;
418 unsigned int codec_isr_bits;
419 unsigned int codec_ready_bits;
420
421 spinlock_t reg_lock;
422
423 u32 bdbars_count;
424 struct snd_dma_buffer bdbars;
425 u32 int_sta_reg; /* interrupt status register */
426 u32 int_sta_mask; /* interrupt status mask */
427};
428
429static const struct pci_device_id snd_intel8x0_ids[] = {
430 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
431 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
432 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
433 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
434 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
435 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
436 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
437 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
438 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
439 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
440 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
441 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
442 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
443 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
444 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
445 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
446 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
447 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
448 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
449 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
450 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
451 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
452 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
453 { 0, }
454};
455
456MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
457
458/*
459 * Lowlevel I/O - busmaster
460 */
461
462static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
463{
464 return ioread8(chip->bmaddr + offset);
465}
466
467static inline u16 igetword(struct intel8x0 *chip, u32 offset)
468{
469 return ioread16(chip->bmaddr + offset);
470}
471
472static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
473{
474 return ioread32(chip->bmaddr + offset);
475}
476
477static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
478{
479 iowrite8(val, chip->bmaddr + offset);
480}
481
482static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
483{
484 iowrite16(val, chip->bmaddr + offset);
485}
486
487static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
488{
489 iowrite32(val, chip->bmaddr + offset);
490}
491
492/*
493 * Lowlevel I/O - AC'97 registers
494 */
495
496static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
497{
498 return ioread16(chip->addr + offset);
499}
500
501static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
502{
503 iowrite16(val, chip->addr + offset);
504}
505
506/*
507 * Basic I/O
508 */
509
510/*
511 * access to AC97 codec via normal i/o (for ICH and SIS7012)
512 */
513
514static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
515{
516 int time;
517
518 if (codec > 2)
519 return -EIO;
520 if (chip->in_sdin_init) {
521 /* we don't know the ready bit assignment at the moment */
522 /* so we check any */
523 codec = chip->codec_isr_bits;
524 } else {
525 codec = chip->codec_bit[chip->ac97_sdin[codec]];
526 }
527
528 /* codec ready ? */
529 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
530 return -EIO;
531
532 if (chip->buggy_semaphore)
533 return 0; /* just ignore ... */
534
535 /* Anyone holding a semaphore for 1 msec should be shot... */
536 time = 100;
537 do {
538 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
539 return 0;
540 udelay(10);
541 } while (time--);
542
543 /* access to some forbidden (non existent) ac97 registers will not
544 * reset the semaphore. So even if you don't get the semaphore, still
545 * continue the access. We don't need the semaphore anyway. */
546 dev_err(chip->card->dev,
547 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
548 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
549 iagetword(chip, 0); /* clear semaphore flag */
550 /* I don't care about the semaphore */
551 return -EBUSY;
552}
553
554static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
555 unsigned short reg,
556 unsigned short val)
557{
558 struct intel8x0 *chip = ac97->private_data;
559
560 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
561 if (! chip->in_ac97_init)
562 dev_err(chip->card->dev,
563 "codec_write %d: semaphore is not ready for register 0x%x\n",
564 ac97->num, reg);
565 }
566 iaputword(chip, reg + ac97->num * 0x80, val);
567}
568
569static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
570 unsigned short reg)
571{
572 struct intel8x0 *chip = ac97->private_data;
573 unsigned short res;
574 unsigned int tmp;
575
576 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
577 if (! chip->in_ac97_init)
578 dev_err(chip->card->dev,
579 "codec_read %d: semaphore is not ready for register 0x%x\n",
580 ac97->num, reg);
581 res = 0xffff;
582 } else {
583 res = iagetword(chip, reg + ac97->num * 0x80);
584 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
585 /* reset RCS and preserve other R/WC bits */
586 iputdword(chip, ICHREG(GLOB_STA), tmp &
587 ~(chip->codec_ready_bits | ICH_GSCI));
588 if (! chip->in_ac97_init)
589 dev_err(chip->card->dev,
590 "codec_read %d: read timeout for register 0x%x\n",
591 ac97->num, reg);
592 res = 0xffff;
593 }
594 }
595 return res;
596}
597
598static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
599 unsigned int codec)
600{
601 unsigned int tmp;
602
603 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
604 iagetword(chip, codec * 0x80);
605 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
606 /* reset RCS and preserve other R/WC bits */
607 iputdword(chip, ICHREG(GLOB_STA), tmp &
608 ~(chip->codec_ready_bits | ICH_GSCI));
609 }
610 }
611}
612
613/*
614 * access to AC97 for Ali5455
615 */
616static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
617{
618 int count = 0;
619 for (count = 0; count < 0x7f; count++) {
620 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
621 if (val & mask)
622 return 0;
623 }
624 if (! chip->in_ac97_init)
625 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
626 return -EBUSY;
627}
628
629static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
630{
631 int time = 100;
632 if (chip->buggy_semaphore)
633 return 0; /* just ignore ... */
634 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
635 udelay(1);
636 if (! time && ! chip->in_ac97_init)
637 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
638 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
639}
640
641static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
642{
643 struct intel8x0 *chip = ac97->private_data;
644 unsigned short data = 0xffff;
645
646 if (snd_intel8x0_ali_codec_semaphore(chip))
647 goto __err;
648 reg |= ALI_CPR_ADDR_READ;
649 if (ac97->num)
650 reg |= ALI_CPR_ADDR_SECONDARY;
651 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
652 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
653 goto __err;
654 data = igetword(chip, ICHREG(ALI_SPR));
655 __err:
656 return data;
657}
658
659static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
660 unsigned short val)
661{
662 struct intel8x0 *chip = ac97->private_data;
663
664 if (snd_intel8x0_ali_codec_semaphore(chip))
665 return;
666 iputword(chip, ICHREG(ALI_CPR), val);
667 if (ac97->num)
668 reg |= ALI_CPR_ADDR_SECONDARY;
669 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
670 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
671}
672
673
674/*
675 * DMA I/O
676 */
677static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
678{
679 int idx;
680 u32 *bdbar = ichdev->bdbar;
681 unsigned long port = ichdev->reg_offset;
682
683 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
684 if (ichdev->size == ichdev->fragsize) {
685 ichdev->ack_reload = ichdev->ack = 2;
686 ichdev->fragsize1 = ichdev->fragsize >> 1;
687 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
688 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
689 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690 ichdev->fragsize1 >> ichdev->pos_shift);
691 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
692 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
693 ichdev->fragsize1 >> ichdev->pos_shift);
694 }
695 ichdev->frags = 2;
696 } else {
697 ichdev->ack_reload = ichdev->ack = 1;
698 ichdev->fragsize1 = ichdev->fragsize;
699 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
700 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
701 (((idx >> 1) * ichdev->fragsize) %
702 ichdev->size));
703 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
704 ichdev->fragsize >> ichdev->pos_shift);
705#if 0
706 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
707 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
708#endif
709 }
710 ichdev->frags = ichdev->size / ichdev->fragsize;
711 }
712 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
713 ichdev->civ = 0;
714 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
715 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
716 ichdev->position = 0;
717#if 0
718 dev_dbg(chip->card->dev,
719 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
720 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
721 ichdev->fragsize1);
722#endif
723 /* clear interrupts */
724 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
725}
726
727#ifdef __i386__
728/*
729 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
730 * which aborts PCI busmaster for audio transfer. A workaround is to set
731 * the pages as non-cached. For details, see the errata in
732 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
733 */
734static void fill_nocache(void *buf, int size, int nocache)
735{
736 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
737 if (nocache)
738 set_pages_uc(virt_to_page(buf), size);
739 else
740 set_pages_wb(virt_to_page(buf), size);
741}
742#else
743#define fill_nocache(buf, size, nocache) do { ; } while (0)
744#endif
745
746/*
747 * Interrupt handler
748 */
749
750static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
751{
752 unsigned long port = ichdev->reg_offset;
753 unsigned long flags;
754 int status, civ, i, step;
755 int ack = 0;
756
757 spin_lock_irqsave(&chip->reg_lock, flags);
758 status = igetbyte(chip, port + ichdev->roff_sr);
759 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
760 if (!(status & ICH_BCIS)) {
761 step = 0;
762 } else if (civ == ichdev->civ) {
763 // snd_printd("civ same %d\n", civ);
764 step = 1;
765 ichdev->civ++;
766 ichdev->civ &= ICH_REG_LVI_MASK;
767 } else {
768 step = civ - ichdev->civ;
769 if (step < 0)
770 step += ICH_REG_LVI_MASK + 1;
771 // if (step != 1)
772 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
773 ichdev->civ = civ;
774 }
775
776 ichdev->position += step * ichdev->fragsize1;
777 if (! chip->in_measurement)
778 ichdev->position %= ichdev->size;
779 ichdev->lvi += step;
780 ichdev->lvi &= ICH_REG_LVI_MASK;
781 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
782 for (i = 0; i < step; i++) {
783 ichdev->lvi_frag++;
784 ichdev->lvi_frag %= ichdev->frags;
785 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
786#if 0
787 dev_dbg(chip->card->dev,
788 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
789 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
790 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
791 inl(port + 4), inb(port + ICH_REG_OFF_CR));
792#endif
793 if (--ichdev->ack == 0) {
794 ichdev->ack = ichdev->ack_reload;
795 ack = 1;
796 }
797 }
798 spin_unlock_irqrestore(&chip->reg_lock, flags);
799 if (ack && ichdev->substream) {
800 snd_pcm_period_elapsed(ichdev->substream);
801 }
802 iputbyte(chip, port + ichdev->roff_sr,
803 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
804}
805
806static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
807{
808 struct intel8x0 *chip = dev_id;
809 struct ichdev *ichdev;
810 unsigned int status;
811 unsigned int i;
812
813 status = igetdword(chip, chip->int_sta_reg);
814 if (status == 0xffffffff) /* we are not yet resumed */
815 return IRQ_NONE;
816
817 if ((status & chip->int_sta_mask) == 0) {
818 if (status) {
819 /* ack */
820 iputdword(chip, chip->int_sta_reg, status);
821 if (! chip->buggy_irq)
822 status = 0;
823 }
824 return IRQ_RETVAL(status);
825 }
826
827 for (i = 0; i < chip->bdbars_count; i++) {
828 ichdev = &chip->ichd[i];
829 if (status & ichdev->int_sta_mask)
830 snd_intel8x0_update(chip, ichdev);
831 }
832
833 /* ack them */
834 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
835
836 return IRQ_HANDLED;
837}
838
839/*
840 * PCM part
841 */
842
843static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
844{
845 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
846 struct ichdev *ichdev = get_ichdev(substream);
847 unsigned char val = 0;
848 unsigned long port = ichdev->reg_offset;
849
850 switch (cmd) {
851 case SNDRV_PCM_TRIGGER_RESUME:
852 ichdev->suspended = 0;
853 /* fallthru */
854 case SNDRV_PCM_TRIGGER_START:
855 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
856 val = ICH_IOCE | ICH_STARTBM;
857 ichdev->last_pos = ichdev->position;
858 break;
859 case SNDRV_PCM_TRIGGER_SUSPEND:
860 ichdev->suspended = 1;
861 /* fallthru */
862 case SNDRV_PCM_TRIGGER_STOP:
863 val = 0;
864 break;
865 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
866 val = ICH_IOCE;
867 break;
868 default:
869 return -EINVAL;
870 }
871 iputbyte(chip, port + ICH_REG_OFF_CR, val);
872 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
873 /* wait until DMA stopped */
874 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
875 /* reset whole DMA things */
876 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
877 }
878 return 0;
879}
880
881static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
882{
883 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
884 struct ichdev *ichdev = get_ichdev(substream);
885 unsigned long port = ichdev->reg_offset;
886 static int fiforeg[] = {
887 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
888 };
889 unsigned int val, fifo;
890
891 val = igetdword(chip, ICHREG(ALI_DMACR));
892 switch (cmd) {
893 case SNDRV_PCM_TRIGGER_RESUME:
894 ichdev->suspended = 0;
895 /* fallthru */
896 case SNDRV_PCM_TRIGGER_START:
897 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
898 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
899 /* clear FIFO for synchronization of channels */
900 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
901 fifo &= ~(0xff << (ichdev->ali_slot % 4));
902 fifo |= 0x83 << (ichdev->ali_slot % 4);
903 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
904 }
905 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
906 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
907 /* start DMA */
908 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
909 break;
910 case SNDRV_PCM_TRIGGER_SUSPEND:
911 ichdev->suspended = 1;
912 /* fallthru */
913 case SNDRV_PCM_TRIGGER_STOP:
914 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
915 /* pause */
916 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
917 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
918 while (igetbyte(chip, port + ICH_REG_OFF_CR))
919 ;
920 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
921 break;
922 /* reset whole DMA things */
923 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
924 /* clear interrupts */
925 iputbyte(chip, port + ICH_REG_OFF_SR,
926 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
927 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
928 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
929 break;
930 default:
931 return -EINVAL;
932 }
933 return 0;
934}
935
936static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
937 struct snd_pcm_hw_params *hw_params)
938{
939 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
940 struct ichdev *ichdev = get_ichdev(substream);
941 struct snd_pcm_runtime *runtime = substream->runtime;
942 int dbl = params_rate(hw_params) > 48000;
943 int err;
944
945 if (chip->fix_nocache && ichdev->page_attr_changed) {
946 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
947 ichdev->page_attr_changed = 0;
948 }
949 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
950 if (err < 0)
951 return err;
952 if (chip->fix_nocache) {
953 if (runtime->dma_area && ! ichdev->page_attr_changed) {
954 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
955 ichdev->page_attr_changed = 1;
956 }
957 }
958 if (ichdev->pcm_open_flag) {
959 snd_ac97_pcm_close(ichdev->pcm);
960 ichdev->pcm_open_flag = 0;
961 }
962 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
963 params_channels(hw_params),
964 ichdev->pcm->r[dbl].slots);
965 if (err >= 0) {
966 ichdev->pcm_open_flag = 1;
967 /* Force SPDIF setting */
968 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
969 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
970 params_rate(hw_params));
971 }
972 return err;
973}
974
975static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
976{
977 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
978 struct ichdev *ichdev = get_ichdev(substream);
979
980 if (ichdev->pcm_open_flag) {
981 snd_ac97_pcm_close(ichdev->pcm);
982 ichdev->pcm_open_flag = 0;
983 }
984 if (chip->fix_nocache && ichdev->page_attr_changed) {
985 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
986 ichdev->page_attr_changed = 0;
987 }
988 return snd_pcm_lib_free_pages(substream);
989}
990
991static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
992 struct snd_pcm_runtime *runtime)
993{
994 unsigned int cnt;
995 int dbl = runtime->rate > 48000;
996
997 spin_lock_irq(&chip->reg_lock);
998 switch (chip->device_type) {
999 case DEVICE_ALI:
1000 cnt = igetdword(chip, ICHREG(ALI_SCR));
1001 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1002 if (runtime->channels == 4 || dbl)
1003 cnt |= ICH_ALI_SC_PCM_4;
1004 else if (runtime->channels == 6)
1005 cnt |= ICH_ALI_SC_PCM_6;
1006 iputdword(chip, ICHREG(ALI_SCR), cnt);
1007 break;
1008 case DEVICE_SIS:
1009 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1010 cnt &= ~ICH_SIS_PCM_246_MASK;
1011 if (runtime->channels == 4 || dbl)
1012 cnt |= ICH_SIS_PCM_4;
1013 else if (runtime->channels == 6)
1014 cnt |= ICH_SIS_PCM_6;
1015 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1016 break;
1017 default:
1018 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1019 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1020 if (runtime->channels == 4 || dbl)
1021 cnt |= ICH_PCM_4;
1022 else if (runtime->channels == 6)
1023 cnt |= ICH_PCM_6;
1024 else if (runtime->channels == 8)
1025 cnt |= ICH_PCM_8;
1026 if (chip->device_type == DEVICE_NFORCE) {
1027 /* reset to 2ch once to keep the 6 channel data in alignment,
1028 * to start from Front Left always
1029 */
1030 if (cnt & ICH_PCM_246_MASK) {
1031 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1032 spin_unlock_irq(&chip->reg_lock);
1033 msleep(50); /* grrr... */
1034 spin_lock_irq(&chip->reg_lock);
1035 }
1036 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1037 if (runtime->sample_bits > 16)
1038 cnt |= ICH_PCM_20BIT;
1039 }
1040 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1041 break;
1042 }
1043 spin_unlock_irq(&chip->reg_lock);
1044}
1045
1046static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1047{
1048 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1049 struct snd_pcm_runtime *runtime = substream->runtime;
1050 struct ichdev *ichdev = get_ichdev(substream);
1051
1052 ichdev->physbuf = runtime->dma_addr;
1053 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1054 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1055 if (ichdev->ichd == ICHD_PCMOUT) {
1056 snd_intel8x0_setup_pcm_out(chip, runtime);
1057 if (chip->device_type == DEVICE_INTEL_ICH4)
1058 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1059 }
1060 snd_intel8x0_setup_periods(chip, ichdev);
1061 return 0;
1062}
1063
1064static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1065{
1066 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1067 struct ichdev *ichdev = get_ichdev(substream);
1068 size_t ptr1, ptr;
1069 int civ, timeout = 10;
1070 unsigned int position;
1071
1072 spin_lock(&chip->reg_lock);
1073 do {
1074 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1075 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1076 position = ichdev->position;
1077 if (ptr1 == 0) {
1078 udelay(10);
1079 continue;
1080 }
1081 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1082 continue;
1083
1084 /* IO read operation is very expensive inside virtual machine
1085 * as it is emulated. The probability that subsequent PICB read
1086 * will return different result is high enough to loop till
1087 * timeout here.
1088 * Same CIV is strict enough condition to be sure that PICB
1089 * is valid inside VM on emulated card. */
1090 if (chip->inside_vm)
1091 break;
1092 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1093 break;
1094 } while (timeout--);
1095 ptr = ichdev->last_pos;
1096 if (ptr1 != 0) {
1097 ptr1 <<= ichdev->pos_shift;
1098 ptr = ichdev->fragsize1 - ptr1;
1099 ptr += position;
1100 if (ptr < ichdev->last_pos) {
1101 unsigned int pos_base, last_base;
1102 pos_base = position / ichdev->fragsize1;
1103 last_base = ichdev->last_pos / ichdev->fragsize1;
1104 /* another sanity check; ptr1 can go back to full
1105 * before the base position is updated
1106 */
1107 if (pos_base == last_base)
1108 ptr = ichdev->last_pos;
1109 }
1110 }
1111 ichdev->last_pos = ptr;
1112 spin_unlock(&chip->reg_lock);
1113 if (ptr >= ichdev->size)
1114 return 0;
1115 return bytes_to_frames(substream->runtime, ptr);
1116}
1117
1118static const struct snd_pcm_hardware snd_intel8x0_stream =
1119{
1120 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1121 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1122 SNDRV_PCM_INFO_MMAP_VALID |
1123 SNDRV_PCM_INFO_PAUSE |
1124 SNDRV_PCM_INFO_RESUME),
1125 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1126 .rates = SNDRV_PCM_RATE_48000,
1127 .rate_min = 48000,
1128 .rate_max = 48000,
1129 .channels_min = 2,
1130 .channels_max = 2,
1131 .buffer_bytes_max = 128 * 1024,
1132 .period_bytes_min = 32,
1133 .period_bytes_max = 128 * 1024,
1134 .periods_min = 1,
1135 .periods_max = 1024,
1136 .fifo_size = 0,
1137};
1138
1139static const unsigned int channels4[] = {
1140 2, 4,
1141};
1142
1143static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1144 .count = ARRAY_SIZE(channels4),
1145 .list = channels4,
1146 .mask = 0,
1147};
1148
1149static const unsigned int channels6[] = {
1150 2, 4, 6,
1151};
1152
1153static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1154 .count = ARRAY_SIZE(channels6),
1155 .list = channels6,
1156 .mask = 0,
1157};
1158
1159static const unsigned int channels8[] = {
1160 2, 4, 6, 8,
1161};
1162
1163static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1164 .count = ARRAY_SIZE(channels8),
1165 .list = channels8,
1166 .mask = 0,
1167};
1168
1169static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1170{
1171 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1172 struct snd_pcm_runtime *runtime = substream->runtime;
1173 int err;
1174
1175 ichdev->substream = substream;
1176 runtime->hw = snd_intel8x0_stream;
1177 runtime->hw.rates = ichdev->pcm->rates;
1178 snd_pcm_limit_hw_rates(runtime);
1179 if (chip->device_type == DEVICE_SIS) {
1180 runtime->hw.buffer_bytes_max = 64*1024;
1181 runtime->hw.period_bytes_max = 64*1024;
1182 }
1183 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1184 return err;
1185 runtime->private_data = ichdev;
1186 return 0;
1187}
1188
1189static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1190{
1191 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1192 struct snd_pcm_runtime *runtime = substream->runtime;
1193 int err;
1194
1195 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1196 if (err < 0)
1197 return err;
1198
1199 if (chip->multi8) {
1200 runtime->hw.channels_max = 8;
1201 snd_pcm_hw_constraint_list(runtime, 0,
1202 SNDRV_PCM_HW_PARAM_CHANNELS,
1203 &hw_constraints_channels8);
1204 } else if (chip->multi6) {
1205 runtime->hw.channels_max = 6;
1206 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1207 &hw_constraints_channels6);
1208 } else if (chip->multi4) {
1209 runtime->hw.channels_max = 4;
1210 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1211 &hw_constraints_channels4);
1212 }
1213 if (chip->dra) {
1214 snd_ac97_pcm_double_rate_rules(runtime);
1215 }
1216 if (chip->smp20bit) {
1217 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1218 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1219 }
1220 return 0;
1221}
1222
1223static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1224{
1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227 chip->ichd[ICHD_PCMOUT].substream = NULL;
1228 return 0;
1229}
1230
1231static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1232{
1233 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234
1235 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1236}
1237
1238static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1239{
1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242 chip->ichd[ICHD_PCMIN].substream = NULL;
1243 return 0;
1244}
1245
1246static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1247{
1248 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1249
1250 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1251}
1252
1253static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1254{
1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256
1257 chip->ichd[ICHD_MIC].substream = NULL;
1258 return 0;
1259}
1260
1261static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1262{
1263 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264
1265 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1266}
1267
1268static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1269{
1270 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1271
1272 chip->ichd[ICHD_MIC2].substream = NULL;
1273 return 0;
1274}
1275
1276static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1277{
1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1279
1280 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1281}
1282
1283static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1284{
1285 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1286
1287 chip->ichd[ICHD_PCM2IN].substream = NULL;
1288 return 0;
1289}
1290
1291static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1292{
1293 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1294 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1295
1296 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1297}
1298
1299static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1300{
1301 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1302 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1303
1304 chip->ichd[idx].substream = NULL;
1305 return 0;
1306}
1307
1308static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1309{
1310 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1311 unsigned int val;
1312
1313 spin_lock_irq(&chip->reg_lock);
1314 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1315 val |= ICH_ALI_IF_AC97SP;
1316 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1317 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1318 spin_unlock_irq(&chip->reg_lock);
1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1321}
1322
1323static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1324{
1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326 unsigned int val;
1327
1328 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1329 spin_lock_irq(&chip->reg_lock);
1330 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1331 val &= ~ICH_ALI_IF_AC97SP;
1332 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1333 spin_unlock_irq(&chip->reg_lock);
1334
1335 return 0;
1336}
1337
1338#if 0 // NYI
1339static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1340{
1341 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1342
1343 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1344}
1345
1346static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1347{
1348 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1349
1350 chip->ichd[ALID_SPDIFIN].substream = NULL;
1351 return 0;
1352}
1353
1354static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1355{
1356 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1357
1358 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1359}
1360
1361static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1362{
1363 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1364
1365 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1366 return 0;
1367}
1368#endif
1369
1370static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1371 .open = snd_intel8x0_playback_open,
1372 .close = snd_intel8x0_playback_close,
1373 .ioctl = snd_pcm_lib_ioctl,
1374 .hw_params = snd_intel8x0_hw_params,
1375 .hw_free = snd_intel8x0_hw_free,
1376 .prepare = snd_intel8x0_pcm_prepare,
1377 .trigger = snd_intel8x0_pcm_trigger,
1378 .pointer = snd_intel8x0_pcm_pointer,
1379};
1380
1381static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1382 .open = snd_intel8x0_capture_open,
1383 .close = snd_intel8x0_capture_close,
1384 .ioctl = snd_pcm_lib_ioctl,
1385 .hw_params = snd_intel8x0_hw_params,
1386 .hw_free = snd_intel8x0_hw_free,
1387 .prepare = snd_intel8x0_pcm_prepare,
1388 .trigger = snd_intel8x0_pcm_trigger,
1389 .pointer = snd_intel8x0_pcm_pointer,
1390};
1391
1392static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1393 .open = snd_intel8x0_mic_open,
1394 .close = snd_intel8x0_mic_close,
1395 .ioctl = snd_pcm_lib_ioctl,
1396 .hw_params = snd_intel8x0_hw_params,
1397 .hw_free = snd_intel8x0_hw_free,
1398 .prepare = snd_intel8x0_pcm_prepare,
1399 .trigger = snd_intel8x0_pcm_trigger,
1400 .pointer = snd_intel8x0_pcm_pointer,
1401};
1402
1403static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1404 .open = snd_intel8x0_mic2_open,
1405 .close = snd_intel8x0_mic2_close,
1406 .ioctl = snd_pcm_lib_ioctl,
1407 .hw_params = snd_intel8x0_hw_params,
1408 .hw_free = snd_intel8x0_hw_free,
1409 .prepare = snd_intel8x0_pcm_prepare,
1410 .trigger = snd_intel8x0_pcm_trigger,
1411 .pointer = snd_intel8x0_pcm_pointer,
1412};
1413
1414static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1415 .open = snd_intel8x0_capture2_open,
1416 .close = snd_intel8x0_capture2_close,
1417 .ioctl = snd_pcm_lib_ioctl,
1418 .hw_params = snd_intel8x0_hw_params,
1419 .hw_free = snd_intel8x0_hw_free,
1420 .prepare = snd_intel8x0_pcm_prepare,
1421 .trigger = snd_intel8x0_pcm_trigger,
1422 .pointer = snd_intel8x0_pcm_pointer,
1423};
1424
1425static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1426 .open = snd_intel8x0_spdif_open,
1427 .close = snd_intel8x0_spdif_close,
1428 .ioctl = snd_pcm_lib_ioctl,
1429 .hw_params = snd_intel8x0_hw_params,
1430 .hw_free = snd_intel8x0_hw_free,
1431 .prepare = snd_intel8x0_pcm_prepare,
1432 .trigger = snd_intel8x0_pcm_trigger,
1433 .pointer = snd_intel8x0_pcm_pointer,
1434};
1435
1436static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1437 .open = snd_intel8x0_playback_open,
1438 .close = snd_intel8x0_playback_close,
1439 .ioctl = snd_pcm_lib_ioctl,
1440 .hw_params = snd_intel8x0_hw_params,
1441 .hw_free = snd_intel8x0_hw_free,
1442 .prepare = snd_intel8x0_pcm_prepare,
1443 .trigger = snd_intel8x0_ali_trigger,
1444 .pointer = snd_intel8x0_pcm_pointer,
1445};
1446
1447static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1448 .open = snd_intel8x0_capture_open,
1449 .close = snd_intel8x0_capture_close,
1450 .ioctl = snd_pcm_lib_ioctl,
1451 .hw_params = snd_intel8x0_hw_params,
1452 .hw_free = snd_intel8x0_hw_free,
1453 .prepare = snd_intel8x0_pcm_prepare,
1454 .trigger = snd_intel8x0_ali_trigger,
1455 .pointer = snd_intel8x0_pcm_pointer,
1456};
1457
1458static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1459 .open = snd_intel8x0_mic_open,
1460 .close = snd_intel8x0_mic_close,
1461 .ioctl = snd_pcm_lib_ioctl,
1462 .hw_params = snd_intel8x0_hw_params,
1463 .hw_free = snd_intel8x0_hw_free,
1464 .prepare = snd_intel8x0_pcm_prepare,
1465 .trigger = snd_intel8x0_ali_trigger,
1466 .pointer = snd_intel8x0_pcm_pointer,
1467};
1468
1469static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1470 .open = snd_intel8x0_ali_ac97spdifout_open,
1471 .close = snd_intel8x0_ali_ac97spdifout_close,
1472 .ioctl = snd_pcm_lib_ioctl,
1473 .hw_params = snd_intel8x0_hw_params,
1474 .hw_free = snd_intel8x0_hw_free,
1475 .prepare = snd_intel8x0_pcm_prepare,
1476 .trigger = snd_intel8x0_ali_trigger,
1477 .pointer = snd_intel8x0_pcm_pointer,
1478};
1479
1480#if 0 // NYI
1481static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1482 .open = snd_intel8x0_ali_spdifin_open,
1483 .close = snd_intel8x0_ali_spdifin_close,
1484 .ioctl = snd_pcm_lib_ioctl,
1485 .hw_params = snd_intel8x0_hw_params,
1486 .hw_free = snd_intel8x0_hw_free,
1487 .prepare = snd_intel8x0_pcm_prepare,
1488 .trigger = snd_intel8x0_pcm_trigger,
1489 .pointer = snd_intel8x0_pcm_pointer,
1490};
1491
1492static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1493 .open = snd_intel8x0_ali_spdifout_open,
1494 .close = snd_intel8x0_ali_spdifout_close,
1495 .ioctl = snd_pcm_lib_ioctl,
1496 .hw_params = snd_intel8x0_hw_params,
1497 .hw_free = snd_intel8x0_hw_free,
1498 .prepare = snd_intel8x0_pcm_prepare,
1499 .trigger = snd_intel8x0_pcm_trigger,
1500 .pointer = snd_intel8x0_pcm_pointer,
1501};
1502#endif // NYI
1503
1504struct ich_pcm_table {
1505 char *suffix;
1506 const struct snd_pcm_ops *playback_ops;
1507 const struct snd_pcm_ops *capture_ops;
1508 size_t prealloc_size;
1509 size_t prealloc_max_size;
1510 int ac97_idx;
1511};
1512
1513static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1514 struct ich_pcm_table *rec)
1515{
1516 struct snd_pcm *pcm;
1517 int err;
1518 char name[32];
1519
1520 if (rec->suffix)
1521 sprintf(name, "Intel ICH - %s", rec->suffix);
1522 else
1523 strcpy(name, "Intel ICH");
1524 err = snd_pcm_new(chip->card, name, device,
1525 rec->playback_ops ? 1 : 0,
1526 rec->capture_ops ? 1 : 0, &pcm);
1527 if (err < 0)
1528 return err;
1529
1530 if (rec->playback_ops)
1531 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1532 if (rec->capture_ops)
1533 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1534
1535 pcm->private_data = chip;
1536 pcm->info_flags = 0;
1537 if (rec->suffix)
1538 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1539 else
1540 strcpy(pcm->name, chip->card->shortname);
1541 chip->pcm[device] = pcm;
1542
1543 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1544 snd_dma_pci_data(chip->pci),
1545 rec->prealloc_size, rec->prealloc_max_size);
1546
1547 if (rec->playback_ops &&
1548 rec->playback_ops->open == snd_intel8x0_playback_open) {
1549 struct snd_pcm_chmap *chmap;
1550 int chs = 2;
1551 if (chip->multi8)
1552 chs = 8;
1553 else if (chip->multi6)
1554 chs = 6;
1555 else if (chip->multi4)
1556 chs = 4;
1557 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1558 snd_pcm_alt_chmaps, chs, 0,
1559 &chmap);
1560 if (err < 0)
1561 return err;
1562 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1563 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1564 }
1565
1566 return 0;
1567}
1568
1569static struct ich_pcm_table intel_pcms[] = {
1570 {
1571 .playback_ops = &snd_intel8x0_playback_ops,
1572 .capture_ops = &snd_intel8x0_capture_ops,
1573 .prealloc_size = 64 * 1024,
1574 .prealloc_max_size = 128 * 1024,
1575 },
1576 {
1577 .suffix = "MIC ADC",
1578 .capture_ops = &snd_intel8x0_capture_mic_ops,
1579 .prealloc_size = 0,
1580 .prealloc_max_size = 128 * 1024,
1581 .ac97_idx = ICHD_MIC,
1582 },
1583 {
1584 .suffix = "MIC2 ADC",
1585 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1586 .prealloc_size = 0,
1587 .prealloc_max_size = 128 * 1024,
1588 .ac97_idx = ICHD_MIC2,
1589 },
1590 {
1591 .suffix = "ADC2",
1592 .capture_ops = &snd_intel8x0_capture2_ops,
1593 .prealloc_size = 0,
1594 .prealloc_max_size = 128 * 1024,
1595 .ac97_idx = ICHD_PCM2IN,
1596 },
1597 {
1598 .suffix = "IEC958",
1599 .playback_ops = &snd_intel8x0_spdif_ops,
1600 .prealloc_size = 64 * 1024,
1601 .prealloc_max_size = 128 * 1024,
1602 .ac97_idx = ICHD_SPBAR,
1603 },
1604};
1605
1606static struct ich_pcm_table nforce_pcms[] = {
1607 {
1608 .playback_ops = &snd_intel8x0_playback_ops,
1609 .capture_ops = &snd_intel8x0_capture_ops,
1610 .prealloc_size = 64 * 1024,
1611 .prealloc_max_size = 128 * 1024,
1612 },
1613 {
1614 .suffix = "MIC ADC",
1615 .capture_ops = &snd_intel8x0_capture_mic_ops,
1616 .prealloc_size = 0,
1617 .prealloc_max_size = 128 * 1024,
1618 .ac97_idx = NVD_MIC,
1619 },
1620 {
1621 .suffix = "IEC958",
1622 .playback_ops = &snd_intel8x0_spdif_ops,
1623 .prealloc_size = 64 * 1024,
1624 .prealloc_max_size = 128 * 1024,
1625 .ac97_idx = NVD_SPBAR,
1626 },
1627};
1628
1629static struct ich_pcm_table ali_pcms[] = {
1630 {
1631 .playback_ops = &snd_intel8x0_ali_playback_ops,
1632 .capture_ops = &snd_intel8x0_ali_capture_ops,
1633 .prealloc_size = 64 * 1024,
1634 .prealloc_max_size = 128 * 1024,
1635 },
1636 {
1637 .suffix = "MIC ADC",
1638 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1639 .prealloc_size = 0,
1640 .prealloc_max_size = 128 * 1024,
1641 .ac97_idx = ALID_MIC,
1642 },
1643 {
1644 .suffix = "IEC958",
1645 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1646 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1647 .prealloc_size = 64 * 1024,
1648 .prealloc_max_size = 128 * 1024,
1649 .ac97_idx = ALID_AC97SPDIFOUT,
1650 },
1651#if 0 // NYI
1652 {
1653 .suffix = "HW IEC958",
1654 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1655 .prealloc_size = 64 * 1024,
1656 .prealloc_max_size = 128 * 1024,
1657 },
1658#endif
1659};
1660
1661static int snd_intel8x0_pcm(struct intel8x0 *chip)
1662{
1663 int i, tblsize, device, err;
1664 struct ich_pcm_table *tbl, *rec;
1665
1666 switch (chip->device_type) {
1667 case DEVICE_INTEL_ICH4:
1668 tbl = intel_pcms;
1669 tblsize = ARRAY_SIZE(intel_pcms);
1670 if (spdif_aclink)
1671 tblsize--;
1672 break;
1673 case DEVICE_NFORCE:
1674 tbl = nforce_pcms;
1675 tblsize = ARRAY_SIZE(nforce_pcms);
1676 if (spdif_aclink)
1677 tblsize--;
1678 break;
1679 case DEVICE_ALI:
1680 tbl = ali_pcms;
1681 tblsize = ARRAY_SIZE(ali_pcms);
1682 break;
1683 default:
1684 tbl = intel_pcms;
1685 tblsize = 2;
1686 break;
1687 }
1688
1689 device = 0;
1690 for (i = 0; i < tblsize; i++) {
1691 rec = tbl + i;
1692 if (i > 0 && rec->ac97_idx) {
1693 /* activate PCM only when associated AC'97 codec */
1694 if (! chip->ichd[rec->ac97_idx].pcm)
1695 continue;
1696 }
1697 err = snd_intel8x0_pcm1(chip, device, rec);
1698 if (err < 0)
1699 return err;
1700 device++;
1701 }
1702
1703 chip->pcm_devs = device;
1704 return 0;
1705}
1706
1707
1708/*
1709 * Mixer part
1710 */
1711
1712static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1713{
1714 struct intel8x0 *chip = bus->private_data;
1715 chip->ac97_bus = NULL;
1716}
1717
1718static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1719{
1720 struct intel8x0 *chip = ac97->private_data;
1721 chip->ac97[ac97->num] = NULL;
1722}
1723
1724static const struct ac97_pcm ac97_pcm_defs[] = {
1725 /* front PCM */
1726 {
1727 .exclusive = 1,
1728 .r = { {
1729 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1730 (1 << AC97_SLOT_PCM_RIGHT) |
1731 (1 << AC97_SLOT_PCM_CENTER) |
1732 (1 << AC97_SLOT_PCM_SLEFT) |
1733 (1 << AC97_SLOT_PCM_SRIGHT) |
1734 (1 << AC97_SLOT_LFE)
1735 },
1736 {
1737 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1738 (1 << AC97_SLOT_PCM_RIGHT) |
1739 (1 << AC97_SLOT_PCM_LEFT_0) |
1740 (1 << AC97_SLOT_PCM_RIGHT_0)
1741 }
1742 }
1743 },
1744 /* PCM IN #1 */
1745 {
1746 .stream = 1,
1747 .exclusive = 1,
1748 .r = { {
1749 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1750 (1 << AC97_SLOT_PCM_RIGHT)
1751 }
1752 }
1753 },
1754 /* MIC IN #1 */
1755 {
1756 .stream = 1,
1757 .exclusive = 1,
1758 .r = { {
1759 .slots = (1 << AC97_SLOT_MIC)
1760 }
1761 }
1762 },
1763 /* S/PDIF PCM */
1764 {
1765 .exclusive = 1,
1766 .spdif = 1,
1767 .r = { {
1768 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1769 (1 << AC97_SLOT_SPDIF_RIGHT2)
1770 }
1771 }
1772 },
1773 /* PCM IN #2 */
1774 {
1775 .stream = 1,
1776 .exclusive = 1,
1777 .r = { {
1778 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1779 (1 << AC97_SLOT_PCM_RIGHT)
1780 }
1781 }
1782 },
1783 /* MIC IN #2 */
1784 {
1785 .stream = 1,
1786 .exclusive = 1,
1787 .r = { {
1788 .slots = (1 << AC97_SLOT_MIC)
1789 }
1790 }
1791 },
1792};
1793
1794static const struct ac97_quirk ac97_quirks[] = {
1795 {
1796 .subvendor = 0x0e11,
1797 .subdevice = 0x000e,
1798 .name = "Compaq Deskpro EN", /* AD1885 */
1799 .type = AC97_TUNE_HP_ONLY
1800 },
1801 {
1802 .subvendor = 0x0e11,
1803 .subdevice = 0x008a,
1804 .name = "Compaq Evo W4000", /* AD1885 */
1805 .type = AC97_TUNE_HP_ONLY
1806 },
1807 {
1808 .subvendor = 0x0e11,
1809 .subdevice = 0x00b8,
1810 .name = "Compaq Evo D510C",
1811 .type = AC97_TUNE_HP_ONLY
1812 },
1813 {
1814 .subvendor = 0x0e11,
1815 .subdevice = 0x0860,
1816 .name = "HP/Compaq nx7010",
1817 .type = AC97_TUNE_MUTE_LED
1818 },
1819 {
1820 .subvendor = 0x1014,
1821 .subdevice = 0x0534,
1822 .name = "ThinkPad X31",
1823 .type = AC97_TUNE_INV_EAPD
1824 },
1825 {
1826 .subvendor = 0x1014,
1827 .subdevice = 0x1f00,
1828 .name = "MS-9128",
1829 .type = AC97_TUNE_ALC_JACK
1830 },
1831 {
1832 .subvendor = 0x1014,
1833 .subdevice = 0x0267,
1834 .name = "IBM NetVista A30p", /* AD1981B */
1835 .type = AC97_TUNE_HP_ONLY
1836 },
1837 {
1838 .subvendor = 0x1025,
1839 .subdevice = 0x0082,
1840 .name = "Acer Travelmate 2310",
1841 .type = AC97_TUNE_HP_ONLY
1842 },
1843 {
1844 .subvendor = 0x1025,
1845 .subdevice = 0x0083,
1846 .name = "Acer Aspire 3003LCi",
1847 .type = AC97_TUNE_HP_ONLY
1848 },
1849 {
1850 .subvendor = 0x1028,
1851 .subdevice = 0x00d8,
1852 .name = "Dell Precision 530", /* AD1885 */
1853 .type = AC97_TUNE_HP_ONLY
1854 },
1855 {
1856 .subvendor = 0x1028,
1857 .subdevice = 0x010d,
1858 .name = "Dell", /* which model? AD1885 */
1859 .type = AC97_TUNE_HP_ONLY
1860 },
1861 {
1862 .subvendor = 0x1028,
1863 .subdevice = 0x0126,
1864 .name = "Dell Optiplex GX260", /* AD1981A */
1865 .type = AC97_TUNE_HP_ONLY
1866 },
1867 {
1868 .subvendor = 0x1028,
1869 .subdevice = 0x012c,
1870 .name = "Dell Precision 650", /* AD1981A */
1871 .type = AC97_TUNE_HP_ONLY
1872 },
1873 {
1874 .subvendor = 0x1028,
1875 .subdevice = 0x012d,
1876 .name = "Dell Precision 450", /* AD1981B*/
1877 .type = AC97_TUNE_HP_ONLY
1878 },
1879 {
1880 .subvendor = 0x1028,
1881 .subdevice = 0x0147,
1882 .name = "Dell", /* which model? AD1981B*/
1883 .type = AC97_TUNE_HP_ONLY
1884 },
1885 {
1886 .subvendor = 0x1028,
1887 .subdevice = 0x0151,
1888 .name = "Dell Optiplex GX270", /* AD1981B */
1889 .type = AC97_TUNE_HP_ONLY
1890 },
1891 {
1892 .subvendor = 0x1028,
1893 .subdevice = 0x014e,
1894 .name = "Dell D800", /* STAC9750/51 */
1895 .type = AC97_TUNE_HP_ONLY
1896 },
1897 {
1898 .subvendor = 0x1028,
1899 .subdevice = 0x0163,
1900 .name = "Dell Unknown", /* STAC9750/51 */
1901 .type = AC97_TUNE_HP_ONLY
1902 },
1903 {
1904 .subvendor = 0x1028,
1905 .subdevice = 0x016a,
1906 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1907 .type = AC97_TUNE_HP_ONLY
1908 },
1909 {
1910 .subvendor = 0x1028,
1911 .subdevice = 0x0182,
1912 .name = "Dell Latitude D610", /* STAC9750/51 */
1913 .type = AC97_TUNE_HP_ONLY
1914 },
1915 {
1916 .subvendor = 0x1028,
1917 .subdevice = 0x0186,
1918 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1919 .type = AC97_TUNE_HP_MUTE_LED
1920 },
1921 {
1922 .subvendor = 0x1028,
1923 .subdevice = 0x0188,
1924 .name = "Dell Inspiron 6000",
1925 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1926 },
1927 {
1928 .subvendor = 0x1028,
1929 .subdevice = 0x0189,
1930 .name = "Dell Inspiron 9300",
1931 .type = AC97_TUNE_HP_MUTE_LED
1932 },
1933 {
1934 .subvendor = 0x1028,
1935 .subdevice = 0x0191,
1936 .name = "Dell Inspiron 8600",
1937 .type = AC97_TUNE_HP_ONLY
1938 },
1939 {
1940 .subvendor = 0x103c,
1941 .subdevice = 0x006d,
1942 .name = "HP zv5000",
1943 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1944 },
1945 { /* FIXME: which codec? */
1946 .subvendor = 0x103c,
1947 .subdevice = 0x00c3,
1948 .name = "HP xw6000",
1949 .type = AC97_TUNE_HP_ONLY
1950 },
1951 {
1952 .subvendor = 0x103c,
1953 .subdevice = 0x088c,
1954 .name = "HP nc8000",
1955 .type = AC97_TUNE_HP_MUTE_LED
1956 },
1957 {
1958 .subvendor = 0x103c,
1959 .subdevice = 0x0890,
1960 .name = "HP nc6000",
1961 .type = AC97_TUNE_MUTE_LED
1962 },
1963 {
1964 .subvendor = 0x103c,
1965 .subdevice = 0x129d,
1966 .name = "HP xw8000",
1967 .type = AC97_TUNE_HP_ONLY
1968 },
1969 {
1970 .subvendor = 0x103c,
1971 .subdevice = 0x0938,
1972 .name = "HP nc4200",
1973 .type = AC97_TUNE_HP_MUTE_LED
1974 },
1975 {
1976 .subvendor = 0x103c,
1977 .subdevice = 0x099c,
1978 .name = "HP nx6110/nc6120",
1979 .type = AC97_TUNE_HP_MUTE_LED
1980 },
1981 {
1982 .subvendor = 0x103c,
1983 .subdevice = 0x0944,
1984 .name = "HP nc6220",
1985 .type = AC97_TUNE_HP_MUTE_LED
1986 },
1987 {
1988 .subvendor = 0x103c,
1989 .subdevice = 0x0934,
1990 .name = "HP nc8220",
1991 .type = AC97_TUNE_HP_MUTE_LED
1992 },
1993 {
1994 .subvendor = 0x103c,
1995 .subdevice = 0x12f1,
1996 .name = "HP xw8200", /* AD1981B*/
1997 .type = AC97_TUNE_HP_ONLY
1998 },
1999 {
2000 .subvendor = 0x103c,
2001 .subdevice = 0x12f2,
2002 .name = "HP xw6200",
2003 .type = AC97_TUNE_HP_ONLY
2004 },
2005 {
2006 .subvendor = 0x103c,
2007 .subdevice = 0x3008,
2008 .name = "HP xw4200", /* AD1981B*/
2009 .type = AC97_TUNE_HP_ONLY
2010 },
2011 {
2012 .subvendor = 0x104d,
2013 .subdevice = 0x8144,
2014 .name = "Sony",
2015 .type = AC97_TUNE_INV_EAPD
2016 },
2017 {
2018 .subvendor = 0x104d,
2019 .subdevice = 0x8197,
2020 .name = "Sony S1XP",
2021 .type = AC97_TUNE_INV_EAPD
2022 },
2023 {
2024 .subvendor = 0x104d,
2025 .subdevice = 0x81c0,
2026 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2027 .type = AC97_TUNE_INV_EAPD
2028 },
2029 {
2030 .subvendor = 0x104d,
2031 .subdevice = 0x81c5,
2032 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2033 .type = AC97_TUNE_INV_EAPD
2034 },
2035 {
2036 .subvendor = 0x1043,
2037 .subdevice = 0x80f3,
2038 .name = "ASUS ICH5/AD1985",
2039 .type = AC97_TUNE_AD_SHARING
2040 },
2041 {
2042 .subvendor = 0x10cf,
2043 .subdevice = 0x11c3,
2044 .name = "Fujitsu-Siemens E4010",
2045 .type = AC97_TUNE_HP_ONLY
2046 },
2047 {
2048 .subvendor = 0x10cf,
2049 .subdevice = 0x1225,
2050 .name = "Fujitsu-Siemens T3010",
2051 .type = AC97_TUNE_HP_ONLY
2052 },
2053 {
2054 .subvendor = 0x10cf,
2055 .subdevice = 0x1253,
2056 .name = "Fujitsu S6210", /* STAC9750/51 */
2057 .type = AC97_TUNE_HP_ONLY
2058 },
2059 {
2060 .subvendor = 0x10cf,
2061 .subdevice = 0x127d,
2062 .name = "Fujitsu Lifebook P7010",
2063 .type = AC97_TUNE_HP_ONLY
2064 },
2065 {
2066 .subvendor = 0x10cf,
2067 .subdevice = 0x127e,
2068 .name = "Fujitsu Lifebook C1211D",
2069 .type = AC97_TUNE_HP_ONLY
2070 },
2071 {
2072 .subvendor = 0x10cf,
2073 .subdevice = 0x12ec,
2074 .name = "Fujitsu-Siemens 4010",
2075 .type = AC97_TUNE_HP_ONLY
2076 },
2077 {
2078 .subvendor = 0x10cf,
2079 .subdevice = 0x12f2,
2080 .name = "Fujitsu-Siemens Celsius H320",
2081 .type = AC97_TUNE_SWAP_HP
2082 },
2083 {
2084 .subvendor = 0x10f1,
2085 .subdevice = 0x2665,
2086 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2087 .type = AC97_TUNE_HP_ONLY
2088 },
2089 {
2090 .subvendor = 0x10f1,
2091 .subdevice = 0x2885,
2092 .name = "AMD64 Mobo", /* ALC650 */
2093 .type = AC97_TUNE_HP_ONLY
2094 },
2095 {
2096 .subvendor = 0x10f1,
2097 .subdevice = 0x2895,
2098 .name = "Tyan Thunder K8WE",
2099 .type = AC97_TUNE_HP_ONLY
2100 },
2101 {
2102 .subvendor = 0x10f7,
2103 .subdevice = 0x834c,
2104 .name = "Panasonic CF-R4",
2105 .type = AC97_TUNE_HP_ONLY,
2106 },
2107 {
2108 .subvendor = 0x110a,
2109 .subdevice = 0x0056,
2110 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2111 .type = AC97_TUNE_HP_ONLY
2112 },
2113 {
2114 .subvendor = 0x11d4,
2115 .subdevice = 0x5375,
2116 .name = "ADI AD1985 (discrete)",
2117 .type = AC97_TUNE_HP_ONLY
2118 },
2119 {
2120 .subvendor = 0x1462,
2121 .subdevice = 0x5470,
2122 .name = "MSI P4 ATX 645 Ultra",
2123 .type = AC97_TUNE_HP_ONLY
2124 },
2125 {
2126 .subvendor = 0x161f,
2127 .subdevice = 0x202f,
2128 .name = "Gateway M520",
2129 .type = AC97_TUNE_INV_EAPD
2130 },
2131 {
2132 .subvendor = 0x161f,
2133 .subdevice = 0x203a,
2134 .name = "Gateway 4525GZ", /* AD1981B */
2135 .type = AC97_TUNE_INV_EAPD
2136 },
2137 {
2138 .subvendor = 0x1734,
2139 .subdevice = 0x0088,
2140 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2141 .type = AC97_TUNE_HP_ONLY
2142 },
2143 {
2144 .subvendor = 0x8086,
2145 .subdevice = 0x2000,
2146 .mask = 0xfff0,
2147 .name = "Intel ICH5/AD1985",
2148 .type = AC97_TUNE_AD_SHARING
2149 },
2150 {
2151 .subvendor = 0x8086,
2152 .subdevice = 0x4000,
2153 .mask = 0xfff0,
2154 .name = "Intel ICH5/AD1985",
2155 .type = AC97_TUNE_AD_SHARING
2156 },
2157 {
2158 .subvendor = 0x8086,
2159 .subdevice = 0x4856,
2160 .name = "Intel D845WN (82801BA)",
2161 .type = AC97_TUNE_SWAP_HP
2162 },
2163 {
2164 .subvendor = 0x8086,
2165 .subdevice = 0x4d44,
2166 .name = "Intel D850EMV2", /* AD1885 */
2167 .type = AC97_TUNE_HP_ONLY
2168 },
2169 {
2170 .subvendor = 0x8086,
2171 .subdevice = 0x4d56,
2172 .name = "Intel ICH/AD1885",
2173 .type = AC97_TUNE_HP_ONLY
2174 },
2175 {
2176 .subvendor = 0x8086,
2177 .subdevice = 0x6000,
2178 .mask = 0xfff0,
2179 .name = "Intel ICH5/AD1985",
2180 .type = AC97_TUNE_AD_SHARING
2181 },
2182 {
2183 .subvendor = 0x8086,
2184 .subdevice = 0xe000,
2185 .mask = 0xfff0,
2186 .name = "Intel ICH5/AD1985",
2187 .type = AC97_TUNE_AD_SHARING
2188 },
2189#if 0 /* FIXME: this seems wrong on most boards */
2190 {
2191 .subvendor = 0x8086,
2192 .subdevice = 0xa000,
2193 .mask = 0xfff0,
2194 .name = "Intel ICH5/AD1985",
2195 .type = AC97_TUNE_HP_ONLY
2196 },
2197#endif
2198 { } /* terminator */
2199};
2200
2201static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2202 const char *quirk_override)
2203{
2204 struct snd_ac97_bus *pbus;
2205 struct snd_ac97_template ac97;
2206 int err;
2207 unsigned int i, codecs;
2208 unsigned int glob_sta = 0;
2209 struct snd_ac97_bus_ops *ops;
2210 static struct snd_ac97_bus_ops standard_bus_ops = {
2211 .write = snd_intel8x0_codec_write,
2212 .read = snd_intel8x0_codec_read,
2213 };
2214 static struct snd_ac97_bus_ops ali_bus_ops = {
2215 .write = snd_intel8x0_ali_codec_write,
2216 .read = snd_intel8x0_ali_codec_read,
2217 };
2218
2219 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2220 if (!spdif_aclink) {
2221 switch (chip->device_type) {
2222 case DEVICE_NFORCE:
2223 chip->spdif_idx = NVD_SPBAR;
2224 break;
2225 case DEVICE_ALI:
2226 chip->spdif_idx = ALID_AC97SPDIFOUT;
2227 break;
2228 case DEVICE_INTEL_ICH4:
2229 chip->spdif_idx = ICHD_SPBAR;
2230 break;
2231 }
2232 }
2233
2234 chip->in_ac97_init = 1;
2235
2236 memset(&ac97, 0, sizeof(ac97));
2237 ac97.private_data = chip;
2238 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2239 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2240 if (chip->xbox)
2241 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2242 if (chip->device_type != DEVICE_ALI) {
2243 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2244 ops = &standard_bus_ops;
2245 chip->in_sdin_init = 1;
2246 codecs = 0;
2247 for (i = 0; i < chip->max_codecs; i++) {
2248 if (! (glob_sta & chip->codec_bit[i]))
2249 continue;
2250 if (chip->device_type == DEVICE_INTEL_ICH4) {
2251 snd_intel8x0_codec_read_test(chip, codecs);
2252 chip->ac97_sdin[codecs] =
2253 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2254 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2255 chip->ac97_sdin[codecs] = 0;
2256 } else
2257 chip->ac97_sdin[codecs] = i;
2258 codecs++;
2259 }
2260 chip->in_sdin_init = 0;
2261 if (! codecs)
2262 codecs = 1;
2263 } else {
2264 ops = &ali_bus_ops;
2265 codecs = 1;
2266 /* detect the secondary codec */
2267 for (i = 0; i < 100; i++) {
2268 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2269 if (reg & 0x40) {
2270 codecs = 2;
2271 break;
2272 }
2273 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2274 udelay(1);
2275 }
2276 }
2277 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2278 goto __err;
2279 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2280 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2281 pbus->clock = ac97_clock;
2282 /* FIXME: my test board doesn't work well with VRA... */
2283 if (chip->device_type == DEVICE_ALI)
2284 pbus->no_vra = 1;
2285 else
2286 pbus->dra = 1;
2287 chip->ac97_bus = pbus;
2288 chip->ncodecs = codecs;
2289
2290 ac97.pci = chip->pci;
2291 for (i = 0; i < codecs; i++) {
2292 ac97.num = i;
2293 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2294 if (err != -EACCES)
2295 dev_err(chip->card->dev,
2296 "Unable to initialize codec #%d\n", i);
2297 if (i == 0)
2298 goto __err;
2299 }
2300 }
2301 /* tune up the primary codec */
2302 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2303 /* enable separate SDINs for ICH4 */
2304 if (chip->device_type == DEVICE_INTEL_ICH4)
2305 pbus->isdin = 1;
2306 /* find the available PCM streams */
2307 i = ARRAY_SIZE(ac97_pcm_defs);
2308 if (chip->device_type != DEVICE_INTEL_ICH4)
2309 i -= 2; /* do not allocate PCM2IN and MIC2 */
2310 if (chip->spdif_idx < 0)
2311 i--; /* do not allocate S/PDIF */
2312 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2313 if (err < 0)
2314 goto __err;
2315 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2316 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2317 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2318 if (chip->spdif_idx >= 0)
2319 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2320 if (chip->device_type == DEVICE_INTEL_ICH4) {
2321 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2322 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2323 }
2324 /* enable separate SDINs for ICH4 */
2325 if (chip->device_type == DEVICE_INTEL_ICH4) {
2326 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2327 u8 tmp = igetbyte(chip, ICHREG(SDM));
2328 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2329 if (pcm) {
2330 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2331 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2332 for (i = 1; i < 4; i++) {
2333 if (pcm->r[0].codec[i]) {
2334 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2335 break;
2336 }
2337 }
2338 } else {
2339 tmp &= ~ICH_SE; /* steer disable */
2340 }
2341 iputbyte(chip, ICHREG(SDM), tmp);
2342 }
2343 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2344 chip->multi4 = 1;
2345 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2346 chip->multi6 = 1;
2347 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2348 chip->multi8 = 1;
2349 }
2350 }
2351 if (pbus->pcms[0].r[1].rslots[0]) {
2352 chip->dra = 1;
2353 }
2354 if (chip->device_type == DEVICE_INTEL_ICH4) {
2355 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2356 chip->smp20bit = 1;
2357 }
2358 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2359 /* 48kHz only */
2360 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2361 }
2362 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2363 /* use slot 10/11 for SPDIF */
2364 u32 val;
2365 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2366 val |= ICH_PCM_SPDIF_1011;
2367 iputdword(chip, ICHREG(GLOB_CNT), val);
2368 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2369 }
2370 chip->in_ac97_init = 0;
2371 return 0;
2372
2373 __err:
2374 /* clear the cold-reset bit for the next chance */
2375 if (chip->device_type != DEVICE_ALI)
2376 iputdword(chip, ICHREG(GLOB_CNT),
2377 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2378 return err;
2379}
2380
2381
2382/*
2383 *
2384 */
2385
2386static void do_ali_reset(struct intel8x0 *chip)
2387{
2388 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2389 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2390 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2391 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2392 iputdword(chip, ICHREG(ALI_INTERFACECR),
2393 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2394 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2395 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2396}
2397
2398#ifdef CONFIG_SND_AC97_POWER_SAVE
2399static struct snd_pci_quirk ich_chip_reset_mode[] = {
2400 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2401 { } /* end */
2402};
2403
2404static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2405{
2406 unsigned int cnt;
2407 /* ACLink on, 2 channels */
2408
2409 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2410 return -EIO;
2411
2412 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2413 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2414
2415 /* do cold reset - the full ac97 powerdown may leave the controller
2416 * in a warm state but actually it cannot communicate with the codec.
2417 */
2418 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2419 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2420 udelay(10);
2421 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2422 msleep(1);
2423 return 0;
2424}
2425#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2426 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2427#else
2428#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2429#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2430#endif
2431
2432static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2433{
2434 unsigned long end_time;
2435 unsigned int cnt;
2436 /* ACLink on, 2 channels */
2437 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2438 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2439 /* finish cold or do warm reset */
2440 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2441 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2442 end_time = (jiffies + (HZ / 4)) + 1;
2443 do {
2444 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2445 return 0;
2446 schedule_timeout_uninterruptible(1);
2447 } while (time_after_eq(end_time, jiffies));
2448 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2449 igetdword(chip, ICHREG(GLOB_CNT)));
2450 return -EIO;
2451}
2452
2453static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2454{
2455 unsigned long end_time;
2456 unsigned int status, nstatus;
2457 unsigned int cnt;
2458 int err;
2459
2460 /* put logic to right state */
2461 /* first clear status bits */
2462 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2463 if (chip->device_type == DEVICE_NFORCE)
2464 status |= ICH_NVSPINT;
2465 cnt = igetdword(chip, ICHREG(GLOB_STA));
2466 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2467
2468 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2469 err = snd_intel8x0_ich_chip_cold_reset(chip);
2470 else
2471 err = snd_intel8x0_ich_chip_reset(chip);
2472 if (err < 0)
2473 return err;
2474
2475 if (probing) {
2476 /* wait for any codec ready status.
2477 * Once it becomes ready it should remain ready
2478 * as long as we do not disable the ac97 link.
2479 */
2480 end_time = jiffies + HZ;
2481 do {
2482 status = igetdword(chip, ICHREG(GLOB_STA)) &
2483 chip->codec_isr_bits;
2484 if (status)
2485 break;
2486 schedule_timeout_uninterruptible(1);
2487 } while (time_after_eq(end_time, jiffies));
2488 if (! status) {
2489 /* no codec is found */
2490 dev_err(chip->card->dev,
2491 "codec_ready: codec is not ready [0x%x]\n",
2492 igetdword(chip, ICHREG(GLOB_STA)));
2493 return -EIO;
2494 }
2495
2496 /* wait for other codecs ready status. */
2497 end_time = jiffies + HZ / 4;
2498 while (status != chip->codec_isr_bits &&
2499 time_after_eq(end_time, jiffies)) {
2500 schedule_timeout_uninterruptible(1);
2501 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2502 chip->codec_isr_bits;
2503 }
2504
2505 } else {
2506 /* resume phase */
2507 int i;
2508 status = 0;
2509 for (i = 0; i < chip->ncodecs; i++)
2510 if (chip->ac97[i])
2511 status |= chip->codec_bit[chip->ac97_sdin[i]];
2512 /* wait until all the probed codecs are ready */
2513 end_time = jiffies + HZ;
2514 do {
2515 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2516 chip->codec_isr_bits;
2517 if (status == nstatus)
2518 break;
2519 schedule_timeout_uninterruptible(1);
2520 } while (time_after_eq(end_time, jiffies));
2521 }
2522
2523 if (chip->device_type == DEVICE_SIS) {
2524 /* unmute the output on SIS7012 */
2525 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2526 }
2527 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2528 /* enable SPDIF interrupt */
2529 unsigned int val;
2530 pci_read_config_dword(chip->pci, 0x4c, &val);
2531 val |= 0x1000000;
2532 pci_write_config_dword(chip->pci, 0x4c, val);
2533 }
2534 return 0;
2535}
2536
2537static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2538{
2539 u32 reg;
2540 int i = 0;
2541
2542 reg = igetdword(chip, ICHREG(ALI_SCR));
2543 if ((reg & 2) == 0) /* Cold required */
2544 reg |= 2;
2545 else
2546 reg |= 1; /* Warm */
2547 reg &= ~0x80000000; /* ACLink on */
2548 iputdword(chip, ICHREG(ALI_SCR), reg);
2549
2550 for (i = 0; i < HZ / 2; i++) {
2551 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2552 goto __ok;
2553 schedule_timeout_uninterruptible(1);
2554 }
2555 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2556 if (probing)
2557 return -EIO;
2558
2559 __ok:
2560 for (i = 0; i < HZ / 2; i++) {
2561 reg = igetdword(chip, ICHREG(ALI_RTSR));
2562 if (reg & 0x80) /* primary codec */
2563 break;
2564 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2565 schedule_timeout_uninterruptible(1);
2566 }
2567
2568 do_ali_reset(chip);
2569 return 0;
2570}
2571
2572static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2573{
2574 unsigned int i, timeout;
2575 int err;
2576
2577 if (chip->device_type != DEVICE_ALI) {
2578 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2579 return err;
2580 iagetword(chip, 0); /* clear semaphore flag */
2581 } else {
2582 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2583 return err;
2584 }
2585
2586 /* disable interrupts */
2587 for (i = 0; i < chip->bdbars_count; i++)
2588 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2589 /* reset channels */
2590 for (i = 0; i < chip->bdbars_count; i++)
2591 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2592 for (i = 0; i < chip->bdbars_count; i++) {
2593 timeout = 100000;
2594 while (--timeout != 0) {
2595 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2596 break;
2597 }
2598 if (timeout == 0)
2599 dev_err(chip->card->dev, "reset of registers failed?\n");
2600 }
2601 /* initialize Buffer Descriptor Lists */
2602 for (i = 0; i < chip->bdbars_count; i++)
2603 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2604 chip->ichd[i].bdbar_addr);
2605 return 0;
2606}
2607
2608static int snd_intel8x0_free(struct intel8x0 *chip)
2609{
2610 unsigned int i;
2611
2612 if (chip->irq < 0)
2613 goto __hw_end;
2614 /* disable interrupts */
2615 for (i = 0; i < chip->bdbars_count; i++)
2616 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2617 /* reset channels */
2618 for (i = 0; i < chip->bdbars_count; i++)
2619 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2620 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2621 /* stop the spdif interrupt */
2622 unsigned int val;
2623 pci_read_config_dword(chip->pci, 0x4c, &val);
2624 val &= ~0x1000000;
2625 pci_write_config_dword(chip->pci, 0x4c, val);
2626 }
2627 /* --- */
2628
2629 __hw_end:
2630 if (chip->irq >= 0)
2631 free_irq(chip->irq, chip);
2632 if (chip->bdbars.area) {
2633 if (chip->fix_nocache)
2634 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2635 snd_dma_free_pages(&chip->bdbars);
2636 }
2637 if (chip->addr)
2638 pci_iounmap(chip->pci, chip->addr);
2639 if (chip->bmaddr)
2640 pci_iounmap(chip->pci, chip->bmaddr);
2641 pci_release_regions(chip->pci);
2642 pci_disable_device(chip->pci);
2643 kfree(chip);
2644 return 0;
2645}
2646
2647#ifdef CONFIG_PM_SLEEP
2648/*
2649 * power management
2650 */
2651static int intel8x0_suspend(struct device *dev)
2652{
2653 struct snd_card *card = dev_get_drvdata(dev);
2654 struct intel8x0 *chip = card->private_data;
2655 int i;
2656
2657 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2658 for (i = 0; i < chip->pcm_devs; i++)
2659 snd_pcm_suspend_all(chip->pcm[i]);
2660 /* clear nocache */
2661 if (chip->fix_nocache) {
2662 for (i = 0; i < chip->bdbars_count; i++) {
2663 struct ichdev *ichdev = &chip->ichd[i];
2664 if (ichdev->substream && ichdev->page_attr_changed) {
2665 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2666 if (runtime->dma_area)
2667 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2668 }
2669 }
2670 }
2671 for (i = 0; i < chip->ncodecs; i++)
2672 snd_ac97_suspend(chip->ac97[i]);
2673 if (chip->device_type == DEVICE_INTEL_ICH4)
2674 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2675
2676 if (chip->irq >= 0) {
2677 free_irq(chip->irq, chip);
2678 chip->irq = -1;
2679 }
2680 return 0;
2681}
2682
2683static int intel8x0_resume(struct device *dev)
2684{
2685 struct pci_dev *pci = to_pci_dev(dev);
2686 struct snd_card *card = dev_get_drvdata(dev);
2687 struct intel8x0 *chip = card->private_data;
2688 int i;
2689
2690 snd_intel8x0_chip_init(chip, 0);
2691 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2692 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2693 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2694 pci->irq);
2695 snd_card_disconnect(card);
2696 return -EIO;
2697 }
2698 chip->irq = pci->irq;
2699 synchronize_irq(chip->irq);
2700
2701 /* re-initialize mixer stuff */
2702 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2703 /* enable separate SDINs for ICH4 */
2704 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2705 /* use slot 10/11 for SPDIF */
2706 iputdword(chip, ICHREG(GLOB_CNT),
2707 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2708 ICH_PCM_SPDIF_1011);
2709 }
2710
2711 /* refill nocache */
2712 if (chip->fix_nocache)
2713 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2714
2715 for (i = 0; i < chip->ncodecs; i++)
2716 snd_ac97_resume(chip->ac97[i]);
2717
2718 /* refill nocache */
2719 if (chip->fix_nocache) {
2720 for (i = 0; i < chip->bdbars_count; i++) {
2721 struct ichdev *ichdev = &chip->ichd[i];
2722 if (ichdev->substream && ichdev->page_attr_changed) {
2723 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2724 if (runtime->dma_area)
2725 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2726 }
2727 }
2728 }
2729
2730 /* resume status */
2731 for (i = 0; i < chip->bdbars_count; i++) {
2732 struct ichdev *ichdev = &chip->ichd[i];
2733 unsigned long port = ichdev->reg_offset;
2734 if (! ichdev->substream || ! ichdev->suspended)
2735 continue;
2736 if (ichdev->ichd == ICHD_PCMOUT)
2737 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2738 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2739 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2740 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2741 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2742 }
2743
2744 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2745 return 0;
2746}
2747
2748static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2749#define INTEL8X0_PM_OPS &intel8x0_pm
2750#else
2751#define INTEL8X0_PM_OPS NULL
2752#endif /* CONFIG_PM_SLEEP */
2753
2754#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2755
2756static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2757{
2758 struct snd_pcm_substream *subs;
2759 struct ichdev *ichdev;
2760 unsigned long port;
2761 unsigned long pos, pos1, t;
2762 int civ, timeout = 1000, attempt = 1;
2763 ktime_t start_time, stop_time;
2764
2765 if (chip->ac97_bus->clock != 48000)
2766 return; /* specified in module option */
2767
2768 __again:
2769 subs = chip->pcm[0]->streams[0].substream;
2770 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2771 dev_warn(chip->card->dev,
2772 "no playback buffer allocated - aborting measure ac97 clock\n");
2773 return;
2774 }
2775 ichdev = &chip->ichd[ICHD_PCMOUT];
2776 ichdev->physbuf = subs->dma_buffer.addr;
2777 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2778 ichdev->substream = NULL; /* don't process interrupts */
2779
2780 /* set rate */
2781 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2782 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2783 chip->ac97_bus->clock);
2784 return;
2785 }
2786 snd_intel8x0_setup_periods(chip, ichdev);
2787 port = ichdev->reg_offset;
2788 spin_lock_irq(&chip->reg_lock);
2789 chip->in_measurement = 1;
2790 /* trigger */
2791 if (chip->device_type != DEVICE_ALI)
2792 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2793 else {
2794 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2795 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2796 }
2797 start_time = ktime_get();
2798 spin_unlock_irq(&chip->reg_lock);
2799 msleep(50);
2800 spin_lock_irq(&chip->reg_lock);
2801 /* check the position */
2802 do {
2803 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2804 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2805 if (pos1 == 0) {
2806 udelay(10);
2807 continue;
2808 }
2809 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2810 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2811 break;
2812 } while (timeout--);
2813 if (pos1 == 0) { /* oops, this value is not reliable */
2814 pos = 0;
2815 } else {
2816 pos = ichdev->fragsize1;
2817 pos -= pos1 << ichdev->pos_shift;
2818 pos += ichdev->position;
2819 }
2820 chip->in_measurement = 0;
2821 stop_time = ktime_get();
2822 /* stop */
2823 if (chip->device_type == DEVICE_ALI) {
2824 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2825 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2826 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2827 ;
2828 } else {
2829 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2830 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2831 ;
2832 }
2833 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2834 spin_unlock_irq(&chip->reg_lock);
2835
2836 if (pos == 0) {
2837 dev_err(chip->card->dev,
2838 "measure - unreliable DMA position..\n");
2839 __retry:
2840 if (attempt < 3) {
2841 msleep(300);
2842 attempt++;
2843 goto __again;
2844 }
2845 goto __end;
2846 }
2847
2848 pos /= 4;
2849 t = ktime_us_delta(stop_time, start_time);
2850 dev_info(chip->card->dev,
2851 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2852 if (t == 0) {
2853 dev_err(chip->card->dev, "?? calculation error..\n");
2854 goto __retry;
2855 }
2856 pos *= 1000;
2857 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2858 if (pos < 40000 || pos >= 60000) {
2859 /* abnormal value. hw problem? */
2860 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2861 goto __retry;
2862 } else if (pos > 40500 && pos < 41500)
2863 /* first exception - 41000Hz reference clock */
2864 chip->ac97_bus->clock = 41000;
2865 else if (pos > 43600 && pos < 44600)
2866 /* second exception - 44100HZ reference clock */
2867 chip->ac97_bus->clock = 44100;
2868 else if (pos < 47500 || pos > 48500)
2869 /* not 48000Hz, tuning the clock.. */
2870 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2871 __end:
2872 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2873 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2874}
2875
2876static struct snd_pci_quirk intel8x0_clock_list[] = {
2877 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2878 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2879 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2880 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2881 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2882 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2883 { } /* terminator */
2884};
2885
2886static int intel8x0_in_clock_list(struct intel8x0 *chip)
2887{
2888 struct pci_dev *pci = chip->pci;
2889 const struct snd_pci_quirk *wl;
2890
2891 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2892 if (!wl)
2893 return 0;
2894 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2895 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2896 chip->ac97_bus->clock = wl->value;
2897 return 1;
2898}
2899
2900static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2901 struct snd_info_buffer *buffer)
2902{
2903 struct intel8x0 *chip = entry->private_data;
2904 unsigned int tmp;
2905
2906 snd_iprintf(buffer, "Intel8x0\n\n");
2907 if (chip->device_type == DEVICE_ALI)
2908 return;
2909 tmp = igetdword(chip, ICHREG(GLOB_STA));
2910 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2911 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2912 if (chip->device_type == DEVICE_INTEL_ICH4)
2913 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2914 snd_iprintf(buffer, "AC'97 codecs ready :");
2915 if (tmp & chip->codec_isr_bits) {
2916 int i;
2917 static const char *codecs[3] = {
2918 "primary", "secondary", "tertiary"
2919 };
2920 for (i = 0; i < chip->max_codecs; i++)
2921 if (tmp & chip->codec_bit[i])
2922 snd_iprintf(buffer, " %s", codecs[i]);
2923 } else
2924 snd_iprintf(buffer, " none");
2925 snd_iprintf(buffer, "\n");
2926 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2927 chip->device_type == DEVICE_SIS)
2928 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2929 chip->ac97_sdin[0],
2930 chip->ac97_sdin[1],
2931 chip->ac97_sdin[2]);
2932}
2933
2934static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2935{
2936 struct snd_info_entry *entry;
2937
2938 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2939 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2940}
2941
2942static int snd_intel8x0_dev_free(struct snd_device *device)
2943{
2944 struct intel8x0 *chip = device->device_data;
2945 return snd_intel8x0_free(chip);
2946}
2947
2948struct ich_reg_info {
2949 unsigned int int_sta_mask;
2950 unsigned int offset;
2951};
2952
2953static unsigned int ich_codec_bits[3] = {
2954 ICH_PCR, ICH_SCR, ICH_TCR
2955};
2956static unsigned int sis_codec_bits[3] = {
2957 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2958};
2959
2960static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2961{
2962 int result = inside_vm;
2963 char *msg = NULL;
2964
2965 /* check module parameter first (override detection) */
2966 if (result >= 0) {
2967 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2968 goto fini;
2969 }
2970
2971 /* check for known (emulated) devices */
2972 result = 0;
2973 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2974 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2975 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2976 msg = "enable KVM";
2977 result = 1;
2978 } else if (pci->subsystem_vendor == 0x1ab8) {
2979 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2980 msg = "enable Parallels VM";
2981 result = 1;
2982 }
2983
2984fini:
2985 if (msg != NULL)
2986 dev_info(&pci->dev, "%s optimization\n", msg);
2987
2988 return result;
2989}
2990
2991static int snd_intel8x0_create(struct snd_card *card,
2992 struct pci_dev *pci,
2993 unsigned long device_type,
2994 struct intel8x0 **r_intel8x0)
2995{
2996 struct intel8x0 *chip;
2997 int err;
2998 unsigned int i;
2999 unsigned int int_sta_masks;
3000 struct ichdev *ichdev;
3001 static struct snd_device_ops ops = {
3002 .dev_free = snd_intel8x0_dev_free,
3003 };
3004
3005 static unsigned int bdbars[] = {
3006 3, /* DEVICE_INTEL */
3007 6, /* DEVICE_INTEL_ICH4 */
3008 3, /* DEVICE_SIS */
3009 6, /* DEVICE_ALI */
3010 4, /* DEVICE_NFORCE */
3011 };
3012 static struct ich_reg_info intel_regs[6] = {
3013 { ICH_PIINT, 0 },
3014 { ICH_POINT, 0x10 },
3015 { ICH_MCINT, 0x20 },
3016 { ICH_M2INT, 0x40 },
3017 { ICH_P2INT, 0x50 },
3018 { ICH_SPINT, 0x60 },
3019 };
3020 static struct ich_reg_info nforce_regs[4] = {
3021 { ICH_PIINT, 0 },
3022 { ICH_POINT, 0x10 },
3023 { ICH_MCINT, 0x20 },
3024 { ICH_NVSPINT, 0x70 },
3025 };
3026 static struct ich_reg_info ali_regs[6] = {
3027 { ALI_INT_PCMIN, 0x40 },
3028 { ALI_INT_PCMOUT, 0x50 },
3029 { ALI_INT_MICIN, 0x60 },
3030 { ALI_INT_CODECSPDIFOUT, 0x70 },
3031 { ALI_INT_SPDIFIN, 0xa0 },
3032 { ALI_INT_SPDIFOUT, 0xb0 },
3033 };
3034 struct ich_reg_info *tbl;
3035
3036 *r_intel8x0 = NULL;
3037
3038 if ((err = pci_enable_device(pci)) < 0)
3039 return err;
3040
3041 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3042 if (chip == NULL) {
3043 pci_disable_device(pci);
3044 return -ENOMEM;
3045 }
3046 spin_lock_init(&chip->reg_lock);
3047 chip->device_type = device_type;
3048 chip->card = card;
3049 chip->pci = pci;
3050 chip->irq = -1;
3051
3052 /* module parameters */
3053 chip->buggy_irq = buggy_irq;
3054 chip->buggy_semaphore = buggy_semaphore;
3055 if (xbox)
3056 chip->xbox = 1;
3057
3058 chip->inside_vm = snd_intel8x0_inside_vm(pci);
3059
3060 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3061 pci->device == PCI_DEVICE_ID_INTEL_440MX)
3062 chip->fix_nocache = 1; /* enable workaround */
3063
3064 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3065 kfree(chip);
3066 pci_disable_device(pci);
3067 return err;
3068 }
3069
3070 if (device_type == DEVICE_ALI) {
3071 /* ALI5455 has no ac97 region */
3072 chip->bmaddr = pci_iomap(pci, 0, 0);
3073 goto port_inited;
3074 }
3075
3076 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3077 chip->addr = pci_iomap(pci, 2, 0);
3078 else
3079 chip->addr = pci_iomap(pci, 0, 0);
3080 if (!chip->addr) {
3081 dev_err(card->dev, "AC'97 space ioremap problem\n");
3082 snd_intel8x0_free(chip);
3083 return -EIO;
3084 }
3085 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3086 chip->bmaddr = pci_iomap(pci, 3, 0);
3087 else
3088 chip->bmaddr = pci_iomap(pci, 1, 0);
3089
3090 port_inited:
3091 if (!chip->bmaddr) {
3092 dev_err(card->dev, "Controller space ioremap problem\n");
3093 snd_intel8x0_free(chip);
3094 return -EIO;
3095 }
3096 chip->bdbars_count = bdbars[device_type];
3097
3098 /* initialize offsets */
3099 switch (device_type) {
3100 case DEVICE_NFORCE:
3101 tbl = nforce_regs;
3102 break;
3103 case DEVICE_ALI:
3104 tbl = ali_regs;
3105 break;
3106 default:
3107 tbl = intel_regs;
3108 break;
3109 }
3110 for (i = 0; i < chip->bdbars_count; i++) {
3111 ichdev = &chip->ichd[i];
3112 ichdev->ichd = i;
3113 ichdev->reg_offset = tbl[i].offset;
3114 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3115 if (device_type == DEVICE_SIS) {
3116 /* SiS 7012 swaps the registers */
3117 ichdev->roff_sr = ICH_REG_OFF_PICB;
3118 ichdev->roff_picb = ICH_REG_OFF_SR;
3119 } else {
3120 ichdev->roff_sr = ICH_REG_OFF_SR;
3121 ichdev->roff_picb = ICH_REG_OFF_PICB;
3122 }
3123 if (device_type == DEVICE_ALI)
3124 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3125 /* SIS7012 handles the pcm data in bytes, others are in samples */
3126 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3127 }
3128
3129 /* allocate buffer descriptor lists */
3130 /* the start of each lists must be aligned to 8 bytes */
3131 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3132 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3133 &chip->bdbars) < 0) {
3134 snd_intel8x0_free(chip);
3135 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3136 return -ENOMEM;
3137 }
3138 /* tables must be aligned to 8 bytes here, but the kernel pages
3139 are much bigger, so we don't care (on i386) */
3140 /* workaround for 440MX */
3141 if (chip->fix_nocache)
3142 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3143 int_sta_masks = 0;
3144 for (i = 0; i < chip->bdbars_count; i++) {
3145 ichdev = &chip->ichd[i];
3146 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3147 (i * ICH_MAX_FRAGS * 2);
3148 ichdev->bdbar_addr = chip->bdbars.addr +
3149 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3150 int_sta_masks |= ichdev->int_sta_mask;
3151 }
3152 chip->int_sta_reg = device_type == DEVICE_ALI ?
3153 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3154 chip->int_sta_mask = int_sta_masks;
3155
3156 pci_set_master(pci);
3157
3158 switch(chip->device_type) {
3159 case DEVICE_INTEL_ICH4:
3160 /* ICH4 can have three codecs */
3161 chip->max_codecs = 3;
3162 chip->codec_bit = ich_codec_bits;
3163 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3164 break;
3165 case DEVICE_SIS:
3166 /* recent SIS7012 can have three codecs */
3167 chip->max_codecs = 3;
3168 chip->codec_bit = sis_codec_bits;
3169 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3170 break;
3171 default:
3172 /* others up to two codecs */
3173 chip->max_codecs = 2;
3174 chip->codec_bit = ich_codec_bits;
3175 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3176 break;
3177 }
3178 for (i = 0; i < chip->max_codecs; i++)
3179 chip->codec_isr_bits |= chip->codec_bit[i];
3180
3181 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3182 snd_intel8x0_free(chip);
3183 return err;
3184 }
3185
3186 /* request irq after initializaing int_sta_mask, etc */
3187 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3188 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3189 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3190 snd_intel8x0_free(chip);
3191 return -EBUSY;
3192 }
3193 chip->irq = pci->irq;
3194
3195 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3196 snd_intel8x0_free(chip);
3197 return err;
3198 }
3199
3200 *r_intel8x0 = chip;
3201 return 0;
3202}
3203
3204static struct shortname_table {
3205 unsigned int id;
3206 const char *s;
3207} shortnames[] = {
3208 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3209 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3210 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3211 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3212 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3213 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3214 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3215 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3216 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3217 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3218 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3219 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3220 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3221 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3222 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3223 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3224 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3225 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3226 { 0x003a, "NVidia MCP04" },
3227 { 0x746d, "AMD AMD8111" },
3228 { 0x7445, "AMD AMD768" },
3229 { 0x5455, "ALi M5455" },
3230 { 0, NULL },
3231};
3232
3233static struct snd_pci_quirk spdif_aclink_defaults[] = {
3234 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3235 { } /* end */
3236};
3237
3238/* look up white/black list for SPDIF over ac-link */
3239static int check_default_spdif_aclink(struct pci_dev *pci)
3240{
3241 const struct snd_pci_quirk *w;
3242
3243 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3244 if (w) {
3245 if (w->value)
3246 dev_dbg(&pci->dev,
3247 "Using SPDIF over AC-Link for %s\n",
3248 snd_pci_quirk_name(w));
3249 else
3250 dev_dbg(&pci->dev,
3251 "Using integrated SPDIF DMA for %s\n",
3252 snd_pci_quirk_name(w));
3253 return w->value;
3254 }
3255 return 0;
3256}
3257
3258static int snd_intel8x0_probe(struct pci_dev *pci,
3259 const struct pci_device_id *pci_id)
3260{
3261 struct snd_card *card;
3262 struct intel8x0 *chip;
3263 int err;
3264 struct shortname_table *name;
3265
3266 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3267 if (err < 0)
3268 return err;
3269
3270 if (spdif_aclink < 0)
3271 spdif_aclink = check_default_spdif_aclink(pci);
3272
3273 strcpy(card->driver, "ICH");
3274 if (!spdif_aclink) {
3275 switch (pci_id->driver_data) {
3276 case DEVICE_NFORCE:
3277 strcpy(card->driver, "NFORCE");
3278 break;
3279 case DEVICE_INTEL_ICH4:
3280 strcpy(card->driver, "ICH4");
3281 }
3282 }
3283
3284 strcpy(card->shortname, "Intel ICH");
3285 for (name = shortnames; name->id; name++) {
3286 if (pci->device == name->id) {
3287 strcpy(card->shortname, name->s);
3288 break;
3289 }
3290 }
3291
3292 if (buggy_irq < 0) {
3293 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3294 * Needs to return IRQ_HANDLED for unknown irqs.
3295 */
3296 if (pci_id->driver_data == DEVICE_NFORCE)
3297 buggy_irq = 1;
3298 else
3299 buggy_irq = 0;
3300 }
3301
3302 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3303 &chip)) < 0) {
3304 snd_card_free(card);
3305 return err;
3306 }
3307 card->private_data = chip;
3308
3309 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3310 snd_card_free(card);
3311 return err;
3312 }
3313 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3314 snd_card_free(card);
3315 return err;
3316 }
3317
3318 snd_intel8x0_proc_init(chip);
3319
3320 snprintf(card->longname, sizeof(card->longname),
3321 "%s with %s at irq %i", card->shortname,
3322 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3323
3324 if (ac97_clock == 0 || ac97_clock == 1) {
3325 if (ac97_clock == 0) {
3326 if (intel8x0_in_clock_list(chip) == 0)
3327 intel8x0_measure_ac97_clock(chip);
3328 } else {
3329 intel8x0_measure_ac97_clock(chip);
3330 }
3331 }
3332
3333 if ((err = snd_card_register(card)) < 0) {
3334 snd_card_free(card);
3335 return err;
3336 }
3337 pci_set_drvdata(pci, card);
3338 return 0;
3339}
3340
3341static void snd_intel8x0_remove(struct pci_dev *pci)
3342{
3343 snd_card_free(pci_get_drvdata(pci));
3344}
3345
3346static struct pci_driver intel8x0_driver = {
3347 .name = KBUILD_MODNAME,
3348 .id_table = snd_intel8x0_ids,
3349 .probe = snd_intel8x0_probe,
3350 .remove = snd_intel8x0_remove,
3351 .driver = {
3352 .pm = INTEL8X0_PM_OPS,
3353 },
3354};
3355
3356module_pci_driver(intel8x0_driver);