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1/*
2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (C) 2013 NVIDIA Corporation
4 *
5 * Author:
6 * Erik Gilling <konkers@google.com>
7 * Benoit Goby <benoit@android.com>
8 * Venu Byravarasu <vbyravarasu@nvidia.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/resource.h>
22#include <linux/delay.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/export.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <linux/usb/of.h>
36#include <linux/usb/ehci_def.h>
37#include <linux/usb/tegra_usb_phy.h>
38#include <linux/regulator/consumer.h>
39
40#define ULPI_VIEWPORT 0x170
41
42/* PORTSC PTS/PHCD bits, Tegra20 only */
43#define TEGRA_USB_PORTSC1 0x184
44#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
45#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
46
47/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
48#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
49#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
50#define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22)
51
52/* Bits of PORTSC1, which will get cleared by writing 1 into them */
53#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
54
55#define USB_SUSP_CTRL 0x400
56#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
57#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
58#define USB_SUSP_CLR (1 << 5)
59#define USB_PHY_CLK_VALID (1 << 7)
60#define UTMIP_RESET (1 << 11)
61#define UHSIC_RESET (1 << 11)
62#define UTMIP_PHY_ENABLE (1 << 12)
63#define ULPI_PHY_ENABLE (1 << 13)
64#define USB_SUSP_SET (1 << 14)
65#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
66
67#define USB1_LEGACY_CTRL 0x410
68#define USB1_NO_LEGACY_MODE (1 << 0)
69#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
70#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
71#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
72 (1 << 1)
73#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
74#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
75
76#define ULPI_TIMING_CTRL_0 0x424
77#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
78#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
79
80#define ULPI_TIMING_CTRL_1 0x428
81#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
82#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
83#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
84#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
85#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
86#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
87
88#define UTMIP_PLL_CFG1 0x804
89#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
90#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
91
92#define UTMIP_XCVR_CFG0 0x808
93#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
94#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
95#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
96#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
97#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
98#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
99#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
100#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
101#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
102#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
103
104#define UTMIP_BIAS_CFG0 0x80c
105#define UTMIP_OTGPD (1 << 11)
106#define UTMIP_BIASPD (1 << 10)
107#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
108#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
109#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
110
111#define UTMIP_HSRX_CFG0 0x810
112#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
113#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
114
115#define UTMIP_HSRX_CFG1 0x814
116#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
117
118#define UTMIP_TX_CFG0 0x820
119#define UTMIP_FS_PREABMLE_J (1 << 19)
120#define UTMIP_HS_DISCON_DISABLE (1 << 8)
121
122#define UTMIP_MISC_CFG0 0x824
123#define UTMIP_DPDM_OBSERVE (1 << 26)
124#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
125#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
126#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
127#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
128#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
129#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
130
131#define UTMIP_MISC_CFG1 0x828
132#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
133#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
134
135#define UTMIP_DEBOUNCE_CFG0 0x82c
136#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
137
138#define UTMIP_BAT_CHRG_CFG0 0x830
139#define UTMIP_PD_CHRG (1 << 0)
140
141#define UTMIP_SPARE_CFG0 0x834
142#define FUSE_SETUP_SEL (1 << 3)
143
144#define UTMIP_XCVR_CFG1 0x838
145#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
146#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
147#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
148#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
149
150#define UTMIP_BIAS_CFG1 0x83c
151#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
152
153/* For Tegra30 and above only, the address is different in Tegra20 */
154#define USB_USBMODE 0x1f8
155#define USB_USBMODE_MASK (3 << 0)
156#define USB_USBMODE_HOST (3 << 0)
157#define USB_USBMODE_DEVICE (2 << 0)
158
159static DEFINE_SPINLOCK(utmip_pad_lock);
160static int utmip_pad_count;
161
162struct tegra_xtal_freq {
163 int freq;
164 u8 enable_delay;
165 u8 stable_count;
166 u8 active_delay;
167 u8 xtal_freq_count;
168 u16 debounce;
169};
170
171static const struct tegra_xtal_freq tegra_freq_table[] = {
172 {
173 .freq = 12000000,
174 .enable_delay = 0x02,
175 .stable_count = 0x2F,
176 .active_delay = 0x04,
177 .xtal_freq_count = 0x76,
178 .debounce = 0x7530,
179 },
180 {
181 .freq = 13000000,
182 .enable_delay = 0x02,
183 .stable_count = 0x33,
184 .active_delay = 0x05,
185 .xtal_freq_count = 0x7F,
186 .debounce = 0x7EF4,
187 },
188 {
189 .freq = 19200000,
190 .enable_delay = 0x03,
191 .stable_count = 0x4B,
192 .active_delay = 0x06,
193 .xtal_freq_count = 0xBB,
194 .debounce = 0xBB80,
195 },
196 {
197 .freq = 26000000,
198 .enable_delay = 0x04,
199 .stable_count = 0x66,
200 .active_delay = 0x09,
201 .xtal_freq_count = 0xFE,
202 .debounce = 0xFDE8,
203 },
204};
205
206static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
207{
208 void __iomem *base = phy->regs;
209 unsigned long val;
210
211 if (phy->soc_config->has_hostpc) {
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
216 } else {
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
220 writel(val, base + TEGRA_USB_PORTSC1);
221 }
222}
223
224static void set_phcd(struct tegra_usb_phy *phy, bool enable)
225{
226 void __iomem *base = phy->regs;
227 unsigned long val;
228
229 if (phy->soc_config->has_hostpc) {
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
231 if (enable)
232 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
233 else
234 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
236 } else {
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
238 if (enable)
239 val |= TEGRA_USB_PORTSC1_PHCD;
240 else
241 val &= ~TEGRA_USB_PORTSC1_PHCD;
242 writel(val, base + TEGRA_USB_PORTSC1);
243 }
244}
245
246static int utmip_pad_open(struct tegra_usb_phy *phy)
247{
248 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
249 if (IS_ERR(phy->pad_clk)) {
250 pr_err("%s: can't get utmip pad clock\n", __func__);
251 return PTR_ERR(phy->pad_clk);
252 }
253
254 return 0;
255}
256
257static void utmip_pad_power_on(struct tegra_usb_phy *phy)
258{
259 unsigned long val, flags;
260 void __iomem *base = phy->pad_regs;
261 struct tegra_utmip_config *config = phy->config;
262
263 clk_prepare_enable(phy->pad_clk);
264
265 spin_lock_irqsave(&utmip_pad_lock, flags);
266
267 if (utmip_pad_count++ == 0) {
268 val = readl(base + UTMIP_BIAS_CFG0);
269 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
270
271 if (phy->soc_config->requires_extra_tuning_parameters) {
272 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
273 UTMIP_HSDISCON_LEVEL(~0) |
274 UTMIP_HSDISCON_LEVEL_MSB(~0));
275
276 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
277 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
278 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
279 }
280 writel(val, base + UTMIP_BIAS_CFG0);
281 }
282
283 spin_unlock_irqrestore(&utmip_pad_lock, flags);
284
285 clk_disable_unprepare(phy->pad_clk);
286}
287
288static int utmip_pad_power_off(struct tegra_usb_phy *phy)
289{
290 unsigned long val, flags;
291 void __iomem *base = phy->pad_regs;
292
293 if (!utmip_pad_count) {
294 pr_err("%s: utmip pad already powered off\n", __func__);
295 return -EINVAL;
296 }
297
298 clk_prepare_enable(phy->pad_clk);
299
300 spin_lock_irqsave(&utmip_pad_lock, flags);
301
302 if (--utmip_pad_count == 0) {
303 val = readl(base + UTMIP_BIAS_CFG0);
304 val |= UTMIP_OTGPD | UTMIP_BIASPD;
305 writel(val, base + UTMIP_BIAS_CFG0);
306 }
307
308 spin_unlock_irqrestore(&utmip_pad_lock, flags);
309
310 clk_disable_unprepare(phy->pad_clk);
311
312 return 0;
313}
314
315static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
316{
317 unsigned long timeout = 2000;
318 do {
319 if ((readl(reg) & mask) == result)
320 return 0;
321 udelay(1);
322 timeout--;
323 } while (timeout);
324 return -1;
325}
326
327static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
328{
329 unsigned long val;
330 void __iomem *base = phy->regs;
331
332 if (phy->is_legacy_phy) {
333 val = readl(base + USB_SUSP_CTRL);
334 val |= USB_SUSP_SET;
335 writel(val, base + USB_SUSP_CTRL);
336
337 udelay(10);
338
339 val = readl(base + USB_SUSP_CTRL);
340 val &= ~USB_SUSP_SET;
341 writel(val, base + USB_SUSP_CTRL);
342 } else
343 set_phcd(phy, true);
344
345 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
346 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
347}
348
349static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
350{
351 unsigned long val;
352 void __iomem *base = phy->regs;
353
354 if (phy->is_legacy_phy) {
355 val = readl(base + USB_SUSP_CTRL);
356 val |= USB_SUSP_CLR;
357 writel(val, base + USB_SUSP_CTRL);
358
359 udelay(10);
360
361 val = readl(base + USB_SUSP_CTRL);
362 val &= ~USB_SUSP_CLR;
363 writel(val, base + USB_SUSP_CTRL);
364 } else
365 set_phcd(phy, false);
366
367 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
368 USB_PHY_CLK_VALID))
369 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
370}
371
372static int utmi_phy_power_on(struct tegra_usb_phy *phy)
373{
374 unsigned long val;
375 void __iomem *base = phy->regs;
376 struct tegra_utmip_config *config = phy->config;
377
378 val = readl(base + USB_SUSP_CTRL);
379 val |= UTMIP_RESET;
380 writel(val, base + USB_SUSP_CTRL);
381
382 if (phy->is_legacy_phy) {
383 val = readl(base + USB1_LEGACY_CTRL);
384 val |= USB1_NO_LEGACY_MODE;
385 writel(val, base + USB1_LEGACY_CTRL);
386 }
387
388 val = readl(base + UTMIP_TX_CFG0);
389 val |= UTMIP_FS_PREABMLE_J;
390 writel(val, base + UTMIP_TX_CFG0);
391
392 val = readl(base + UTMIP_HSRX_CFG0);
393 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
394 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
395 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
396 writel(val, base + UTMIP_HSRX_CFG0);
397
398 val = readl(base + UTMIP_HSRX_CFG1);
399 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
400 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
401 writel(val, base + UTMIP_HSRX_CFG1);
402
403 val = readl(base + UTMIP_DEBOUNCE_CFG0);
404 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
405 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
406 writel(val, base + UTMIP_DEBOUNCE_CFG0);
407
408 val = readl(base + UTMIP_MISC_CFG0);
409 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
410 writel(val, base + UTMIP_MISC_CFG0);
411
412 if (!phy->soc_config->utmi_pll_config_in_car_module) {
413 val = readl(base + UTMIP_MISC_CFG1);
414 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
415 UTMIP_PLLU_STABLE_COUNT(~0));
416 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
417 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
418 writel(val, base + UTMIP_MISC_CFG1);
419
420 val = readl(base + UTMIP_PLL_CFG1);
421 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
422 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
423 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
424 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
425 writel(val, base + UTMIP_PLL_CFG1);
426 }
427
428 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
429 val = readl(base + USB_SUSP_CTRL);
430 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
431 writel(val, base + USB_SUSP_CTRL);
432
433 val = readl(base + UTMIP_BAT_CHRG_CFG0);
434 val &= ~UTMIP_PD_CHRG;
435 writel(val, base + UTMIP_BAT_CHRG_CFG0);
436 } else {
437 val = readl(base + UTMIP_BAT_CHRG_CFG0);
438 val |= UTMIP_PD_CHRG;
439 writel(val, base + UTMIP_BAT_CHRG_CFG0);
440 }
441
442 utmip_pad_power_on(phy);
443
444 val = readl(base + UTMIP_XCVR_CFG0);
445 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
446 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
447 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
448 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
449
450 if (!config->xcvr_setup_use_fuses) {
451 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
452 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
453 }
454 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
455 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
456
457 if (phy->soc_config->requires_extra_tuning_parameters) {
458 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
459 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
460 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
461 }
462 writel(val, base + UTMIP_XCVR_CFG0);
463
464 val = readl(base + UTMIP_XCVR_CFG1);
465 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
466 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
467 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
468 writel(val, base + UTMIP_XCVR_CFG1);
469
470 val = readl(base + UTMIP_BIAS_CFG1);
471 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
472 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
473 writel(val, base + UTMIP_BIAS_CFG1);
474
475 val = readl(base + UTMIP_SPARE_CFG0);
476 if (config->xcvr_setup_use_fuses)
477 val |= FUSE_SETUP_SEL;
478 else
479 val &= ~FUSE_SETUP_SEL;
480 writel(val, base + UTMIP_SPARE_CFG0);
481
482 if (!phy->is_legacy_phy) {
483 val = readl(base + USB_SUSP_CTRL);
484 val |= UTMIP_PHY_ENABLE;
485 writel(val, base + USB_SUSP_CTRL);
486 }
487
488 val = readl(base + USB_SUSP_CTRL);
489 val &= ~UTMIP_RESET;
490 writel(val, base + USB_SUSP_CTRL);
491
492 if (phy->is_legacy_phy) {
493 val = readl(base + USB1_LEGACY_CTRL);
494 val &= ~USB1_VBUS_SENSE_CTL_MASK;
495 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
496 writel(val, base + USB1_LEGACY_CTRL);
497
498 val = readl(base + USB_SUSP_CTRL);
499 val &= ~USB_SUSP_SET;
500 writel(val, base + USB_SUSP_CTRL);
501 }
502
503 utmi_phy_clk_enable(phy);
504
505 if (phy->soc_config->requires_usbmode_setup) {
506 val = readl(base + USB_USBMODE);
507 val &= ~USB_USBMODE_MASK;
508 if (phy->mode == USB_DR_MODE_HOST)
509 val |= USB_USBMODE_HOST;
510 else
511 val |= USB_USBMODE_DEVICE;
512 writel(val, base + USB_USBMODE);
513 }
514
515 if (!phy->is_legacy_phy)
516 set_pts(phy, 0);
517
518 return 0;
519}
520
521static int utmi_phy_power_off(struct tegra_usb_phy *phy)
522{
523 unsigned long val;
524 void __iomem *base = phy->regs;
525
526 utmi_phy_clk_disable(phy);
527
528 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
529 val = readl(base + USB_SUSP_CTRL);
530 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
531 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
532 writel(val, base + USB_SUSP_CTRL);
533 }
534
535 val = readl(base + USB_SUSP_CTRL);
536 val |= UTMIP_RESET;
537 writel(val, base + USB_SUSP_CTRL);
538
539 val = readl(base + UTMIP_BAT_CHRG_CFG0);
540 val |= UTMIP_PD_CHRG;
541 writel(val, base + UTMIP_BAT_CHRG_CFG0);
542
543 val = readl(base + UTMIP_XCVR_CFG0);
544 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
545 UTMIP_FORCE_PDZI_POWERDOWN;
546 writel(val, base + UTMIP_XCVR_CFG0);
547
548 val = readl(base + UTMIP_XCVR_CFG1);
549 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
550 UTMIP_FORCE_PDDR_POWERDOWN;
551 writel(val, base + UTMIP_XCVR_CFG1);
552
553 return utmip_pad_power_off(phy);
554}
555
556static void utmi_phy_preresume(struct tegra_usb_phy *phy)
557{
558 unsigned long val;
559 void __iomem *base = phy->regs;
560
561 val = readl(base + UTMIP_TX_CFG0);
562 val |= UTMIP_HS_DISCON_DISABLE;
563 writel(val, base + UTMIP_TX_CFG0);
564}
565
566static void utmi_phy_postresume(struct tegra_usb_phy *phy)
567{
568 unsigned long val;
569 void __iomem *base = phy->regs;
570
571 val = readl(base + UTMIP_TX_CFG0);
572 val &= ~UTMIP_HS_DISCON_DISABLE;
573 writel(val, base + UTMIP_TX_CFG0);
574}
575
576static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
577 enum tegra_usb_phy_port_speed port_speed)
578{
579 unsigned long val;
580 void __iomem *base = phy->regs;
581
582 val = readl(base + UTMIP_MISC_CFG0);
583 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
584 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
585 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
586 else
587 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
588 writel(val, base + UTMIP_MISC_CFG0);
589 udelay(1);
590
591 val = readl(base + UTMIP_MISC_CFG0);
592 val |= UTMIP_DPDM_OBSERVE;
593 writel(val, base + UTMIP_MISC_CFG0);
594 udelay(10);
595}
596
597static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
598{
599 unsigned long val;
600 void __iomem *base = phy->regs;
601
602 val = readl(base + UTMIP_MISC_CFG0);
603 val &= ~UTMIP_DPDM_OBSERVE;
604 writel(val, base + UTMIP_MISC_CFG0);
605 udelay(10);
606}
607
608static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
609{
610 int ret;
611 unsigned long val;
612 void __iomem *base = phy->regs;
613
614 ret = gpio_direction_output(phy->reset_gpio, 0);
615 if (ret < 0) {
616 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
617 phy->reset_gpio);
618 return ret;
619 }
620 msleep(5);
621 ret = gpio_direction_output(phy->reset_gpio, 1);
622 if (ret < 0) {
623 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
624 phy->reset_gpio);
625 return ret;
626 }
627
628 clk_prepare_enable(phy->clk);
629 msleep(1);
630
631 val = readl(base + USB_SUSP_CTRL);
632 val |= UHSIC_RESET;
633 writel(val, base + USB_SUSP_CTRL);
634
635 val = readl(base + ULPI_TIMING_CTRL_0);
636 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
637 writel(val, base + ULPI_TIMING_CTRL_0);
638
639 val = readl(base + USB_SUSP_CTRL);
640 val |= ULPI_PHY_ENABLE;
641 writel(val, base + USB_SUSP_CTRL);
642
643 val = 0;
644 writel(val, base + ULPI_TIMING_CTRL_1);
645
646 val |= ULPI_DATA_TRIMMER_SEL(4);
647 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
648 val |= ULPI_DIR_TRIMMER_SEL(4);
649 writel(val, base + ULPI_TIMING_CTRL_1);
650 udelay(10);
651
652 val |= ULPI_DATA_TRIMMER_LOAD;
653 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
654 val |= ULPI_DIR_TRIMMER_LOAD;
655 writel(val, base + ULPI_TIMING_CTRL_1);
656
657 /* Fix VbusInvalid due to floating VBUS */
658 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
659 if (ret) {
660 pr_err("%s: ulpi write failed\n", __func__);
661 return ret;
662 }
663
664 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
665 if (ret) {
666 pr_err("%s: ulpi write failed\n", __func__);
667 return ret;
668 }
669
670 val = readl(base + USB_SUSP_CTRL);
671 val |= USB_SUSP_CLR;
672 writel(val, base + USB_SUSP_CTRL);
673 udelay(100);
674
675 val = readl(base + USB_SUSP_CTRL);
676 val &= ~USB_SUSP_CLR;
677 writel(val, base + USB_SUSP_CTRL);
678
679 return 0;
680}
681
682static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
683{
684 clk_disable(phy->clk);
685 return gpio_direction_output(phy->reset_gpio, 0);
686}
687
688static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
689{
690 if (!IS_ERR(phy->vbus))
691 regulator_disable(phy->vbus);
692
693 clk_disable_unprepare(phy->pll_u);
694}
695
696static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
697{
698 if (phy->is_ulpi_phy)
699 return ulpi_phy_power_on(phy);
700 else
701 return utmi_phy_power_on(phy);
702}
703
704static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
705{
706 if (phy->is_ulpi_phy)
707 return ulpi_phy_power_off(phy);
708 else
709 return utmi_phy_power_off(phy);
710}
711
712static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
713{
714 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
715 if (suspend)
716 return tegra_usb_phy_power_off(phy);
717 else
718 return tegra_usb_phy_power_on(phy);
719}
720
721static int ulpi_open(struct tegra_usb_phy *phy)
722{
723 int err;
724
725 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
726 if (IS_ERR(phy->clk)) {
727 pr_err("%s: can't get ulpi clock\n", __func__);
728 return PTR_ERR(phy->clk);
729 }
730
731 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
732 "ulpi_phy_reset_b");
733 if (err < 0) {
734 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
735 phy->reset_gpio);
736 return err;
737 }
738
739 err = gpio_direction_output(phy->reset_gpio, 0);
740 if (err < 0) {
741 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
742 phy->reset_gpio);
743 return err;
744 }
745
746 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
747 if (!phy->ulpi) {
748 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
749 err = -ENOMEM;
750 return err;
751 }
752
753 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
754 return 0;
755}
756
757static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
758{
759 unsigned long parent_rate;
760 int i;
761 int err;
762
763 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
764 if (IS_ERR(phy->pll_u)) {
765 pr_err("Can't get pll_u clock\n");
766 return PTR_ERR(phy->pll_u);
767 }
768
769 err = clk_prepare_enable(phy->pll_u);
770 if (err)
771 return err;
772
773 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
774 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
775 if (tegra_freq_table[i].freq == parent_rate) {
776 phy->freq = &tegra_freq_table[i];
777 break;
778 }
779 }
780 if (!phy->freq) {
781 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
782 err = -EINVAL;
783 goto fail;
784 }
785
786 if (!IS_ERR(phy->vbus)) {
787 err = regulator_enable(phy->vbus);
788 if (err) {
789 dev_err(phy->u_phy.dev,
790 "failed to enable usb vbus regulator: %d\n",
791 err);
792 goto fail;
793 }
794 }
795
796 if (phy->is_ulpi_phy)
797 err = ulpi_open(phy);
798 else
799 err = utmip_pad_open(phy);
800 if (err < 0)
801 goto fail;
802
803 return 0;
804
805fail:
806 clk_disable_unprepare(phy->pll_u);
807 return err;
808}
809
810void tegra_usb_phy_preresume(struct usb_phy *x)
811{
812 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
813
814 if (!phy->is_ulpi_phy)
815 utmi_phy_preresume(phy);
816}
817EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
818
819void tegra_usb_phy_postresume(struct usb_phy *x)
820{
821 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
822
823 if (!phy->is_ulpi_phy)
824 utmi_phy_postresume(phy);
825}
826EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
827
828void tegra_ehci_phy_restore_start(struct usb_phy *x,
829 enum tegra_usb_phy_port_speed port_speed)
830{
831 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
832
833 if (!phy->is_ulpi_phy)
834 utmi_phy_restore_start(phy, port_speed);
835}
836EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
837
838void tegra_ehci_phy_restore_end(struct usb_phy *x)
839{
840 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
841
842 if (!phy->is_ulpi_phy)
843 utmi_phy_restore_end(phy);
844}
845EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
846
847static int read_utmi_param(struct platform_device *pdev, const char *param,
848 u8 *dest)
849{
850 u32 value;
851 int err = of_property_read_u32(pdev->dev.of_node, param, &value);
852 *dest = (u8)value;
853 if (err < 0)
854 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
855 param, err);
856 return err;
857}
858
859static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
860 struct platform_device *pdev)
861{
862 struct resource *res;
863 int err;
864 struct tegra_utmip_config *config;
865
866 tegra_phy->is_ulpi_phy = false;
867
868 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
869 if (!res) {
870 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
871 return -ENXIO;
872 }
873
874 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
875 resource_size(res));
876 if (!tegra_phy->pad_regs) {
877 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
878 return -ENOMEM;
879 }
880
881 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
882 GFP_KERNEL);
883 if (!tegra_phy->config)
884 return -ENOMEM;
885
886 config = tegra_phy->config;
887
888 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
889 &config->hssync_start_delay);
890 if (err < 0)
891 return err;
892
893 err = read_utmi_param(pdev, "nvidia,elastic-limit",
894 &config->elastic_limit);
895 if (err < 0)
896 return err;
897
898 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
899 &config->idle_wait_delay);
900 if (err < 0)
901 return err;
902
903 err = read_utmi_param(pdev, "nvidia,term-range-adj",
904 &config->term_range_adj);
905 if (err < 0)
906 return err;
907
908 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
909 &config->xcvr_lsfslew);
910 if (err < 0)
911 return err;
912
913 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
914 &config->xcvr_lsrslew);
915 if (err < 0)
916 return err;
917
918 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
919 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
920 &config->xcvr_hsslew);
921 if (err < 0)
922 return err;
923
924 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
925 &config->hssquelch_level);
926 if (err < 0)
927 return err;
928
929 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
930 &config->hsdiscon_level);
931 if (err < 0)
932 return err;
933 }
934
935 config->xcvr_setup_use_fuses = of_property_read_bool(
936 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
937
938 if (!config->xcvr_setup_use_fuses) {
939 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
940 &config->xcvr_setup);
941 if (err < 0)
942 return err;
943 }
944
945 return 0;
946}
947
948static const struct tegra_phy_soc_config tegra20_soc_config = {
949 .utmi_pll_config_in_car_module = false,
950 .has_hostpc = false,
951 .requires_usbmode_setup = false,
952 .requires_extra_tuning_parameters = false,
953};
954
955static const struct tegra_phy_soc_config tegra30_soc_config = {
956 .utmi_pll_config_in_car_module = true,
957 .has_hostpc = true,
958 .requires_usbmode_setup = true,
959 .requires_extra_tuning_parameters = true,
960};
961
962static const struct of_device_id tegra_usb_phy_id_table[] = {
963 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
964 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
965 { },
966};
967MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
968
969static int tegra_usb_phy_probe(struct platform_device *pdev)
970{
971 const struct of_device_id *match;
972 struct resource *res;
973 struct tegra_usb_phy *tegra_phy = NULL;
974 struct device_node *np = pdev->dev.of_node;
975 enum usb_phy_interface phy_type;
976 int err;
977
978 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
979 if (!tegra_phy)
980 return -ENOMEM;
981
982 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
983 if (!match) {
984 dev_err(&pdev->dev, "Error: No device match found\n");
985 return -ENODEV;
986 }
987 tegra_phy->soc_config = match->data;
988
989 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 if (!res) {
991 dev_err(&pdev->dev, "Failed to get I/O memory\n");
992 return -ENXIO;
993 }
994
995 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
996 resource_size(res));
997 if (!tegra_phy->regs) {
998 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
999 return -ENOMEM;
1000 }
1001
1002 tegra_phy->is_legacy_phy =
1003 of_property_read_bool(np, "nvidia,has-legacy-mode");
1004
1005 phy_type = of_usb_get_phy_mode(np);
1006 switch (phy_type) {
1007 case USBPHY_INTERFACE_MODE_UTMI:
1008 err = utmi_phy_probe(tegra_phy, pdev);
1009 if (err < 0)
1010 return err;
1011 break;
1012
1013 case USBPHY_INTERFACE_MODE_ULPI:
1014 tegra_phy->is_ulpi_phy = true;
1015
1016 tegra_phy->reset_gpio =
1017 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1018 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1019 dev_err(&pdev->dev, "invalid gpio: %d\n",
1020 tegra_phy->reset_gpio);
1021 return tegra_phy->reset_gpio;
1022 }
1023 tegra_phy->config = NULL;
1024 break;
1025
1026 default:
1027 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1028 return -EINVAL;
1029 }
1030
1031 if (of_find_property(np, "dr_mode", NULL))
1032 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1033 else
1034 tegra_phy->mode = USB_DR_MODE_HOST;
1035
1036 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1037 dev_err(&pdev->dev, "dr_mode is invalid\n");
1038 return -EINVAL;
1039 }
1040
1041 /* On some boards, the VBUS regulator doesn't need to be controlled */
1042 if (of_find_property(np, "vbus-supply", NULL)) {
1043 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1044 if (IS_ERR(tegra_phy->vbus))
1045 return PTR_ERR(tegra_phy->vbus);
1046 } else {
1047 dev_notice(&pdev->dev, "no vbus regulator");
1048 tegra_phy->vbus = ERR_PTR(-ENODEV);
1049 }
1050
1051 tegra_phy->u_phy.dev = &pdev->dev;
1052 err = tegra_usb_phy_init(tegra_phy);
1053 if (err < 0)
1054 return err;
1055
1056 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1057
1058 platform_set_drvdata(pdev, tegra_phy);
1059
1060 err = usb_add_phy_dev(&tegra_phy->u_phy);
1061 if (err < 0) {
1062 tegra_usb_phy_close(tegra_phy);
1063 return err;
1064 }
1065
1066 return 0;
1067}
1068
1069static int tegra_usb_phy_remove(struct platform_device *pdev)
1070{
1071 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1072
1073 usb_remove_phy(&tegra_phy->u_phy);
1074 tegra_usb_phy_close(tegra_phy);
1075
1076 return 0;
1077}
1078
1079static struct platform_driver tegra_usb_phy_driver = {
1080 .probe = tegra_usb_phy_probe,
1081 .remove = tegra_usb_phy_remove,
1082 .driver = {
1083 .name = "tegra-phy",
1084 .of_match_table = tegra_usb_phy_id_table,
1085 },
1086};
1087module_platform_driver(tegra_usb_phy_driver);
1088
1089MODULE_DESCRIPTION("Tegra USB PHY driver");
1090MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (C) 2013 NVIDIA Corporation
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 */
11
12#include <linux/resource.h>
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/export.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/iopoll.h>
20#include <linux/gpio.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
26#include <linux/usb/of.h>
27#include <linux/usb/ehci_def.h>
28#include <linux/usb/tegra_usb_phy.h>
29#include <linux/regulator/consumer.h>
30
31#define ULPI_VIEWPORT 0x170
32
33/* PORTSC PTS/PHCD bits, Tegra20 only */
34#define TEGRA_USB_PORTSC1 0x184
35#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
36#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
37
38/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
39#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
40#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
41#define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22)
42
43/* Bits of PORTSC1, which will get cleared by writing 1 into them */
44#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
45
46#define USB_SUSP_CTRL 0x400
47#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
48#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
49#define USB_SUSP_CLR (1 << 5)
50#define USB_PHY_CLK_VALID (1 << 7)
51#define UTMIP_RESET (1 << 11)
52#define UHSIC_RESET (1 << 11)
53#define UTMIP_PHY_ENABLE (1 << 12)
54#define ULPI_PHY_ENABLE (1 << 13)
55#define USB_SUSP_SET (1 << 14)
56#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
57
58#define USB1_LEGACY_CTRL 0x410
59#define USB1_NO_LEGACY_MODE (1 << 0)
60#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
61#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
62#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
63 (1 << 1)
64#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
65#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
66
67#define ULPI_TIMING_CTRL_0 0x424
68#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
69#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
70
71#define ULPI_TIMING_CTRL_1 0x428
72#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
73#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
74#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
75#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
76#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
77#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
78
79#define UTMIP_PLL_CFG1 0x804
80#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
81#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
82
83#define UTMIP_XCVR_CFG0 0x808
84#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
85#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
86#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
87#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
88#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
89#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
90#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
91#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
92#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
93#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
94
95#define UTMIP_BIAS_CFG0 0x80c
96#define UTMIP_OTGPD (1 << 11)
97#define UTMIP_BIASPD (1 << 10)
98#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
99#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
100#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
101
102#define UTMIP_HSRX_CFG0 0x810
103#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
105
106#define UTMIP_HSRX_CFG1 0x814
107#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
108
109#define UTMIP_TX_CFG0 0x820
110#define UTMIP_FS_PREABMLE_J (1 << 19)
111#define UTMIP_HS_DISCON_DISABLE (1 << 8)
112
113#define UTMIP_MISC_CFG0 0x824
114#define UTMIP_DPDM_OBSERVE (1 << 26)
115#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
121
122#define UTMIP_MISC_CFG1 0x828
123#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
125
126#define UTMIP_DEBOUNCE_CFG0 0x82c
127#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
128
129#define UTMIP_BAT_CHRG_CFG0 0x830
130#define UTMIP_PD_CHRG (1 << 0)
131
132#define UTMIP_SPARE_CFG0 0x834
133#define FUSE_SETUP_SEL (1 << 3)
134
135#define UTMIP_XCVR_CFG1 0x838
136#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
140
141#define UTMIP_BIAS_CFG1 0x83c
142#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
143
144/* For Tegra30 and above only, the address is different in Tegra20 */
145#define USB_USBMODE 0x1f8
146#define USB_USBMODE_MASK (3 << 0)
147#define USB_USBMODE_HOST (3 << 0)
148#define USB_USBMODE_DEVICE (2 << 0)
149
150static DEFINE_SPINLOCK(utmip_pad_lock);
151static int utmip_pad_count;
152
153struct tegra_xtal_freq {
154 int freq;
155 u8 enable_delay;
156 u8 stable_count;
157 u8 active_delay;
158 u8 xtal_freq_count;
159 u16 debounce;
160};
161
162static const struct tegra_xtal_freq tegra_freq_table[] = {
163 {
164 .freq = 12000000,
165 .enable_delay = 0x02,
166 .stable_count = 0x2F,
167 .active_delay = 0x04,
168 .xtal_freq_count = 0x76,
169 .debounce = 0x7530,
170 },
171 {
172 .freq = 13000000,
173 .enable_delay = 0x02,
174 .stable_count = 0x33,
175 .active_delay = 0x05,
176 .xtal_freq_count = 0x7F,
177 .debounce = 0x7EF4,
178 },
179 {
180 .freq = 19200000,
181 .enable_delay = 0x03,
182 .stable_count = 0x4B,
183 .active_delay = 0x06,
184 .xtal_freq_count = 0xBB,
185 .debounce = 0xBB80,
186 },
187 {
188 .freq = 26000000,
189 .enable_delay = 0x04,
190 .stable_count = 0x66,
191 .active_delay = 0x09,
192 .xtal_freq_count = 0xFE,
193 .debounce = 0xFDE8,
194 },
195};
196
197static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
198{
199 void __iomem *base = phy->regs;
200 unsigned long val;
201
202 if (phy->soc_config->has_hostpc) {
203 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
204 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
205 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
206 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
207 } else {
208 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
209 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
210 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
211 writel(val, base + TEGRA_USB_PORTSC1);
212 }
213}
214
215static void set_phcd(struct tegra_usb_phy *phy, bool enable)
216{
217 void __iomem *base = phy->regs;
218 unsigned long val;
219
220 if (phy->soc_config->has_hostpc) {
221 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
222 if (enable)
223 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
224 else
225 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
226 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
227 } else {
228 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
229 if (enable)
230 val |= TEGRA_USB_PORTSC1_PHCD;
231 else
232 val &= ~TEGRA_USB_PORTSC1_PHCD;
233 writel(val, base + TEGRA_USB_PORTSC1);
234 }
235}
236
237static int utmip_pad_open(struct tegra_usb_phy *phy)
238{
239 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
240 if (IS_ERR(phy->pad_clk)) {
241 pr_err("%s: can't get utmip pad clock\n", __func__);
242 return PTR_ERR(phy->pad_clk);
243 }
244
245 return 0;
246}
247
248static void utmip_pad_power_on(struct tegra_usb_phy *phy)
249{
250 unsigned long val, flags;
251 void __iomem *base = phy->pad_regs;
252 struct tegra_utmip_config *config = phy->config;
253
254 clk_prepare_enable(phy->pad_clk);
255
256 spin_lock_irqsave(&utmip_pad_lock, flags);
257
258 if (utmip_pad_count++ == 0) {
259 val = readl(base + UTMIP_BIAS_CFG0);
260 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
261
262 if (phy->soc_config->requires_extra_tuning_parameters) {
263 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
264 UTMIP_HSDISCON_LEVEL(~0) |
265 UTMIP_HSDISCON_LEVEL_MSB(~0));
266
267 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
268 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
269 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
270 }
271 writel(val, base + UTMIP_BIAS_CFG0);
272 }
273
274 spin_unlock_irqrestore(&utmip_pad_lock, flags);
275
276 clk_disable_unprepare(phy->pad_clk);
277}
278
279static int utmip_pad_power_off(struct tegra_usb_phy *phy)
280{
281 unsigned long val, flags;
282 void __iomem *base = phy->pad_regs;
283
284 if (!utmip_pad_count) {
285 pr_err("%s: utmip pad already powered off\n", __func__);
286 return -EINVAL;
287 }
288
289 clk_prepare_enable(phy->pad_clk);
290
291 spin_lock_irqsave(&utmip_pad_lock, flags);
292
293 if (--utmip_pad_count == 0) {
294 val = readl(base + UTMIP_BIAS_CFG0);
295 val |= UTMIP_OTGPD | UTMIP_BIASPD;
296 writel(val, base + UTMIP_BIAS_CFG0);
297 }
298
299 spin_unlock_irqrestore(&utmip_pad_lock, flags);
300
301 clk_disable_unprepare(phy->pad_clk);
302
303 return 0;
304}
305
306static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
307{
308 u32 tmp;
309
310 return readl_poll_timeout(reg, tmp, (tmp & mask) == result,
311 2000, 6000);
312}
313
314static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
315{
316 unsigned long val;
317 void __iomem *base = phy->regs;
318
319 /*
320 * The USB driver may have already initiated the phy clock
321 * disable so wait to see if the clock turns off and if not
322 * then proceed with gating the clock.
323 */
324 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
325 return;
326
327 if (phy->is_legacy_phy) {
328 val = readl(base + USB_SUSP_CTRL);
329 val |= USB_SUSP_SET;
330 writel(val, base + USB_SUSP_CTRL);
331
332 udelay(10);
333
334 val = readl(base + USB_SUSP_CTRL);
335 val &= ~USB_SUSP_SET;
336 writel(val, base + USB_SUSP_CTRL);
337 } else
338 set_phcd(phy, true);
339
340 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
341 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
342}
343
344static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
345{
346 unsigned long val;
347 void __iomem *base = phy->regs;
348
349 /*
350 * The USB driver may have already initiated the phy clock
351 * enable so wait to see if the clock turns on and if not
352 * then proceed with ungating the clock.
353 */
354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
355 USB_PHY_CLK_VALID) == 0)
356 return;
357
358 if (phy->is_legacy_phy) {
359 val = readl(base + USB_SUSP_CTRL);
360 val |= USB_SUSP_CLR;
361 writel(val, base + USB_SUSP_CTRL);
362
363 udelay(10);
364
365 val = readl(base + USB_SUSP_CTRL);
366 val &= ~USB_SUSP_CLR;
367 writel(val, base + USB_SUSP_CTRL);
368 } else
369 set_phcd(phy, false);
370
371 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
372 USB_PHY_CLK_VALID))
373 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
374}
375
376static int utmi_phy_power_on(struct tegra_usb_phy *phy)
377{
378 unsigned long val;
379 void __iomem *base = phy->regs;
380 struct tegra_utmip_config *config = phy->config;
381
382 val = readl(base + USB_SUSP_CTRL);
383 val |= UTMIP_RESET;
384 writel(val, base + USB_SUSP_CTRL);
385
386 if (phy->is_legacy_phy) {
387 val = readl(base + USB1_LEGACY_CTRL);
388 val |= USB1_NO_LEGACY_MODE;
389 writel(val, base + USB1_LEGACY_CTRL);
390 }
391
392 val = readl(base + UTMIP_TX_CFG0);
393 val |= UTMIP_FS_PREABMLE_J;
394 writel(val, base + UTMIP_TX_CFG0);
395
396 val = readl(base + UTMIP_HSRX_CFG0);
397 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
398 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
399 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
400 writel(val, base + UTMIP_HSRX_CFG0);
401
402 val = readl(base + UTMIP_HSRX_CFG1);
403 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
404 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
405 writel(val, base + UTMIP_HSRX_CFG1);
406
407 val = readl(base + UTMIP_DEBOUNCE_CFG0);
408 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
409 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
410 writel(val, base + UTMIP_DEBOUNCE_CFG0);
411
412 val = readl(base + UTMIP_MISC_CFG0);
413 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
414 writel(val, base + UTMIP_MISC_CFG0);
415
416 if (!phy->soc_config->utmi_pll_config_in_car_module) {
417 val = readl(base + UTMIP_MISC_CFG1);
418 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
419 UTMIP_PLLU_STABLE_COUNT(~0));
420 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
421 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
422 writel(val, base + UTMIP_MISC_CFG1);
423
424 val = readl(base + UTMIP_PLL_CFG1);
425 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
426 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
427 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
428 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
429 writel(val, base + UTMIP_PLL_CFG1);
430 }
431
432 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
433 val = readl(base + USB_SUSP_CTRL);
434 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
435 writel(val, base + USB_SUSP_CTRL);
436
437 val = readl(base + UTMIP_BAT_CHRG_CFG0);
438 val &= ~UTMIP_PD_CHRG;
439 writel(val, base + UTMIP_BAT_CHRG_CFG0);
440 } else {
441 val = readl(base + UTMIP_BAT_CHRG_CFG0);
442 val |= UTMIP_PD_CHRG;
443 writel(val, base + UTMIP_BAT_CHRG_CFG0);
444 }
445
446 utmip_pad_power_on(phy);
447
448 val = readl(base + UTMIP_XCVR_CFG0);
449 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
450 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
451 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
452 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
453
454 if (!config->xcvr_setup_use_fuses) {
455 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
456 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
457 }
458 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
459 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
460
461 if (phy->soc_config->requires_extra_tuning_parameters) {
462 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
463 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
464 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
465 }
466 writel(val, base + UTMIP_XCVR_CFG0);
467
468 val = readl(base + UTMIP_XCVR_CFG1);
469 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
470 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
471 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
472 writel(val, base + UTMIP_XCVR_CFG1);
473
474 val = readl(base + UTMIP_BIAS_CFG1);
475 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
476 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
477 writel(val, base + UTMIP_BIAS_CFG1);
478
479 val = readl(base + UTMIP_SPARE_CFG0);
480 if (config->xcvr_setup_use_fuses)
481 val |= FUSE_SETUP_SEL;
482 else
483 val &= ~FUSE_SETUP_SEL;
484 writel(val, base + UTMIP_SPARE_CFG0);
485
486 if (!phy->is_legacy_phy) {
487 val = readl(base + USB_SUSP_CTRL);
488 val |= UTMIP_PHY_ENABLE;
489 writel(val, base + USB_SUSP_CTRL);
490 }
491
492 val = readl(base + USB_SUSP_CTRL);
493 val &= ~UTMIP_RESET;
494 writel(val, base + USB_SUSP_CTRL);
495
496 if (phy->is_legacy_phy) {
497 val = readl(base + USB1_LEGACY_CTRL);
498 val &= ~USB1_VBUS_SENSE_CTL_MASK;
499 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
500 writel(val, base + USB1_LEGACY_CTRL);
501
502 val = readl(base + USB_SUSP_CTRL);
503 val &= ~USB_SUSP_SET;
504 writel(val, base + USB_SUSP_CTRL);
505 }
506
507 utmi_phy_clk_enable(phy);
508
509 if (phy->soc_config->requires_usbmode_setup) {
510 val = readl(base + USB_USBMODE);
511 val &= ~USB_USBMODE_MASK;
512 if (phy->mode == USB_DR_MODE_HOST)
513 val |= USB_USBMODE_HOST;
514 else
515 val |= USB_USBMODE_DEVICE;
516 writel(val, base + USB_USBMODE);
517 }
518
519 if (!phy->is_legacy_phy)
520 set_pts(phy, 0);
521
522 return 0;
523}
524
525static int utmi_phy_power_off(struct tegra_usb_phy *phy)
526{
527 unsigned long val;
528 void __iomem *base = phy->regs;
529
530 utmi_phy_clk_disable(phy);
531
532 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
533 val = readl(base + USB_SUSP_CTRL);
534 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
535 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
536 writel(val, base + USB_SUSP_CTRL);
537 }
538
539 val = readl(base + USB_SUSP_CTRL);
540 val |= UTMIP_RESET;
541 writel(val, base + USB_SUSP_CTRL);
542
543 val = readl(base + UTMIP_BAT_CHRG_CFG0);
544 val |= UTMIP_PD_CHRG;
545 writel(val, base + UTMIP_BAT_CHRG_CFG0);
546
547 val = readl(base + UTMIP_XCVR_CFG0);
548 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
549 UTMIP_FORCE_PDZI_POWERDOWN;
550 writel(val, base + UTMIP_XCVR_CFG0);
551
552 val = readl(base + UTMIP_XCVR_CFG1);
553 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
554 UTMIP_FORCE_PDDR_POWERDOWN;
555 writel(val, base + UTMIP_XCVR_CFG1);
556
557 return utmip_pad_power_off(phy);
558}
559
560static void utmi_phy_preresume(struct tegra_usb_phy *phy)
561{
562 unsigned long val;
563 void __iomem *base = phy->regs;
564
565 val = readl(base + UTMIP_TX_CFG0);
566 val |= UTMIP_HS_DISCON_DISABLE;
567 writel(val, base + UTMIP_TX_CFG0);
568}
569
570static void utmi_phy_postresume(struct tegra_usb_phy *phy)
571{
572 unsigned long val;
573 void __iomem *base = phy->regs;
574
575 val = readl(base + UTMIP_TX_CFG0);
576 val &= ~UTMIP_HS_DISCON_DISABLE;
577 writel(val, base + UTMIP_TX_CFG0);
578}
579
580static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
581 enum tegra_usb_phy_port_speed port_speed)
582{
583 unsigned long val;
584 void __iomem *base = phy->regs;
585
586 val = readl(base + UTMIP_MISC_CFG0);
587 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
588 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
589 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
590 else
591 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
592 writel(val, base + UTMIP_MISC_CFG0);
593 udelay(1);
594
595 val = readl(base + UTMIP_MISC_CFG0);
596 val |= UTMIP_DPDM_OBSERVE;
597 writel(val, base + UTMIP_MISC_CFG0);
598 udelay(10);
599}
600
601static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
602{
603 unsigned long val;
604 void __iomem *base = phy->regs;
605
606 val = readl(base + UTMIP_MISC_CFG0);
607 val &= ~UTMIP_DPDM_OBSERVE;
608 writel(val, base + UTMIP_MISC_CFG0);
609 udelay(10);
610}
611
612static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
613{
614 int ret;
615 unsigned long val;
616 void __iomem *base = phy->regs;
617
618 ret = gpio_direction_output(phy->reset_gpio, 0);
619 if (ret < 0) {
620 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
621 phy->reset_gpio);
622 return ret;
623 }
624 msleep(5);
625 ret = gpio_direction_output(phy->reset_gpio, 1);
626 if (ret < 0) {
627 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
628 phy->reset_gpio);
629 return ret;
630 }
631
632 clk_prepare_enable(phy->clk);
633 msleep(1);
634
635 val = readl(base + USB_SUSP_CTRL);
636 val |= UHSIC_RESET;
637 writel(val, base + USB_SUSP_CTRL);
638
639 val = readl(base + ULPI_TIMING_CTRL_0);
640 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
641 writel(val, base + ULPI_TIMING_CTRL_0);
642
643 val = readl(base + USB_SUSP_CTRL);
644 val |= ULPI_PHY_ENABLE;
645 writel(val, base + USB_SUSP_CTRL);
646
647 val = 0;
648 writel(val, base + ULPI_TIMING_CTRL_1);
649
650 val |= ULPI_DATA_TRIMMER_SEL(4);
651 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
652 val |= ULPI_DIR_TRIMMER_SEL(4);
653 writel(val, base + ULPI_TIMING_CTRL_1);
654 udelay(10);
655
656 val |= ULPI_DATA_TRIMMER_LOAD;
657 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
658 val |= ULPI_DIR_TRIMMER_LOAD;
659 writel(val, base + ULPI_TIMING_CTRL_1);
660
661 /* Fix VbusInvalid due to floating VBUS */
662 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
663 if (ret) {
664 pr_err("%s: ulpi write failed\n", __func__);
665 return ret;
666 }
667
668 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
669 if (ret) {
670 pr_err("%s: ulpi write failed\n", __func__);
671 return ret;
672 }
673
674 val = readl(base + USB_SUSP_CTRL);
675 val |= USB_SUSP_CLR;
676 writel(val, base + USB_SUSP_CTRL);
677 udelay(100);
678
679 val = readl(base + USB_SUSP_CTRL);
680 val &= ~USB_SUSP_CLR;
681 writel(val, base + USB_SUSP_CTRL);
682
683 return 0;
684}
685
686static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
687{
688 clk_disable(phy->clk);
689 return gpio_direction_output(phy->reset_gpio, 0);
690}
691
692static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
693{
694 if (!IS_ERR(phy->vbus))
695 regulator_disable(phy->vbus);
696
697 clk_disable_unprepare(phy->pll_u);
698}
699
700static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
701{
702 if (phy->is_ulpi_phy)
703 return ulpi_phy_power_on(phy);
704 else
705 return utmi_phy_power_on(phy);
706}
707
708static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
709{
710 if (phy->is_ulpi_phy)
711 return ulpi_phy_power_off(phy);
712 else
713 return utmi_phy_power_off(phy);
714}
715
716static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
717{
718 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
719 if (suspend)
720 return tegra_usb_phy_power_off(phy);
721 else
722 return tegra_usb_phy_power_on(phy);
723}
724
725static int ulpi_open(struct tegra_usb_phy *phy)
726{
727 int err;
728
729 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
730 if (IS_ERR(phy->clk)) {
731 pr_err("%s: can't get ulpi clock\n", __func__);
732 return PTR_ERR(phy->clk);
733 }
734
735 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
736 "ulpi_phy_reset_b");
737 if (err < 0) {
738 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
739 phy->reset_gpio);
740 return err;
741 }
742
743 err = gpio_direction_output(phy->reset_gpio, 0);
744 if (err < 0) {
745 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
746 phy->reset_gpio);
747 return err;
748 }
749
750 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
751 if (!phy->ulpi) {
752 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
753 err = -ENOMEM;
754 return err;
755 }
756
757 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
758 return 0;
759}
760
761static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
762{
763 unsigned long parent_rate;
764 int i;
765 int err;
766
767 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
768 if (IS_ERR(phy->pll_u)) {
769 pr_err("Can't get pll_u clock\n");
770 return PTR_ERR(phy->pll_u);
771 }
772
773 err = clk_prepare_enable(phy->pll_u);
774 if (err)
775 return err;
776
777 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
778 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
779 if (tegra_freq_table[i].freq == parent_rate) {
780 phy->freq = &tegra_freq_table[i];
781 break;
782 }
783 }
784 if (!phy->freq) {
785 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
786 err = -EINVAL;
787 goto fail;
788 }
789
790 if (!IS_ERR(phy->vbus)) {
791 err = regulator_enable(phy->vbus);
792 if (err) {
793 dev_err(phy->u_phy.dev,
794 "failed to enable usb vbus regulator: %d\n",
795 err);
796 goto fail;
797 }
798 }
799
800 if (phy->is_ulpi_phy)
801 err = ulpi_open(phy);
802 else
803 err = utmip_pad_open(phy);
804 if (err < 0)
805 goto fail;
806
807 return 0;
808
809fail:
810 clk_disable_unprepare(phy->pll_u);
811 return err;
812}
813
814void tegra_usb_phy_preresume(struct usb_phy *x)
815{
816 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
817
818 if (!phy->is_ulpi_phy)
819 utmi_phy_preresume(phy);
820}
821EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
822
823void tegra_usb_phy_postresume(struct usb_phy *x)
824{
825 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
826
827 if (!phy->is_ulpi_phy)
828 utmi_phy_postresume(phy);
829}
830EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
831
832void tegra_ehci_phy_restore_start(struct usb_phy *x,
833 enum tegra_usb_phy_port_speed port_speed)
834{
835 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
836
837 if (!phy->is_ulpi_phy)
838 utmi_phy_restore_start(phy, port_speed);
839}
840EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
841
842void tegra_ehci_phy_restore_end(struct usb_phy *x)
843{
844 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
845
846 if (!phy->is_ulpi_phy)
847 utmi_phy_restore_end(phy);
848}
849EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
850
851static int read_utmi_param(struct platform_device *pdev, const char *param,
852 u8 *dest)
853{
854 u32 value;
855 int err = of_property_read_u32(pdev->dev.of_node, param, &value);
856 *dest = (u8)value;
857 if (err < 0)
858 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
859 param, err);
860 return err;
861}
862
863static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
864 struct platform_device *pdev)
865{
866 struct resource *res;
867 int err;
868 struct tegra_utmip_config *config;
869
870 tegra_phy->is_ulpi_phy = false;
871
872 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
873 if (!res) {
874 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
875 return -ENXIO;
876 }
877
878 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
879 resource_size(res));
880 if (!tegra_phy->pad_regs) {
881 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
882 return -ENOMEM;
883 }
884
885 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
886 GFP_KERNEL);
887 if (!tegra_phy->config)
888 return -ENOMEM;
889
890 config = tegra_phy->config;
891
892 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
893 &config->hssync_start_delay);
894 if (err < 0)
895 return err;
896
897 err = read_utmi_param(pdev, "nvidia,elastic-limit",
898 &config->elastic_limit);
899 if (err < 0)
900 return err;
901
902 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
903 &config->idle_wait_delay);
904 if (err < 0)
905 return err;
906
907 err = read_utmi_param(pdev, "nvidia,term-range-adj",
908 &config->term_range_adj);
909 if (err < 0)
910 return err;
911
912 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
913 &config->xcvr_lsfslew);
914 if (err < 0)
915 return err;
916
917 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
918 &config->xcvr_lsrslew);
919 if (err < 0)
920 return err;
921
922 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
923 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
924 &config->xcvr_hsslew);
925 if (err < 0)
926 return err;
927
928 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
929 &config->hssquelch_level);
930 if (err < 0)
931 return err;
932
933 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
934 &config->hsdiscon_level);
935 if (err < 0)
936 return err;
937 }
938
939 config->xcvr_setup_use_fuses = of_property_read_bool(
940 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
941
942 if (!config->xcvr_setup_use_fuses) {
943 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
944 &config->xcvr_setup);
945 if (err < 0)
946 return err;
947 }
948
949 return 0;
950}
951
952static const struct tegra_phy_soc_config tegra20_soc_config = {
953 .utmi_pll_config_in_car_module = false,
954 .has_hostpc = false,
955 .requires_usbmode_setup = false,
956 .requires_extra_tuning_parameters = false,
957};
958
959static const struct tegra_phy_soc_config tegra30_soc_config = {
960 .utmi_pll_config_in_car_module = true,
961 .has_hostpc = true,
962 .requires_usbmode_setup = true,
963 .requires_extra_tuning_parameters = true,
964};
965
966static const struct of_device_id tegra_usb_phy_id_table[] = {
967 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
968 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
969 { },
970};
971MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
972
973static int tegra_usb_phy_probe(struct platform_device *pdev)
974{
975 const struct of_device_id *match;
976 struct resource *res;
977 struct tegra_usb_phy *tegra_phy = NULL;
978 struct device_node *np = pdev->dev.of_node;
979 enum usb_phy_interface phy_type;
980 int err;
981
982 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
983 if (!tegra_phy)
984 return -ENOMEM;
985
986 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
987 if (!match) {
988 dev_err(&pdev->dev, "Error: No device match found\n");
989 return -ENODEV;
990 }
991 tegra_phy->soc_config = match->data;
992
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 if (!res) {
995 dev_err(&pdev->dev, "Failed to get I/O memory\n");
996 return -ENXIO;
997 }
998
999 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1000 resource_size(res));
1001 if (!tegra_phy->regs) {
1002 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1003 return -ENOMEM;
1004 }
1005
1006 tegra_phy->is_legacy_phy =
1007 of_property_read_bool(np, "nvidia,has-legacy-mode");
1008
1009 phy_type = of_usb_get_phy_mode(np);
1010 switch (phy_type) {
1011 case USBPHY_INTERFACE_MODE_UTMI:
1012 err = utmi_phy_probe(tegra_phy, pdev);
1013 if (err < 0)
1014 return err;
1015 break;
1016
1017 case USBPHY_INTERFACE_MODE_ULPI:
1018 tegra_phy->is_ulpi_phy = true;
1019
1020 tegra_phy->reset_gpio =
1021 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1022 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1023 dev_err(&pdev->dev, "invalid gpio: %d\n",
1024 tegra_phy->reset_gpio);
1025 return tegra_phy->reset_gpio;
1026 }
1027 tegra_phy->config = NULL;
1028 break;
1029
1030 default:
1031 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1032 return -EINVAL;
1033 }
1034
1035 if (of_find_property(np, "dr_mode", NULL))
1036 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1037 else
1038 tegra_phy->mode = USB_DR_MODE_HOST;
1039
1040 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1041 dev_err(&pdev->dev, "dr_mode is invalid\n");
1042 return -EINVAL;
1043 }
1044
1045 /* On some boards, the VBUS regulator doesn't need to be controlled */
1046 if (of_find_property(np, "vbus-supply", NULL)) {
1047 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1048 if (IS_ERR(tegra_phy->vbus))
1049 return PTR_ERR(tegra_phy->vbus);
1050 } else {
1051 dev_notice(&pdev->dev, "no vbus regulator");
1052 tegra_phy->vbus = ERR_PTR(-ENODEV);
1053 }
1054
1055 tegra_phy->u_phy.dev = &pdev->dev;
1056 err = tegra_usb_phy_init(tegra_phy);
1057 if (err < 0)
1058 return err;
1059
1060 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1061
1062 platform_set_drvdata(pdev, tegra_phy);
1063
1064 err = usb_add_phy_dev(&tegra_phy->u_phy);
1065 if (err < 0) {
1066 tegra_usb_phy_close(tegra_phy);
1067 return err;
1068 }
1069
1070 return 0;
1071}
1072
1073static int tegra_usb_phy_remove(struct platform_device *pdev)
1074{
1075 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1076
1077 usb_remove_phy(&tegra_phy->u_phy);
1078 tegra_usb_phy_close(tegra_phy);
1079
1080 return 0;
1081}
1082
1083static struct platform_driver tegra_usb_phy_driver = {
1084 .probe = tegra_usb_phy_probe,
1085 .remove = tegra_usb_phy_remove,
1086 .driver = {
1087 .name = "tegra-phy",
1088 .of_match_table = tegra_usb_phy_id_table,
1089 },
1090};
1091module_platform_driver(tegra_usb_phy_driver);
1092
1093MODULE_DESCRIPTION("Tegra USB PHY driver");
1094MODULE_LICENSE("GPL v2");