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1/*
2 * Cadence UART driver (found in Xilinx Zynq)
3 *
4 * 2011 - 2014 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
15 */
16
17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/console.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/module.h>
33
34#define CDNS_UART_TTY_NAME "ttyPS"
35#define CDNS_UART_NAME "xuartps"
36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38#define CDNS_UART_NR_PORTS 2
39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40#define CDNS_UART_REGISTER_SPACE 0x1000
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/* Register offsets for the UART. */
53#define CDNS_UART_CR 0x00 /* Control Register */
54#define CDNS_UART_MR 0x04 /* Mode Register */
55#define CDNS_UART_IER 0x08 /* Interrupt Enable */
56#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58#define CDNS_UART_ISR 0x14 /* Interrupt Status */
59#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64#define CDNS_UART_SR 0x2C /* Channel Status */
65#define CDNS_UART_FIFO 0x30 /* FIFO */
66#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71
72/* Control Register Bit Definitions */
73#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92
93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95
96#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101
102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
105
106/*
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
116 */
117#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
128
129#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \
130 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \
131 CDNS_UART_IXR_TOUT)
132
133/* Goes in read_status_mask for break detection as the HW doesn't do it*/
134#define CDNS_UART_IXR_BRK 0x80000000
135
136/*
137 * Modem Control register:
138 * The read/write Modem Control register controls the interface with the modem
139 * or data set, or a peripheral device emulating a modem.
140 */
141#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
142#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
143#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
144
145/*
146 * Channel Status Register:
147 * The channel status register (CSR) is provided to enable the control logic
148 * to monitor the status of bits in the channel interrupt status register,
149 * even if these are masked out by the interrupt mask register.
150 */
151#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
152#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
153#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
154#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
155
156/* baud dividers min/max values */
157#define CDNS_UART_BDIV_MIN 4
158#define CDNS_UART_BDIV_MAX 255
159#define CDNS_UART_CD_MAX 65535
160
161/**
162 * struct cdns_uart - device data
163 * @port: Pointer to the UART port
164 * @uartclk: Reference clock
165 * @pclk: APB clock
166 * @baud: Current baud rate
167 * @clk_rate_change_nb: Notifier block for clock changes
168 */
169struct cdns_uart {
170 struct uart_port *port;
171 struct clk *uartclk;
172 struct clk *pclk;
173 unsigned int baud;
174 struct notifier_block clk_rate_change_nb;
175};
176#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
177 clk_rate_change_nb);
178
179static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
180{
181 /*
182 * There is no hardware break detection, so we interpret framing
183 * error with all-zeros data as a break sequence. Most of the time,
184 * there's another non-zero byte at the end of the sequence.
185 */
186 if (isrstatus & CDNS_UART_IXR_FRAMING) {
187 while (!(readl(port->membase + CDNS_UART_SR) &
188 CDNS_UART_SR_RXEMPTY)) {
189 if (!readl(port->membase + CDNS_UART_FIFO)) {
190 port->read_status_mask |= CDNS_UART_IXR_BRK;
191 isrstatus &= ~CDNS_UART_IXR_FRAMING;
192 }
193 }
194 writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
195 }
196
197 /* drop byte with parity error if IGNPAR specified */
198 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
199 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
200
201 isrstatus &= port->read_status_mask;
202 isrstatus &= ~port->ignore_status_mask;
203
204 if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
205 return;
206
207 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
208 u32 data;
209 char status = TTY_NORMAL;
210
211 data = readl(port->membase + CDNS_UART_FIFO);
212
213 /* Non-NULL byte after BREAK is garbage (99%) */
214 if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
215 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
216 port->icount.brk++;
217 if (uart_handle_break(port))
218 continue;
219 }
220
221 if (uart_handle_sysrq_char(port, data))
222 continue;
223
224 port->icount.rx++;
225
226 if (isrstatus & CDNS_UART_IXR_PARITY) {
227 port->icount.parity++;
228 status = TTY_PARITY;
229 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
230 port->icount.frame++;
231 status = TTY_FRAME;
232 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
233 port->icount.overrun++;
234 }
235
236 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
237 data, status);
238 }
239 tty_flip_buffer_push(&port->state->port);
240}
241
242static void cdns_uart_handle_tx(struct uart_port *port)
243{
244 unsigned int numbytes;
245
246 if (uart_circ_empty(&port->state->xmit)) {
247 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
248 return;
249 }
250
251 numbytes = port->fifosize;
252 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
253 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
254 /*
255 * Get the data from the UART circular buffer
256 * and write it to the cdns_uart's TX_FIFO
257 * register.
258 */
259 writel(port->state->xmit.buf[port->state->xmit.tail],
260 port->membase + CDNS_UART_FIFO);
261 port->icount.tx++;
262
263 /*
264 * Adjust the tail of the UART buffer and wrap
265 * the buffer if it reaches limit.
266 */
267 port->state->xmit.tail =
268 (port->state->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
269
270 numbytes--;
271 }
272
273 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(port);
275}
276
277/**
278 * cdns_uart_isr - Interrupt handler
279 * @irq: Irq number
280 * @dev_id: Id of the port
281 *
282 * Return: IRQHANDLED
283 */
284static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
285{
286 struct uart_port *port = (struct uart_port *)dev_id;
287 unsigned long flags;
288 unsigned int isrstatus;
289
290 spin_lock_irqsave(&port->lock, flags);
291
292 /* Read the interrupt status register to determine which
293 * interrupt(s) is/are active.
294 */
295 isrstatus = readl(port->membase + CDNS_UART_ISR);
296
297 if (isrstatus & CDNS_UART_RX_IRQS)
298 cdns_uart_handle_rx(port, isrstatus);
299
300 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY)
301 cdns_uart_handle_tx(port);
302
303 writel(isrstatus, port->membase + CDNS_UART_ISR);
304
305 /* be sure to release the lock and tty before leaving */
306 spin_unlock_irqrestore(&port->lock, flags);
307
308 return IRQ_HANDLED;
309}
310
311/**
312 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
313 * @clk: UART module input clock
314 * @baud: Desired baud rate
315 * @rbdiv: BDIV value (return value)
316 * @rcd: CD value (return value)
317 * @div8: Value for clk_sel bit in mod (return value)
318 * Return: baud rate, requested baud when possible, or actual baud when there
319 * was too much error, zero if no valid divisors are found.
320 *
321 * Formula to obtain baud rate is
322 * baud_tx/rx rate = clk/CD * (BDIV + 1)
323 * input_clk = (Uart User Defined Clock or Apb Clock)
324 * depends on UCLKEN in MR Reg
325 * clk = input_clk or input_clk/8;
326 * depends on CLKS in MR reg
327 * CD and BDIV depends on values in
328 * baud rate generate register
329 * baud rate clock divisor register
330 */
331static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
332 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
333{
334 u32 cd, bdiv;
335 unsigned int calc_baud;
336 unsigned int bestbaud = 0;
337 unsigned int bauderror;
338 unsigned int besterror = ~0;
339
340 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
341 *div8 = 1;
342 clk /= 8;
343 } else {
344 *div8 = 0;
345 }
346
347 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
348 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
349 if (cd < 1 || cd > CDNS_UART_CD_MAX)
350 continue;
351
352 calc_baud = clk / (cd * (bdiv + 1));
353
354 if (baud > calc_baud)
355 bauderror = baud - calc_baud;
356 else
357 bauderror = calc_baud - baud;
358
359 if (besterror > bauderror) {
360 *rbdiv = bdiv;
361 *rcd = cd;
362 bestbaud = calc_baud;
363 besterror = bauderror;
364 }
365 }
366 /* use the values when percent error is acceptable */
367 if (((besterror * 100) / baud) < 3)
368 bestbaud = baud;
369
370 return bestbaud;
371}
372
373/**
374 * cdns_uart_set_baud_rate - Calculate and set the baud rate
375 * @port: Handle to the uart port structure
376 * @baud: Baud rate to set
377 * Return: baud rate, requested baud when possible, or actual baud when there
378 * was too much error, zero if no valid divisors are found.
379 */
380static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
381 unsigned int baud)
382{
383 unsigned int calc_baud;
384 u32 cd = 0, bdiv = 0;
385 u32 mreg;
386 int div8;
387 struct cdns_uart *cdns_uart = port->private_data;
388
389 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
390 &div8);
391
392 /* Write new divisors to hardware */
393 mreg = readl(port->membase + CDNS_UART_MR);
394 if (div8)
395 mreg |= CDNS_UART_MR_CLKSEL;
396 else
397 mreg &= ~CDNS_UART_MR_CLKSEL;
398 writel(mreg, port->membase + CDNS_UART_MR);
399 writel(cd, port->membase + CDNS_UART_BAUDGEN);
400 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
401 cdns_uart->baud = baud;
402
403 return calc_baud;
404}
405
406#ifdef CONFIG_COMMON_CLK
407/**
408 * cdns_uart_clk_notitifer_cb - Clock notifier callback
409 * @nb: Notifier block
410 * @event: Notify event
411 * @data: Notifier data
412 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
413 */
414static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
415 unsigned long event, void *data)
416{
417 u32 ctrl_reg;
418 struct uart_port *port;
419 int locked = 0;
420 struct clk_notifier_data *ndata = data;
421 unsigned long flags = 0;
422 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
423
424 port = cdns_uart->port;
425 if (port->suspended)
426 return NOTIFY_OK;
427
428 switch (event) {
429 case PRE_RATE_CHANGE:
430 {
431 u32 bdiv, cd;
432 int div8;
433
434 /*
435 * Find out if current baud-rate can be achieved with new clock
436 * frequency.
437 */
438 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
439 &bdiv, &cd, &div8)) {
440 dev_warn(port->dev, "clock rate change rejected\n");
441 return NOTIFY_BAD;
442 }
443
444 spin_lock_irqsave(&cdns_uart->port->lock, flags);
445
446 /* Disable the TX and RX to set baud rate */
447 ctrl_reg = readl(port->membase + CDNS_UART_CR);
448 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
449 writel(ctrl_reg, port->membase + CDNS_UART_CR);
450
451 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
452
453 return NOTIFY_OK;
454 }
455 case POST_RATE_CHANGE:
456 /*
457 * Set clk dividers to generate correct baud with new clock
458 * frequency.
459 */
460
461 spin_lock_irqsave(&cdns_uart->port->lock, flags);
462
463 locked = 1;
464 port->uartclk = ndata->new_rate;
465
466 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
467 cdns_uart->baud);
468 /* fall through */
469 case ABORT_RATE_CHANGE:
470 if (!locked)
471 spin_lock_irqsave(&cdns_uart->port->lock, flags);
472
473 /* Set TX/RX Reset */
474 ctrl_reg = readl(port->membase + CDNS_UART_CR);
475 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
476 writel(ctrl_reg, port->membase + CDNS_UART_CR);
477
478 while (readl(port->membase + CDNS_UART_CR) &
479 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
480 cpu_relax();
481
482 /*
483 * Clear the RX disable and TX disable bits and then set the TX
484 * enable bit and RX enable bit to enable the transmitter and
485 * receiver.
486 */
487 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
488 ctrl_reg = readl(port->membase + CDNS_UART_CR);
489 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
490 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
491 writel(ctrl_reg, port->membase + CDNS_UART_CR);
492
493 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
494
495 return NOTIFY_OK;
496 default:
497 return NOTIFY_DONE;
498 }
499}
500#endif
501
502/**
503 * cdns_uart_start_tx - Start transmitting bytes
504 * @port: Handle to the uart port structure
505 */
506static void cdns_uart_start_tx(struct uart_port *port)
507{
508 unsigned int status;
509
510 if (uart_tx_stopped(port))
511 return;
512
513 /*
514 * Set the TX enable bit and clear the TX disable bit to enable the
515 * transmitter.
516 */
517 status = readl(port->membase + CDNS_UART_CR);
518 status &= ~CDNS_UART_CR_TX_DIS;
519 status |= CDNS_UART_CR_TX_EN;
520 writel(status, port->membase + CDNS_UART_CR);
521
522 if (uart_circ_empty(&port->state->xmit))
523 return;
524
525 cdns_uart_handle_tx(port);
526
527 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
528 /* Enable the TX Empty interrupt */
529 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
530}
531
532/**
533 * cdns_uart_stop_tx - Stop TX
534 * @port: Handle to the uart port structure
535 */
536static void cdns_uart_stop_tx(struct uart_port *port)
537{
538 unsigned int regval;
539
540 regval = readl(port->membase + CDNS_UART_CR);
541 regval |= CDNS_UART_CR_TX_DIS;
542 /* Disable the transmitter */
543 writel(regval, port->membase + CDNS_UART_CR);
544}
545
546/**
547 * cdns_uart_stop_rx - Stop RX
548 * @port: Handle to the uart port structure
549 */
550static void cdns_uart_stop_rx(struct uart_port *port)
551{
552 unsigned int regval;
553
554 /* Disable RX IRQs */
555 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
556
557 /* Disable the receiver */
558 regval = readl(port->membase + CDNS_UART_CR);
559 regval |= CDNS_UART_CR_RX_DIS;
560 writel(regval, port->membase + CDNS_UART_CR);
561}
562
563/**
564 * cdns_uart_tx_empty - Check whether TX is empty
565 * @port: Handle to the uart port structure
566 *
567 * Return: TIOCSER_TEMT on success, 0 otherwise
568 */
569static unsigned int cdns_uart_tx_empty(struct uart_port *port)
570{
571 unsigned int status;
572
573 status = readl(port->membase + CDNS_UART_SR) &
574 CDNS_UART_SR_TXEMPTY;
575 return status ? TIOCSER_TEMT : 0;
576}
577
578/**
579 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
580 * transmitting char breaks
581 * @port: Handle to the uart port structure
582 * @ctl: Value based on which start or stop decision is taken
583 */
584static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
585{
586 unsigned int status;
587 unsigned long flags;
588
589 spin_lock_irqsave(&port->lock, flags);
590
591 status = readl(port->membase + CDNS_UART_CR);
592
593 if (ctl == -1)
594 writel(CDNS_UART_CR_STARTBRK | status,
595 port->membase + CDNS_UART_CR);
596 else {
597 if ((status & CDNS_UART_CR_STOPBRK) == 0)
598 writel(CDNS_UART_CR_STOPBRK | status,
599 port->membase + CDNS_UART_CR);
600 }
601 spin_unlock_irqrestore(&port->lock, flags);
602}
603
604/**
605 * cdns_uart_set_termios - termios operations, handling data length, parity,
606 * stop bits, flow control, baud rate
607 * @port: Handle to the uart port structure
608 * @termios: Handle to the input termios structure
609 * @old: Values of the previously saved termios structure
610 */
611static void cdns_uart_set_termios(struct uart_port *port,
612 struct ktermios *termios, struct ktermios *old)
613{
614 unsigned int cval = 0;
615 unsigned int baud, minbaud, maxbaud;
616 unsigned long flags;
617 unsigned int ctrl_reg, mode_reg;
618
619 spin_lock_irqsave(&port->lock, flags);
620
621 /* Wait for the transmit FIFO to empty before making changes */
622 if (!(readl(port->membase + CDNS_UART_CR) &
623 CDNS_UART_CR_TX_DIS)) {
624 while (!(readl(port->membase + CDNS_UART_SR) &
625 CDNS_UART_SR_TXEMPTY)) {
626 cpu_relax();
627 }
628 }
629
630 /* Disable the TX and RX to set baud rate */
631 ctrl_reg = readl(port->membase + CDNS_UART_CR);
632 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
633 writel(ctrl_reg, port->membase + CDNS_UART_CR);
634
635 /*
636 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
637 * min and max baud should be calculated here based on port->uartclk.
638 * this way we get a valid baud and can safely call set_baud()
639 */
640 minbaud = port->uartclk /
641 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
642 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
643 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
644 baud = cdns_uart_set_baud_rate(port, baud);
645 if (tty_termios_baud_rate(termios))
646 tty_termios_encode_baud_rate(termios, baud, baud);
647
648 /* Update the per-port timeout. */
649 uart_update_timeout(port, termios->c_cflag, baud);
650
651 /* Set TX/RX Reset */
652 ctrl_reg = readl(port->membase + CDNS_UART_CR);
653 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
654 writel(ctrl_reg, port->membase + CDNS_UART_CR);
655
656 /*
657 * Clear the RX disable and TX disable bits and then set the TX enable
658 * bit and RX enable bit to enable the transmitter and receiver.
659 */
660 ctrl_reg = readl(port->membase + CDNS_UART_CR);
661 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
662 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
663 writel(ctrl_reg, port->membase + CDNS_UART_CR);
664
665 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
666
667 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
668 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
669 port->ignore_status_mask = 0;
670
671 if (termios->c_iflag & INPCK)
672 port->read_status_mask |= CDNS_UART_IXR_PARITY |
673 CDNS_UART_IXR_FRAMING;
674
675 if (termios->c_iflag & IGNPAR)
676 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
677 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
678
679 /* ignore all characters if CREAD is not set */
680 if ((termios->c_cflag & CREAD) == 0)
681 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
682 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
683 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
684
685 mode_reg = readl(port->membase + CDNS_UART_MR);
686
687 /* Handling Data Size */
688 switch (termios->c_cflag & CSIZE) {
689 case CS6:
690 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
691 break;
692 case CS7:
693 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
694 break;
695 default:
696 case CS8:
697 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
698 termios->c_cflag &= ~CSIZE;
699 termios->c_cflag |= CS8;
700 break;
701 }
702
703 /* Handling Parity and Stop Bits length */
704 if (termios->c_cflag & CSTOPB)
705 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
706 else
707 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
708
709 if (termios->c_cflag & PARENB) {
710 /* Mark or Space parity */
711 if (termios->c_cflag & CMSPAR) {
712 if (termios->c_cflag & PARODD)
713 cval |= CDNS_UART_MR_PARITY_MARK;
714 else
715 cval |= CDNS_UART_MR_PARITY_SPACE;
716 } else {
717 if (termios->c_cflag & PARODD)
718 cval |= CDNS_UART_MR_PARITY_ODD;
719 else
720 cval |= CDNS_UART_MR_PARITY_EVEN;
721 }
722 } else {
723 cval |= CDNS_UART_MR_PARITY_NONE;
724 }
725 cval |= mode_reg & 1;
726 writel(cval, port->membase + CDNS_UART_MR);
727
728 spin_unlock_irqrestore(&port->lock, flags);
729}
730
731/**
732 * cdns_uart_startup - Called when an application opens a cdns_uart port
733 * @port: Handle to the uart port structure
734 *
735 * Return: 0 on success, negative errno otherwise
736 */
737static int cdns_uart_startup(struct uart_port *port)
738{
739 int ret;
740 unsigned long flags;
741 unsigned int status = 0;
742
743 spin_lock_irqsave(&port->lock, flags);
744
745 /* Disable the TX and RX */
746 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
747 port->membase + CDNS_UART_CR);
748
749 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
750 * no break chars.
751 */
752 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
753 port->membase + CDNS_UART_CR);
754
755 /*
756 * Clear the RX disable bit and then set the RX enable bit to enable
757 * the receiver.
758 */
759 status = readl(port->membase + CDNS_UART_CR);
760 status &= CDNS_UART_CR_RX_DIS;
761 status |= CDNS_UART_CR_RX_EN;
762 writel(status, port->membase + CDNS_UART_CR);
763
764 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
765 * no parity.
766 */
767 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
768 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
769 port->membase + CDNS_UART_MR);
770
771 /*
772 * Set the RX FIFO Trigger level to use most of the FIFO, but it
773 * can be tuned with a module parameter
774 */
775 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
776
777 /*
778 * Receive Timeout register is enabled but it
779 * can be tuned with a module parameter
780 */
781 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
782
783 /* Clear out any pending interrupts before enabling them */
784 writel(readl(port->membase + CDNS_UART_ISR),
785 port->membase + CDNS_UART_ISR);
786
787 spin_unlock_irqrestore(&port->lock, flags);
788
789 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
790 if (ret) {
791 dev_err(port->dev, "request_irq '%d' failed with %d\n",
792 port->irq, ret);
793 return ret;
794 }
795
796 /* Set the Interrupt Registers with desired interrupts */
797 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
798
799 return 0;
800}
801
802/**
803 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
804 * @port: Handle to the uart port structure
805 */
806static void cdns_uart_shutdown(struct uart_port *port)
807{
808 int status;
809 unsigned long flags;
810
811 spin_lock_irqsave(&port->lock, flags);
812
813 /* Disable interrupts */
814 status = readl(port->membase + CDNS_UART_IMR);
815 writel(status, port->membase + CDNS_UART_IDR);
816 writel(0xffffffff, port->membase + CDNS_UART_ISR);
817
818 /* Disable the TX and RX */
819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
820 port->membase + CDNS_UART_CR);
821
822 spin_unlock_irqrestore(&port->lock, flags);
823
824 free_irq(port->irq, port);
825}
826
827/**
828 * cdns_uart_type - Set UART type to cdns_uart port
829 * @port: Handle to the uart port structure
830 *
831 * Return: string on success, NULL otherwise
832 */
833static const char *cdns_uart_type(struct uart_port *port)
834{
835 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
836}
837
838/**
839 * cdns_uart_verify_port - Verify the port params
840 * @port: Handle to the uart port structure
841 * @ser: Handle to the structure whose members are compared
842 *
843 * Return: 0 on success, negative errno otherwise.
844 */
845static int cdns_uart_verify_port(struct uart_port *port,
846 struct serial_struct *ser)
847{
848 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
849 return -EINVAL;
850 if (port->irq != ser->irq)
851 return -EINVAL;
852 if (ser->io_type != UPIO_MEM)
853 return -EINVAL;
854 if (port->iobase != ser->port)
855 return -EINVAL;
856 if (ser->hub6 != 0)
857 return -EINVAL;
858 return 0;
859}
860
861/**
862 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
863 * called when the driver adds a cdns_uart port via
864 * uart_add_one_port()
865 * @port: Handle to the uart port structure
866 *
867 * Return: 0 on success, negative errno otherwise.
868 */
869static int cdns_uart_request_port(struct uart_port *port)
870{
871 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
872 CDNS_UART_NAME)) {
873 return -ENOMEM;
874 }
875
876 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
877 if (!port->membase) {
878 dev_err(port->dev, "Unable to map registers\n");
879 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
880 return -ENOMEM;
881 }
882 return 0;
883}
884
885/**
886 * cdns_uart_release_port - Release UART port
887 * @port: Handle to the uart port structure
888 *
889 * Release the memory region attached to a cdns_uart port. Called when the
890 * driver removes a cdns_uart port via uart_remove_one_port().
891 */
892static void cdns_uart_release_port(struct uart_port *port)
893{
894 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
895 iounmap(port->membase);
896 port->membase = NULL;
897}
898
899/**
900 * cdns_uart_config_port - Configure UART port
901 * @port: Handle to the uart port structure
902 * @flags: If any
903 */
904static void cdns_uart_config_port(struct uart_port *port, int flags)
905{
906 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
907 port->type = PORT_XUARTPS;
908}
909
910/**
911 * cdns_uart_get_mctrl - Get the modem control state
912 * @port: Handle to the uart port structure
913 *
914 * Return: the modem control state
915 */
916static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
917{
918 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
919}
920
921static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
922{
923 u32 val;
924
925 val = readl(port->membase + CDNS_UART_MODEMCR);
926
927 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
928
929 if (mctrl & TIOCM_RTS)
930 val |= CDNS_UART_MODEMCR_RTS;
931 if (mctrl & TIOCM_DTR)
932 val |= CDNS_UART_MODEMCR_DTR;
933
934 writel(val, port->membase + CDNS_UART_MODEMCR);
935}
936
937#ifdef CONFIG_CONSOLE_POLL
938static int cdns_uart_poll_get_char(struct uart_port *port)
939{
940 int c;
941 unsigned long flags;
942
943 spin_lock_irqsave(&port->lock, flags);
944
945 /* Check if FIFO is empty */
946 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
947 c = NO_POLL_CHAR;
948 else /* Read a character */
949 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
950
951 spin_unlock_irqrestore(&port->lock, flags);
952
953 return c;
954}
955
956static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
957{
958 unsigned long flags;
959
960 spin_lock_irqsave(&port->lock, flags);
961
962 /* Wait until FIFO is empty */
963 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
964 cpu_relax();
965
966 /* Write a character */
967 writel(c, port->membase + CDNS_UART_FIFO);
968
969 /* Wait until FIFO is empty */
970 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
971 cpu_relax();
972
973 spin_unlock_irqrestore(&port->lock, flags);
974
975 return;
976}
977#endif
978
979static struct uart_ops cdns_uart_ops = {
980 .set_mctrl = cdns_uart_set_mctrl,
981 .get_mctrl = cdns_uart_get_mctrl,
982 .start_tx = cdns_uart_start_tx,
983 .stop_tx = cdns_uart_stop_tx,
984 .stop_rx = cdns_uart_stop_rx,
985 .tx_empty = cdns_uart_tx_empty,
986 .break_ctl = cdns_uart_break_ctl,
987 .set_termios = cdns_uart_set_termios,
988 .startup = cdns_uart_startup,
989 .shutdown = cdns_uart_shutdown,
990 .type = cdns_uart_type,
991 .verify_port = cdns_uart_verify_port,
992 .request_port = cdns_uart_request_port,
993 .release_port = cdns_uart_release_port,
994 .config_port = cdns_uart_config_port,
995#ifdef CONFIG_CONSOLE_POLL
996 .poll_get_char = cdns_uart_poll_get_char,
997 .poll_put_char = cdns_uart_poll_put_char,
998#endif
999};
1000
1001static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1002
1003/**
1004 * cdns_uart_get_port - Configure the port from platform device resource info
1005 * @id: Port id
1006 *
1007 * Return: a pointer to a uart_port or NULL for failure
1008 */
1009static struct uart_port *cdns_uart_get_port(int id)
1010{
1011 struct uart_port *port;
1012
1013 /* Try the given port id if failed use default method */
1014 if (cdns_uart_port[id].mapbase != 0) {
1015 /* Find the next unused port */
1016 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1017 if (cdns_uart_port[id].mapbase == 0)
1018 break;
1019 }
1020
1021 if (id >= CDNS_UART_NR_PORTS)
1022 return NULL;
1023
1024 port = &cdns_uart_port[id];
1025
1026 /* At this point, we've got an empty uart_port struct, initialize it */
1027 spin_lock_init(&port->lock);
1028 port->membase = NULL;
1029 port->irq = 0;
1030 port->type = PORT_UNKNOWN;
1031 port->iotype = UPIO_MEM32;
1032 port->flags = UPF_BOOT_AUTOCONF;
1033 port->ops = &cdns_uart_ops;
1034 port->fifosize = CDNS_UART_FIFO_SIZE;
1035 port->line = id;
1036 port->dev = NULL;
1037 return port;
1038}
1039
1040#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1041/**
1042 * cdns_uart_console_wait_tx - Wait for the TX to be full
1043 * @port: Handle to the uart port structure
1044 */
1045static void cdns_uart_console_wait_tx(struct uart_port *port)
1046{
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 barrier();
1049}
1050
1051/**
1052 * cdns_uart_console_putchar - write the character to the FIFO buffer
1053 * @port: Handle to the uart port structure
1054 * @ch: Character to be written
1055 */
1056static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1057{
1058 cdns_uart_console_wait_tx(port);
1059 writel(ch, port->membase + CDNS_UART_FIFO);
1060}
1061
1062static void __init cdns_early_write(struct console *con, const char *s,
1063 unsigned n)
1064{
1065 struct earlycon_device *dev = con->data;
1066
1067 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1068}
1069
1070static int __init cdns_early_console_setup(struct earlycon_device *device,
1071 const char *opt)
1072{
1073 if (!device->port.membase)
1074 return -ENODEV;
1075
1076 device->con->write = cdns_early_write;
1077
1078 return 0;
1079}
1080OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1081OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1082OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1083
1084/**
1085 * cdns_uart_console_write - perform write operation
1086 * @co: Console handle
1087 * @s: Pointer to character array
1088 * @count: No of characters
1089 */
1090static void cdns_uart_console_write(struct console *co, const char *s,
1091 unsigned int count)
1092{
1093 struct uart_port *port = &cdns_uart_port[co->index];
1094 unsigned long flags;
1095 unsigned int imr, ctrl;
1096 int locked = 1;
1097
1098 if (port->sysrq)
1099 locked = 0;
1100 else if (oops_in_progress)
1101 locked = spin_trylock_irqsave(&port->lock, flags);
1102 else
1103 spin_lock_irqsave(&port->lock, flags);
1104
1105 /* save and disable interrupt */
1106 imr = readl(port->membase + CDNS_UART_IMR);
1107 writel(imr, port->membase + CDNS_UART_IDR);
1108
1109 /*
1110 * Make sure that the tx part is enabled. Set the TX enable bit and
1111 * clear the TX disable bit to enable the transmitter.
1112 */
1113 ctrl = readl(port->membase + CDNS_UART_CR);
1114 ctrl &= ~CDNS_UART_CR_TX_DIS;
1115 ctrl |= CDNS_UART_CR_TX_EN;
1116 writel(ctrl, port->membase + CDNS_UART_CR);
1117
1118 uart_console_write(port, s, count, cdns_uart_console_putchar);
1119 cdns_uart_console_wait_tx(port);
1120
1121 writel(ctrl, port->membase + CDNS_UART_CR);
1122
1123 /* restore interrupt state */
1124 writel(imr, port->membase + CDNS_UART_IER);
1125
1126 if (locked)
1127 spin_unlock_irqrestore(&port->lock, flags);
1128}
1129
1130/**
1131 * cdns_uart_console_setup - Initialize the uart to default config
1132 * @co: Console handle
1133 * @options: Initial settings of uart
1134 *
1135 * Return: 0 on success, negative errno otherwise.
1136 */
1137static int __init cdns_uart_console_setup(struct console *co, char *options)
1138{
1139 struct uart_port *port = &cdns_uart_port[co->index];
1140 int baud = 9600;
1141 int bits = 8;
1142 int parity = 'n';
1143 int flow = 'n';
1144
1145 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1146 return -EINVAL;
1147
1148 if (!port->membase) {
1149 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1150 co->index);
1151 return -ENODEV;
1152 }
1153
1154 if (options)
1155 uart_parse_options(options, &baud, &parity, &bits, &flow);
1156
1157 return uart_set_options(port, co, baud, parity, bits, flow);
1158}
1159
1160static struct uart_driver cdns_uart_uart_driver;
1161
1162static struct console cdns_uart_console = {
1163 .name = CDNS_UART_TTY_NAME,
1164 .write = cdns_uart_console_write,
1165 .device = uart_console_device,
1166 .setup = cdns_uart_console_setup,
1167 .flags = CON_PRINTBUFFER,
1168 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1169 .data = &cdns_uart_uart_driver,
1170};
1171
1172/**
1173 * cdns_uart_console_init - Initialization call
1174 *
1175 * Return: 0 on success, negative errno otherwise
1176 */
1177static int __init cdns_uart_console_init(void)
1178{
1179 register_console(&cdns_uart_console);
1180 return 0;
1181}
1182
1183console_initcall(cdns_uart_console_init);
1184
1185#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1186
1187static struct uart_driver cdns_uart_uart_driver = {
1188 .owner = THIS_MODULE,
1189 .driver_name = CDNS_UART_NAME,
1190 .dev_name = CDNS_UART_TTY_NAME,
1191 .major = CDNS_UART_MAJOR,
1192 .minor = CDNS_UART_MINOR,
1193 .nr = CDNS_UART_NR_PORTS,
1194#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1195 .cons = &cdns_uart_console,
1196#endif
1197};
1198
1199#ifdef CONFIG_PM_SLEEP
1200/**
1201 * cdns_uart_suspend - suspend event
1202 * @device: Pointer to the device structure
1203 *
1204 * Return: 0
1205 */
1206static int cdns_uart_suspend(struct device *device)
1207{
1208 struct uart_port *port = dev_get_drvdata(device);
1209 struct tty_struct *tty;
1210 struct device *tty_dev;
1211 int may_wake = 0;
1212
1213 /* Get the tty which could be NULL so don't assume it's valid */
1214 tty = tty_port_tty_get(&port->state->port);
1215 if (tty) {
1216 tty_dev = tty->dev;
1217 may_wake = device_may_wakeup(tty_dev);
1218 tty_kref_put(tty);
1219 }
1220
1221 /*
1222 * Call the API provided in serial_core.c file which handles
1223 * the suspend.
1224 */
1225 uart_suspend_port(&cdns_uart_uart_driver, port);
1226 if (console_suspend_enabled && !may_wake) {
1227 struct cdns_uart *cdns_uart = port->private_data;
1228
1229 clk_disable(cdns_uart->uartclk);
1230 clk_disable(cdns_uart->pclk);
1231 } else {
1232 unsigned long flags = 0;
1233
1234 spin_lock_irqsave(&port->lock, flags);
1235 /* Empty the receive FIFO 1st before making changes */
1236 while (!(readl(port->membase + CDNS_UART_SR) &
1237 CDNS_UART_SR_RXEMPTY))
1238 readl(port->membase + CDNS_UART_FIFO);
1239 /* set RX trigger level to 1 */
1240 writel(1, port->membase + CDNS_UART_RXWM);
1241 /* disable RX timeout interrups */
1242 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1243 spin_unlock_irqrestore(&port->lock, flags);
1244 }
1245
1246 return 0;
1247}
1248
1249/**
1250 * cdns_uart_resume - Resume after a previous suspend
1251 * @device: Pointer to the device structure
1252 *
1253 * Return: 0
1254 */
1255static int cdns_uart_resume(struct device *device)
1256{
1257 struct uart_port *port = dev_get_drvdata(device);
1258 unsigned long flags = 0;
1259 u32 ctrl_reg;
1260 struct tty_struct *tty;
1261 struct device *tty_dev;
1262 int may_wake = 0;
1263
1264 /* Get the tty which could be NULL so don't assume it's valid */
1265 tty = tty_port_tty_get(&port->state->port);
1266 if (tty) {
1267 tty_dev = tty->dev;
1268 may_wake = device_may_wakeup(tty_dev);
1269 tty_kref_put(tty);
1270 }
1271
1272 if (console_suspend_enabled && !may_wake) {
1273 struct cdns_uart *cdns_uart = port->private_data;
1274
1275 clk_enable(cdns_uart->pclk);
1276 clk_enable(cdns_uart->uartclk);
1277
1278 spin_lock_irqsave(&port->lock, flags);
1279
1280 /* Set TX/RX Reset */
1281 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1282 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1283 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1284 while (readl(port->membase + CDNS_UART_CR) &
1285 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1286 cpu_relax();
1287
1288 /* restore rx timeout value */
1289 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1290 /* Enable Tx/Rx */
1291 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1292 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1293 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1294 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1295
1296 spin_unlock_irqrestore(&port->lock, flags);
1297 } else {
1298 spin_lock_irqsave(&port->lock, flags);
1299 /* restore original rx trigger level */
1300 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1301 /* enable RX timeout interrupt */
1302 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 }
1305
1306 return uart_resume_port(&cdns_uart_uart_driver, port);
1307}
1308#endif /* ! CONFIG_PM_SLEEP */
1309
1310static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1311 cdns_uart_resume);
1312
1313/**
1314 * cdns_uart_probe - Platform driver probe
1315 * @pdev: Pointer to the platform device structure
1316 *
1317 * Return: 0 on success, negative errno otherwise
1318 */
1319static int cdns_uart_probe(struct platform_device *pdev)
1320{
1321 int rc, id, irq;
1322 struct uart_port *port;
1323 struct resource *res;
1324 struct cdns_uart *cdns_uart_data;
1325
1326 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1327 GFP_KERNEL);
1328 if (!cdns_uart_data)
1329 return -ENOMEM;
1330
1331 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1332 if (IS_ERR(cdns_uart_data->pclk)) {
1333 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1334 if (!IS_ERR(cdns_uart_data->pclk))
1335 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1336 }
1337 if (IS_ERR(cdns_uart_data->pclk)) {
1338 dev_err(&pdev->dev, "pclk clock not found.\n");
1339 return PTR_ERR(cdns_uart_data->pclk);
1340 }
1341
1342 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1343 if (IS_ERR(cdns_uart_data->uartclk)) {
1344 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1345 if (!IS_ERR(cdns_uart_data->uartclk))
1346 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1347 }
1348 if (IS_ERR(cdns_uart_data->uartclk)) {
1349 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1350 return PTR_ERR(cdns_uart_data->uartclk);
1351 }
1352
1353 rc = clk_prepare_enable(cdns_uart_data->pclk);
1354 if (rc) {
1355 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1356 return rc;
1357 }
1358 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1359 if (rc) {
1360 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1361 goto err_out_clk_dis_pclk;
1362 }
1363
1364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1365 if (!res) {
1366 rc = -ENODEV;
1367 goto err_out_clk_disable;
1368 }
1369
1370 irq = platform_get_irq(pdev, 0);
1371 if (irq <= 0) {
1372 rc = -ENXIO;
1373 goto err_out_clk_disable;
1374 }
1375
1376#ifdef CONFIG_COMMON_CLK
1377 cdns_uart_data->clk_rate_change_nb.notifier_call =
1378 cdns_uart_clk_notifier_cb;
1379 if (clk_notifier_register(cdns_uart_data->uartclk,
1380 &cdns_uart_data->clk_rate_change_nb))
1381 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1382#endif
1383 /* Look for a serialN alias */
1384 id = of_alias_get_id(pdev->dev.of_node, "serial");
1385 if (id < 0)
1386 id = 0;
1387
1388 /* Initialize the port structure */
1389 port = cdns_uart_get_port(id);
1390
1391 if (!port) {
1392 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1393 rc = -ENODEV;
1394 goto err_out_notif_unreg;
1395 }
1396
1397 /*
1398 * Register the port.
1399 * This function also registers this device with the tty layer
1400 * and triggers invocation of the config_port() entry point.
1401 */
1402 port->mapbase = res->start;
1403 port->irq = irq;
1404 port->dev = &pdev->dev;
1405 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1406 port->private_data = cdns_uart_data;
1407 cdns_uart_data->port = port;
1408 platform_set_drvdata(pdev, port);
1409
1410 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1411 if (rc) {
1412 dev_err(&pdev->dev,
1413 "uart_add_one_port() failed; err=%i\n", rc);
1414 goto err_out_notif_unreg;
1415 }
1416
1417 return 0;
1418
1419err_out_notif_unreg:
1420#ifdef CONFIG_COMMON_CLK
1421 clk_notifier_unregister(cdns_uart_data->uartclk,
1422 &cdns_uart_data->clk_rate_change_nb);
1423#endif
1424err_out_clk_disable:
1425 clk_disable_unprepare(cdns_uart_data->uartclk);
1426err_out_clk_dis_pclk:
1427 clk_disable_unprepare(cdns_uart_data->pclk);
1428
1429 return rc;
1430}
1431
1432/**
1433 * cdns_uart_remove - called when the platform driver is unregistered
1434 * @pdev: Pointer to the platform device structure
1435 *
1436 * Return: 0 on success, negative errno otherwise
1437 */
1438static int cdns_uart_remove(struct platform_device *pdev)
1439{
1440 struct uart_port *port = platform_get_drvdata(pdev);
1441 struct cdns_uart *cdns_uart_data = port->private_data;
1442 int rc;
1443
1444 /* Remove the cdns_uart port from the serial core */
1445#ifdef CONFIG_COMMON_CLK
1446 clk_notifier_unregister(cdns_uart_data->uartclk,
1447 &cdns_uart_data->clk_rate_change_nb);
1448#endif
1449 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1450 port->mapbase = 0;
1451 clk_disable_unprepare(cdns_uart_data->uartclk);
1452 clk_disable_unprepare(cdns_uart_data->pclk);
1453 return rc;
1454}
1455
1456/* Match table for of_platform binding */
1457static const struct of_device_id cdns_uart_of_match[] = {
1458 { .compatible = "xlnx,xuartps", },
1459 { .compatible = "cdns,uart-r1p8", },
1460 {}
1461};
1462MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1463
1464static struct platform_driver cdns_uart_platform_driver = {
1465 .probe = cdns_uart_probe,
1466 .remove = cdns_uart_remove,
1467 .driver = {
1468 .name = CDNS_UART_NAME,
1469 .of_match_table = cdns_uart_of_match,
1470 .pm = &cdns_uart_dev_pm_ops,
1471 },
1472};
1473
1474static int __init cdns_uart_init(void)
1475{
1476 int retval = 0;
1477
1478 /* Register the cdns_uart driver with the serial core */
1479 retval = uart_register_driver(&cdns_uart_uart_driver);
1480 if (retval)
1481 return retval;
1482
1483 /* Register the platform driver */
1484 retval = platform_driver_register(&cdns_uart_platform_driver);
1485 if (retval)
1486 uart_unregister_driver(&cdns_uart_uart_driver);
1487
1488 return retval;
1489}
1490
1491static void __exit cdns_uart_exit(void)
1492{
1493 /* Unregister the platform driver */
1494 platform_driver_unregister(&cdns_uart_platform_driver);
1495
1496 /* Unregister the cdns_uart driver */
1497 uart_unregister_driver(&cdns_uart_uart_driver);
1498}
1499
1500module_init(cdns_uart_init);
1501module_exit(cdns_uart_exit);
1502
1503MODULE_DESCRIPTION("Driver for Cadence UART");
1504MODULE_AUTHOR("Xilinx Inc.");
1505MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * 2011 - 2014 (C) Xilinx Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/console.h>
19#include <linux/serial_core.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29
30#define CDNS_UART_TTY_NAME "ttyPS"
31#define CDNS_UART_NAME "xuartps"
32#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
34#define CDNS_UART_NR_PORTS 2
35#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
36#define CDNS_UART_REGISTER_SPACE 0x1000
37
38/* Rx Trigger level */
39static int rx_trigger_level = 56;
40module_param(rx_trigger_level, uint, S_IRUGO);
41MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43/* Rx Timeout */
44static int rx_timeout = 10;
45module_param(rx_timeout, uint, S_IRUGO);
46MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48/* Register offsets for the UART. */
49#define CDNS_UART_CR 0x00 /* Control Register */
50#define CDNS_UART_MR 0x04 /* Mode Register */
51#define CDNS_UART_IER 0x08 /* Interrupt Enable */
52#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54#define CDNS_UART_ISR 0x14 /* Interrupt Status */
55#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60#define CDNS_UART_SR 0x2C /* Channel Status */
61#define CDNS_UART_FIFO 0x30 /* FIFO */
62#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69/* Control Register Bit Definitions */
70#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107/*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147/* Goes in read_status_mask for break detection as the HW doesn't do it*/
148#define CDNS_UART_IXR_BRK 0x00002000
149
150#define CDNS_UART_RXBS_SUPPORT BIT(1)
151/*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160/*
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
165 */
166#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
170
171/* baud dividers min/max values */
172#define CDNS_UART_BDIV_MIN 4
173#define CDNS_UART_BDIV_MAX 255
174#define CDNS_UART_CD_MAX 65535
175#define UART_AUTOSUSPEND_TIMEOUT 3000
176
177/**
178 * struct cdns_uart - device data
179 * @port: Pointer to the UART port
180 * @uartclk: Reference clock
181 * @pclk: APB clock
182 * @baud: Current baud rate
183 * @clk_rate_change_nb: Notifier block for clock changes
184 * @quirks: Flags for RXBS support.
185 */
186struct cdns_uart {
187 struct uart_port *port;
188 struct clk *uartclk;
189 struct clk *pclk;
190 unsigned int baud;
191 struct notifier_block clk_rate_change_nb;
192 u32 quirks;
193};
194struct cdns_platform_data {
195 u32 quirks;
196};
197#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
198 clk_rate_change_nb);
199
200/**
201 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
202 * @dev_id: Id of the UART port
203 * @isrstatus: The interrupt status register value as read
204 * Return: None
205 */
206static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
207{
208 struct uart_port *port = (struct uart_port *)dev_id;
209 struct cdns_uart *cdns_uart = port->private_data;
210 unsigned int data;
211 unsigned int rxbs_status = 0;
212 unsigned int status_mask;
213 unsigned int framerrprocessed = 0;
214 char status = TTY_NORMAL;
215 bool is_rxbs_support;
216
217 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
218
219 while ((readl(port->membase + CDNS_UART_SR) &
220 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
221 if (is_rxbs_support)
222 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
223 data = readl(port->membase + CDNS_UART_FIFO);
224 port->icount.rx++;
225 /*
226 * There is no hardware break detection in Zynq, so we interpret
227 * framing error with all-zeros data as a break sequence.
228 * Most of the time, there's another non-zero byte at the
229 * end of the sequence.
230 */
231 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
232 if (!data) {
233 port->read_status_mask |= CDNS_UART_IXR_BRK;
234 framerrprocessed = 1;
235 continue;
236 }
237 }
238 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
239 port->icount.brk++;
240 status = TTY_BREAK;
241 if (uart_handle_break(port))
242 continue;
243 }
244
245 isrstatus &= port->read_status_mask;
246 isrstatus &= ~port->ignore_status_mask;
247 status_mask = port->read_status_mask;
248 status_mask &= ~port->ignore_status_mask;
249
250 if (data &&
251 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
252 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
253 port->icount.brk++;
254 if (uart_handle_break(port))
255 continue;
256 }
257
258 if (uart_handle_sysrq_char(port, data))
259 continue;
260
261 if (is_rxbs_support) {
262 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
263 && (status_mask & CDNS_UART_IXR_PARITY)) {
264 port->icount.parity++;
265 status = TTY_PARITY;
266 }
267 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
268 && (status_mask & CDNS_UART_IXR_PARITY)) {
269 port->icount.frame++;
270 status = TTY_FRAME;
271 }
272 } else {
273 if (isrstatus & CDNS_UART_IXR_PARITY) {
274 port->icount.parity++;
275 status = TTY_PARITY;
276 }
277 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
278 !framerrprocessed) {
279 port->icount.frame++;
280 status = TTY_FRAME;
281 }
282 }
283 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
284 port->icount.overrun++;
285 tty_insert_flip_char(&port->state->port, 0,
286 TTY_OVERRUN);
287 }
288 tty_insert_flip_char(&port->state->port, data, status);
289 isrstatus = 0;
290 }
291 spin_unlock(&port->lock);
292 tty_flip_buffer_push(&port->state->port);
293 spin_lock(&port->lock);
294}
295
296/**
297 * cdns_uart_handle_tx - Handle the bytes to be Txed.
298 * @dev_id: Id of the UART port
299 * Return: None
300 */
301static void cdns_uart_handle_tx(void *dev_id)
302{
303 struct uart_port *port = (struct uart_port *)dev_id;
304 unsigned int numbytes;
305
306 if (uart_circ_empty(&port->state->xmit)) {
307 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
308 } else {
309 numbytes = port->fifosize;
310 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
311 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
312 /*
313 * Get the data from the UART circular buffer
314 * and write it to the cdns_uart's TX_FIFO
315 * register.
316 */
317 writel(
318 port->state->xmit.buf[port->state->xmit.
319 tail], port->membase + CDNS_UART_FIFO);
320
321 port->icount.tx++;
322
323 /*
324 * Adjust the tail of the UART buffer and wrap
325 * the buffer if it reaches limit.
326 */
327 port->state->xmit.tail =
328 (port->state->xmit.tail + 1) &
329 (UART_XMIT_SIZE - 1);
330
331 numbytes--;
332 }
333
334 if (uart_circ_chars_pending(
335 &port->state->xmit) < WAKEUP_CHARS)
336 uart_write_wakeup(port);
337 }
338}
339
340/**
341 * cdns_uart_isr - Interrupt handler
342 * @irq: Irq number
343 * @dev_id: Id of the port
344 *
345 * Return: IRQHANDLED
346 */
347static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
348{
349 struct uart_port *port = (struct uart_port *)dev_id;
350 unsigned int isrstatus;
351
352 spin_lock(&port->lock);
353
354 /* Read the interrupt status register to determine which
355 * interrupt(s) is/are active and clear them.
356 */
357 isrstatus = readl(port->membase + CDNS_UART_ISR);
358 writel(isrstatus, port->membase + CDNS_UART_ISR);
359
360 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
361 cdns_uart_handle_tx(dev_id);
362 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
363 }
364 if (isrstatus & CDNS_UART_IXR_MASK)
365 cdns_uart_handle_rx(dev_id, isrstatus);
366
367 spin_unlock(&port->lock);
368 return IRQ_HANDLED;
369}
370
371/**
372 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
373 * @clk: UART module input clock
374 * @baud: Desired baud rate
375 * @rbdiv: BDIV value (return value)
376 * @rcd: CD value (return value)
377 * @div8: Value for clk_sel bit in mod (return value)
378 * Return: baud rate, requested baud when possible, or actual baud when there
379 * was too much error, zero if no valid divisors are found.
380 *
381 * Formula to obtain baud rate is
382 * baud_tx/rx rate = clk/CD * (BDIV + 1)
383 * input_clk = (Uart User Defined Clock or Apb Clock)
384 * depends on UCLKEN in MR Reg
385 * clk = input_clk or input_clk/8;
386 * depends on CLKS in MR reg
387 * CD and BDIV depends on values in
388 * baud rate generate register
389 * baud rate clock divisor register
390 */
391static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
392 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
393{
394 u32 cd, bdiv;
395 unsigned int calc_baud;
396 unsigned int bestbaud = 0;
397 unsigned int bauderror;
398 unsigned int besterror = ~0;
399
400 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
401 *div8 = 1;
402 clk /= 8;
403 } else {
404 *div8 = 0;
405 }
406
407 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
408 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
409 if (cd < 1 || cd > CDNS_UART_CD_MAX)
410 continue;
411
412 calc_baud = clk / (cd * (bdiv + 1));
413
414 if (baud > calc_baud)
415 bauderror = baud - calc_baud;
416 else
417 bauderror = calc_baud - baud;
418
419 if (besterror > bauderror) {
420 *rbdiv = bdiv;
421 *rcd = cd;
422 bestbaud = calc_baud;
423 besterror = bauderror;
424 }
425 }
426 /* use the values when percent error is acceptable */
427 if (((besterror * 100) / baud) < 3)
428 bestbaud = baud;
429
430 return bestbaud;
431}
432
433/**
434 * cdns_uart_set_baud_rate - Calculate and set the baud rate
435 * @port: Handle to the uart port structure
436 * @baud: Baud rate to set
437 * Return: baud rate, requested baud when possible, or actual baud when there
438 * was too much error, zero if no valid divisors are found.
439 */
440static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
441 unsigned int baud)
442{
443 unsigned int calc_baud;
444 u32 cd = 0, bdiv = 0;
445 u32 mreg;
446 int div8;
447 struct cdns_uart *cdns_uart = port->private_data;
448
449 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
450 &div8);
451
452 /* Write new divisors to hardware */
453 mreg = readl(port->membase + CDNS_UART_MR);
454 if (div8)
455 mreg |= CDNS_UART_MR_CLKSEL;
456 else
457 mreg &= ~CDNS_UART_MR_CLKSEL;
458 writel(mreg, port->membase + CDNS_UART_MR);
459 writel(cd, port->membase + CDNS_UART_BAUDGEN);
460 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
461 cdns_uart->baud = baud;
462
463 return calc_baud;
464}
465
466#ifdef CONFIG_COMMON_CLK
467/**
468 * cdns_uart_clk_notitifer_cb - Clock notifier callback
469 * @nb: Notifier block
470 * @event: Notify event
471 * @data: Notifier data
472 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
473 */
474static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
475 unsigned long event, void *data)
476{
477 u32 ctrl_reg;
478 struct uart_port *port;
479 int locked = 0;
480 struct clk_notifier_data *ndata = data;
481 unsigned long flags = 0;
482 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
483
484 port = cdns_uart->port;
485 if (port->suspended)
486 return NOTIFY_OK;
487
488 switch (event) {
489 case PRE_RATE_CHANGE:
490 {
491 u32 bdiv, cd;
492 int div8;
493
494 /*
495 * Find out if current baud-rate can be achieved with new clock
496 * frequency.
497 */
498 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
499 &bdiv, &cd, &div8)) {
500 dev_warn(port->dev, "clock rate change rejected\n");
501 return NOTIFY_BAD;
502 }
503
504 spin_lock_irqsave(&cdns_uart->port->lock, flags);
505
506 /* Disable the TX and RX to set baud rate */
507 ctrl_reg = readl(port->membase + CDNS_UART_CR);
508 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
509 writel(ctrl_reg, port->membase + CDNS_UART_CR);
510
511 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
512
513 return NOTIFY_OK;
514 }
515 case POST_RATE_CHANGE:
516 /*
517 * Set clk dividers to generate correct baud with new clock
518 * frequency.
519 */
520
521 spin_lock_irqsave(&cdns_uart->port->lock, flags);
522
523 locked = 1;
524 port->uartclk = ndata->new_rate;
525
526 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
527 cdns_uart->baud);
528 /* fall through */
529 case ABORT_RATE_CHANGE:
530 if (!locked)
531 spin_lock_irqsave(&cdns_uart->port->lock, flags);
532
533 /* Set TX/RX Reset */
534 ctrl_reg = readl(port->membase + CDNS_UART_CR);
535 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
536 writel(ctrl_reg, port->membase + CDNS_UART_CR);
537
538 while (readl(port->membase + CDNS_UART_CR) &
539 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
540 cpu_relax();
541
542 /*
543 * Clear the RX disable and TX disable bits and then set the TX
544 * enable bit and RX enable bit to enable the transmitter and
545 * receiver.
546 */
547 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
548 ctrl_reg = readl(port->membase + CDNS_UART_CR);
549 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
550 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
551 writel(ctrl_reg, port->membase + CDNS_UART_CR);
552
553 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
554
555 return NOTIFY_OK;
556 default:
557 return NOTIFY_DONE;
558 }
559}
560#endif
561
562/**
563 * cdns_uart_start_tx - Start transmitting bytes
564 * @port: Handle to the uart port structure
565 */
566static void cdns_uart_start_tx(struct uart_port *port)
567{
568 unsigned int status;
569
570 if (uart_tx_stopped(port))
571 return;
572
573 /*
574 * Set the TX enable bit and clear the TX disable bit to enable the
575 * transmitter.
576 */
577 status = readl(port->membase + CDNS_UART_CR);
578 status &= ~CDNS_UART_CR_TX_DIS;
579 status |= CDNS_UART_CR_TX_EN;
580 writel(status, port->membase + CDNS_UART_CR);
581
582 if (uart_circ_empty(&port->state->xmit))
583 return;
584
585 cdns_uart_handle_tx(port);
586
587 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
588 /* Enable the TX Empty interrupt */
589 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
590}
591
592/**
593 * cdns_uart_stop_tx - Stop TX
594 * @port: Handle to the uart port structure
595 */
596static void cdns_uart_stop_tx(struct uart_port *port)
597{
598 unsigned int regval;
599
600 regval = readl(port->membase + CDNS_UART_CR);
601 regval |= CDNS_UART_CR_TX_DIS;
602 /* Disable the transmitter */
603 writel(regval, port->membase + CDNS_UART_CR);
604}
605
606/**
607 * cdns_uart_stop_rx - Stop RX
608 * @port: Handle to the uart port structure
609 */
610static void cdns_uart_stop_rx(struct uart_port *port)
611{
612 unsigned int regval;
613
614 /* Disable RX IRQs */
615 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
616
617 /* Disable the receiver */
618 regval = readl(port->membase + CDNS_UART_CR);
619 regval |= CDNS_UART_CR_RX_DIS;
620 writel(regval, port->membase + CDNS_UART_CR);
621}
622
623/**
624 * cdns_uart_tx_empty - Check whether TX is empty
625 * @port: Handle to the uart port structure
626 *
627 * Return: TIOCSER_TEMT on success, 0 otherwise
628 */
629static unsigned int cdns_uart_tx_empty(struct uart_port *port)
630{
631 unsigned int status;
632
633 status = readl(port->membase + CDNS_UART_SR) &
634 CDNS_UART_SR_TXEMPTY;
635 return status ? TIOCSER_TEMT : 0;
636}
637
638/**
639 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
640 * transmitting char breaks
641 * @port: Handle to the uart port structure
642 * @ctl: Value based on which start or stop decision is taken
643 */
644static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
645{
646 unsigned int status;
647 unsigned long flags;
648
649 spin_lock_irqsave(&port->lock, flags);
650
651 status = readl(port->membase + CDNS_UART_CR);
652
653 if (ctl == -1)
654 writel(CDNS_UART_CR_STARTBRK | status,
655 port->membase + CDNS_UART_CR);
656 else {
657 if ((status & CDNS_UART_CR_STOPBRK) == 0)
658 writel(CDNS_UART_CR_STOPBRK | status,
659 port->membase + CDNS_UART_CR);
660 }
661 spin_unlock_irqrestore(&port->lock, flags);
662}
663
664/**
665 * cdns_uart_set_termios - termios operations, handling data length, parity,
666 * stop bits, flow control, baud rate
667 * @port: Handle to the uart port structure
668 * @termios: Handle to the input termios structure
669 * @old: Values of the previously saved termios structure
670 */
671static void cdns_uart_set_termios(struct uart_port *port,
672 struct ktermios *termios, struct ktermios *old)
673{
674 unsigned int cval = 0;
675 unsigned int baud, minbaud, maxbaud;
676 unsigned long flags;
677 unsigned int ctrl_reg, mode_reg;
678
679 spin_lock_irqsave(&port->lock, flags);
680
681 /* Wait for the transmit FIFO to empty before making changes */
682 if (!(readl(port->membase + CDNS_UART_CR) &
683 CDNS_UART_CR_TX_DIS)) {
684 while (!(readl(port->membase + CDNS_UART_SR) &
685 CDNS_UART_SR_TXEMPTY)) {
686 cpu_relax();
687 }
688 }
689
690 /* Disable the TX and RX to set baud rate */
691 ctrl_reg = readl(port->membase + CDNS_UART_CR);
692 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
693 writel(ctrl_reg, port->membase + CDNS_UART_CR);
694
695 /*
696 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
697 * min and max baud should be calculated here based on port->uartclk.
698 * this way we get a valid baud and can safely call set_baud()
699 */
700 minbaud = port->uartclk /
701 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
702 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
703 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
704 baud = cdns_uart_set_baud_rate(port, baud);
705 if (tty_termios_baud_rate(termios))
706 tty_termios_encode_baud_rate(termios, baud, baud);
707
708 /* Update the per-port timeout. */
709 uart_update_timeout(port, termios->c_cflag, baud);
710
711 /* Set TX/RX Reset */
712 ctrl_reg = readl(port->membase + CDNS_UART_CR);
713 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
714 writel(ctrl_reg, port->membase + CDNS_UART_CR);
715
716 while (readl(port->membase + CDNS_UART_CR) &
717 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
718 cpu_relax();
719
720 /*
721 * Clear the RX disable and TX disable bits and then set the TX enable
722 * bit and RX enable bit to enable the transmitter and receiver.
723 */
724 ctrl_reg = readl(port->membase + CDNS_UART_CR);
725 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
726 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
727 writel(ctrl_reg, port->membase + CDNS_UART_CR);
728
729 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
730
731 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
732 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
733 port->ignore_status_mask = 0;
734
735 if (termios->c_iflag & INPCK)
736 port->read_status_mask |= CDNS_UART_IXR_PARITY |
737 CDNS_UART_IXR_FRAMING;
738
739 if (termios->c_iflag & IGNPAR)
740 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
741 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
742
743 /* ignore all characters if CREAD is not set */
744 if ((termios->c_cflag & CREAD) == 0)
745 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
746 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
748
749 mode_reg = readl(port->membase + CDNS_UART_MR);
750
751 /* Handling Data Size */
752 switch (termios->c_cflag & CSIZE) {
753 case CS6:
754 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
755 break;
756 case CS7:
757 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
758 break;
759 default:
760 case CS8:
761 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
762 termios->c_cflag &= ~CSIZE;
763 termios->c_cflag |= CS8;
764 break;
765 }
766
767 /* Handling Parity and Stop Bits length */
768 if (termios->c_cflag & CSTOPB)
769 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
770 else
771 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
772
773 if (termios->c_cflag & PARENB) {
774 /* Mark or Space parity */
775 if (termios->c_cflag & CMSPAR) {
776 if (termios->c_cflag & PARODD)
777 cval |= CDNS_UART_MR_PARITY_MARK;
778 else
779 cval |= CDNS_UART_MR_PARITY_SPACE;
780 } else {
781 if (termios->c_cflag & PARODD)
782 cval |= CDNS_UART_MR_PARITY_ODD;
783 else
784 cval |= CDNS_UART_MR_PARITY_EVEN;
785 }
786 } else {
787 cval |= CDNS_UART_MR_PARITY_NONE;
788 }
789 cval |= mode_reg & 1;
790 writel(cval, port->membase + CDNS_UART_MR);
791
792 spin_unlock_irqrestore(&port->lock, flags);
793}
794
795/**
796 * cdns_uart_startup - Called when an application opens a cdns_uart port
797 * @port: Handle to the uart port structure
798 *
799 * Return: 0 on success, negative errno otherwise
800 */
801static int cdns_uart_startup(struct uart_port *port)
802{
803 struct cdns_uart *cdns_uart = port->private_data;
804 bool is_brk_support;
805 int ret;
806 unsigned long flags;
807 unsigned int status = 0;
808
809 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
810
811 spin_lock_irqsave(&port->lock, flags);
812
813 /* Disable the TX and RX */
814 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
815 port->membase + CDNS_UART_CR);
816
817 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
818 * no break chars.
819 */
820 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
821 port->membase + CDNS_UART_CR);
822
823 while (readl(port->membase + CDNS_UART_CR) &
824 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
825 cpu_relax();
826
827 /*
828 * Clear the RX disable bit and then set the RX enable bit to enable
829 * the receiver.
830 */
831 status = readl(port->membase + CDNS_UART_CR);
832 status &= CDNS_UART_CR_RX_DIS;
833 status |= CDNS_UART_CR_RX_EN;
834 writel(status, port->membase + CDNS_UART_CR);
835
836 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
837 * no parity.
838 */
839 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
840 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
841 port->membase + CDNS_UART_MR);
842
843 /*
844 * Set the RX FIFO Trigger level to use most of the FIFO, but it
845 * can be tuned with a module parameter
846 */
847 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
848
849 /*
850 * Receive Timeout register is enabled but it
851 * can be tuned with a module parameter
852 */
853 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
854
855 /* Clear out any pending interrupts before enabling them */
856 writel(readl(port->membase + CDNS_UART_ISR),
857 port->membase + CDNS_UART_ISR);
858
859 spin_unlock_irqrestore(&port->lock, flags);
860
861 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
862 if (ret) {
863 dev_err(port->dev, "request_irq '%d' failed with %d\n",
864 port->irq, ret);
865 return ret;
866 }
867
868 /* Set the Interrupt Registers with desired interrupts */
869 if (is_brk_support)
870 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
871 port->membase + CDNS_UART_IER);
872 else
873 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
874
875 return 0;
876}
877
878/**
879 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
880 * @port: Handle to the uart port structure
881 */
882static void cdns_uart_shutdown(struct uart_port *port)
883{
884 int status;
885 unsigned long flags;
886
887 spin_lock_irqsave(&port->lock, flags);
888
889 /* Disable interrupts */
890 status = readl(port->membase + CDNS_UART_IMR);
891 writel(status, port->membase + CDNS_UART_IDR);
892 writel(0xffffffff, port->membase + CDNS_UART_ISR);
893
894 /* Disable the TX and RX */
895 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
896 port->membase + CDNS_UART_CR);
897
898 spin_unlock_irqrestore(&port->lock, flags);
899
900 free_irq(port->irq, port);
901}
902
903/**
904 * cdns_uart_type - Set UART type to cdns_uart port
905 * @port: Handle to the uart port structure
906 *
907 * Return: string on success, NULL otherwise
908 */
909static const char *cdns_uart_type(struct uart_port *port)
910{
911 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
912}
913
914/**
915 * cdns_uart_verify_port - Verify the port params
916 * @port: Handle to the uart port structure
917 * @ser: Handle to the structure whose members are compared
918 *
919 * Return: 0 on success, negative errno otherwise.
920 */
921static int cdns_uart_verify_port(struct uart_port *port,
922 struct serial_struct *ser)
923{
924 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
925 return -EINVAL;
926 if (port->irq != ser->irq)
927 return -EINVAL;
928 if (ser->io_type != UPIO_MEM)
929 return -EINVAL;
930 if (port->iobase != ser->port)
931 return -EINVAL;
932 if (ser->hub6 != 0)
933 return -EINVAL;
934 return 0;
935}
936
937/**
938 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
939 * called when the driver adds a cdns_uart port via
940 * uart_add_one_port()
941 * @port: Handle to the uart port structure
942 *
943 * Return: 0 on success, negative errno otherwise.
944 */
945static int cdns_uart_request_port(struct uart_port *port)
946{
947 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
948 CDNS_UART_NAME)) {
949 return -ENOMEM;
950 }
951
952 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
953 if (!port->membase) {
954 dev_err(port->dev, "Unable to map registers\n");
955 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
956 return -ENOMEM;
957 }
958 return 0;
959}
960
961/**
962 * cdns_uart_release_port - Release UART port
963 * @port: Handle to the uart port structure
964 *
965 * Release the memory region attached to a cdns_uart port. Called when the
966 * driver removes a cdns_uart port via uart_remove_one_port().
967 */
968static void cdns_uart_release_port(struct uart_port *port)
969{
970 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
971 iounmap(port->membase);
972 port->membase = NULL;
973}
974
975/**
976 * cdns_uart_config_port - Configure UART port
977 * @port: Handle to the uart port structure
978 * @flags: If any
979 */
980static void cdns_uart_config_port(struct uart_port *port, int flags)
981{
982 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
983 port->type = PORT_XUARTPS;
984}
985
986/**
987 * cdns_uart_get_mctrl - Get the modem control state
988 * @port: Handle to the uart port structure
989 *
990 * Return: the modem control state
991 */
992static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
993{
994 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
995}
996
997static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
998{
999 u32 val;
1000 u32 mode_reg;
1001
1002 val = readl(port->membase + CDNS_UART_MODEMCR);
1003 mode_reg = readl(port->membase + CDNS_UART_MR);
1004
1005 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1006 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1007
1008 if (mctrl & TIOCM_RTS)
1009 val |= CDNS_UART_MODEMCR_RTS;
1010 if (mctrl & TIOCM_DTR)
1011 val |= CDNS_UART_MODEMCR_DTR;
1012 if (mctrl & TIOCM_LOOP)
1013 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1014 else
1015 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1016
1017 writel(val, port->membase + CDNS_UART_MODEMCR);
1018 writel(mode_reg, port->membase + CDNS_UART_MR);
1019}
1020
1021#ifdef CONFIG_CONSOLE_POLL
1022static int cdns_uart_poll_get_char(struct uart_port *port)
1023{
1024 int c;
1025 unsigned long flags;
1026
1027 spin_lock_irqsave(&port->lock, flags);
1028
1029 /* Check if FIFO is empty */
1030 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1031 c = NO_POLL_CHAR;
1032 else /* Read a character */
1033 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1034
1035 spin_unlock_irqrestore(&port->lock, flags);
1036
1037 return c;
1038}
1039
1040static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1041{
1042 unsigned long flags;
1043
1044 spin_lock_irqsave(&port->lock, flags);
1045
1046 /* Wait until FIFO is empty */
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 cpu_relax();
1049
1050 /* Write a character */
1051 writel(c, port->membase + CDNS_UART_FIFO);
1052
1053 /* Wait until FIFO is empty */
1054 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1055 cpu_relax();
1056
1057 spin_unlock_irqrestore(&port->lock, flags);
1058
1059 return;
1060}
1061#endif
1062
1063static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1064 unsigned int oldstate)
1065{
1066 switch (state) {
1067 case UART_PM_STATE_OFF:
1068 pm_runtime_mark_last_busy(port->dev);
1069 pm_runtime_put_autosuspend(port->dev);
1070 break;
1071 default:
1072 pm_runtime_get_sync(port->dev);
1073 break;
1074 }
1075}
1076
1077static const struct uart_ops cdns_uart_ops = {
1078 .set_mctrl = cdns_uart_set_mctrl,
1079 .get_mctrl = cdns_uart_get_mctrl,
1080 .start_tx = cdns_uart_start_tx,
1081 .stop_tx = cdns_uart_stop_tx,
1082 .stop_rx = cdns_uart_stop_rx,
1083 .tx_empty = cdns_uart_tx_empty,
1084 .break_ctl = cdns_uart_break_ctl,
1085 .set_termios = cdns_uart_set_termios,
1086 .startup = cdns_uart_startup,
1087 .shutdown = cdns_uart_shutdown,
1088 .pm = cdns_uart_pm,
1089 .type = cdns_uart_type,
1090 .verify_port = cdns_uart_verify_port,
1091 .request_port = cdns_uart_request_port,
1092 .release_port = cdns_uart_release_port,
1093 .config_port = cdns_uart_config_port,
1094#ifdef CONFIG_CONSOLE_POLL
1095 .poll_get_char = cdns_uart_poll_get_char,
1096 .poll_put_char = cdns_uart_poll_put_char,
1097#endif
1098};
1099
1100static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1101
1102/**
1103 * cdns_uart_get_port - Configure the port from platform device resource info
1104 * @id: Port id
1105 *
1106 * Return: a pointer to a uart_port or NULL for failure
1107 */
1108static struct uart_port *cdns_uart_get_port(int id)
1109{
1110 struct uart_port *port;
1111
1112 /* Try the given port id if failed use default method */
1113 if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) {
1114 /* Find the next unused port */
1115 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1116 if (cdns_uart_port[id].mapbase == 0)
1117 break;
1118 }
1119
1120 if (id >= CDNS_UART_NR_PORTS)
1121 return NULL;
1122
1123 port = &cdns_uart_port[id];
1124
1125 /* At this point, we've got an empty uart_port struct, initialize it */
1126 spin_lock_init(&port->lock);
1127 port->membase = NULL;
1128 port->irq = 0;
1129 port->type = PORT_UNKNOWN;
1130 port->iotype = UPIO_MEM32;
1131 port->flags = UPF_BOOT_AUTOCONF;
1132 port->ops = &cdns_uart_ops;
1133 port->fifosize = CDNS_UART_FIFO_SIZE;
1134 port->line = id;
1135 port->dev = NULL;
1136 return port;
1137}
1138
1139#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1140/**
1141 * cdns_uart_console_wait_tx - Wait for the TX to be full
1142 * @port: Handle to the uart port structure
1143 */
1144static void cdns_uart_console_wait_tx(struct uart_port *port)
1145{
1146 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1147 barrier();
1148}
1149
1150/**
1151 * cdns_uart_console_putchar - write the character to the FIFO buffer
1152 * @port: Handle to the uart port structure
1153 * @ch: Character to be written
1154 */
1155static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1156{
1157 cdns_uart_console_wait_tx(port);
1158 writel(ch, port->membase + CDNS_UART_FIFO);
1159}
1160
1161static void cdns_early_write(struct console *con, const char *s,
1162 unsigned n)
1163{
1164 struct earlycon_device *dev = con->data;
1165
1166 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1167}
1168
1169static int __init cdns_early_console_setup(struct earlycon_device *device,
1170 const char *opt)
1171{
1172 struct uart_port *port = &device->port;
1173
1174 if (!port->membase)
1175 return -ENODEV;
1176
1177 /* initialise control register */
1178 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1179 port->membase + CDNS_UART_CR);
1180
1181 /* only set baud if specified on command line - otherwise
1182 * assume it has been initialized by a boot loader.
1183 */
1184 if (port->uartclk && device->baud) {
1185 u32 cd = 0, bdiv = 0;
1186 u32 mr;
1187 int div8;
1188
1189 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1190 &bdiv, &cd, &div8);
1191 mr = CDNS_UART_MR_PARITY_NONE;
1192 if (div8)
1193 mr |= CDNS_UART_MR_CLKSEL;
1194
1195 writel(mr, port->membase + CDNS_UART_MR);
1196 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1197 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1198 }
1199
1200 device->con->write = cdns_early_write;
1201
1202 return 0;
1203}
1204OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1205OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1206OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1207OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1208
1209/**
1210 * cdns_uart_console_write - perform write operation
1211 * @co: Console handle
1212 * @s: Pointer to character array
1213 * @count: No of characters
1214 */
1215static void cdns_uart_console_write(struct console *co, const char *s,
1216 unsigned int count)
1217{
1218 struct uart_port *port = &cdns_uart_port[co->index];
1219 unsigned long flags;
1220 unsigned int imr, ctrl;
1221 int locked = 1;
1222
1223 if (port->sysrq)
1224 locked = 0;
1225 else if (oops_in_progress)
1226 locked = spin_trylock_irqsave(&port->lock, flags);
1227 else
1228 spin_lock_irqsave(&port->lock, flags);
1229
1230 /* save and disable interrupt */
1231 imr = readl(port->membase + CDNS_UART_IMR);
1232 writel(imr, port->membase + CDNS_UART_IDR);
1233
1234 /*
1235 * Make sure that the tx part is enabled. Set the TX enable bit and
1236 * clear the TX disable bit to enable the transmitter.
1237 */
1238 ctrl = readl(port->membase + CDNS_UART_CR);
1239 ctrl &= ~CDNS_UART_CR_TX_DIS;
1240 ctrl |= CDNS_UART_CR_TX_EN;
1241 writel(ctrl, port->membase + CDNS_UART_CR);
1242
1243 uart_console_write(port, s, count, cdns_uart_console_putchar);
1244 cdns_uart_console_wait_tx(port);
1245
1246 writel(ctrl, port->membase + CDNS_UART_CR);
1247
1248 /* restore interrupt state */
1249 writel(imr, port->membase + CDNS_UART_IER);
1250
1251 if (locked)
1252 spin_unlock_irqrestore(&port->lock, flags);
1253}
1254
1255/**
1256 * cdns_uart_console_setup - Initialize the uart to default config
1257 * @co: Console handle
1258 * @options: Initial settings of uart
1259 *
1260 * Return: 0 on success, negative errno otherwise.
1261 */
1262static int __init cdns_uart_console_setup(struct console *co, char *options)
1263{
1264 struct uart_port *port = &cdns_uart_port[co->index];
1265 int baud = 9600;
1266 int bits = 8;
1267 int parity = 'n';
1268 int flow = 'n';
1269
1270 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1271 return -EINVAL;
1272
1273 if (!port->membase) {
1274 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1275 co->index);
1276 return -ENODEV;
1277 }
1278
1279 if (options)
1280 uart_parse_options(options, &baud, &parity, &bits, &flow);
1281
1282 return uart_set_options(port, co, baud, parity, bits, flow);
1283}
1284
1285static struct uart_driver cdns_uart_uart_driver;
1286
1287static struct console cdns_uart_console = {
1288 .name = CDNS_UART_TTY_NAME,
1289 .write = cdns_uart_console_write,
1290 .device = uart_console_device,
1291 .setup = cdns_uart_console_setup,
1292 .flags = CON_PRINTBUFFER,
1293 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1294 .data = &cdns_uart_uart_driver,
1295};
1296
1297/**
1298 * cdns_uart_console_init - Initialization call
1299 *
1300 * Return: 0 on success, negative errno otherwise
1301 */
1302static int __init cdns_uart_console_init(void)
1303{
1304 register_console(&cdns_uart_console);
1305 return 0;
1306}
1307
1308console_initcall(cdns_uart_console_init);
1309
1310#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1311
1312static struct uart_driver cdns_uart_uart_driver = {
1313 .owner = THIS_MODULE,
1314 .driver_name = CDNS_UART_NAME,
1315 .dev_name = CDNS_UART_TTY_NAME,
1316 .major = CDNS_UART_MAJOR,
1317 .minor = CDNS_UART_MINOR,
1318 .nr = CDNS_UART_NR_PORTS,
1319#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1320 .cons = &cdns_uart_console,
1321#endif
1322};
1323
1324#ifdef CONFIG_PM_SLEEP
1325/**
1326 * cdns_uart_suspend - suspend event
1327 * @device: Pointer to the device structure
1328 *
1329 * Return: 0
1330 */
1331static int cdns_uart_suspend(struct device *device)
1332{
1333 struct uart_port *port = dev_get_drvdata(device);
1334 struct tty_struct *tty;
1335 struct device *tty_dev;
1336 int may_wake = 0;
1337
1338 /* Get the tty which could be NULL so don't assume it's valid */
1339 tty = tty_port_tty_get(&port->state->port);
1340 if (tty) {
1341 tty_dev = tty->dev;
1342 may_wake = device_may_wakeup(tty_dev);
1343 tty_kref_put(tty);
1344 }
1345
1346 /*
1347 * Call the API provided in serial_core.c file which handles
1348 * the suspend.
1349 */
1350 uart_suspend_port(&cdns_uart_uart_driver, port);
1351 if (!(console_suspend_enabled && !may_wake)) {
1352 unsigned long flags = 0;
1353
1354 spin_lock_irqsave(&port->lock, flags);
1355 /* Empty the receive FIFO 1st before making changes */
1356 while (!(readl(port->membase + CDNS_UART_SR) &
1357 CDNS_UART_SR_RXEMPTY))
1358 readl(port->membase + CDNS_UART_FIFO);
1359 /* set RX trigger level to 1 */
1360 writel(1, port->membase + CDNS_UART_RXWM);
1361 /* disable RX timeout interrups */
1362 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1363 spin_unlock_irqrestore(&port->lock, flags);
1364 }
1365
1366 return 0;
1367}
1368
1369/**
1370 * cdns_uart_resume - Resume after a previous suspend
1371 * @device: Pointer to the device structure
1372 *
1373 * Return: 0
1374 */
1375static int cdns_uart_resume(struct device *device)
1376{
1377 struct uart_port *port = dev_get_drvdata(device);
1378 unsigned long flags = 0;
1379 u32 ctrl_reg;
1380 struct tty_struct *tty;
1381 struct device *tty_dev;
1382 int may_wake = 0;
1383
1384 /* Get the tty which could be NULL so don't assume it's valid */
1385 tty = tty_port_tty_get(&port->state->port);
1386 if (tty) {
1387 tty_dev = tty->dev;
1388 may_wake = device_may_wakeup(tty_dev);
1389 tty_kref_put(tty);
1390 }
1391
1392 if (console_suspend_enabled && !may_wake) {
1393 struct cdns_uart *cdns_uart = port->private_data;
1394
1395 clk_enable(cdns_uart->pclk);
1396 clk_enable(cdns_uart->uartclk);
1397
1398 spin_lock_irqsave(&port->lock, flags);
1399
1400 /* Set TX/RX Reset */
1401 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1402 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1403 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1404 while (readl(port->membase + CDNS_UART_CR) &
1405 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1406 cpu_relax();
1407
1408 /* restore rx timeout value */
1409 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1410 /* Enable Tx/Rx */
1411 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1412 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1413 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1414 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1415
1416 clk_disable(cdns_uart->uartclk);
1417 clk_disable(cdns_uart->pclk);
1418 spin_unlock_irqrestore(&port->lock, flags);
1419 } else {
1420 spin_lock_irqsave(&port->lock, flags);
1421 /* restore original rx trigger level */
1422 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1423 /* enable RX timeout interrupt */
1424 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1425 spin_unlock_irqrestore(&port->lock, flags);
1426 }
1427
1428 return uart_resume_port(&cdns_uart_uart_driver, port);
1429}
1430#endif /* ! CONFIG_PM_SLEEP */
1431static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1432{
1433 struct platform_device *pdev = to_platform_device(dev);
1434 struct uart_port *port = platform_get_drvdata(pdev);
1435 struct cdns_uart *cdns_uart = port->private_data;
1436
1437 clk_disable(cdns_uart->uartclk);
1438 clk_disable(cdns_uart->pclk);
1439 return 0;
1440};
1441
1442static int __maybe_unused cdns_runtime_resume(struct device *dev)
1443{
1444 struct platform_device *pdev = to_platform_device(dev);
1445 struct uart_port *port = platform_get_drvdata(pdev);
1446 struct cdns_uart *cdns_uart = port->private_data;
1447
1448 clk_enable(cdns_uart->pclk);
1449 clk_enable(cdns_uart->uartclk);
1450 return 0;
1451};
1452
1453static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1454 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1455 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1456 cdns_runtime_resume, NULL)
1457};
1458
1459static const struct cdns_platform_data zynqmp_uart_def = {
1460 .quirks = CDNS_UART_RXBS_SUPPORT, };
1461
1462/* Match table for of_platform binding */
1463static const struct of_device_id cdns_uart_of_match[] = {
1464 { .compatible = "xlnx,xuartps", },
1465 { .compatible = "cdns,uart-r1p8", },
1466 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1467 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1468 {}
1469};
1470MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1471
1472/**
1473 * cdns_uart_probe - Platform driver probe
1474 * @pdev: Pointer to the platform device structure
1475 *
1476 * Return: 0 on success, negative errno otherwise
1477 */
1478static int cdns_uart_probe(struct platform_device *pdev)
1479{
1480 int rc, id, irq;
1481 struct uart_port *port;
1482 struct resource *res;
1483 struct cdns_uart *cdns_uart_data;
1484 const struct of_device_id *match;
1485
1486 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1487 GFP_KERNEL);
1488 if (!cdns_uart_data)
1489 return -ENOMEM;
1490
1491 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1492 if (match && match->data) {
1493 const struct cdns_platform_data *data = match->data;
1494
1495 cdns_uart_data->quirks = data->quirks;
1496 }
1497
1498 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1499 if (IS_ERR(cdns_uart_data->pclk)) {
1500 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1501 if (!IS_ERR(cdns_uart_data->pclk))
1502 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1503 }
1504 if (IS_ERR(cdns_uart_data->pclk)) {
1505 dev_err(&pdev->dev, "pclk clock not found.\n");
1506 return PTR_ERR(cdns_uart_data->pclk);
1507 }
1508
1509 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1510 if (IS_ERR(cdns_uart_data->uartclk)) {
1511 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1512 if (!IS_ERR(cdns_uart_data->uartclk))
1513 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1514 }
1515 if (IS_ERR(cdns_uart_data->uartclk)) {
1516 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1517 return PTR_ERR(cdns_uart_data->uartclk);
1518 }
1519
1520 rc = clk_prepare_enable(cdns_uart_data->pclk);
1521 if (rc) {
1522 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1523 return rc;
1524 }
1525 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1526 if (rc) {
1527 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1528 goto err_out_clk_dis_pclk;
1529 }
1530
1531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 if (!res) {
1533 rc = -ENODEV;
1534 goto err_out_clk_disable;
1535 }
1536
1537 irq = platform_get_irq(pdev, 0);
1538 if (irq <= 0) {
1539 rc = -ENXIO;
1540 goto err_out_clk_disable;
1541 }
1542
1543#ifdef CONFIG_COMMON_CLK
1544 cdns_uart_data->clk_rate_change_nb.notifier_call =
1545 cdns_uart_clk_notifier_cb;
1546 if (clk_notifier_register(cdns_uart_data->uartclk,
1547 &cdns_uart_data->clk_rate_change_nb))
1548 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1549#endif
1550 /* Look for a serialN alias */
1551 id = of_alias_get_id(pdev->dev.of_node, "serial");
1552 if (id < 0)
1553 id = 0;
1554
1555 /* Initialize the port structure */
1556 port = cdns_uart_get_port(id);
1557
1558 if (!port) {
1559 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1560 rc = -ENODEV;
1561 goto err_out_notif_unreg;
1562 }
1563
1564 /*
1565 * Register the port.
1566 * This function also registers this device with the tty layer
1567 * and triggers invocation of the config_port() entry point.
1568 */
1569 port->mapbase = res->start;
1570 port->irq = irq;
1571 port->dev = &pdev->dev;
1572 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1573 port->private_data = cdns_uart_data;
1574 cdns_uart_data->port = port;
1575 platform_set_drvdata(pdev, port);
1576
1577 pm_runtime_use_autosuspend(&pdev->dev);
1578 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1579 pm_runtime_set_active(&pdev->dev);
1580 pm_runtime_enable(&pdev->dev);
1581
1582 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1583 if (rc) {
1584 dev_err(&pdev->dev,
1585 "uart_add_one_port() failed; err=%i\n", rc);
1586 goto err_out_pm_disable;
1587 }
1588
1589 return 0;
1590
1591err_out_pm_disable:
1592 pm_runtime_disable(&pdev->dev);
1593 pm_runtime_set_suspended(&pdev->dev);
1594 pm_runtime_dont_use_autosuspend(&pdev->dev);
1595err_out_notif_unreg:
1596#ifdef CONFIG_COMMON_CLK
1597 clk_notifier_unregister(cdns_uart_data->uartclk,
1598 &cdns_uart_data->clk_rate_change_nb);
1599#endif
1600err_out_clk_disable:
1601 clk_disable_unprepare(cdns_uart_data->uartclk);
1602err_out_clk_dis_pclk:
1603 clk_disable_unprepare(cdns_uart_data->pclk);
1604
1605 return rc;
1606}
1607
1608/**
1609 * cdns_uart_remove - called when the platform driver is unregistered
1610 * @pdev: Pointer to the platform device structure
1611 *
1612 * Return: 0 on success, negative errno otherwise
1613 */
1614static int cdns_uart_remove(struct platform_device *pdev)
1615{
1616 struct uart_port *port = platform_get_drvdata(pdev);
1617 struct cdns_uart *cdns_uart_data = port->private_data;
1618 int rc;
1619
1620 /* Remove the cdns_uart port from the serial core */
1621#ifdef CONFIG_COMMON_CLK
1622 clk_notifier_unregister(cdns_uart_data->uartclk,
1623 &cdns_uart_data->clk_rate_change_nb);
1624#endif
1625 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1626 port->mapbase = 0;
1627 clk_disable_unprepare(cdns_uart_data->uartclk);
1628 clk_disable_unprepare(cdns_uart_data->pclk);
1629 pm_runtime_disable(&pdev->dev);
1630 pm_runtime_set_suspended(&pdev->dev);
1631 pm_runtime_dont_use_autosuspend(&pdev->dev);
1632 return rc;
1633}
1634
1635static struct platform_driver cdns_uart_platform_driver = {
1636 .probe = cdns_uart_probe,
1637 .remove = cdns_uart_remove,
1638 .driver = {
1639 .name = CDNS_UART_NAME,
1640 .of_match_table = cdns_uart_of_match,
1641 .pm = &cdns_uart_dev_pm_ops,
1642 },
1643};
1644
1645static int __init cdns_uart_init(void)
1646{
1647 int retval = 0;
1648
1649 /* Register the cdns_uart driver with the serial core */
1650 retval = uart_register_driver(&cdns_uart_uart_driver);
1651 if (retval)
1652 return retval;
1653
1654 /* Register the platform driver */
1655 retval = platform_driver_register(&cdns_uart_platform_driver);
1656 if (retval)
1657 uart_unregister_driver(&cdns_uart_uart_driver);
1658
1659 return retval;
1660}
1661
1662static void __exit cdns_uart_exit(void)
1663{
1664 /* Unregister the platform driver */
1665 platform_driver_unregister(&cdns_uart_platform_driver);
1666
1667 /* Unregister the cdns_uart driver */
1668 uart_unregister_driver(&cdns_uart_uart_driver);
1669}
1670
1671arch_initcall(cdns_uart_init);
1672module_exit(cdns_uart_exit);
1673
1674MODULE_DESCRIPTION("Driver for Cadence UART");
1675MODULE_AUTHOR("Xilinx Inc.");
1676MODULE_LICENSE("GPL");