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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef TEGRA_DC_H
11#define TEGRA_DC_H 1
12
13#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
14#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
15#define SYNCPT_CNTRL_NO_STALL (1 << 8)
16#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
17#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
18#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
19#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
20#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
21#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
22#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
23#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
24#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
25#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
26#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
27#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
28#define SYNCPT_VSYNC_ENABLE (1 << 8)
29#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
30#define DC_CMD_DISPLAY_COMMAND 0x032
31#define DISP_CTRL_MODE_STOP (0 << 5)
32#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
33#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
34#define DISP_CTRL_MODE_MASK (3 << 5)
35#define DC_CMD_SIGNAL_RAISE 0x033
36#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
37#define PW0_ENABLE (1 << 0)
38#define PW1_ENABLE (1 << 2)
39#define PW2_ENABLE (1 << 4)
40#define PW3_ENABLE (1 << 6)
41#define PW4_ENABLE (1 << 8)
42#define PM0_ENABLE (1 << 16)
43#define PM1_ENABLE (1 << 18)
44
45#define DC_CMD_INT_STATUS 0x037
46#define DC_CMD_INT_MASK 0x038
47#define DC_CMD_INT_ENABLE 0x039
48#define DC_CMD_INT_TYPE 0x03a
49#define DC_CMD_INT_POLARITY 0x03b
50#define CTXSW_INT (1 << 0)
51#define FRAME_END_INT (1 << 1)
52#define VBLANK_INT (1 << 2)
53#define WIN_A_UF_INT (1 << 8)
54#define WIN_B_UF_INT (1 << 9)
55#define WIN_C_UF_INT (1 << 10)
56#define WIN_A_OF_INT (1 << 14)
57#define WIN_B_OF_INT (1 << 15)
58#define WIN_C_OF_INT (1 << 16)
59
60#define DC_CMD_SIGNAL_RAISE1 0x03c
61#define DC_CMD_SIGNAL_RAISE2 0x03d
62#define DC_CMD_SIGNAL_RAISE3 0x03e
63
64#define DC_CMD_STATE_ACCESS 0x040
65#define READ_MUX (1 << 0)
66#define WRITE_MUX (1 << 2)
67
68#define DC_CMD_STATE_CONTROL 0x041
69#define GENERAL_ACT_REQ (1 << 0)
70#define WIN_A_ACT_REQ (1 << 1)
71#define WIN_B_ACT_REQ (1 << 2)
72#define WIN_C_ACT_REQ (1 << 3)
73#define CURSOR_ACT_REQ (1 << 7)
74#define GENERAL_UPDATE (1 << 8)
75#define WIN_A_UPDATE (1 << 9)
76#define WIN_B_UPDATE (1 << 10)
77#define WIN_C_UPDATE (1 << 11)
78#define CURSOR_UPDATE (1 << 15)
79#define NC_HOST_TRIG (1 << 24)
80
81#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
82#define WINDOW_A_SELECT (1 << 4)
83#define WINDOW_B_SELECT (1 << 5)
84#define WINDOW_C_SELECT (1 << 6)
85
86#define DC_CMD_REG_ACT_CONTROL 0x043
87
88#define DC_COM_CRC_CONTROL 0x300
89#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
90#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
91#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
92#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
93#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
94#define DC_COM_CRC_CHECKSUM 0x301
95#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
96#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
97#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
98#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
99#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
100#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
101#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
102#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
103
104#define DC_COM_PIN_MISC_CONTROL 0x31b
105#define DC_COM_PIN_PM0_CONTROL 0x31c
106#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
107#define DC_COM_PIN_PM1_CONTROL 0x31e
108#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
109
110#define DC_COM_SPI_CONTROL 0x320
111#define DC_COM_SPI_START_BYTE 0x321
112#define DC_COM_HSPI_WRITE_DATA_AB 0x322
113#define DC_COM_HSPI_WRITE_DATA_CD 0x323
114#define DC_COM_HSPI_CS_DC 0x324
115#define DC_COM_SCRATCH_REGISTER_A 0x325
116#define DC_COM_SCRATCH_REGISTER_B 0x326
117#define DC_COM_GPIO_CTRL 0x327
118#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
119#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
120
121#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
122#define H_PULSE0_ENABLE (1 << 8)
123#define H_PULSE1_ENABLE (1 << 10)
124#define H_PULSE2_ENABLE (1 << 12)
125
126#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
127
128#define DC_DISP_DISP_WIN_OPTIONS 0x402
129#define HDMI_ENABLE (1 << 30)
130#define DSI_ENABLE (1 << 29)
131#define SOR1_TIMING_CYA (1 << 27)
132#define SOR1_ENABLE (1 << 26)
133#define SOR_ENABLE (1 << 25)
134#define CURSOR_ENABLE (1 << 16)
135
136#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
137#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
138#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
139#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
140#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
141
142#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
143#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
144#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
145#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
146#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
147
148#define DC_DISP_DISP_TIMING_OPTIONS 0x405
149#define VSYNC_H_POSITION(x) ((x) & 0xfff)
150
151#define DC_DISP_REF_TO_SYNC 0x406
152#define DC_DISP_SYNC_WIDTH 0x407
153#define DC_DISP_BACK_PORCH 0x408
154#define DC_DISP_ACTIVE 0x409
155#define DC_DISP_FRONT_PORCH 0x40a
156#define DC_DISP_H_PULSE0_CONTROL 0x40b
157#define DC_DISP_H_PULSE0_POSITION_A 0x40c
158#define DC_DISP_H_PULSE0_POSITION_B 0x40d
159#define DC_DISP_H_PULSE0_POSITION_C 0x40e
160#define DC_DISP_H_PULSE0_POSITION_D 0x40f
161#define DC_DISP_H_PULSE1_CONTROL 0x410
162#define DC_DISP_H_PULSE1_POSITION_A 0x411
163#define DC_DISP_H_PULSE1_POSITION_B 0x412
164#define DC_DISP_H_PULSE1_POSITION_C 0x413
165#define DC_DISP_H_PULSE1_POSITION_D 0x414
166#define DC_DISP_H_PULSE2_CONTROL 0x415
167#define DC_DISP_H_PULSE2_POSITION_A 0x416
168#define DC_DISP_H_PULSE2_POSITION_B 0x417
169#define DC_DISP_H_PULSE2_POSITION_C 0x418
170#define DC_DISP_H_PULSE2_POSITION_D 0x419
171#define DC_DISP_V_PULSE0_CONTROL 0x41a
172#define DC_DISP_V_PULSE0_POSITION_A 0x41b
173#define DC_DISP_V_PULSE0_POSITION_B 0x41c
174#define DC_DISP_V_PULSE0_POSITION_C 0x41d
175#define DC_DISP_V_PULSE1_CONTROL 0x41e
176#define DC_DISP_V_PULSE1_POSITION_A 0x41f
177#define DC_DISP_V_PULSE1_POSITION_B 0x420
178#define DC_DISP_V_PULSE1_POSITION_C 0x421
179#define DC_DISP_V_PULSE2_CONTROL 0x422
180#define DC_DISP_V_PULSE2_POSITION_A 0x423
181#define DC_DISP_V_PULSE3_CONTROL 0x424
182#define DC_DISP_V_PULSE3_POSITION_A 0x425
183#define DC_DISP_M0_CONTROL 0x426
184#define DC_DISP_M1_CONTROL 0x427
185#define DC_DISP_DI_CONTROL 0x428
186#define DC_DISP_PP_CONTROL 0x429
187#define DC_DISP_PP_SELECT_A 0x42a
188#define DC_DISP_PP_SELECT_B 0x42b
189#define DC_DISP_PP_SELECT_C 0x42c
190#define DC_DISP_PP_SELECT_D 0x42d
191
192#define PULSE_MODE_NORMAL (0 << 3)
193#define PULSE_MODE_ONE_CLOCK (1 << 3)
194#define PULSE_POLARITY_HIGH (0 << 4)
195#define PULSE_POLARITY_LOW (1 << 4)
196#define PULSE_QUAL_ALWAYS (0 << 6)
197#define PULSE_QUAL_VACTIVE (2 << 6)
198#define PULSE_QUAL_VACTIVE1 (3 << 6)
199#define PULSE_LAST_START_A (0 << 8)
200#define PULSE_LAST_END_A (1 << 8)
201#define PULSE_LAST_START_B (2 << 8)
202#define PULSE_LAST_END_B (3 << 8)
203#define PULSE_LAST_START_C (4 << 8)
204#define PULSE_LAST_END_C (5 << 8)
205#define PULSE_LAST_START_D (6 << 8)
206#define PULSE_LAST_END_D (7 << 8)
207
208#define PULSE_START(x) (((x) & 0xfff) << 0)
209#define PULSE_END(x) (((x) & 0xfff) << 16)
210
211#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
212#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
213#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
214#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
215#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
216#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
217#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
218#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
219#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
220#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
221#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
222#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
223#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
224#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
225#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
226
227#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
228#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
229#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
230#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
231#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
232#define DISP_DATA_FORMAT_DF2S (4 << 0)
233#define DISP_DATA_FORMAT_DF3S (5 << 0)
234#define DISP_DATA_FORMAT_DFSPI (6 << 0)
235#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
236#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
237#define DISP_ALIGNMENT_MSB (0 << 8)
238#define DISP_ALIGNMENT_LSB (1 << 8)
239#define DISP_ORDER_RED_BLUE (0 << 9)
240#define DISP_ORDER_BLUE_RED (1 << 9)
241
242#define DC_DISP_DISP_COLOR_CONTROL 0x430
243#define BASE_COLOR_SIZE666 (0 << 0)
244#define BASE_COLOR_SIZE111 (1 << 0)
245#define BASE_COLOR_SIZE222 (2 << 0)
246#define BASE_COLOR_SIZE333 (3 << 0)
247#define BASE_COLOR_SIZE444 (4 << 0)
248#define BASE_COLOR_SIZE555 (5 << 0)
249#define BASE_COLOR_SIZE565 (6 << 0)
250#define BASE_COLOR_SIZE332 (7 << 0)
251#define BASE_COLOR_SIZE888 (8 << 0)
252#define DITHER_CONTROL_MASK (3 << 8)
253#define DITHER_CONTROL_DISABLE (0 << 8)
254#define DITHER_CONTROL_ORDERED (2 << 8)
255#define DITHER_CONTROL_ERRDIFF (3 << 8)
256#define BASE_COLOR_SIZE_MASK (0xf << 0)
257#define BASE_COLOR_SIZE_666 (0 << 0)
258#define BASE_COLOR_SIZE_111 (1 << 0)
259#define BASE_COLOR_SIZE_222 (2 << 0)
260#define BASE_COLOR_SIZE_333 (3 << 0)
261#define BASE_COLOR_SIZE_444 (4 << 0)
262#define BASE_COLOR_SIZE_555 (5 << 0)
263#define BASE_COLOR_SIZE_565 (6 << 0)
264#define BASE_COLOR_SIZE_332 (7 << 0)
265#define BASE_COLOR_SIZE_888 (8 << 0)
266
267#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
268#define SC1_H_QUALIFIER_NONE (1 << 16)
269#define SC0_H_QUALIFIER_NONE (1 << 0)
270
271#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
272#define DE_SELECT_ACTIVE_BLANK (0 << 0)
273#define DE_SELECT_ACTIVE (1 << 0)
274#define DE_SELECT_ACTIVE_IS (2 << 0)
275#define DE_CONTROL_ONECLK (0 << 2)
276#define DE_CONTROL_NORMAL (1 << 2)
277#define DE_CONTROL_EARLY_EXT (2 << 2)
278#define DE_CONTROL_EARLY (3 << 2)
279#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
280
281#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
282#define DC_DISP_LCD_SPI_OPTIONS 0x434
283#define DC_DISP_BORDER_COLOR 0x435
284#define DC_DISP_COLOR_KEY0_LOWER 0x436
285#define DC_DISP_COLOR_KEY0_UPPER 0x437
286#define DC_DISP_COLOR_KEY1_LOWER 0x438
287#define DC_DISP_COLOR_KEY1_UPPER 0x439
288
289#define DC_DISP_CURSOR_FOREGROUND 0x43c
290#define DC_DISP_CURSOR_BACKGROUND 0x43d
291
292#define DC_DISP_CURSOR_START_ADDR 0x43e
293#define CURSOR_CLIP_DISPLAY (0 << 28)
294#define CURSOR_CLIP_WIN_A (1 << 28)
295#define CURSOR_CLIP_WIN_B (2 << 28)
296#define CURSOR_CLIP_WIN_C (3 << 28)
297#define CURSOR_SIZE_32x32 (0 << 24)
298#define CURSOR_SIZE_64x64 (1 << 24)
299#define CURSOR_SIZE_128x128 (2 << 24)
300#define CURSOR_SIZE_256x256 (3 << 24)
301#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
302
303#define DC_DISP_CURSOR_POSITION 0x440
304#define DC_DISP_CURSOR_POSITION_NS 0x441
305
306#define DC_DISP_INIT_SEQ_CONTROL 0x442
307#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
308#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
309#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
310#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
311
312#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
313#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
314#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
315#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
316#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
317
318#define DC_DISP_DAC_CRT_CTRL 0x4c0
319#define DC_DISP_DISP_MISC_CONTROL 0x4c1
320#define DC_DISP_SD_CONTROL 0x4c2
321#define DC_DISP_SD_CSC_COEFF 0x4c3
322#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
323#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
324#define DC_DISP_DC_PIXEL_COUNT 0x4ce
325#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
326#define DC_DISP_SD_BL_PARAMETERS 0x4d7
327#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
328#define DC_DISP_SD_BL_CONTROL 0x4dc
329#define DC_DISP_SD_HW_K_VALUES 0x4dd
330#define DC_DISP_SD_MAN_K_VALUES 0x4de
331
332#define DC_DISP_INTERLACE_CONTROL 0x4e5
333#define INTERLACE_STATUS (1 << 2)
334#define INTERLACE_START (1 << 1)
335#define INTERLACE_ENABLE (1 << 0)
336
337#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
338#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
339#define CURSOR_MODE_LEGACY (0 << 24)
340#define CURSOR_MODE_NORMAL (1 << 24)
341#define CURSOR_DST_BLEND_ZERO (0 << 16)
342#define CURSOR_DST_BLEND_K1 (1 << 16)
343#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
344#define CURSOR_DST_BLEND_MASK (3 << 16)
345#define CURSOR_SRC_BLEND_K1 (0 << 8)
346#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
347#define CURSOR_SRC_BLEND_MASK (3 << 8)
348#define CURSOR_ALPHA 0xff
349
350#define DC_WIN_CSC_YOF 0x611
351#define DC_WIN_CSC_KYRGB 0x612
352#define DC_WIN_CSC_KUR 0x613
353#define DC_WIN_CSC_KVR 0x614
354#define DC_WIN_CSC_KUG 0x615
355#define DC_WIN_CSC_KVG 0x616
356#define DC_WIN_CSC_KUB 0x617
357#define DC_WIN_CSC_KVB 0x618
358
359#define DC_WIN_WIN_OPTIONS 0x700
360#define H_DIRECTION (1 << 0)
361#define V_DIRECTION (1 << 2)
362#define COLOR_EXPAND (1 << 6)
363#define CSC_ENABLE (1 << 18)
364#define WIN_ENABLE (1 << 30)
365
366#define DC_WIN_BYTE_SWAP 0x701
367#define BYTE_SWAP_NOSWAP (0 << 0)
368#define BYTE_SWAP_SWAP2 (1 << 0)
369#define BYTE_SWAP_SWAP4 (2 << 0)
370#define BYTE_SWAP_SWAP4HW (3 << 0)
371
372#define DC_WIN_BUFFER_CONTROL 0x702
373#define BUFFER_CONTROL_HOST (0 << 0)
374#define BUFFER_CONTROL_VI (1 << 0)
375#define BUFFER_CONTROL_EPP (2 << 0)
376#define BUFFER_CONTROL_MPEGE (3 << 0)
377#define BUFFER_CONTROL_SB2D (4 << 0)
378
379#define DC_WIN_COLOR_DEPTH 0x703
380#define WIN_COLOR_DEPTH_P1 0
381#define WIN_COLOR_DEPTH_P2 1
382#define WIN_COLOR_DEPTH_P4 2
383#define WIN_COLOR_DEPTH_P8 3
384#define WIN_COLOR_DEPTH_B4G4R4A4 4
385#define WIN_COLOR_DEPTH_B5G5R5A 5
386#define WIN_COLOR_DEPTH_B5G6R5 6
387#define WIN_COLOR_DEPTH_AB5G5R5 7
388#define WIN_COLOR_DEPTH_B8G8R8A8 12
389#define WIN_COLOR_DEPTH_R8G8B8A8 13
390#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
391#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
392#define WIN_COLOR_DEPTH_YCbCr422 16
393#define WIN_COLOR_DEPTH_YUV422 17
394#define WIN_COLOR_DEPTH_YCbCr420P 18
395#define WIN_COLOR_DEPTH_YUV420P 19
396#define WIN_COLOR_DEPTH_YCbCr422P 20
397#define WIN_COLOR_DEPTH_YUV422P 21
398#define WIN_COLOR_DEPTH_YCbCr422R 22
399#define WIN_COLOR_DEPTH_YUV422R 23
400#define WIN_COLOR_DEPTH_YCbCr422RA 24
401#define WIN_COLOR_DEPTH_YUV422RA 25
402
403#define DC_WIN_POSITION 0x704
404#define H_POSITION(x) (((x) & 0x1fff) << 0)
405#define V_POSITION(x) (((x) & 0x1fff) << 16)
406
407#define DC_WIN_SIZE 0x705
408#define H_SIZE(x) (((x) & 0x1fff) << 0)
409#define V_SIZE(x) (((x) & 0x1fff) << 16)
410
411#define DC_WIN_PRESCALED_SIZE 0x706
412#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
413#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
414
415#define DC_WIN_H_INITIAL_DDA 0x707
416#define DC_WIN_V_INITIAL_DDA 0x708
417#define DC_WIN_DDA_INC 0x709
418#define H_DDA_INC(x) (((x) & 0xffff) << 0)
419#define V_DDA_INC(x) (((x) & 0xffff) << 16)
420
421#define DC_WIN_LINE_STRIDE 0x70a
422#define DC_WIN_BUF_STRIDE 0x70b
423#define DC_WIN_UV_BUF_STRIDE 0x70c
424#define DC_WIN_BUFFER_ADDR_MODE 0x70d
425#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
426#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
427#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
428#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
429#define DC_WIN_DV_CONTROL 0x70e
430
431#define DC_WIN_BLEND_NOKEY 0x70f
432#define DC_WIN_BLEND_1WIN 0x710
433#define DC_WIN_BLEND_2WIN_X 0x711
434#define DC_WIN_BLEND_2WIN_Y 0x712
435#define DC_WIN_BLEND_3WIN_XY 0x713
436
437#define DC_WIN_HP_FETCH_CONTROL 0x714
438
439#define DC_WINBUF_START_ADDR 0x800
440#define DC_WINBUF_START_ADDR_NS 0x801
441#define DC_WINBUF_START_ADDR_U 0x802
442#define DC_WINBUF_START_ADDR_U_NS 0x803
443#define DC_WINBUF_START_ADDR_V 0x804
444#define DC_WINBUF_START_ADDR_V_NS 0x805
445
446#define DC_WINBUF_ADDR_H_OFFSET 0x806
447#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
448#define DC_WINBUF_ADDR_V_OFFSET 0x808
449#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
450
451#define DC_WINBUF_UFLOW_STATUS 0x80a
452#define DC_WINBUF_SURFACE_KIND 0x80b
453#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
454#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
455#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
456#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
457
458#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
459#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
460#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
461
462#endif /* TEGRA_DC_H */
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef TEGRA_DC_H
11#define TEGRA_DC_H 1
12
13#include <linux/host1x.h>
14
15#include <drm/drm_crtc.h>
16
17#include "drm.h"
18
19struct tegra_output;
20
21struct tegra_dc_state {
22 struct drm_crtc_state base;
23
24 struct clk *clk;
25 unsigned long pclk;
26 unsigned int div;
27
28 u32 planes;
29};
30
31static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
32{
33 if (state)
34 return container_of(state, struct tegra_dc_state, base);
35
36 return NULL;
37}
38
39struct tegra_dc_stats {
40 unsigned long frames;
41 unsigned long vblank;
42 unsigned long underflow;
43 unsigned long overflow;
44};
45
46struct tegra_windowgroup_soc {
47 unsigned int index;
48 unsigned int dc;
49 const unsigned int *windows;
50 unsigned int num_windows;
51};
52
53struct tegra_dc_soc_info {
54 bool supports_background_color;
55 bool supports_interlacing;
56 bool supports_cursor;
57 bool supports_block_linear;
58 bool supports_blending;
59 unsigned int pitch_align;
60 bool has_powergate;
61 bool coupled_pm;
62 bool has_nvdisplay;
63 const struct tegra_windowgroup_soc *wgrps;
64 unsigned int num_wgrps;
65 const u32 *primary_formats;
66 unsigned int num_primary_formats;
67 const u32 *overlay_formats;
68 unsigned int num_overlay_formats;
69 const u64 *modifiers;
70};
71
72struct tegra_dc {
73 struct host1x_client client;
74 struct host1x_syncpt *syncpt;
75 struct device *dev;
76
77 struct drm_crtc base;
78 unsigned int powergate;
79 int pipe;
80
81 struct clk *clk;
82 struct reset_control *rst;
83 void __iomem *regs;
84 int irq;
85
86 struct tegra_output *rgb;
87
88 struct tegra_dc_stats stats;
89 struct list_head list;
90
91 struct drm_info_list *debugfs_files;
92
93 const struct tegra_dc_soc_info *soc;
94
95 struct iommu_domain *domain;
96};
97
98static inline struct tegra_dc *
99host1x_client_to_dc(struct host1x_client *client)
100{
101 return container_of(client, struct tegra_dc, client);
102}
103
104static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
105{
106 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
107}
108
109static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
110 unsigned int offset)
111{
112 trace_dc_writel(dc->dev, offset, value);
113 writel(value, dc->regs + (offset << 2));
114}
115
116static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
117{
118 u32 value = readl(dc->regs + (offset << 2));
119
120 trace_dc_readl(dc->dev, offset, value);
121
122 return value;
123}
124
125struct tegra_dc_window {
126 struct {
127 unsigned int x;
128 unsigned int y;
129 unsigned int w;
130 unsigned int h;
131 } src;
132 struct {
133 unsigned int x;
134 unsigned int y;
135 unsigned int w;
136 unsigned int h;
137 } dst;
138 unsigned int bits_per_pixel;
139 unsigned int stride[2];
140 unsigned long base[3];
141 unsigned int zpos;
142 bool bottom_up;
143
144 struct tegra_bo_tiling tiling;
145 u32 format;
146 u32 swap;
147};
148
149/* from dc.c */
150bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
151void tegra_dc_commit(struct tegra_dc *dc);
152int tegra_dc_state_setup_clock(struct tegra_dc *dc,
153 struct drm_crtc_state *crtc_state,
154 struct clk *clk, unsigned long pclk,
155 unsigned int div);
156
157/* from rgb.c */
158int tegra_dc_rgb_probe(struct tegra_dc *dc);
159int tegra_dc_rgb_remove(struct tegra_dc *dc);
160int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
161int tegra_dc_rgb_exit(struct tegra_dc *dc);
162
163#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
164#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
165#define SYNCPT_CNTRL_NO_STALL (1 << 8)
166#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
167#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
168#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
169#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
170#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
171#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
172#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
173#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
174#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
175#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
176#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
177#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
178#define SYNCPT_VSYNC_ENABLE (1 << 8)
179#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
180#define DC_CMD_DISPLAY_COMMAND 0x032
181#define DISP_CTRL_MODE_STOP (0 << 5)
182#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
183#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
184#define DISP_CTRL_MODE_MASK (3 << 5)
185#define DC_CMD_SIGNAL_RAISE 0x033
186#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
187#define PW0_ENABLE (1 << 0)
188#define PW1_ENABLE (1 << 2)
189#define PW2_ENABLE (1 << 4)
190#define PW3_ENABLE (1 << 6)
191#define PW4_ENABLE (1 << 8)
192#define PM0_ENABLE (1 << 16)
193#define PM1_ENABLE (1 << 18)
194
195#define DC_CMD_INT_STATUS 0x037
196#define DC_CMD_INT_MASK 0x038
197#define DC_CMD_INT_ENABLE 0x039
198#define DC_CMD_INT_TYPE 0x03a
199#define DC_CMD_INT_POLARITY 0x03b
200#define CTXSW_INT (1 << 0)
201#define FRAME_END_INT (1 << 1)
202#define VBLANK_INT (1 << 2)
203#define V_PULSE3_INT (1 << 4)
204#define V_PULSE2_INT (1 << 5)
205#define REGION_CRC_INT (1 << 6)
206#define REG_TMOUT_INT (1 << 7)
207#define WIN_A_UF_INT (1 << 8)
208#define WIN_B_UF_INT (1 << 9)
209#define WIN_C_UF_INT (1 << 10)
210#define MSF_INT (1 << 12)
211#define WIN_A_OF_INT (1 << 14)
212#define WIN_B_OF_INT (1 << 15)
213#define WIN_C_OF_INT (1 << 16)
214#define HEAD_UF_INT (1 << 23)
215#define SD3_BUCKET_WALK_DONE_INT (1 << 24)
216#define DSC_OBUF_UF_INT (1 << 26)
217#define DSC_RBUF_UF_INT (1 << 27)
218#define DSC_BBUF_UF_INT (1 << 28)
219#define DSC_TO_UF_INT (1 << 29)
220
221#define DC_CMD_SIGNAL_RAISE1 0x03c
222#define DC_CMD_SIGNAL_RAISE2 0x03d
223#define DC_CMD_SIGNAL_RAISE3 0x03e
224
225#define DC_CMD_STATE_ACCESS 0x040
226#define READ_MUX (1 << 0)
227#define WRITE_MUX (1 << 2)
228
229#define DC_CMD_STATE_CONTROL 0x041
230#define GENERAL_ACT_REQ (1 << 0)
231#define WIN_A_ACT_REQ (1 << 1)
232#define WIN_B_ACT_REQ (1 << 2)
233#define WIN_C_ACT_REQ (1 << 3)
234#define CURSOR_ACT_REQ (1 << 7)
235#define GENERAL_UPDATE (1 << 8)
236#define WIN_A_UPDATE (1 << 9)
237#define WIN_B_UPDATE (1 << 10)
238#define WIN_C_UPDATE (1 << 11)
239#define CURSOR_UPDATE (1 << 15)
240#define COMMON_ACTREQ (1 << 16)
241#define COMMON_UPDATE (1 << 17)
242#define NC_HOST_TRIG (1 << 24)
243
244#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
245#define WINDOW_A_SELECT (1 << 4)
246#define WINDOW_B_SELECT (1 << 5)
247#define WINDOW_C_SELECT (1 << 6)
248
249#define DC_CMD_REG_ACT_CONTROL 0x043
250
251#define DC_COM_CRC_CONTROL 0x300
252#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
253#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
254#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
255#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
256#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
257#define DC_COM_CRC_CHECKSUM 0x301
258#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
259#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
260#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
261#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
262#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
263#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
264#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
265#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
266
267#define DC_COM_PIN_MISC_CONTROL 0x31b
268#define DC_COM_PIN_PM0_CONTROL 0x31c
269#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
270#define DC_COM_PIN_PM1_CONTROL 0x31e
271#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
272
273#define DC_COM_SPI_CONTROL 0x320
274#define DC_COM_SPI_START_BYTE 0x321
275#define DC_COM_HSPI_WRITE_DATA_AB 0x322
276#define DC_COM_HSPI_WRITE_DATA_CD 0x323
277#define DC_COM_HSPI_CS_DC 0x324
278#define DC_COM_SCRATCH_REGISTER_A 0x325
279#define DC_COM_SCRATCH_REGISTER_B 0x326
280#define DC_COM_GPIO_CTRL 0x327
281#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
282#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
283
284#define DC_COM_RG_UNDERFLOW 0x365
285#define UNDERFLOW_MODE_RED (1 << 8)
286#define UNDERFLOW_REPORT_ENABLE (1 << 0)
287
288#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
289#define H_PULSE0_ENABLE (1 << 8)
290#define H_PULSE1_ENABLE (1 << 10)
291#define H_PULSE2_ENABLE (1 << 12)
292
293#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
294
295#define DC_DISP_DISP_WIN_OPTIONS 0x402
296#define HDMI_ENABLE (1 << 30)
297#define DSI_ENABLE (1 << 29)
298#define SOR1_TIMING_CYA (1 << 27)
299#define CURSOR_ENABLE (1 << 16)
300
301#define SOR_ENABLE(x) (1 << (25 + (x)))
302
303#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
304#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
305#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
306#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
307#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
308
309#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
310#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
311#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
312#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
313#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
314
315#define DC_DISP_DISP_TIMING_OPTIONS 0x405
316#define VSYNC_H_POSITION(x) ((x) & 0xfff)
317
318#define DC_DISP_REF_TO_SYNC 0x406
319#define DC_DISP_SYNC_WIDTH 0x407
320#define DC_DISP_BACK_PORCH 0x408
321#define DC_DISP_ACTIVE 0x409
322#define DC_DISP_FRONT_PORCH 0x40a
323#define DC_DISP_H_PULSE0_CONTROL 0x40b
324#define DC_DISP_H_PULSE0_POSITION_A 0x40c
325#define DC_DISP_H_PULSE0_POSITION_B 0x40d
326#define DC_DISP_H_PULSE0_POSITION_C 0x40e
327#define DC_DISP_H_PULSE0_POSITION_D 0x40f
328#define DC_DISP_H_PULSE1_CONTROL 0x410
329#define DC_DISP_H_PULSE1_POSITION_A 0x411
330#define DC_DISP_H_PULSE1_POSITION_B 0x412
331#define DC_DISP_H_PULSE1_POSITION_C 0x413
332#define DC_DISP_H_PULSE1_POSITION_D 0x414
333#define DC_DISP_H_PULSE2_CONTROL 0x415
334#define DC_DISP_H_PULSE2_POSITION_A 0x416
335#define DC_DISP_H_PULSE2_POSITION_B 0x417
336#define DC_DISP_H_PULSE2_POSITION_C 0x418
337#define DC_DISP_H_PULSE2_POSITION_D 0x419
338#define DC_DISP_V_PULSE0_CONTROL 0x41a
339#define DC_DISP_V_PULSE0_POSITION_A 0x41b
340#define DC_DISP_V_PULSE0_POSITION_B 0x41c
341#define DC_DISP_V_PULSE0_POSITION_C 0x41d
342#define DC_DISP_V_PULSE1_CONTROL 0x41e
343#define DC_DISP_V_PULSE1_POSITION_A 0x41f
344#define DC_DISP_V_PULSE1_POSITION_B 0x420
345#define DC_DISP_V_PULSE1_POSITION_C 0x421
346#define DC_DISP_V_PULSE2_CONTROL 0x422
347#define DC_DISP_V_PULSE2_POSITION_A 0x423
348#define DC_DISP_V_PULSE3_CONTROL 0x424
349#define DC_DISP_V_PULSE3_POSITION_A 0x425
350#define DC_DISP_M0_CONTROL 0x426
351#define DC_DISP_M1_CONTROL 0x427
352#define DC_DISP_DI_CONTROL 0x428
353#define DC_DISP_PP_CONTROL 0x429
354#define DC_DISP_PP_SELECT_A 0x42a
355#define DC_DISP_PP_SELECT_B 0x42b
356#define DC_DISP_PP_SELECT_C 0x42c
357#define DC_DISP_PP_SELECT_D 0x42d
358
359#define PULSE_MODE_NORMAL (0 << 3)
360#define PULSE_MODE_ONE_CLOCK (1 << 3)
361#define PULSE_POLARITY_HIGH (0 << 4)
362#define PULSE_POLARITY_LOW (1 << 4)
363#define PULSE_QUAL_ALWAYS (0 << 6)
364#define PULSE_QUAL_VACTIVE (2 << 6)
365#define PULSE_QUAL_VACTIVE1 (3 << 6)
366#define PULSE_LAST_START_A (0 << 8)
367#define PULSE_LAST_END_A (1 << 8)
368#define PULSE_LAST_START_B (2 << 8)
369#define PULSE_LAST_END_B (3 << 8)
370#define PULSE_LAST_START_C (4 << 8)
371#define PULSE_LAST_END_C (5 << 8)
372#define PULSE_LAST_START_D (6 << 8)
373#define PULSE_LAST_END_D (7 << 8)
374
375#define PULSE_START(x) (((x) & 0xfff) << 0)
376#define PULSE_END(x) (((x) & 0xfff) << 16)
377
378#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
379#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
380#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
381#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
382#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
383#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
384#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
385#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
386#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
387#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
388#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
389#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
390#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
391#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
392#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
393
394#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
395#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
396#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
397#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
398#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
399#define DISP_DATA_FORMAT_DF2S (4 << 0)
400#define DISP_DATA_FORMAT_DF3S (5 << 0)
401#define DISP_DATA_FORMAT_DFSPI (6 << 0)
402#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
403#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
404#define DISP_ALIGNMENT_MSB (0 << 8)
405#define DISP_ALIGNMENT_LSB (1 << 8)
406#define DISP_ORDER_RED_BLUE (0 << 9)
407#define DISP_ORDER_BLUE_RED (1 << 9)
408
409#define DC_DISP_DISP_COLOR_CONTROL 0x430
410#define BASE_COLOR_SIZE666 ( 0 << 0)
411#define BASE_COLOR_SIZE111 ( 1 << 0)
412#define BASE_COLOR_SIZE222 ( 2 << 0)
413#define BASE_COLOR_SIZE333 ( 3 << 0)
414#define BASE_COLOR_SIZE444 ( 4 << 0)
415#define BASE_COLOR_SIZE555 ( 5 << 0)
416#define BASE_COLOR_SIZE565 ( 6 << 0)
417#define BASE_COLOR_SIZE332 ( 7 << 0)
418#define BASE_COLOR_SIZE888 ( 8 << 0)
419#define BASE_COLOR_SIZE101010 (10 << 0)
420#define BASE_COLOR_SIZE121212 (12 << 0)
421#define DITHER_CONTROL_MASK (3 << 8)
422#define DITHER_CONTROL_DISABLE (0 << 8)
423#define DITHER_CONTROL_ORDERED (2 << 8)
424#define DITHER_CONTROL_ERRDIFF (3 << 8)
425#define BASE_COLOR_SIZE_MASK (0xf << 0)
426#define BASE_COLOR_SIZE_666 ( 0 << 0)
427#define BASE_COLOR_SIZE_111 ( 1 << 0)
428#define BASE_COLOR_SIZE_222 ( 2 << 0)
429#define BASE_COLOR_SIZE_333 ( 3 << 0)
430#define BASE_COLOR_SIZE_444 ( 4 << 0)
431#define BASE_COLOR_SIZE_555 ( 5 << 0)
432#define BASE_COLOR_SIZE_565 ( 6 << 0)
433#define BASE_COLOR_SIZE_332 ( 7 << 0)
434#define BASE_COLOR_SIZE_888 ( 8 << 0)
435#define BASE_COLOR_SIZE_101010 ( 10 << 0)
436#define BASE_COLOR_SIZE_121212 ( 12 << 0)
437
438#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
439#define SC1_H_QUALIFIER_NONE (1 << 16)
440#define SC0_H_QUALIFIER_NONE (1 << 0)
441
442#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
443#define DE_SELECT_ACTIVE_BLANK (0 << 0)
444#define DE_SELECT_ACTIVE (1 << 0)
445#define DE_SELECT_ACTIVE_IS (2 << 0)
446#define DE_CONTROL_ONECLK (0 << 2)
447#define DE_CONTROL_NORMAL (1 << 2)
448#define DE_CONTROL_EARLY_EXT (2 << 2)
449#define DE_CONTROL_EARLY (3 << 2)
450#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
451
452#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
453#define DC_DISP_LCD_SPI_OPTIONS 0x434
454#define DC_DISP_BORDER_COLOR 0x435
455#define DC_DISP_COLOR_KEY0_LOWER 0x436
456#define DC_DISP_COLOR_KEY0_UPPER 0x437
457#define DC_DISP_COLOR_KEY1_LOWER 0x438
458#define DC_DISP_COLOR_KEY1_UPPER 0x439
459
460#define DC_DISP_CURSOR_FOREGROUND 0x43c
461#define DC_DISP_CURSOR_BACKGROUND 0x43d
462
463#define DC_DISP_CURSOR_START_ADDR 0x43e
464#define CURSOR_CLIP_DISPLAY (0 << 28)
465#define CURSOR_CLIP_WIN_A (1 << 28)
466#define CURSOR_CLIP_WIN_B (2 << 28)
467#define CURSOR_CLIP_WIN_C (3 << 28)
468#define CURSOR_SIZE_32x32 (0 << 24)
469#define CURSOR_SIZE_64x64 (1 << 24)
470#define CURSOR_SIZE_128x128 (2 << 24)
471#define CURSOR_SIZE_256x256 (3 << 24)
472#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
473
474#define DC_DISP_CURSOR_POSITION 0x440
475#define DC_DISP_CURSOR_POSITION_NS 0x441
476
477#define DC_DISP_INIT_SEQ_CONTROL 0x442
478#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
479#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
480#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
481#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
482
483#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
484#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
485#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
486#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
487#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
488
489#define DC_DISP_DAC_CRT_CTRL 0x4c0
490#define DC_DISP_DISP_MISC_CONTROL 0x4c1
491#define DC_DISP_SD_CONTROL 0x4c2
492#define DC_DISP_SD_CSC_COEFF 0x4c3
493#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
494#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
495#define DC_DISP_DC_PIXEL_COUNT 0x4ce
496#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
497#define DC_DISP_SD_BL_PARAMETERS 0x4d7
498#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
499#define DC_DISP_SD_BL_CONTROL 0x4dc
500#define DC_DISP_SD_HW_K_VALUES 0x4dd
501#define DC_DISP_SD_MAN_K_VALUES 0x4de
502
503#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
504#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
505#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
506#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
507#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
508
509#define DC_DISP_INTERLACE_CONTROL 0x4e5
510#define INTERLACE_STATUS (1 << 2)
511#define INTERLACE_START (1 << 1)
512#define INTERLACE_ENABLE (1 << 0)
513
514#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
515#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
516#define CURSOR_MODE_LEGACY (0 << 24)
517#define CURSOR_MODE_NORMAL (1 << 24)
518#define CURSOR_DST_BLEND_ZERO (0 << 16)
519#define CURSOR_DST_BLEND_K1 (1 << 16)
520#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
521#define CURSOR_DST_BLEND_MASK (3 << 16)
522#define CURSOR_SRC_BLEND_K1 (0 << 8)
523#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
524#define CURSOR_SRC_BLEND_MASK (3 << 8)
525#define CURSOR_ALPHA 0xff
526
527#define DC_WIN_CORE_ACT_CONTROL 0x50e
528#define VCOUNTER (0 << 0)
529#define HCOUNTER (1 << 0)
530
531#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
532#define LATENCY_CTL_MODE_ENABLE (1 << 2)
533
534#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
535#define WATERMARK_MASK 0x1fffffff
536
537#define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
538#define PIPE_METER_INT(x) (((x) & 0xff) << 8)
539#define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
540
541#define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
542#define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
543
544#define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
545#define SLOTS(x) (((x) & 0xff) << 0)
546
547#define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
548#define MODE_TWO_LINES (0 << 14)
549#define MODE_FOUR_LINES (1 << 14)
550
551#define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
552#define THREAD_NUM_MASK (0x1f << 1)
553#define THREAD_NUM(x) (((x) & 0x1f) << 1)
554#define THREAD_GROUP_ENABLE (1 << 0)
555
556#define DC_WIN_CSC_YOF 0x611
557#define DC_WIN_CSC_KYRGB 0x612
558#define DC_WIN_CSC_KUR 0x613
559#define DC_WIN_CSC_KVR 0x614
560#define DC_WIN_CSC_KUG 0x615
561#define DC_WIN_CSC_KVG 0x616
562#define DC_WIN_CSC_KUB 0x617
563#define DC_WIN_CSC_KVB 0x618
564
565#define DC_WIN_WIN_OPTIONS 0x700
566#define H_DIRECTION (1 << 0)
567#define V_DIRECTION (1 << 2)
568#define COLOR_EXPAND (1 << 6)
569#define CSC_ENABLE (1 << 18)
570#define WIN_ENABLE (1 << 30)
571
572#define DC_WIN_BYTE_SWAP 0x701
573#define BYTE_SWAP_NOSWAP (0 << 0)
574#define BYTE_SWAP_SWAP2 (1 << 0)
575#define BYTE_SWAP_SWAP4 (2 << 0)
576#define BYTE_SWAP_SWAP4HW (3 << 0)
577
578#define DC_WIN_BUFFER_CONTROL 0x702
579#define BUFFER_CONTROL_HOST (0 << 0)
580#define BUFFER_CONTROL_VI (1 << 0)
581#define BUFFER_CONTROL_EPP (2 << 0)
582#define BUFFER_CONTROL_MPEGE (3 << 0)
583#define BUFFER_CONTROL_SB2D (4 << 0)
584
585#define DC_WIN_COLOR_DEPTH 0x703
586#define WIN_COLOR_DEPTH_P1 0
587#define WIN_COLOR_DEPTH_P2 1
588#define WIN_COLOR_DEPTH_P4 2
589#define WIN_COLOR_DEPTH_P8 3
590#define WIN_COLOR_DEPTH_B4G4R4A4 4
591#define WIN_COLOR_DEPTH_B5G5R5A1 5
592#define WIN_COLOR_DEPTH_B5G6R5 6
593#define WIN_COLOR_DEPTH_A1B5G5R5 7
594#define WIN_COLOR_DEPTH_B8G8R8A8 12
595#define WIN_COLOR_DEPTH_R8G8B8A8 13
596#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
597#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
598#define WIN_COLOR_DEPTH_YCbCr422 16
599#define WIN_COLOR_DEPTH_YUV422 17
600#define WIN_COLOR_DEPTH_YCbCr420P 18
601#define WIN_COLOR_DEPTH_YUV420P 19
602#define WIN_COLOR_DEPTH_YCbCr422P 20
603#define WIN_COLOR_DEPTH_YUV422P 21
604#define WIN_COLOR_DEPTH_YCbCr422R 22
605#define WIN_COLOR_DEPTH_YUV422R 23
606#define WIN_COLOR_DEPTH_YCbCr422RA 24
607#define WIN_COLOR_DEPTH_YUV422RA 25
608#define WIN_COLOR_DEPTH_R4G4B4A4 27
609#define WIN_COLOR_DEPTH_R5G5B5A 28
610#define WIN_COLOR_DEPTH_AR5G5B5 29
611#define WIN_COLOR_DEPTH_B5G5R5X1 30
612#define WIN_COLOR_DEPTH_X1B5G5R5 31
613#define WIN_COLOR_DEPTH_R5G5B5X1 32
614#define WIN_COLOR_DEPTH_X1R5G5B5 33
615#define WIN_COLOR_DEPTH_R5G6B5 34
616#define WIN_COLOR_DEPTH_A8R8G8B8 35
617#define WIN_COLOR_DEPTH_A8B8G8R8 36
618#define WIN_COLOR_DEPTH_B8G8R8X8 37
619#define WIN_COLOR_DEPTH_R8G8B8X8 38
620#define WIN_COLOR_DEPTH_X8B8G8R8 65
621#define WIN_COLOR_DEPTH_X8R8G8B8 66
622
623#define DC_WIN_POSITION 0x704
624#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
625#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
626
627#define DC_WIN_SIZE 0x705
628#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
629#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
630
631#define DC_WIN_PRESCALED_SIZE 0x706
632#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
633#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
634
635#define DC_WIN_H_INITIAL_DDA 0x707
636#define DC_WIN_V_INITIAL_DDA 0x708
637#define DC_WIN_DDA_INC 0x709
638#define H_DDA_INC(x) (((x) & 0xffff) << 0)
639#define V_DDA_INC(x) (((x) & 0xffff) << 16)
640
641#define DC_WIN_LINE_STRIDE 0x70a
642#define DC_WIN_BUF_STRIDE 0x70b
643#define DC_WIN_UV_BUF_STRIDE 0x70c
644#define DC_WIN_BUFFER_ADDR_MODE 0x70d
645#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
646#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
647#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
648#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
649
650#define DC_WIN_DV_CONTROL 0x70e
651
652#define DC_WIN_BLEND_NOKEY 0x70f
653#define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
654#define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
655
656#define DC_WIN_BLEND_1WIN 0x710
657#define BLEND_CONTROL_FIX (0 << 2)
658#define BLEND_CONTROL_ALPHA (1 << 2)
659#define BLEND_COLOR_KEY_NONE (0 << 0)
660#define BLEND_COLOR_KEY_0 (1 << 0)
661#define BLEND_COLOR_KEY_1 (2 << 0)
662#define BLEND_COLOR_KEY_BOTH (3 << 0)
663
664#define DC_WIN_BLEND_2WIN_X 0x711
665#define BLEND_CONTROL_DEPENDENT (2 << 2)
666
667#define DC_WIN_BLEND_2WIN_Y 0x712
668#define DC_WIN_BLEND_3WIN_XY 0x713
669
670#define DC_WIN_HP_FETCH_CONTROL 0x714
671
672#define DC_WINBUF_START_ADDR 0x800
673#define DC_WINBUF_START_ADDR_NS 0x801
674#define DC_WINBUF_START_ADDR_U 0x802
675#define DC_WINBUF_START_ADDR_U_NS 0x803
676#define DC_WINBUF_START_ADDR_V 0x804
677#define DC_WINBUF_START_ADDR_V_NS 0x805
678
679#define DC_WINBUF_ADDR_H_OFFSET 0x806
680#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
681#define DC_WINBUF_ADDR_V_OFFSET 0x808
682#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
683
684#define DC_WINBUF_UFLOW_STATUS 0x80a
685#define DC_WINBUF_SURFACE_KIND 0x80b
686#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
687#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
688#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
689#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
690
691#define DC_WINBUF_START_ADDR_HI 0x80d
692
693#define DC_WINBUF_CDE_CONTROL 0x82f
694#define ENABLE_SURFACE (1 << 0)
695
696#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
697#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
698#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
699
700/* Tegra186 and later */
701#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
702#define PROTOCOL_MASK (0xf << 8)
703#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
704
705#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
706#define OWNER_MASK (0xf << 0)
707#define OWNER(x) (((x) & 0xf) << 0)
708
709#define DC_WIN_CROPPED_SIZE 0x706
710
711#define DC_WIN_PLANAR_STORAGE 0x709
712#define PITCH(x) (((x) >> 6) & 0x1fff)
713
714#define DC_WIN_SET_PARAMS 0x70d
715#define CLAMP_BEFORE_BLEND (1 << 15)
716#define DEGAMMA_NONE (0 << 13)
717#define DEGAMMA_SRGB (1 << 13)
718#define DEGAMMA_YUV8_10 (2 << 13)
719#define DEGAMMA_YUV12 (3 << 13)
720#define INPUT_RANGE_BYPASS (0 << 10)
721#define INPUT_RANGE_LIMITED (1 << 10)
722#define INPUT_RANGE_FULL (2 << 10)
723#define COLOR_SPACE_RGB (0 << 8)
724#define COLOR_SPACE_YUV_601 (1 << 8)
725#define COLOR_SPACE_YUV_709 (2 << 8)
726#define COLOR_SPACE_YUV_2020 (3 << 8)
727
728#define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
729#define HORIZONTAL_TAPS_2 (1 << 3)
730#define HORIZONTAL_TAPS_5 (4 << 3)
731#define VERTICAL_TAPS_2 (1 << 0)
732#define VERTICAL_TAPS_5 (4 << 0)
733
734#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
735#define INPUT_SCALER_USE422 (1 << 2)
736#define INPUT_SCALER_VBYPASS (1 << 1)
737#define INPUT_SCALER_HBYPASS (1 << 0)
738
739#define DC_WIN_BLEND_LAYER_CONTROL 0x716
740#define COLOR_KEY_NONE (0 << 25)
741#define COLOR_KEY_SRC (1 << 25)
742#define COLOR_KEY_DST (2 << 25)
743#define BLEND_BYPASS (1 << 24)
744#define K2(x) (((x) & 0xff) << 16)
745#define K1(x) (((x) & 0xff) << 8)
746#define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
747
748#define DC_WIN_BLEND_MATCH_SELECT 0x717
749#define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
750#define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
751#define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
752#define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
753#define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
754#define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
755#define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
756#define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
757#define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
758#define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
759#define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
760#define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
761#define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
762#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
763#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
764#define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
765#define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
766#define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
767#define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
768#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
769#define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
770#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
771
772#define DC_WIN_BLEND_NOMATCH_SELECT 0x718
773
774#define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
775#define SWAP_UV (1 << 0)
776
777#define DC_WIN_WINDOW_SET_CONTROL 0x730
778#define CONTROL_CSC_ENABLE (1 << 5)
779
780#define DC_WINBUF_CROPPED_POINT 0x806
781#define OFFSET_Y(x) (((x) & 0xffff) << 16)
782#define OFFSET_X(x) (((x) & 0xffff) << 0)
783
784#endif /* TEGRA_DC_H */