Loading...
Note: File does not exist in v4.6.
1/*
2 * Rockchip SoC DP (Display Port) interface driver.
3 *
4 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
5 * Author: Andy Yan <andy.yan@rock-chips.com>
6 * Yakir Yang <ykk@rock-chips.com>
7 * Jeff Chen <jeff.chen@rock-chips.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/component.h>
16#include <linux/mfd/syscon.h>
17#include <linux/of_device.h>
18#include <linux/of_graph.h>
19#include <linux/regmap.h>
20#include <linux/reset.h>
21#include <linux/clk.h>
22
23#include <drm/drmP.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_dp_helper.h>
26#include <drm/drm_of.h>
27#include <drm/drm_panel.h>
28
29#include <video/of_videomode.h>
30#include <video/videomode.h>
31
32#include <drm/bridge/analogix_dp.h>
33
34#include "rockchip_drm_drv.h"
35#include "rockchip_drm_psr.h"
36#include "rockchip_drm_vop.h"
37
38#define RK3288_GRF_SOC_CON6 0x25c
39#define RK3288_EDP_LCDC_SEL BIT(5)
40#define RK3399_GRF_SOC_CON20 0x6250
41#define RK3399_EDP_LCDC_SEL BIT(5)
42
43#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
44
45#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
46
47#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
48
49/**
50 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
51 * @lcdsel_grf_reg: grf register offset of lcdc select
52 * @lcdsel_big: reg value of selecting vop big for eDP
53 * @lcdsel_lit: reg value of selecting vop little for eDP
54 * @chip_type: specific chip type
55 */
56struct rockchip_dp_chip_data {
57 u32 lcdsel_grf_reg;
58 u32 lcdsel_big;
59 u32 lcdsel_lit;
60 u32 chip_type;
61};
62
63struct rockchip_dp_device {
64 struct drm_device *drm_dev;
65 struct device *dev;
66 struct drm_encoder encoder;
67 struct drm_display_mode mode;
68
69 struct clk *pclk;
70 struct clk *grfclk;
71 struct regmap *grf;
72 struct reset_control *rst;
73
74 const struct rockchip_dp_chip_data *data;
75
76 struct analogix_dp_device *adp;
77 struct analogix_dp_plat_data plat_data;
78};
79
80static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
81{
82 struct rockchip_dp_device *dp = to_dp(encoder);
83 int ret;
84
85 if (!analogix_dp_psr_enabled(dp->adp))
86 return;
87
88 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
89
90 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
91 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
92 if (ret) {
93 DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
94 return;
95 }
96
97 if (enabled)
98 analogix_dp_enable_psr(dp->adp);
99 else
100 analogix_dp_disable_psr(dp->adp);
101}
102
103static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
104{
105 reset_control_assert(dp->rst);
106 usleep_range(10, 20);
107 reset_control_deassert(dp->rst);
108
109 return 0;
110}
111
112static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
113{
114 struct rockchip_dp_device *dp = to_dp(plat_data);
115 int ret;
116
117 ret = clk_prepare_enable(dp->pclk);
118 if (ret < 0) {
119 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
120 return ret;
121 }
122
123 ret = rockchip_dp_pre_init(dp);
124 if (ret < 0) {
125 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
126 clk_disable_unprepare(dp->pclk);
127 return ret;
128 }
129
130 return rockchip_drm_psr_activate(&dp->encoder);
131}
132
133static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
134{
135 struct rockchip_dp_device *dp = to_dp(plat_data);
136 int ret;
137
138 ret = rockchip_drm_psr_deactivate(&dp->encoder);
139 if (ret != 0)
140 return ret;
141
142 clk_disable_unprepare(dp->pclk);
143
144 return 0;
145}
146
147static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
148 struct drm_connector *connector)
149{
150 struct drm_display_info *di = &connector->display_info;
151 /* VOP couldn't output YUV video format for eDP rightly */
152 u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
153
154 if ((di->color_formats & mask)) {
155 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
156 di->color_formats &= ~mask;
157 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
158 di->bpc = 8;
159 }
160
161 return 0;
162}
163
164static bool
165rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
166 const struct drm_display_mode *mode,
167 struct drm_display_mode *adjusted_mode)
168{
169 /* do nothing */
170 return true;
171}
172
173static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
174 struct drm_display_mode *mode,
175 struct drm_display_mode *adjusted)
176{
177 /* do nothing */
178}
179
180static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
181{
182 struct rockchip_dp_device *dp = to_dp(encoder);
183 int ret;
184 u32 val;
185
186 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
187 if (ret < 0)
188 return;
189
190 if (ret)
191 val = dp->data->lcdsel_lit;
192 else
193 val = dp->data->lcdsel_big;
194
195 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
196
197 ret = clk_prepare_enable(dp->grfclk);
198 if (ret < 0) {
199 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
200 return;
201 }
202
203 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
204 if (ret != 0)
205 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
206
207 clk_disable_unprepare(dp->grfclk);
208}
209
210static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
211{
212 /* do nothing */
213}
214
215static int
216rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
217 struct drm_crtc_state *crtc_state,
218 struct drm_connector_state *conn_state)
219{
220 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
221
222 /*
223 * The hardware IC designed that VOP must output the RGB10 video
224 * format to eDP controller, and if eDP panel only support RGB8,
225 * then eDP controller should cut down the video data, not via VOP
226 * controller, that's why we need to hardcode the VOP output mode
227 * to RGA10 here.
228 */
229
230 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
231 s->output_type = DRM_MODE_CONNECTOR_eDP;
232
233 return 0;
234}
235
236static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
237 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
238 .mode_set = rockchip_dp_drm_encoder_mode_set,
239 .enable = rockchip_dp_drm_encoder_enable,
240 .disable = rockchip_dp_drm_encoder_nop,
241 .atomic_check = rockchip_dp_drm_encoder_atomic_check,
242};
243
244static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
245 .destroy = drm_encoder_cleanup,
246};
247
248static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
249{
250 struct device *dev = dp->dev;
251 struct device_node *np = dev->of_node;
252
253 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
254 if (IS_ERR(dp->grf)) {
255 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
256 return PTR_ERR(dp->grf);
257 }
258
259 dp->grfclk = devm_clk_get(dev, "grf");
260 if (PTR_ERR(dp->grfclk) == -ENOENT) {
261 dp->grfclk = NULL;
262 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
263 return -EPROBE_DEFER;
264 } else if (IS_ERR(dp->grfclk)) {
265 DRM_DEV_ERROR(dev, "failed to get grf clock\n");
266 return PTR_ERR(dp->grfclk);
267 }
268
269 dp->pclk = devm_clk_get(dev, "pclk");
270 if (IS_ERR(dp->pclk)) {
271 DRM_DEV_ERROR(dev, "failed to get pclk property\n");
272 return PTR_ERR(dp->pclk);
273 }
274
275 dp->rst = devm_reset_control_get(dev, "dp");
276 if (IS_ERR(dp->rst)) {
277 DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
278 return PTR_ERR(dp->rst);
279 }
280
281 return 0;
282}
283
284static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
285{
286 struct drm_encoder *encoder = &dp->encoder;
287 struct drm_device *drm_dev = dp->drm_dev;
288 struct device *dev = dp->dev;
289 int ret;
290
291 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
292 dev->of_node);
293 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
294
295 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
296 DRM_MODE_ENCODER_TMDS, NULL);
297 if (ret) {
298 DRM_ERROR("failed to initialize encoder with drm\n");
299 return ret;
300 }
301
302 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
303
304 return 0;
305}
306
307static int rockchip_dp_bind(struct device *dev, struct device *master,
308 void *data)
309{
310 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
311 const struct rockchip_dp_chip_data *dp_data;
312 struct drm_device *drm_dev = data;
313 int ret;
314
315 dp_data = of_device_get_match_data(dev);
316 if (!dp_data)
317 return -ENODEV;
318
319 dp->data = dp_data;
320 dp->drm_dev = drm_dev;
321
322 ret = rockchip_dp_drm_create_encoder(dp);
323 if (ret) {
324 DRM_ERROR("failed to create drm encoder\n");
325 return ret;
326 }
327
328 dp->plat_data.encoder = &dp->encoder;
329
330 dp->plat_data.dev_type = dp->data->chip_type;
331 dp->plat_data.power_on = rockchip_dp_poweron;
332 dp->plat_data.power_off = rockchip_dp_powerdown;
333 dp->plat_data.get_modes = rockchip_dp_get_modes;
334
335 ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
336 if (ret < 0)
337 goto err_cleanup_encoder;
338
339 dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
340 if (IS_ERR(dp->adp)) {
341 ret = PTR_ERR(dp->adp);
342 goto err_unreg_psr;
343 }
344
345 return 0;
346err_unreg_psr:
347 rockchip_drm_psr_unregister(&dp->encoder);
348err_cleanup_encoder:
349 dp->encoder.funcs->destroy(&dp->encoder);
350 return ret;
351}
352
353static void rockchip_dp_unbind(struct device *dev, struct device *master,
354 void *data)
355{
356 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
357
358 analogix_dp_unbind(dp->adp);
359 rockchip_drm_psr_unregister(&dp->encoder);
360 dp->encoder.funcs->destroy(&dp->encoder);
361}
362
363static const struct component_ops rockchip_dp_component_ops = {
364 .bind = rockchip_dp_bind,
365 .unbind = rockchip_dp_unbind,
366};
367
368static int rockchip_dp_probe(struct platform_device *pdev)
369{
370 struct device *dev = &pdev->dev;
371 struct drm_panel *panel = NULL;
372 struct rockchip_dp_device *dp;
373 int ret;
374
375 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
376 if (ret < 0)
377 return ret;
378
379 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
380 if (!dp)
381 return -ENOMEM;
382
383 dp->dev = dev;
384 dp->plat_data.panel = panel;
385
386 ret = rockchip_dp_of_probe(dp);
387 if (ret < 0)
388 return ret;
389
390 platform_set_drvdata(pdev, dp);
391
392 return component_add(dev, &rockchip_dp_component_ops);
393}
394
395static int rockchip_dp_remove(struct platform_device *pdev)
396{
397 component_del(&pdev->dev, &rockchip_dp_component_ops);
398
399 return 0;
400}
401
402#ifdef CONFIG_PM_SLEEP
403static int rockchip_dp_suspend(struct device *dev)
404{
405 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
406
407 return analogix_dp_suspend(dp->adp);
408}
409
410static int rockchip_dp_resume(struct device *dev)
411{
412 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
413
414 return analogix_dp_resume(dp->adp);
415}
416#endif
417
418static const struct dev_pm_ops rockchip_dp_pm_ops = {
419#ifdef CONFIG_PM_SLEEP
420 .suspend = rockchip_dp_suspend,
421 .resume_early = rockchip_dp_resume,
422#endif
423};
424
425static const struct rockchip_dp_chip_data rk3399_edp = {
426 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
427 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
428 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
429 .chip_type = RK3399_EDP,
430};
431
432static const struct rockchip_dp_chip_data rk3288_dp = {
433 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
434 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
435 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
436 .chip_type = RK3288_DP,
437};
438
439static const struct of_device_id rockchip_dp_dt_ids[] = {
440 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
441 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
442 {}
443};
444MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
445
446struct platform_driver rockchip_dp_driver = {
447 .probe = rockchip_dp_probe,
448 .remove = rockchip_dp_remove,
449 .driver = {
450 .name = "rockchip-dp",
451 .pm = &rockchip_dp_pm_ops,
452 .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
453 },
454};