1/*
  2 * Copyright © 2014-2017 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include "intel_guc.h"
 26#include "intel_guc_ads.h"
 27#include "intel_guc_submission.h"
 28#include "i915_drv.h"
 29
 30static void gen8_guc_raise_irq(struct intel_guc *guc)
 31{
 32	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 33
 34	I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
 35}
 36
 37static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
 38{
 39	GEM_BUG_ON(!guc->send_regs.base);
 40	GEM_BUG_ON(!guc->send_regs.count);
 41	GEM_BUG_ON(i >= guc->send_regs.count);
 42
 43	return _MMIO(guc->send_regs.base + 4 * i);
 44}
 45
 46void intel_guc_init_send_regs(struct intel_guc *guc)
 47{
 48	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 49	enum forcewake_domains fw_domains = 0;
 50	unsigned int i;
 51
 52	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
 53	guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
 54
 55	for (i = 0; i < guc->send_regs.count; i++) {
 56		fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
 57					guc_send_reg(guc, i),
 58					FW_REG_READ | FW_REG_WRITE);
 59	}
 60	guc->send_regs.fw_domains = fw_domains;
 61}
 62
 63void intel_guc_init_early(struct intel_guc *guc)
 64{
 65	intel_guc_fw_init_early(guc);
 66	intel_guc_ct_init_early(&guc->ct);
 67	intel_guc_log_init_early(guc);
 68
 69	mutex_init(&guc->send_mutex);
 70	guc->send = intel_guc_send_nop;
 71	guc->notify = gen8_guc_raise_irq;
 72}
 73
 74int intel_guc_init_wq(struct intel_guc *guc)
 75{
 76	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 77
 78	/*
 79	 * GuC log buffer flush work item has to do register access to
 80	 * send the ack to GuC and this work item, if not synced before
 81	 * suspend, can potentially get executed after the GFX device is
 82	 * suspended.
 83	 * By marking the WQ as freezable, we don't have to bother about
 84	 * flushing of this work item from the suspend hooks, the pending
 85	 * work item if any will be either executed before the suspend
 86	 * or scheduled later on resume. This way the handling of work
 87	 * item can be kept same between system suspend & rpm suspend.
 88	 */
 89	guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
 90						WQ_HIGHPRI | WQ_FREEZABLE);
 91	if (!guc->log.runtime.flush_wq) {
 92		DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
 93		return -ENOMEM;
 94	}
 95
 96	/*
 97	 * Even though both sending GuC action, and adding a new workitem to
 98	 * GuC workqueue are serialized (each with its own locking), since
 99	 * we're using mutliple engines, it's possible that we're going to
100	 * issue a preempt request with two (or more - each for different
101	 * engine) workitems in GuC queue. In this situation, GuC may submit
102	 * all of them, which will make us very confused.
103	 * Our preemption contexts may even already be complete - before we
104	 * even had the chance to sent the preempt action to GuC!. Rather
105	 * than introducing yet another lock, we can just use ordered workqueue
106	 * to make sure we're always sending a single preemption request with a
107	 * single workitem.
108	 */
109	if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
110	    USES_GUC_SUBMISSION(dev_priv)) {
111		guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
112							  WQ_HIGHPRI);
113		if (!guc->preempt_wq) {
114			destroy_workqueue(guc->log.runtime.flush_wq);
115			DRM_ERROR("Couldn't allocate workqueue for GuC "
116				  "preemption\n");
117			return -ENOMEM;
118		}
119	}
120
121	return 0;
122}
123
124void intel_guc_fini_wq(struct intel_guc *guc)
125{
126	struct drm_i915_private *dev_priv = guc_to_i915(guc);
127
128	if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
129	    USES_GUC_SUBMISSION(dev_priv))
130		destroy_workqueue(guc->preempt_wq);
131
132	destroy_workqueue(guc->log.runtime.flush_wq);
133}
134
135static int guc_shared_data_create(struct intel_guc *guc)
136{
137	struct i915_vma *vma;
138	void *vaddr;
139
140	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
141	if (IS_ERR(vma))
142		return PTR_ERR(vma);
143
144	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
145	if (IS_ERR(vaddr)) {
146		i915_vma_unpin_and_release(&vma);
147		return PTR_ERR(vaddr);
148	}
149
150	guc->shared_data = vma;
151	guc->shared_data_vaddr = vaddr;
152
153	return 0;
154}
155
156static void guc_shared_data_destroy(struct intel_guc *guc)
157{
158	i915_gem_object_unpin_map(guc->shared_data->obj);
159	i915_vma_unpin_and_release(&guc->shared_data);
160}
161
162int intel_guc_init(struct intel_guc *guc)
163{
164	struct drm_i915_private *dev_priv = guc_to_i915(guc);
165	int ret;
166
167	ret = guc_shared_data_create(guc);
168	if (ret)
169		return ret;
170	GEM_BUG_ON(!guc->shared_data);
171
172	ret = intel_guc_log_create(guc);
173	if (ret)
174		goto err_shared;
175
176	ret = intel_guc_ads_create(guc);
177	if (ret)
178		goto err_log;
179	GEM_BUG_ON(!guc->ads_vma);
180
181	/* We need to notify the guc whenever we change the GGTT */
182	i915_ggtt_enable_guc(dev_priv);
183
184	return 0;
185
186err_log:
187	intel_guc_log_destroy(guc);
188err_shared:
189	guc_shared_data_destroy(guc);
190	return ret;
191}
192
193void intel_guc_fini(struct intel_guc *guc)
194{
195	struct drm_i915_private *dev_priv = guc_to_i915(guc);
196
197	i915_ggtt_disable_guc(dev_priv);
198	intel_guc_ads_destroy(guc);
199	intel_guc_log_destroy(guc);
200	guc_shared_data_destroy(guc);
201}
202
203static u32 get_gt_type(struct drm_i915_private *dev_priv)
204{
205	/* XXX: GT type based on PCI device ID? field seems unused by fw */
206	return 0;
207}
208
209static u32 get_core_family(struct drm_i915_private *dev_priv)
210{
211	u32 gen = INTEL_GEN(dev_priv);
212
213	switch (gen) {
214	case 9:
215		return GUC_CORE_FAMILY_GEN9;
216
217	default:
218		MISSING_CASE(gen);
219		return GUC_CORE_FAMILY_UNKNOWN;
220	}
221}
222
223static u32 get_log_verbosity_flags(void)
224{
225	if (i915_modparams.guc_log_level > 0) {
226		u32 verbosity = i915_modparams.guc_log_level - 1;
227
228		GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
229		return verbosity << GUC_LOG_VERBOSITY_SHIFT;
230	}
231
232	GEM_BUG_ON(i915_modparams.enable_guc < 0);
233	return GUC_LOG_DISABLED;
234}
235
236/*
237 * Initialise the GuC parameter block before starting the firmware
238 * transfer. These parameters are read by the firmware on startup
239 * and cannot be changed thereafter.
240 */
241void intel_guc_init_params(struct intel_guc *guc)
242{
243	struct drm_i915_private *dev_priv = guc_to_i915(guc);
244	u32 params[GUC_CTL_MAX_DWORDS];
245	int i;
246
247	memset(params, 0, sizeof(params));
248
249	params[GUC_CTL_DEVICE_INFO] |=
250		(get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
251		(get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
252
253	/*
254	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
255	 * second. This ARAR is calculated by:
256	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
257	 */
258	params[GUC_CTL_ARAT_HIGH] = 0;
259	params[GUC_CTL_ARAT_LOW] = 100000000;
260
261	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
262
263	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
264			GUC_CTL_VCS2_ENABLED;
265
266	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
267
268	params[GUC_CTL_DEBUG] = get_log_verbosity_flags();
269
270	/* If GuC submission is enabled, set up additional parameters here */
271	if (USES_GUC_SUBMISSION(dev_priv)) {
272		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
273		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
274		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
275
276		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
277		params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
278
279		pgs >>= PAGE_SHIFT;
280		params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
281			(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
282
283		params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
284
285		/* Unmask this bit to enable the GuC's internal scheduler */
286		params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
287	}
288
289	/*
290	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
291	 * they are power context saved so it's ok to release forcewake
292	 * when we are done here and take it again at xfer time.
293	 */
294	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
295
296	I915_WRITE(SOFT_SCRATCH(0), 0);
297
298	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
299		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
300
301	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
302}
303
304int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
305{
306	WARN(1, "Unexpected send: action=%#x\n", *action);
307	return -ENODEV;
308}
309
310/*
311 * This function implements the MMIO based host to GuC interface.
312 */
313int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
314{
315	struct drm_i915_private *dev_priv = guc_to_i915(guc);
316	u32 status;
317	int i;
318	int ret;
319
320	GEM_BUG_ON(!len);
321	GEM_BUG_ON(len > guc->send_regs.count);
322
323	/* If CT is available, we expect to use MMIO only during init/fini */
324	GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
325		*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
326		*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
327
328	mutex_lock(&guc->send_mutex);
329	intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
330
331	for (i = 0; i < len; i++)
332		I915_WRITE(guc_send_reg(guc, i), action[i]);
333
334	POSTING_READ(guc_send_reg(guc, i - 1));
335
336	intel_guc_notify(guc);
337
338	/*
339	 * No GuC command should ever take longer than 10ms.
340	 * Fast commands should still complete in 10us.
341	 */
342	ret = __intel_wait_for_register_fw(dev_priv,
343					   guc_send_reg(guc, 0),
344					   INTEL_GUC_RECV_MASK,
345					   INTEL_GUC_RECV_MASK,
346					   10, 10, &status);
347	if (status != INTEL_GUC_STATUS_SUCCESS) {
348		/*
349		 * Either the GuC explicitly returned an error (which
350		 * we convert to -EIO here) or no response at all was
351		 * received within the timeout limit (-ETIMEDOUT)
352		 */
353		if (ret != -ETIMEDOUT)
354			ret = -EIO;
355
356		DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
357			 " ret=%d status=0x%08X response=0x%08X\n",
358			 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
359	}
360
361	intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
362	mutex_unlock(&guc->send_mutex);
363
364	return ret;
365}
366
367int intel_guc_sample_forcewake(struct intel_guc *guc)
368{
369	struct drm_i915_private *dev_priv = guc_to_i915(guc);
370	u32 action[2];
371
372	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
373	/* WaRsDisableCoarsePowerGating:skl,cnl */
374	if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
375		action[1] = 0;
376	else
377		/* bit 0 and 1 are for Render and Media domain separately */
378		action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
379
380	return intel_guc_send(guc, action, ARRAY_SIZE(action));
381}
382
383/**
384 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
385 * @guc: intel_guc structure
386 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
387 *
388 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
389 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
390 * intel_huc_auth().
391 *
392 * Return:	non-zero code on error
393 */
394int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
395{
396	u32 action[] = {
397		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
398		rsa_offset
399	};
400
401	return intel_guc_send(guc, action, ARRAY_SIZE(action));
402}
403
404/**
405 * intel_guc_suspend() - notify GuC entering suspend state
406 * @guc:	the guc
407 */
408int intel_guc_suspend(struct intel_guc *guc)
409{
410	u32 data[] = {
411		INTEL_GUC_ACTION_ENTER_S_STATE,
412		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
413		guc_ggtt_offset(guc->shared_data)
414	};
415
416	return intel_guc_send(guc, data, ARRAY_SIZE(data));
417}
418
419/**
420 * intel_guc_reset_engine() - ask GuC to reset an engine
421 * @guc:	intel_guc structure
422 * @engine:	engine to be reset
423 */
424int intel_guc_reset_engine(struct intel_guc *guc,
425			   struct intel_engine_cs *engine)
426{
427	u32 data[7];
428
429	GEM_BUG_ON(!guc->execbuf_client);
430
431	data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
432	data[1] = engine->guc_id;
433	data[2] = 0;
434	data[3] = 0;
435	data[4] = 0;
436	data[5] = guc->execbuf_client->stage_id;
437	data[6] = guc_ggtt_offset(guc->shared_data);
438
439	return intel_guc_send(guc, data, ARRAY_SIZE(data));
440}
441
442/**
443 * intel_guc_resume() - notify GuC resuming from suspend state
444 * @guc:	the guc
445 */
446int intel_guc_resume(struct intel_guc *guc)
447{
448	u32 data[] = {
449		INTEL_GUC_ACTION_EXIT_S_STATE,
450		GUC_POWER_D0,
451		guc_ggtt_offset(guc->shared_data)
452	};
453
454	return intel_guc_send(guc, data, ARRAY_SIZE(data));
455}
456
457/**
458 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
459 * @guc:	the guc
460 * @size:	size of area to allocate (both virtual space and memory)
461 *
462 * This is a wrapper to create an object for use with the GuC. In order to
463 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
464 * both some backing storage and a range inside the Global GTT. We must pin
465 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
466 * range is reserved inside GuC.
467 *
468 * Return:	A i915_vma if successful, otherwise an ERR_PTR.
469 */
470struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
471{
472	struct drm_i915_private *dev_priv = guc_to_i915(guc);
473	struct drm_i915_gem_object *obj;
474	struct i915_vma *vma;
475	int ret;
476
477	obj = i915_gem_object_create(dev_priv, size);
478	if (IS_ERR(obj))
479		return ERR_CAST(obj);
480
481	vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
482	if (IS_ERR(vma))
483		goto err;
484
485	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
486			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
487	if (ret) {
488		vma = ERR_PTR(ret);
489		goto err;
490	}
491
492	return vma;
493
494err:
495	i915_gem_object_put(obj);
496	return vma;
497}
498
499u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
500{
501	u32 wopcm_size = GUC_WOPCM_TOP;
502
503	/* On BXT, the top of WOPCM is reserved for RC6 context */
504	if (IS_GEN9_LP(dev_priv))
505		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
506
507	return wopcm_size;
508}