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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28#include <linux/device.h>
29#include <linux/module.h>
30#include <linux/stat.h>
31#include <linux/sysfs.h>
32#include "intel_drv.h"
33#include "i915_drv.h"
34
35#define dev_to_drm_minor(d) dev_get_drvdata((d))
36
37#ifdef CONFIG_PM
38static u32 calc_residency(struct drm_device *dev,
39 i915_reg_t reg)
40{
41 struct drm_i915_private *dev_priv = dev->dev_private;
42 u64 raw_time; /* 32b value may overflow during fixed point math */
43 u64 units = 128ULL, div = 100000ULL;
44 u32 ret;
45
46 if (!intel_enable_rc6(dev))
47 return 0;
48
49 intel_runtime_pm_get(dev_priv);
50
51 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
52 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
53 units = 1;
54 div = dev_priv->czclk_freq;
55
56 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
57 units <<= 8;
58 } else if (IS_BROXTON(dev)) {
59 units = 1;
60 div = 1200; /* 833.33ns */
61 }
62
63 raw_time = I915_READ(reg) * units;
64 ret = DIV_ROUND_UP_ULL(raw_time, div);
65
66 intel_runtime_pm_put(dev_priv);
67 return ret;
68}
69
70static ssize_t
71show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
72{
73 struct drm_minor *dminor = dev_to_drm_minor(kdev);
74 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
75}
76
77static ssize_t
78show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
79{
80 struct drm_minor *dminor = dev_get_drvdata(kdev);
81 u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
82 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
83}
84
85static ssize_t
86show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
87{
88 struct drm_minor *dminor = dev_to_drm_minor(kdev);
89 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
90 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
91}
92
93static ssize_t
94show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
95{
96 struct drm_minor *dminor = dev_to_drm_minor(kdev);
97 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
98 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
99}
100
101static ssize_t
102show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
103{
104 struct drm_minor *dminor = dev_get_drvdata(kdev);
105 u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
106 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
107}
108
109static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
110static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
111static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
112static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
113static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
114
115static struct attribute *rc6_attrs[] = {
116 &dev_attr_rc6_enable.attr,
117 &dev_attr_rc6_residency_ms.attr,
118 NULL
119};
120
121static struct attribute_group rc6_attr_group = {
122 .name = power_group_name,
123 .attrs = rc6_attrs
124};
125
126static struct attribute *rc6p_attrs[] = {
127 &dev_attr_rc6p_residency_ms.attr,
128 &dev_attr_rc6pp_residency_ms.attr,
129 NULL
130};
131
132static struct attribute_group rc6p_attr_group = {
133 .name = power_group_name,
134 .attrs = rc6p_attrs
135};
136
137static struct attribute *media_rc6_attrs[] = {
138 &dev_attr_media_rc6_residency_ms.attr,
139 NULL
140};
141
142static struct attribute_group media_rc6_attr_group = {
143 .name = power_group_name,
144 .attrs = media_rc6_attrs
145};
146#endif
147
148static int l3_access_valid(struct drm_device *dev, loff_t offset)
149{
150 if (!HAS_L3_DPF(dev))
151 return -EPERM;
152
153 if (offset % 4 != 0)
154 return -EINVAL;
155
156 if (offset >= GEN7_L3LOG_SIZE)
157 return -ENXIO;
158
159 return 0;
160}
161
162static ssize_t
163i915_l3_read(struct file *filp, struct kobject *kobj,
164 struct bin_attribute *attr, char *buf,
165 loff_t offset, size_t count)
166{
167 struct device *dev = kobj_to_dev(kobj);
168 struct drm_minor *dminor = dev_to_drm_minor(dev);
169 struct drm_device *drm_dev = dminor->dev;
170 struct drm_i915_private *dev_priv = drm_dev->dev_private;
171 int slice = (int)(uintptr_t)attr->private;
172 int ret;
173
174 count = round_down(count, 4);
175
176 ret = l3_access_valid(drm_dev, offset);
177 if (ret)
178 return ret;
179
180 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
181
182 ret = i915_mutex_lock_interruptible(drm_dev);
183 if (ret)
184 return ret;
185
186 if (dev_priv->l3_parity.remap_info[slice])
187 memcpy(buf,
188 dev_priv->l3_parity.remap_info[slice] + (offset/4),
189 count);
190 else
191 memset(buf, 0, count);
192
193 mutex_unlock(&drm_dev->struct_mutex);
194
195 return count;
196}
197
198static ssize_t
199i915_l3_write(struct file *filp, struct kobject *kobj,
200 struct bin_attribute *attr, char *buf,
201 loff_t offset, size_t count)
202{
203 struct device *dev = kobj_to_dev(kobj);
204 struct drm_minor *dminor = dev_to_drm_minor(dev);
205 struct drm_device *drm_dev = dminor->dev;
206 struct drm_i915_private *dev_priv = drm_dev->dev_private;
207 struct intel_context *ctx;
208 u32 *temp = NULL; /* Just here to make handling failures easy */
209 int slice = (int)(uintptr_t)attr->private;
210 int ret;
211
212 if (!HAS_HW_CONTEXTS(drm_dev))
213 return -ENXIO;
214
215 ret = l3_access_valid(drm_dev, offset);
216 if (ret)
217 return ret;
218
219 ret = i915_mutex_lock_interruptible(drm_dev);
220 if (ret)
221 return ret;
222
223 if (!dev_priv->l3_parity.remap_info[slice]) {
224 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
225 if (!temp) {
226 mutex_unlock(&drm_dev->struct_mutex);
227 return -ENOMEM;
228 }
229 }
230
231 ret = i915_gpu_idle(drm_dev);
232 if (ret) {
233 kfree(temp);
234 mutex_unlock(&drm_dev->struct_mutex);
235 return ret;
236 }
237
238 /* TODO: Ideally we really want a GPU reset here to make sure errors
239 * aren't propagated. Since I cannot find a stable way to reset the GPU
240 * at this point it is left as a TODO.
241 */
242 if (temp)
243 dev_priv->l3_parity.remap_info[slice] = temp;
244
245 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
246
247 /* NB: We defer the remapping until we switch to the context */
248 list_for_each_entry(ctx, &dev_priv->context_list, link)
249 ctx->remap_slice |= (1<<slice);
250
251 mutex_unlock(&drm_dev->struct_mutex);
252
253 return count;
254}
255
256static struct bin_attribute dpf_attrs = {
257 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
258 .size = GEN7_L3LOG_SIZE,
259 .read = i915_l3_read,
260 .write = i915_l3_write,
261 .mmap = NULL,
262 .private = (void *)0
263};
264
265static struct bin_attribute dpf_attrs_1 = {
266 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
267 .size = GEN7_L3LOG_SIZE,
268 .read = i915_l3_read,
269 .write = i915_l3_write,
270 .mmap = NULL,
271 .private = (void *)1
272};
273
274static ssize_t gt_act_freq_mhz_show(struct device *kdev,
275 struct device_attribute *attr, char *buf)
276{
277 struct drm_minor *minor = dev_to_drm_minor(kdev);
278 struct drm_device *dev = minor->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 int ret;
281
282 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
283
284 intel_runtime_pm_get(dev_priv);
285
286 mutex_lock(&dev_priv->rps.hw_lock);
287 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
288 u32 freq;
289 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
290 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
291 } else {
292 u32 rpstat = I915_READ(GEN6_RPSTAT1);
293 if (IS_GEN9(dev_priv))
294 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
295 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
296 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
297 else
298 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
299 ret = intel_gpu_freq(dev_priv, ret);
300 }
301 mutex_unlock(&dev_priv->rps.hw_lock);
302
303 intel_runtime_pm_put(dev_priv);
304
305 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
306}
307
308static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
309 struct device_attribute *attr, char *buf)
310{
311 struct drm_minor *minor = dev_to_drm_minor(kdev);
312 struct drm_device *dev = minor->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 int ret;
315
316 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
317
318 intel_runtime_pm_get(dev_priv);
319
320 mutex_lock(&dev_priv->rps.hw_lock);
321 ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
322 mutex_unlock(&dev_priv->rps.hw_lock);
323
324 intel_runtime_pm_put(dev_priv);
325
326 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
327}
328
329static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
330 struct device_attribute *attr, char *buf)
331{
332 struct drm_minor *minor = dev_to_drm_minor(kdev);
333 struct drm_device *dev = minor->dev;
334 struct drm_i915_private *dev_priv = dev->dev_private;
335
336 return snprintf(buf, PAGE_SIZE,
337 "%d\n",
338 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
339}
340
341static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
342{
343 struct drm_minor *minor = dev_to_drm_minor(kdev);
344 struct drm_device *dev = minor->dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 int ret;
347
348 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
349
350 mutex_lock(&dev_priv->rps.hw_lock);
351 ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
352 mutex_unlock(&dev_priv->rps.hw_lock);
353
354 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
355}
356
357static ssize_t gt_max_freq_mhz_store(struct device *kdev,
358 struct device_attribute *attr,
359 const char *buf, size_t count)
360{
361 struct drm_minor *minor = dev_to_drm_minor(kdev);
362 struct drm_device *dev = minor->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 u32 val;
365 ssize_t ret;
366
367 ret = kstrtou32(buf, 0, &val);
368 if (ret)
369 return ret;
370
371 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
372
373 mutex_lock(&dev_priv->rps.hw_lock);
374
375 val = intel_freq_opcode(dev_priv, val);
376
377 if (val < dev_priv->rps.min_freq ||
378 val > dev_priv->rps.max_freq ||
379 val < dev_priv->rps.min_freq_softlimit) {
380 mutex_unlock(&dev_priv->rps.hw_lock);
381 return -EINVAL;
382 }
383
384 if (val > dev_priv->rps.rp0_freq)
385 DRM_DEBUG("User requested overclocking to %d\n",
386 intel_gpu_freq(dev_priv, val));
387
388 dev_priv->rps.max_freq_softlimit = val;
389
390 val = clamp_t(int, dev_priv->rps.cur_freq,
391 dev_priv->rps.min_freq_softlimit,
392 dev_priv->rps.max_freq_softlimit);
393
394 /* We still need *_set_rps to process the new max_delay and
395 * update the interrupt limits and PMINTRMSK even though
396 * frequency request may be unchanged. */
397 intel_set_rps(dev, val);
398
399 mutex_unlock(&dev_priv->rps.hw_lock);
400
401 return count;
402}
403
404static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
405{
406 struct drm_minor *minor = dev_to_drm_minor(kdev);
407 struct drm_device *dev = minor->dev;
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 int ret;
410
411 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
412
413 mutex_lock(&dev_priv->rps.hw_lock);
414 ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
415 mutex_unlock(&dev_priv->rps.hw_lock);
416
417 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
418}
419
420static ssize_t gt_min_freq_mhz_store(struct device *kdev,
421 struct device_attribute *attr,
422 const char *buf, size_t count)
423{
424 struct drm_minor *minor = dev_to_drm_minor(kdev);
425 struct drm_device *dev = minor->dev;
426 struct drm_i915_private *dev_priv = dev->dev_private;
427 u32 val;
428 ssize_t ret;
429
430 ret = kstrtou32(buf, 0, &val);
431 if (ret)
432 return ret;
433
434 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
435
436 mutex_lock(&dev_priv->rps.hw_lock);
437
438 val = intel_freq_opcode(dev_priv, val);
439
440 if (val < dev_priv->rps.min_freq ||
441 val > dev_priv->rps.max_freq ||
442 val > dev_priv->rps.max_freq_softlimit) {
443 mutex_unlock(&dev_priv->rps.hw_lock);
444 return -EINVAL;
445 }
446
447 dev_priv->rps.min_freq_softlimit = val;
448
449 val = clamp_t(int, dev_priv->rps.cur_freq,
450 dev_priv->rps.min_freq_softlimit,
451 dev_priv->rps.max_freq_softlimit);
452
453 /* We still need *_set_rps to process the new min_delay and
454 * update the interrupt limits and PMINTRMSK even though
455 * frequency request may be unchanged. */
456 intel_set_rps(dev, val);
457
458 mutex_unlock(&dev_priv->rps.hw_lock);
459
460 return count;
461
462}
463
464static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
465static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
466static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
467static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
468
469static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
470
471static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
472static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
473static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
474static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
475
476/* For now we have a static number of RP states */
477static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
478{
479 struct drm_minor *minor = dev_to_drm_minor(kdev);
480 struct drm_device *dev = minor->dev;
481 struct drm_i915_private *dev_priv = dev->dev_private;
482 u32 val;
483
484 if (attr == &dev_attr_gt_RP0_freq_mhz)
485 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
486 else if (attr == &dev_attr_gt_RP1_freq_mhz)
487 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
488 else if (attr == &dev_attr_gt_RPn_freq_mhz)
489 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
490 else
491 BUG();
492
493 return snprintf(buf, PAGE_SIZE, "%d\n", val);
494}
495
496static const struct attribute *gen6_attrs[] = {
497 &dev_attr_gt_act_freq_mhz.attr,
498 &dev_attr_gt_cur_freq_mhz.attr,
499 &dev_attr_gt_max_freq_mhz.attr,
500 &dev_attr_gt_min_freq_mhz.attr,
501 &dev_attr_gt_RP0_freq_mhz.attr,
502 &dev_attr_gt_RP1_freq_mhz.attr,
503 &dev_attr_gt_RPn_freq_mhz.attr,
504 NULL,
505};
506
507static const struct attribute *vlv_attrs[] = {
508 &dev_attr_gt_act_freq_mhz.attr,
509 &dev_attr_gt_cur_freq_mhz.attr,
510 &dev_attr_gt_max_freq_mhz.attr,
511 &dev_attr_gt_min_freq_mhz.attr,
512 &dev_attr_gt_RP0_freq_mhz.attr,
513 &dev_attr_gt_RP1_freq_mhz.attr,
514 &dev_attr_gt_RPn_freq_mhz.attr,
515 &dev_attr_vlv_rpe_freq_mhz.attr,
516 NULL,
517};
518
519static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
520 struct bin_attribute *attr, char *buf,
521 loff_t off, size_t count)
522{
523
524 struct device *kdev = kobj_to_dev(kobj);
525 struct drm_minor *minor = dev_to_drm_minor(kdev);
526 struct drm_device *dev = minor->dev;
527 struct i915_error_state_file_priv error_priv;
528 struct drm_i915_error_state_buf error_str;
529 ssize_t ret_count = 0;
530 int ret;
531
532 memset(&error_priv, 0, sizeof(error_priv));
533
534 ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off);
535 if (ret)
536 return ret;
537
538 error_priv.dev = dev;
539 i915_error_state_get(dev, &error_priv);
540
541 ret = i915_error_state_to_str(&error_str, &error_priv);
542 if (ret)
543 goto out;
544
545 ret_count = count < error_str.bytes ? count : error_str.bytes;
546
547 memcpy(buf, error_str.buf, ret_count);
548out:
549 i915_error_state_put(&error_priv);
550 i915_error_state_buf_release(&error_str);
551
552 return ret ?: ret_count;
553}
554
555static ssize_t error_state_write(struct file *file, struct kobject *kobj,
556 struct bin_attribute *attr, char *buf,
557 loff_t off, size_t count)
558{
559 struct device *kdev = kobj_to_dev(kobj);
560 struct drm_minor *minor = dev_to_drm_minor(kdev);
561 struct drm_device *dev = minor->dev;
562 int ret;
563
564 DRM_DEBUG_DRIVER("Resetting error state\n");
565
566 ret = mutex_lock_interruptible(&dev->struct_mutex);
567 if (ret)
568 return ret;
569
570 i915_destroy_error_state(dev);
571 mutex_unlock(&dev->struct_mutex);
572
573 return count;
574}
575
576static struct bin_attribute error_state_attr = {
577 .attr.name = "error",
578 .attr.mode = S_IRUSR | S_IWUSR,
579 .size = 0,
580 .read = error_state_read,
581 .write = error_state_write,
582};
583
584void i915_setup_sysfs(struct drm_device *dev)
585{
586 int ret;
587
588#ifdef CONFIG_PM
589 if (HAS_RC6(dev)) {
590 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
591 &rc6_attr_group);
592 if (ret)
593 DRM_ERROR("RC6 residency sysfs setup failed\n");
594 }
595 if (HAS_RC6p(dev)) {
596 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
597 &rc6p_attr_group);
598 if (ret)
599 DRM_ERROR("RC6p residency sysfs setup failed\n");
600 }
601 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
602 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
603 &media_rc6_attr_group);
604 if (ret)
605 DRM_ERROR("Media RC6 residency sysfs setup failed\n");
606 }
607#endif
608 if (HAS_L3_DPF(dev)) {
609 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
610 if (ret)
611 DRM_ERROR("l3 parity sysfs setup failed\n");
612
613 if (NUM_L3_SLICES(dev) > 1) {
614 ret = device_create_bin_file(dev->primary->kdev,
615 &dpf_attrs_1);
616 if (ret)
617 DRM_ERROR("l3 parity slice 1 setup failed\n");
618 }
619 }
620
621 ret = 0;
622 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
623 ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
624 else if (INTEL_INFO(dev)->gen >= 6)
625 ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
626 if (ret)
627 DRM_ERROR("RPS sysfs setup failed\n");
628
629 ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
630 &error_state_attr);
631 if (ret)
632 DRM_ERROR("error_state sysfs setup failed\n");
633}
634
635void i915_teardown_sysfs(struct drm_device *dev)
636{
637 sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
638 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
639 sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
640 else
641 sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
642 device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1);
643 device_remove_bin_file(dev->primary->kdev, &dpf_attrs);
644#ifdef CONFIG_PM
645 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
646 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group);
647#endif
648}
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28#include <linux/device.h>
29#include <linux/module.h>
30#include <linux/stat.h>
31#include <linux/sysfs.h>
32#include "intel_drv.h"
33#include "i915_drv.h"
34
35static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
36{
37 struct drm_minor *minor = dev_get_drvdata(kdev);
38 return to_i915(minor->dev);
39}
40
41#ifdef CONFIG_PM
42static u32 calc_residency(struct drm_i915_private *dev_priv,
43 i915_reg_t reg)
44{
45 u64 res;
46
47 intel_runtime_pm_get(dev_priv);
48 res = intel_rc6_residency_us(dev_priv, reg);
49 intel_runtime_pm_put(dev_priv);
50
51 return DIV_ROUND_CLOSEST_ULL(res, 1000);
52}
53
54static ssize_t
55show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
56{
57 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
58 unsigned int mask;
59
60 mask = 0;
61 if (HAS_RC6(dev_priv))
62 mask |= BIT(0);
63 if (HAS_RC6p(dev_priv))
64 mask |= BIT(1);
65 if (HAS_RC6pp(dev_priv))
66 mask |= BIT(2);
67
68 return snprintf(buf, PAGE_SIZE, "%x\n", mask);
69}
70
71static ssize_t
72show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
73{
74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
75 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
77}
78
79static ssize_t
80show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
81{
82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
83 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
84 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
85}
86
87static ssize_t
88show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
89{
90 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
91 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
92 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
93}
94
95static ssize_t
96show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
97{
98 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
99 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
100 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
101}
102
103static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
104static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
105static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
106static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
107static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
108
109static struct attribute *rc6_attrs[] = {
110 &dev_attr_rc6_enable.attr,
111 &dev_attr_rc6_residency_ms.attr,
112 NULL
113};
114
115static const struct attribute_group rc6_attr_group = {
116 .name = power_group_name,
117 .attrs = rc6_attrs
118};
119
120static struct attribute *rc6p_attrs[] = {
121 &dev_attr_rc6p_residency_ms.attr,
122 &dev_attr_rc6pp_residency_ms.attr,
123 NULL
124};
125
126static const struct attribute_group rc6p_attr_group = {
127 .name = power_group_name,
128 .attrs = rc6p_attrs
129};
130
131static struct attribute *media_rc6_attrs[] = {
132 &dev_attr_media_rc6_residency_ms.attr,
133 NULL
134};
135
136static const struct attribute_group media_rc6_attr_group = {
137 .name = power_group_name,
138 .attrs = media_rc6_attrs
139};
140#endif
141
142static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
143{
144 if (!HAS_L3_DPF(dev_priv))
145 return -EPERM;
146
147 if (offset % 4 != 0)
148 return -EINVAL;
149
150 if (offset >= GEN7_L3LOG_SIZE)
151 return -ENXIO;
152
153 return 0;
154}
155
156static ssize_t
157i915_l3_read(struct file *filp, struct kobject *kobj,
158 struct bin_attribute *attr, char *buf,
159 loff_t offset, size_t count)
160{
161 struct device *kdev = kobj_to_dev(kobj);
162 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
163 struct drm_device *dev = &dev_priv->drm;
164 int slice = (int)(uintptr_t)attr->private;
165 int ret;
166
167 count = round_down(count, 4);
168
169 ret = l3_access_valid(dev_priv, offset);
170 if (ret)
171 return ret;
172
173 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
174
175 ret = i915_mutex_lock_interruptible(dev);
176 if (ret)
177 return ret;
178
179 if (dev_priv->l3_parity.remap_info[slice])
180 memcpy(buf,
181 dev_priv->l3_parity.remap_info[slice] + (offset/4),
182 count);
183 else
184 memset(buf, 0, count);
185
186 mutex_unlock(&dev->struct_mutex);
187
188 return count;
189}
190
191static ssize_t
192i915_l3_write(struct file *filp, struct kobject *kobj,
193 struct bin_attribute *attr, char *buf,
194 loff_t offset, size_t count)
195{
196 struct device *kdev = kobj_to_dev(kobj);
197 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
198 struct drm_device *dev = &dev_priv->drm;
199 struct i915_gem_context *ctx;
200 int slice = (int)(uintptr_t)attr->private;
201 u32 **remap_info;
202 int ret;
203
204 ret = l3_access_valid(dev_priv, offset);
205 if (ret)
206 return ret;
207
208 ret = i915_mutex_lock_interruptible(dev);
209 if (ret)
210 return ret;
211
212 remap_info = &dev_priv->l3_parity.remap_info[slice];
213 if (!*remap_info) {
214 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
215 if (!*remap_info) {
216 ret = -ENOMEM;
217 goto out;
218 }
219 }
220
221 /* TODO: Ideally we really want a GPU reset here to make sure errors
222 * aren't propagated. Since I cannot find a stable way to reset the GPU
223 * at this point it is left as a TODO.
224 */
225 memcpy(*remap_info + (offset/4), buf, count);
226
227 /* NB: We defer the remapping until we switch to the context */
228 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
229 ctx->remap_slice |= (1<<slice);
230
231 ret = count;
232
233out:
234 mutex_unlock(&dev->struct_mutex);
235
236 return ret;
237}
238
239static const struct bin_attribute dpf_attrs = {
240 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
241 .size = GEN7_L3LOG_SIZE,
242 .read = i915_l3_read,
243 .write = i915_l3_write,
244 .mmap = NULL,
245 .private = (void *)0
246};
247
248static const struct bin_attribute dpf_attrs_1 = {
249 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
250 .size = GEN7_L3LOG_SIZE,
251 .read = i915_l3_read,
252 .write = i915_l3_write,
253 .mmap = NULL,
254 .private = (void *)1
255};
256
257static ssize_t gt_act_freq_mhz_show(struct device *kdev,
258 struct device_attribute *attr, char *buf)
259{
260 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
261 int ret;
262
263 intel_runtime_pm_get(dev_priv);
264
265 mutex_lock(&dev_priv->pcu_lock);
266 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
267 u32 freq;
268 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
269 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
270 } else {
271 ret = intel_gpu_freq(dev_priv,
272 intel_get_cagf(dev_priv,
273 I915_READ(GEN6_RPSTAT1)));
274 }
275 mutex_unlock(&dev_priv->pcu_lock);
276
277 intel_runtime_pm_put(dev_priv);
278
279 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
280}
281
282static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
283 struct device_attribute *attr, char *buf)
284{
285 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
286
287 return snprintf(buf, PAGE_SIZE, "%d\n",
288 intel_gpu_freq(dev_priv,
289 dev_priv->gt_pm.rps.cur_freq));
290}
291
292static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
293{
294 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
295
296 return snprintf(buf, PAGE_SIZE, "%d\n",
297 intel_gpu_freq(dev_priv,
298 dev_priv->gt_pm.rps.boost_freq));
299}
300
301static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
302 struct device_attribute *attr,
303 const char *buf, size_t count)
304{
305 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
306 struct intel_rps *rps = &dev_priv->gt_pm.rps;
307 bool boost = false;
308 ssize_t ret;
309 u32 val;
310
311 ret = kstrtou32(buf, 0, &val);
312 if (ret)
313 return ret;
314
315 /* Validate against (static) hardware limits */
316 val = intel_freq_opcode(dev_priv, val);
317 if (val < rps->min_freq || val > rps->max_freq)
318 return -EINVAL;
319
320 mutex_lock(&dev_priv->pcu_lock);
321 if (val != rps->boost_freq) {
322 rps->boost_freq = val;
323 boost = atomic_read(&rps->num_waiters);
324 }
325 mutex_unlock(&dev_priv->pcu_lock);
326 if (boost)
327 schedule_work(&rps->work);
328
329 return count;
330}
331
332static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
333 struct device_attribute *attr, char *buf)
334{
335 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
336
337 return snprintf(buf, PAGE_SIZE, "%d\n",
338 intel_gpu_freq(dev_priv,
339 dev_priv->gt_pm.rps.efficient_freq));
340}
341
342static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
343{
344 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
345
346 return snprintf(buf, PAGE_SIZE, "%d\n",
347 intel_gpu_freq(dev_priv,
348 dev_priv->gt_pm.rps.max_freq_softlimit));
349}
350
351static ssize_t gt_max_freq_mhz_store(struct device *kdev,
352 struct device_attribute *attr,
353 const char *buf, size_t count)
354{
355 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
356 struct intel_rps *rps = &dev_priv->gt_pm.rps;
357 u32 val;
358 ssize_t ret;
359
360 ret = kstrtou32(buf, 0, &val);
361 if (ret)
362 return ret;
363
364 intel_runtime_pm_get(dev_priv);
365
366 mutex_lock(&dev_priv->pcu_lock);
367
368 val = intel_freq_opcode(dev_priv, val);
369
370 if (val < rps->min_freq ||
371 val > rps->max_freq ||
372 val < rps->min_freq_softlimit) {
373 mutex_unlock(&dev_priv->pcu_lock);
374 intel_runtime_pm_put(dev_priv);
375 return -EINVAL;
376 }
377
378 if (val > rps->rp0_freq)
379 DRM_DEBUG("User requested overclocking to %d\n",
380 intel_gpu_freq(dev_priv, val));
381
382 rps->max_freq_softlimit = val;
383
384 val = clamp_t(int, rps->cur_freq,
385 rps->min_freq_softlimit,
386 rps->max_freq_softlimit);
387
388 /* We still need *_set_rps to process the new max_delay and
389 * update the interrupt limits and PMINTRMSK even though
390 * frequency request may be unchanged. */
391 ret = intel_set_rps(dev_priv, val);
392
393 mutex_unlock(&dev_priv->pcu_lock);
394
395 intel_runtime_pm_put(dev_priv);
396
397 return ret ?: count;
398}
399
400static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
401{
402 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
403
404 return snprintf(buf, PAGE_SIZE, "%d\n",
405 intel_gpu_freq(dev_priv,
406 dev_priv->gt_pm.rps.min_freq_softlimit));
407}
408
409static ssize_t gt_min_freq_mhz_store(struct device *kdev,
410 struct device_attribute *attr,
411 const char *buf, size_t count)
412{
413 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
414 struct intel_rps *rps = &dev_priv->gt_pm.rps;
415 u32 val;
416 ssize_t ret;
417
418 ret = kstrtou32(buf, 0, &val);
419 if (ret)
420 return ret;
421
422 intel_runtime_pm_get(dev_priv);
423
424 mutex_lock(&dev_priv->pcu_lock);
425
426 val = intel_freq_opcode(dev_priv, val);
427
428 if (val < rps->min_freq ||
429 val > rps->max_freq ||
430 val > rps->max_freq_softlimit) {
431 mutex_unlock(&dev_priv->pcu_lock);
432 intel_runtime_pm_put(dev_priv);
433 return -EINVAL;
434 }
435
436 rps->min_freq_softlimit = val;
437
438 val = clamp_t(int, rps->cur_freq,
439 rps->min_freq_softlimit,
440 rps->max_freq_softlimit);
441
442 /* We still need *_set_rps to process the new min_delay and
443 * update the interrupt limits and PMINTRMSK even though
444 * frequency request may be unchanged. */
445 ret = intel_set_rps(dev_priv, val);
446
447 mutex_unlock(&dev_priv->pcu_lock);
448
449 intel_runtime_pm_put(dev_priv);
450
451 return ret ?: count;
452}
453
454static DEVICE_ATTR_RO(gt_act_freq_mhz);
455static DEVICE_ATTR_RO(gt_cur_freq_mhz);
456static DEVICE_ATTR_RW(gt_boost_freq_mhz);
457static DEVICE_ATTR_RW(gt_max_freq_mhz);
458static DEVICE_ATTR_RW(gt_min_freq_mhz);
459
460static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
461
462static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
463static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
464static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
465static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
466
467/* For now we have a static number of RP states */
468static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
469{
470 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
471 struct intel_rps *rps = &dev_priv->gt_pm.rps;
472 u32 val;
473
474 if (attr == &dev_attr_gt_RP0_freq_mhz)
475 val = intel_gpu_freq(dev_priv, rps->rp0_freq);
476 else if (attr == &dev_attr_gt_RP1_freq_mhz)
477 val = intel_gpu_freq(dev_priv, rps->rp1_freq);
478 else if (attr == &dev_attr_gt_RPn_freq_mhz)
479 val = intel_gpu_freq(dev_priv, rps->min_freq);
480 else
481 BUG();
482
483 return snprintf(buf, PAGE_SIZE, "%d\n", val);
484}
485
486static const struct attribute *gen6_attrs[] = {
487 &dev_attr_gt_act_freq_mhz.attr,
488 &dev_attr_gt_cur_freq_mhz.attr,
489 &dev_attr_gt_boost_freq_mhz.attr,
490 &dev_attr_gt_max_freq_mhz.attr,
491 &dev_attr_gt_min_freq_mhz.attr,
492 &dev_attr_gt_RP0_freq_mhz.attr,
493 &dev_attr_gt_RP1_freq_mhz.attr,
494 &dev_attr_gt_RPn_freq_mhz.attr,
495 NULL,
496};
497
498static const struct attribute *vlv_attrs[] = {
499 &dev_attr_gt_act_freq_mhz.attr,
500 &dev_attr_gt_cur_freq_mhz.attr,
501 &dev_attr_gt_boost_freq_mhz.attr,
502 &dev_attr_gt_max_freq_mhz.attr,
503 &dev_attr_gt_min_freq_mhz.attr,
504 &dev_attr_gt_RP0_freq_mhz.attr,
505 &dev_attr_gt_RP1_freq_mhz.attr,
506 &dev_attr_gt_RPn_freq_mhz.attr,
507 &dev_attr_vlv_rpe_freq_mhz.attr,
508 NULL,
509};
510
511#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
512
513static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
514 struct bin_attribute *attr, char *buf,
515 loff_t off, size_t count)
516{
517
518 struct device *kdev = kobj_to_dev(kobj);
519 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
520 struct drm_i915_error_state_buf error_str;
521 struct i915_gpu_state *gpu;
522 ssize_t ret;
523
524 ret = i915_error_state_buf_init(&error_str, dev_priv, count, off);
525 if (ret)
526 return ret;
527
528 gpu = i915_first_error_state(dev_priv);
529 ret = i915_error_state_to_str(&error_str, gpu);
530 if (ret)
531 goto out;
532
533 ret = count < error_str.bytes ? count : error_str.bytes;
534 memcpy(buf, error_str.buf, ret);
535
536out:
537 i915_gpu_state_put(gpu);
538 i915_error_state_buf_release(&error_str);
539
540 return ret;
541}
542
543static ssize_t error_state_write(struct file *file, struct kobject *kobj,
544 struct bin_attribute *attr, char *buf,
545 loff_t off, size_t count)
546{
547 struct device *kdev = kobj_to_dev(kobj);
548 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
549
550 DRM_DEBUG_DRIVER("Resetting error state\n");
551 i915_reset_error_state(dev_priv);
552
553 return count;
554}
555
556static const struct bin_attribute error_state_attr = {
557 .attr.name = "error",
558 .attr.mode = S_IRUSR | S_IWUSR,
559 .size = 0,
560 .read = error_state_read,
561 .write = error_state_write,
562};
563
564static void i915_setup_error_capture(struct device *kdev)
565{
566 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
567 DRM_ERROR("error_state sysfs setup failed\n");
568}
569
570static void i915_teardown_error_capture(struct device *kdev)
571{
572 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
573}
574#else
575static void i915_setup_error_capture(struct device *kdev) {}
576static void i915_teardown_error_capture(struct device *kdev) {}
577#endif
578
579void i915_setup_sysfs(struct drm_i915_private *dev_priv)
580{
581 struct device *kdev = dev_priv->drm.primary->kdev;
582 int ret;
583
584#ifdef CONFIG_PM
585 if (HAS_RC6(dev_priv)) {
586 ret = sysfs_merge_group(&kdev->kobj,
587 &rc6_attr_group);
588 if (ret)
589 DRM_ERROR("RC6 residency sysfs setup failed\n");
590 }
591 if (HAS_RC6p(dev_priv)) {
592 ret = sysfs_merge_group(&kdev->kobj,
593 &rc6p_attr_group);
594 if (ret)
595 DRM_ERROR("RC6p residency sysfs setup failed\n");
596 }
597 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
598 ret = sysfs_merge_group(&kdev->kobj,
599 &media_rc6_attr_group);
600 if (ret)
601 DRM_ERROR("Media RC6 residency sysfs setup failed\n");
602 }
603#endif
604 if (HAS_L3_DPF(dev_priv)) {
605 ret = device_create_bin_file(kdev, &dpf_attrs);
606 if (ret)
607 DRM_ERROR("l3 parity sysfs setup failed\n");
608
609 if (NUM_L3_SLICES(dev_priv) > 1) {
610 ret = device_create_bin_file(kdev,
611 &dpf_attrs_1);
612 if (ret)
613 DRM_ERROR("l3 parity slice 1 setup failed\n");
614 }
615 }
616
617 ret = 0;
618 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
619 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
620 else if (INTEL_GEN(dev_priv) >= 6)
621 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
622 if (ret)
623 DRM_ERROR("RPS sysfs setup failed\n");
624
625 i915_setup_error_capture(kdev);
626}
627
628void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
629{
630 struct device *kdev = dev_priv->drm.primary->kdev;
631
632 i915_teardown_error_capture(kdev);
633
634 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
635 sysfs_remove_files(&kdev->kobj, vlv_attrs);
636 else
637 sysfs_remove_files(&kdev->kobj, gen6_attrs);
638 device_remove_bin_file(kdev, &dpf_attrs_1);
639 device_remove_bin_file(kdev, &dpf_attrs);
640#ifdef CONFIG_PM
641 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
642 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
643#endif
644}