1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 */
 23
 24#ifndef _I915_PVINFO_H_
 25#define _I915_PVINFO_H_
 26
 27/* The MMIO offset of the shared info between guest and host emulator */
 28#define VGT_PVINFO_PAGE	0x78000
 29#define VGT_PVINFO_SIZE	0x1000
 30
 31/*
 32 * The following structure pages are defined in GEN MMIO space
 33 * for virtualization. (One page for now)
 34 */
 35#define VGT_MAGIC         0x4776544776544776ULL	/* 'vGTvGTvG' */
 36#define VGT_VERSION_MAJOR 1
 37#define VGT_VERSION_MINOR 0
 38
 39/*
 40 * notifications from guest to vgpu device model
 41 */
 42enum vgt_g2v_type {
 43	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
 44	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
 45	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
 46	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 47	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 48	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
 49	VGT_G2V_MAX,
 50};
 51
 52/*
 53 * VGT capabilities type
 54 */
 55#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
 56#define VGT_CAPS_HWSP_EMULATION		BIT(3)
 57
 58struct vgt_if {
 59	u64 magic;		/* VGT_MAGIC */
 60	u16 version_major;
 61	u16 version_minor;
 62	u32 vgt_id;		/* ID of vGT instance */
 63	u32 vgt_caps;		/* VGT capabilities */
 64	u32 rsv1[11];		/* pad to offset 0x40 */
 65	/*
 66	 *  Data structure to describe the balooning info of resources.
 67	 *  Each VM can only have one portion of continuous area for now.
 68	 *  (May support scattered resource in future)
 69	 *  (starting from offset 0x40)
 70	 */
 71	struct {
 72		/* Aperture register balooning */
 73		struct {
 74			u32 base;
 75			u32 size;
 76		} mappable_gmadr;	/* aperture */
 77		/* GMADR register balooning */
 78		struct {
 79			u32 base;
 80			u32 size;
 81		} nonmappable_gmadr;	/* non aperture */
 82		/* allowed fence registers */
 83		u32 fence_num;
 84		u32 rsv2[3];
 85	} avail_rs;		/* available/assigned resource */
 86	u32 rsv3[0x200 - 24];	/* pad to half page */
 87	/*
 88	 * The bottom half page is for response from Gfx driver to hypervisor.
 89	 */
 90	u32 rsv4;
 91	u32 display_ready;	/* ready for display owner switch */
 92
 93	u32 rsv5[4];
 94
 95	u32 g2v_notify;
 96	u32 rsv6[7];
 97
 98	struct {
 99		u32 lo;
100		u32 hi;
101	} pdp[4];
102
103	u32 execlist_context_descriptor_lo;
104	u32 execlist_context_descriptor_hi;
105
106	u32  rsv7[0x200 - 24];    /* pad to one page */
107} __packed;
108
109#define vgtif_reg(x) \
110	_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
111
112/* vGPU display status to be used by the host side */
113#define VGT_DRV_DISPLAY_NOT_READY 0
114#define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
115
116#endif /* _I915_PVINFO_H_ */