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1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/device.h>
31#include <linux/acpi.h>
32#include <drm/drmP.h>
33#include <drm/i915_drm.h>
34#include "i915_drv.h"
35#include "i915_trace.h"
36#include "intel_drv.h"
37
38#include <linux/apple-gmux.h>
39#include <linux/console.h>
40#include <linux/module.h>
41#include <linux/pm_runtime.h>
42#include <linux/vgaarb.h>
43#include <linux/vga_switcheroo.h>
44#include <drm/drm_crtc_helper.h>
45
46static struct drm_driver driver;
47
48#define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
54
55#define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
62
63#define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
65
66#define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68
69static const struct intel_device_info intel_i830_info = {
70 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
71 .has_overlay = 1, .overlay_needs_physical = 1,
72 .ring_mask = RENDER_RING,
73 GEN_DEFAULT_PIPEOFFSETS,
74 CURSOR_OFFSETS,
75};
76
77static const struct intel_device_info intel_845g_info = {
78 .gen = 2, .num_pipes = 1,
79 .has_overlay = 1, .overlay_needs_physical = 1,
80 .ring_mask = RENDER_RING,
81 GEN_DEFAULT_PIPEOFFSETS,
82 CURSOR_OFFSETS,
83};
84
85static const struct intel_device_info intel_i85x_info = {
86 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
87 .cursor_needs_physical = 1,
88 .has_overlay = 1, .overlay_needs_physical = 1,
89 .has_fbc = 1,
90 .ring_mask = RENDER_RING,
91 GEN_DEFAULT_PIPEOFFSETS,
92 CURSOR_OFFSETS,
93};
94
95static const struct intel_device_info intel_i865g_info = {
96 .gen = 2, .num_pipes = 1,
97 .has_overlay = 1, .overlay_needs_physical = 1,
98 .ring_mask = RENDER_RING,
99 GEN_DEFAULT_PIPEOFFSETS,
100 CURSOR_OFFSETS,
101};
102
103static const struct intel_device_info intel_i915g_info = {
104 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
105 .has_overlay = 1, .overlay_needs_physical = 1,
106 .ring_mask = RENDER_RING,
107 GEN_DEFAULT_PIPEOFFSETS,
108 CURSOR_OFFSETS,
109};
110static const struct intel_device_info intel_i915gm_info = {
111 .gen = 3, .is_mobile = 1, .num_pipes = 2,
112 .cursor_needs_physical = 1,
113 .has_overlay = 1, .overlay_needs_physical = 1,
114 .supports_tv = 1,
115 .has_fbc = 1,
116 .ring_mask = RENDER_RING,
117 GEN_DEFAULT_PIPEOFFSETS,
118 CURSOR_OFFSETS,
119};
120static const struct intel_device_info intel_i945g_info = {
121 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
122 .has_overlay = 1, .overlay_needs_physical = 1,
123 .ring_mask = RENDER_RING,
124 GEN_DEFAULT_PIPEOFFSETS,
125 CURSOR_OFFSETS,
126};
127static const struct intel_device_info intel_i945gm_info = {
128 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
129 .has_hotplug = 1, .cursor_needs_physical = 1,
130 .has_overlay = 1, .overlay_needs_physical = 1,
131 .supports_tv = 1,
132 .has_fbc = 1,
133 .ring_mask = RENDER_RING,
134 GEN_DEFAULT_PIPEOFFSETS,
135 CURSOR_OFFSETS,
136};
137
138static const struct intel_device_info intel_i965g_info = {
139 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
140 .has_hotplug = 1,
141 .has_overlay = 1,
142 .ring_mask = RENDER_RING,
143 GEN_DEFAULT_PIPEOFFSETS,
144 CURSOR_OFFSETS,
145};
146
147static const struct intel_device_info intel_i965gm_info = {
148 .gen = 4, .is_crestline = 1, .num_pipes = 2,
149 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
150 .has_overlay = 1,
151 .supports_tv = 1,
152 .ring_mask = RENDER_RING,
153 GEN_DEFAULT_PIPEOFFSETS,
154 CURSOR_OFFSETS,
155};
156
157static const struct intel_device_info intel_g33_info = {
158 .gen = 3, .is_g33 = 1, .num_pipes = 2,
159 .need_gfx_hws = 1, .has_hotplug = 1,
160 .has_overlay = 1,
161 .ring_mask = RENDER_RING,
162 GEN_DEFAULT_PIPEOFFSETS,
163 CURSOR_OFFSETS,
164};
165
166static const struct intel_device_info intel_g45_info = {
167 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
168 .has_pipe_cxsr = 1, .has_hotplug = 1,
169 .ring_mask = RENDER_RING | BSD_RING,
170 GEN_DEFAULT_PIPEOFFSETS,
171 CURSOR_OFFSETS,
172};
173
174static const struct intel_device_info intel_gm45_info = {
175 .gen = 4, .is_g4x = 1, .num_pipes = 2,
176 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
177 .has_pipe_cxsr = 1, .has_hotplug = 1,
178 .supports_tv = 1,
179 .ring_mask = RENDER_RING | BSD_RING,
180 GEN_DEFAULT_PIPEOFFSETS,
181 CURSOR_OFFSETS,
182};
183
184static const struct intel_device_info intel_pineview_info = {
185 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
186 .need_gfx_hws = 1, .has_hotplug = 1,
187 .has_overlay = 1,
188 GEN_DEFAULT_PIPEOFFSETS,
189 CURSOR_OFFSETS,
190};
191
192static const struct intel_device_info intel_ironlake_d_info = {
193 .gen = 5, .num_pipes = 2,
194 .need_gfx_hws = 1, .has_hotplug = 1,
195 .ring_mask = RENDER_RING | BSD_RING,
196 GEN_DEFAULT_PIPEOFFSETS,
197 CURSOR_OFFSETS,
198};
199
200static const struct intel_device_info intel_ironlake_m_info = {
201 .gen = 5, .is_mobile = 1, .num_pipes = 2,
202 .need_gfx_hws = 1, .has_hotplug = 1,
203 .has_fbc = 1,
204 .ring_mask = RENDER_RING | BSD_RING,
205 GEN_DEFAULT_PIPEOFFSETS,
206 CURSOR_OFFSETS,
207};
208
209static const struct intel_device_info intel_sandybridge_d_info = {
210 .gen = 6, .num_pipes = 2,
211 .need_gfx_hws = 1, .has_hotplug = 1,
212 .has_fbc = 1,
213 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
214 .has_llc = 1,
215 GEN_DEFAULT_PIPEOFFSETS,
216 CURSOR_OFFSETS,
217};
218
219static const struct intel_device_info intel_sandybridge_m_info = {
220 .gen = 6, .is_mobile = 1, .num_pipes = 2,
221 .need_gfx_hws = 1, .has_hotplug = 1,
222 .has_fbc = 1,
223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
224 .has_llc = 1,
225 GEN_DEFAULT_PIPEOFFSETS,
226 CURSOR_OFFSETS,
227};
228
229#define GEN7_FEATURES \
230 .gen = 7, .num_pipes = 3, \
231 .need_gfx_hws = 1, .has_hotplug = 1, \
232 .has_fbc = 1, \
233 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
234 .has_llc = 1, \
235 GEN_DEFAULT_PIPEOFFSETS, \
236 IVB_CURSOR_OFFSETS
237
238static const struct intel_device_info intel_ivybridge_d_info = {
239 GEN7_FEATURES,
240 .is_ivybridge = 1,
241};
242
243static const struct intel_device_info intel_ivybridge_m_info = {
244 GEN7_FEATURES,
245 .is_ivybridge = 1,
246 .is_mobile = 1,
247};
248
249static const struct intel_device_info intel_ivybridge_q_info = {
250 GEN7_FEATURES,
251 .is_ivybridge = 1,
252 .num_pipes = 0, /* legal, last one wins */
253};
254
255#define VLV_FEATURES \
256 .gen = 7, .num_pipes = 2, \
257 .need_gfx_hws = 1, .has_hotplug = 1, \
258 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
259 .display_mmio_offset = VLV_DISPLAY_BASE, \
260 GEN_DEFAULT_PIPEOFFSETS, \
261 CURSOR_OFFSETS
262
263static const struct intel_device_info intel_valleyview_m_info = {
264 VLV_FEATURES,
265 .is_valleyview = 1,
266 .is_mobile = 1,
267};
268
269static const struct intel_device_info intel_valleyview_d_info = {
270 VLV_FEATURES,
271 .is_valleyview = 1,
272};
273
274#define HSW_FEATURES \
275 GEN7_FEATURES, \
276 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
277 .has_ddi = 1, \
278 .has_fpga_dbg = 1
279
280static const struct intel_device_info intel_haswell_d_info = {
281 HSW_FEATURES,
282 .is_haswell = 1,
283};
284
285static const struct intel_device_info intel_haswell_m_info = {
286 HSW_FEATURES,
287 .is_haswell = 1,
288 .is_mobile = 1,
289};
290
291static const struct intel_device_info intel_broadwell_d_info = {
292 HSW_FEATURES,
293 .gen = 8,
294};
295
296static const struct intel_device_info intel_broadwell_m_info = {
297 HSW_FEATURES,
298 .gen = 8, .is_mobile = 1,
299};
300
301static const struct intel_device_info intel_broadwell_gt3d_info = {
302 HSW_FEATURES,
303 .gen = 8,
304 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
305};
306
307static const struct intel_device_info intel_broadwell_gt3m_info = {
308 HSW_FEATURES,
309 .gen = 8, .is_mobile = 1,
310 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
311};
312
313static const struct intel_device_info intel_cherryview_info = {
314 .gen = 8, .num_pipes = 3,
315 .need_gfx_hws = 1, .has_hotplug = 1,
316 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
317 .is_cherryview = 1,
318 .display_mmio_offset = VLV_DISPLAY_BASE,
319 GEN_CHV_PIPEOFFSETS,
320 CURSOR_OFFSETS,
321};
322
323static const struct intel_device_info intel_skylake_info = {
324 HSW_FEATURES,
325 .is_skylake = 1,
326 .gen = 9,
327};
328
329static const struct intel_device_info intel_skylake_gt3_info = {
330 HSW_FEATURES,
331 .is_skylake = 1,
332 .gen = 9,
333 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
334};
335
336static const struct intel_device_info intel_broxton_info = {
337 .is_preliminary = 1,
338 .is_broxton = 1,
339 .gen = 9,
340 .need_gfx_hws = 1, .has_hotplug = 1,
341 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
342 .num_pipes = 3,
343 .has_ddi = 1,
344 .has_fpga_dbg = 1,
345 .has_fbc = 1,
346 GEN_DEFAULT_PIPEOFFSETS,
347 IVB_CURSOR_OFFSETS,
348};
349
350static const struct intel_device_info intel_kabylake_info = {
351 HSW_FEATURES,
352 .is_preliminary = 1,
353 .is_kabylake = 1,
354 .gen = 9,
355};
356
357static const struct intel_device_info intel_kabylake_gt3_info = {
358 HSW_FEATURES,
359 .is_preliminary = 1,
360 .is_kabylake = 1,
361 .gen = 9,
362 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
363};
364
365/*
366 * Make sure any device matches here are from most specific to most
367 * general. For example, since the Quanta match is based on the subsystem
368 * and subvendor IDs, we need it to come before the more general IVB
369 * PCI ID matches, otherwise we'll use the wrong info struct above.
370 */
371static const struct pci_device_id pciidlist[] = {
372 INTEL_I830_IDS(&intel_i830_info),
373 INTEL_I845G_IDS(&intel_845g_info),
374 INTEL_I85X_IDS(&intel_i85x_info),
375 INTEL_I865G_IDS(&intel_i865g_info),
376 INTEL_I915G_IDS(&intel_i915g_info),
377 INTEL_I915GM_IDS(&intel_i915gm_info),
378 INTEL_I945G_IDS(&intel_i945g_info),
379 INTEL_I945GM_IDS(&intel_i945gm_info),
380 INTEL_I965G_IDS(&intel_i965g_info),
381 INTEL_G33_IDS(&intel_g33_info),
382 INTEL_I965GM_IDS(&intel_i965gm_info),
383 INTEL_GM45_IDS(&intel_gm45_info),
384 INTEL_G45_IDS(&intel_g45_info),
385 INTEL_PINEVIEW_IDS(&intel_pineview_info),
386 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
387 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
388 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
389 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
390 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
391 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
392 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
393 INTEL_HSW_D_IDS(&intel_haswell_d_info),
394 INTEL_HSW_M_IDS(&intel_haswell_m_info),
395 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
396 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
397 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
398 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
399 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
400 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
401 INTEL_CHV_IDS(&intel_cherryview_info),
402 INTEL_SKL_GT1_IDS(&intel_skylake_info),
403 INTEL_SKL_GT2_IDS(&intel_skylake_info),
404 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
405 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
406 INTEL_BXT_IDS(&intel_broxton_info),
407 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
408 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
409 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
410 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
411 {0, 0, 0}
412};
413
414MODULE_DEVICE_TABLE(pci, pciidlist);
415
416static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
417{
418 enum intel_pch ret = PCH_NOP;
419
420 /*
421 * In a virtualized passthrough environment we can be in a
422 * setup where the ISA bridge is not able to be passed through.
423 * In this case, a south bridge can be emulated and we have to
424 * make an educated guess as to which PCH is really there.
425 */
426
427 if (IS_GEN5(dev)) {
428 ret = PCH_IBX;
429 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
430 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
431 ret = PCH_CPT;
432 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
433 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
434 ret = PCH_LPT;
435 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
436 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
437 ret = PCH_SPT;
438 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
439 }
440
441 return ret;
442}
443
444void intel_detect_pch(struct drm_device *dev)
445{
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 struct pci_dev *pch = NULL;
448
449 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
450 * (which really amounts to a PCH but no South Display).
451 */
452 if (INTEL_INFO(dev)->num_pipes == 0) {
453 dev_priv->pch_type = PCH_NOP;
454 return;
455 }
456
457 /*
458 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
459 * make graphics device passthrough work easy for VMM, that only
460 * need to expose ISA bridge to let driver know the real hardware
461 * underneath. This is a requirement from virtualization team.
462 *
463 * In some virtualized environments (e.g. XEN), there is irrelevant
464 * ISA bridge in the system. To work reliably, we should scan trhough
465 * all the ISA bridge devices and check for the first match, instead
466 * of only checking the first one.
467 */
468 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
469 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
470 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
471 dev_priv->pch_id = id;
472
473 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
474 dev_priv->pch_type = PCH_IBX;
475 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
476 WARN_ON(!IS_GEN5(dev));
477 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
478 dev_priv->pch_type = PCH_CPT;
479 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
480 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
481 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
482 /* PantherPoint is CPT compatible */
483 dev_priv->pch_type = PCH_CPT;
484 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
485 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
486 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_LPT;
488 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
489 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
490 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
491 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
492 dev_priv->pch_type = PCH_LPT;
493 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
494 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
495 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
496 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
497 dev_priv->pch_type = PCH_SPT;
498 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
499 WARN_ON(!IS_SKYLAKE(dev) &&
500 !IS_KABYLAKE(dev));
501 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
502 dev_priv->pch_type = PCH_SPT;
503 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
504 WARN_ON(!IS_SKYLAKE(dev) &&
505 !IS_KABYLAKE(dev));
506 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
507 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
508 pch->subsystem_vendor == 0x1af4 &&
509 pch->subsystem_device == 0x1100)) {
510 dev_priv->pch_type = intel_virt_detect_pch(dev);
511 } else
512 continue;
513
514 break;
515 }
516 }
517 if (!pch)
518 DRM_DEBUG_KMS("No PCH found.\n");
519
520 pci_dev_put(pch);
521}
522
523bool i915_semaphore_is_enabled(struct drm_device *dev)
524{
525 if (INTEL_INFO(dev)->gen < 6)
526 return false;
527
528 if (i915.semaphores >= 0)
529 return i915.semaphores;
530
531 /* TODO: make semaphores and Execlists play nicely together */
532 if (i915.enable_execlists)
533 return false;
534
535 /* Until we get further testing... */
536 if (IS_GEN8(dev))
537 return false;
538
539#ifdef CONFIG_INTEL_IOMMU
540 /* Enable semaphores on SNB when IO remapping is off */
541 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
542 return false;
543#endif
544
545 return true;
546}
547
548static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
549{
550 struct drm_device *dev = dev_priv->dev;
551 struct intel_encoder *encoder;
552
553 drm_modeset_lock_all(dev);
554 for_each_intel_encoder(dev, encoder)
555 if (encoder->suspend)
556 encoder->suspend(encoder);
557 drm_modeset_unlock_all(dev);
558}
559
560static int intel_suspend_complete(struct drm_i915_private *dev_priv);
561static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
562 bool rpm_resume);
563static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
564
565static bool suspend_to_idle(struct drm_i915_private *dev_priv)
566{
567#if IS_ENABLED(CONFIG_ACPI_SLEEP)
568 if (acpi_target_system_state() < ACPI_STATE_S3)
569 return true;
570#endif
571 return false;
572}
573
574static int i915_drm_suspend(struct drm_device *dev)
575{
576 struct drm_i915_private *dev_priv = dev->dev_private;
577 pci_power_t opregion_target_state;
578 int error;
579
580 /* ignore lid events during suspend */
581 mutex_lock(&dev_priv->modeset_restore_lock);
582 dev_priv->modeset_restore = MODESET_SUSPENDED;
583 mutex_unlock(&dev_priv->modeset_restore_lock);
584
585 disable_rpm_wakeref_asserts(dev_priv);
586
587 /* We do a lot of poking in a lot of registers, make sure they work
588 * properly. */
589 intel_display_set_init_power(dev_priv, true);
590
591 drm_kms_helper_poll_disable(dev);
592
593 pci_save_state(dev->pdev);
594
595 error = i915_gem_suspend(dev);
596 if (error) {
597 dev_err(&dev->pdev->dev,
598 "GEM idle failed, resume might fail\n");
599 goto out;
600 }
601
602 intel_guc_suspend(dev);
603
604 intel_suspend_gt_powersave(dev);
605
606 intel_display_suspend(dev);
607
608 intel_dp_mst_suspend(dev);
609
610 intel_runtime_pm_disable_interrupts(dev_priv);
611 intel_hpd_cancel_work(dev_priv);
612
613 intel_suspend_encoders(dev_priv);
614
615 intel_suspend_hw(dev);
616
617 i915_gem_suspend_gtt_mappings(dev);
618
619 i915_save_state(dev);
620
621 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
622 intel_opregion_notify_adapter(dev, opregion_target_state);
623
624 intel_uncore_forcewake_reset(dev, false);
625 intel_opregion_fini(dev);
626
627 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
628
629 dev_priv->suspend_count++;
630
631 intel_display_set_init_power(dev_priv, false);
632
633 if (HAS_CSR(dev_priv))
634 flush_work(&dev_priv->csr.work);
635
636out:
637 enable_rpm_wakeref_asserts(dev_priv);
638
639 return error;
640}
641
642static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
643{
644 struct drm_i915_private *dev_priv = drm_dev->dev_private;
645 bool fw_csr;
646 int ret;
647
648 disable_rpm_wakeref_asserts(dev_priv);
649
650 fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
651 /*
652 * In case of firmware assisted context save/restore don't manually
653 * deinit the power domains. This also means the CSR/DMC firmware will
654 * stay active, it will power down any HW resources as required and
655 * also enable deeper system power states that would be blocked if the
656 * firmware was inactive.
657 */
658 if (!fw_csr)
659 intel_power_domains_suspend(dev_priv);
660
661 ret = intel_suspend_complete(dev_priv);
662
663 if (ret) {
664 DRM_ERROR("Suspend complete failed: %d\n", ret);
665 if (!fw_csr)
666 intel_power_domains_init_hw(dev_priv, true);
667
668 goto out;
669 }
670
671 pci_disable_device(drm_dev->pdev);
672 /*
673 * During hibernation on some platforms the BIOS may try to access
674 * the device even though it's already in D3 and hang the machine. So
675 * leave the device in D0 on those platforms and hope the BIOS will
676 * power down the device properly. The issue was seen on multiple old
677 * GENs with different BIOS vendors, so having an explicit blacklist
678 * is inpractical; apply the workaround on everything pre GEN6. The
679 * platforms where the issue was seen:
680 * Lenovo Thinkpad X301, X61s, X60, T60, X41
681 * Fujitsu FSC S7110
682 * Acer Aspire 1830T
683 */
684 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
685 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
686
687 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
688
689out:
690 enable_rpm_wakeref_asserts(dev_priv);
691
692 return ret;
693}
694
695int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
696{
697 int error;
698
699 if (!dev || !dev->dev_private) {
700 DRM_ERROR("dev: %p\n", dev);
701 DRM_ERROR("DRM not initialized, aborting suspend.\n");
702 return -ENODEV;
703 }
704
705 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
706 state.event != PM_EVENT_FREEZE))
707 return -EINVAL;
708
709 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
710 return 0;
711
712 error = i915_drm_suspend(dev);
713 if (error)
714 return error;
715
716 return i915_drm_suspend_late(dev, false);
717}
718
719static int i915_drm_resume(struct drm_device *dev)
720{
721 struct drm_i915_private *dev_priv = dev->dev_private;
722
723 disable_rpm_wakeref_asserts(dev_priv);
724
725 mutex_lock(&dev->struct_mutex);
726 i915_gem_restore_gtt_mappings(dev);
727 mutex_unlock(&dev->struct_mutex);
728
729 i915_restore_state(dev);
730 intel_opregion_setup(dev);
731
732 intel_init_pch_refclk(dev);
733 drm_mode_config_reset(dev);
734
735 /*
736 * Interrupts have to be enabled before any batches are run. If not the
737 * GPU will hang. i915_gem_init_hw() will initiate batches to
738 * update/restore the context.
739 *
740 * Modeset enabling in intel_modeset_init_hw() also needs working
741 * interrupts.
742 */
743 intel_runtime_pm_enable_interrupts(dev_priv);
744
745 mutex_lock(&dev->struct_mutex);
746 if (i915_gem_init_hw(dev)) {
747 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
748 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
749 }
750 mutex_unlock(&dev->struct_mutex);
751
752 intel_guc_resume(dev);
753
754 intel_modeset_init_hw(dev);
755
756 spin_lock_irq(&dev_priv->irq_lock);
757 if (dev_priv->display.hpd_irq_setup)
758 dev_priv->display.hpd_irq_setup(dev);
759 spin_unlock_irq(&dev_priv->irq_lock);
760
761 intel_dp_mst_resume(dev);
762
763 intel_display_resume(dev);
764
765 /*
766 * ... but also need to make sure that hotplug processing
767 * doesn't cause havoc. Like in the driver load code we don't
768 * bother with the tiny race here where we might loose hotplug
769 * notifications.
770 * */
771 intel_hpd_init(dev_priv);
772 /* Config may have changed between suspend and resume */
773 drm_helper_hpd_irq_event(dev);
774
775 intel_opregion_init(dev);
776
777 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
778
779 mutex_lock(&dev_priv->modeset_restore_lock);
780 dev_priv->modeset_restore = MODESET_DONE;
781 mutex_unlock(&dev_priv->modeset_restore_lock);
782
783 intel_opregion_notify_adapter(dev, PCI_D0);
784
785 drm_kms_helper_poll_enable(dev);
786
787 enable_rpm_wakeref_asserts(dev_priv);
788
789 return 0;
790}
791
792static int i915_drm_resume_early(struct drm_device *dev)
793{
794 struct drm_i915_private *dev_priv = dev->dev_private;
795 int ret;
796
797 /*
798 * We have a resume ordering issue with the snd-hda driver also
799 * requiring our device to be power up. Due to the lack of a
800 * parent/child relationship we currently solve this with an early
801 * resume hook.
802 *
803 * FIXME: This should be solved with a special hdmi sink device or
804 * similar so that power domains can be employed.
805 */
806
807 /*
808 * Note that we need to set the power state explicitly, since we
809 * powered off the device during freeze and the PCI core won't power
810 * it back up for us during thaw. Powering off the device during
811 * freeze is not a hard requirement though, and during the
812 * suspend/resume phases the PCI core makes sure we get here with the
813 * device powered on. So in case we change our freeze logic and keep
814 * the device powered we can also remove the following set power state
815 * call.
816 */
817 ret = pci_set_power_state(dev->pdev, PCI_D0);
818 if (ret) {
819 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
820 goto out;
821 }
822
823 /*
824 * Note that pci_enable_device() first enables any parent bridge
825 * device and only then sets the power state for this device. The
826 * bridge enabling is a nop though, since bridge devices are resumed
827 * first. The order of enabling power and enabling the device is
828 * imposed by the PCI core as described above, so here we preserve the
829 * same order for the freeze/thaw phases.
830 *
831 * TODO: eventually we should remove pci_disable_device() /
832 * pci_enable_enable_device() from suspend/resume. Due to how they
833 * depend on the device enable refcount we can't anyway depend on them
834 * disabling/enabling the device.
835 */
836 if (pci_enable_device(dev->pdev)) {
837 ret = -EIO;
838 goto out;
839 }
840
841 pci_set_master(dev->pdev);
842
843 disable_rpm_wakeref_asserts(dev_priv);
844
845 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
846 ret = vlv_resume_prepare(dev_priv, false);
847 if (ret)
848 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
849 ret);
850
851 intel_uncore_early_sanitize(dev, true);
852
853 if (IS_BROXTON(dev))
854 ret = bxt_resume_prepare(dev_priv);
855 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
856 hsw_disable_pc8(dev_priv);
857
858 intel_uncore_sanitize(dev);
859
860 if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
861 intel_power_domains_init_hw(dev_priv, true);
862
863out:
864 dev_priv->suspended_to_idle = false;
865
866 enable_rpm_wakeref_asserts(dev_priv);
867
868 return ret;
869}
870
871int i915_resume_switcheroo(struct drm_device *dev)
872{
873 int ret;
874
875 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
876 return 0;
877
878 ret = i915_drm_resume_early(dev);
879 if (ret)
880 return ret;
881
882 return i915_drm_resume(dev);
883}
884
885/**
886 * i915_reset - reset chip after a hang
887 * @dev: drm device to reset
888 *
889 * Reset the chip. Useful if a hang is detected. Returns zero on successful
890 * reset or otherwise an error code.
891 *
892 * Procedure is fairly simple:
893 * - reset the chip using the reset reg
894 * - re-init context state
895 * - re-init hardware status page
896 * - re-init ring buffer
897 * - re-init interrupt state
898 * - re-init display
899 */
900int i915_reset(struct drm_device *dev)
901{
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 bool simulated;
904 int ret;
905
906 intel_reset_gt_powersave(dev);
907
908 mutex_lock(&dev->struct_mutex);
909
910 i915_gem_reset(dev);
911
912 simulated = dev_priv->gpu_error.stop_rings != 0;
913
914 ret = intel_gpu_reset(dev);
915
916 /* Also reset the gpu hangman. */
917 if (simulated) {
918 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
919 dev_priv->gpu_error.stop_rings = 0;
920 if (ret == -ENODEV) {
921 DRM_INFO("Reset not implemented, but ignoring "
922 "error for simulated gpu hangs\n");
923 ret = 0;
924 }
925 }
926
927 if (i915_stop_ring_allow_warn(dev_priv))
928 pr_notice("drm/i915: Resetting chip after gpu hang\n");
929
930 if (ret) {
931 DRM_ERROR("Failed to reset chip: %i\n", ret);
932 mutex_unlock(&dev->struct_mutex);
933 return ret;
934 }
935
936 intel_overlay_reset(dev_priv);
937
938 /* Ok, now get things going again... */
939
940 /*
941 * Everything depends on having the GTT running, so we need to start
942 * there. Fortunately we don't need to do this unless we reset the
943 * chip at a PCI level.
944 *
945 * Next we need to restore the context, but we don't use those
946 * yet either...
947 *
948 * Ring buffer needs to be re-initialized in the KMS case, or if X
949 * was running at the time of the reset (i.e. we weren't VT
950 * switched away).
951 */
952
953 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
954 dev_priv->gpu_error.reload_in_reset = true;
955
956 ret = i915_gem_init_hw(dev);
957
958 dev_priv->gpu_error.reload_in_reset = false;
959
960 mutex_unlock(&dev->struct_mutex);
961 if (ret) {
962 DRM_ERROR("Failed hw init on reset %d\n", ret);
963 return ret;
964 }
965
966 /*
967 * rps/rc6 re-init is necessary to restore state lost after the
968 * reset and the re-install of gt irqs. Skip for ironlake per
969 * previous concerns that it doesn't respond well to some forms
970 * of re-init after reset.
971 */
972 if (INTEL_INFO(dev)->gen > 5)
973 intel_enable_gt_powersave(dev);
974
975 return 0;
976}
977
978static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
979{
980 struct intel_device_info *intel_info =
981 (struct intel_device_info *) ent->driver_data;
982
983 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
984 DRM_INFO("This hardware requires preliminary hardware support.\n"
985 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
986 return -ENODEV;
987 }
988
989 /* Only bind to function 0 of the device. Early generations
990 * used function 1 as a placeholder for multi-head. This causes
991 * us confusion instead, especially on the systems where both
992 * functions have the same PCI-ID!
993 */
994 if (PCI_FUNC(pdev->devfn))
995 return -ENODEV;
996
997 /*
998 * apple-gmux is needed on dual GPU MacBook Pro
999 * to probe the panel if we're the inactive GPU.
1000 */
1001 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1002 apple_gmux_present() && pdev != vga_default_device() &&
1003 !vga_switcheroo_handler_flags())
1004 return -EPROBE_DEFER;
1005
1006 return drm_get_pci_dev(pdev, ent, &driver);
1007}
1008
1009static void
1010i915_pci_remove(struct pci_dev *pdev)
1011{
1012 struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014 drm_put_dev(dev);
1015}
1016
1017static int i915_pm_suspend(struct device *dev)
1018{
1019 struct pci_dev *pdev = to_pci_dev(dev);
1020 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1021
1022 if (!drm_dev || !drm_dev->dev_private) {
1023 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1024 return -ENODEV;
1025 }
1026
1027 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1028 return 0;
1029
1030 return i915_drm_suspend(drm_dev);
1031}
1032
1033static int i915_pm_suspend_late(struct device *dev)
1034{
1035 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1036
1037 /*
1038 * We have a suspend ordering issue with the snd-hda driver also
1039 * requiring our device to be power up. Due to the lack of a
1040 * parent/child relationship we currently solve this with an late
1041 * suspend hook.
1042 *
1043 * FIXME: This should be solved with a special hdmi sink device or
1044 * similar so that power domains can be employed.
1045 */
1046 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1047 return 0;
1048
1049 return i915_drm_suspend_late(drm_dev, false);
1050}
1051
1052static int i915_pm_poweroff_late(struct device *dev)
1053{
1054 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1055
1056 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1057 return 0;
1058
1059 return i915_drm_suspend_late(drm_dev, true);
1060}
1061
1062static int i915_pm_resume_early(struct device *dev)
1063{
1064 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1065
1066 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1067 return 0;
1068
1069 return i915_drm_resume_early(drm_dev);
1070}
1071
1072static int i915_pm_resume(struct device *dev)
1073{
1074 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1075
1076 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1077 return 0;
1078
1079 return i915_drm_resume(drm_dev);
1080}
1081
1082static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1083{
1084 hsw_enable_pc8(dev_priv);
1085
1086 return 0;
1087}
1088
1089static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1090{
1091 struct drm_device *dev = dev_priv->dev;
1092
1093 /* TODO: when DC5 support is added disable DC5 here. */
1094
1095 broxton_ddi_phy_uninit(dev);
1096 broxton_uninit_cdclk(dev);
1097 bxt_enable_dc9(dev_priv);
1098
1099 return 0;
1100}
1101
1102static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1103{
1104 struct drm_device *dev = dev_priv->dev;
1105
1106 /* TODO: when CSR FW support is added make sure the FW is loaded */
1107
1108 bxt_disable_dc9(dev_priv);
1109
1110 /*
1111 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1112 * is available.
1113 */
1114 broxton_init_cdclk(dev);
1115 broxton_ddi_phy_init(dev);
1116
1117 return 0;
1118}
1119
1120/*
1121 * Save all Gunit registers that may be lost after a D3 and a subsequent
1122 * S0i[R123] transition. The list of registers needing a save/restore is
1123 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1124 * registers in the following way:
1125 * - Driver: saved/restored by the driver
1126 * - Punit : saved/restored by the Punit firmware
1127 * - No, w/o marking: no need to save/restore, since the register is R/O or
1128 * used internally by the HW in a way that doesn't depend
1129 * keeping the content across a suspend/resume.
1130 * - Debug : used for debugging
1131 *
1132 * We save/restore all registers marked with 'Driver', with the following
1133 * exceptions:
1134 * - Registers out of use, including also registers marked with 'Debug'.
1135 * These have no effect on the driver's operation, so we don't save/restore
1136 * them to reduce the overhead.
1137 * - Registers that are fully setup by an initialization function called from
1138 * the resume path. For example many clock gating and RPS/RC6 registers.
1139 * - Registers that provide the right functionality with their reset defaults.
1140 *
1141 * TODO: Except for registers that based on the above 3 criteria can be safely
1142 * ignored, we save/restore all others, practically treating the HW context as
1143 * a black-box for the driver. Further investigation is needed to reduce the
1144 * saved/restored registers even further, by following the same 3 criteria.
1145 */
1146static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1147{
1148 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1149 int i;
1150
1151 /* GAM 0x4000-0x4770 */
1152 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1153 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1154 s->arb_mode = I915_READ(ARB_MODE);
1155 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1156 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1157
1158 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1159 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1160
1161 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1162 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1163
1164 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1165 s->ecochk = I915_READ(GAM_ECOCHK);
1166 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1167 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1168
1169 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1170
1171 /* MBC 0x9024-0x91D0, 0x8500 */
1172 s->g3dctl = I915_READ(VLV_G3DCTL);
1173 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1174 s->mbctl = I915_READ(GEN6_MBCTL);
1175
1176 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1177 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1178 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1179 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1180 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1181 s->rstctl = I915_READ(GEN6_RSTCTL);
1182 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1183
1184 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1185 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1186 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1187 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1188 s->ecobus = I915_READ(ECOBUS);
1189 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1190 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1191 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1192 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1193 s->rcedata = I915_READ(VLV_RCEDATA);
1194 s->spare2gh = I915_READ(VLV_SPAREG2H);
1195
1196 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1197 s->gt_imr = I915_READ(GTIMR);
1198 s->gt_ier = I915_READ(GTIER);
1199 s->pm_imr = I915_READ(GEN6_PMIMR);
1200 s->pm_ier = I915_READ(GEN6_PMIER);
1201
1202 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1203 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1204
1205 /* GT SA CZ domain, 0x100000-0x138124 */
1206 s->tilectl = I915_READ(TILECTL);
1207 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1208 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1209 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1210 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1211
1212 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1213 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1214 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1215 s->pcbr = I915_READ(VLV_PCBR);
1216 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1217
1218 /*
1219 * Not saving any of:
1220 * DFT, 0x9800-0x9EC0
1221 * SARB, 0xB000-0xB1FC
1222 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1223 * PCI CFG
1224 */
1225}
1226
1227static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1228{
1229 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1230 u32 val;
1231 int i;
1232
1233 /* GAM 0x4000-0x4770 */
1234 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1235 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1236 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1237 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1238 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1239
1240 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1241 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1242
1243 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1244 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1245
1246 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1247 I915_WRITE(GAM_ECOCHK, s->ecochk);
1248 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1249 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1250
1251 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1252
1253 /* MBC 0x9024-0x91D0, 0x8500 */
1254 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1255 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1256 I915_WRITE(GEN6_MBCTL, s->mbctl);
1257
1258 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1259 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1260 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1261 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1262 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1263 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1264 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1265
1266 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1267 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1268 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1269 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1270 I915_WRITE(ECOBUS, s->ecobus);
1271 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1272 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1273 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1274 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1275 I915_WRITE(VLV_RCEDATA, s->rcedata);
1276 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1277
1278 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1279 I915_WRITE(GTIMR, s->gt_imr);
1280 I915_WRITE(GTIER, s->gt_ier);
1281 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1282 I915_WRITE(GEN6_PMIER, s->pm_ier);
1283
1284 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1285 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1286
1287 /* GT SA CZ domain, 0x100000-0x138124 */
1288 I915_WRITE(TILECTL, s->tilectl);
1289 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1290 /*
1291 * Preserve the GT allow wake and GFX force clock bit, they are not
1292 * be restored, as they are used to control the s0ix suspend/resume
1293 * sequence by the caller.
1294 */
1295 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1296 val &= VLV_GTLC_ALLOWWAKEREQ;
1297 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1298 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1299
1300 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1301 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1302 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1303 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1304
1305 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1306
1307 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1308 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1309 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1310 I915_WRITE(VLV_PCBR, s->pcbr);
1311 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1312}
1313
1314int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1315{
1316 u32 val;
1317 int err;
1318
1319#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1320
1321 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1322 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1323 if (force_on)
1324 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1325 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1326
1327 if (!force_on)
1328 return 0;
1329
1330 err = wait_for(COND, 20);
1331 if (err)
1332 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1333 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1334
1335 return err;
1336#undef COND
1337}
1338
1339static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1340{
1341 u32 val;
1342 int err = 0;
1343
1344 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1345 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1346 if (allow)
1347 val |= VLV_GTLC_ALLOWWAKEREQ;
1348 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1349 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1350
1351#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1352 allow)
1353 err = wait_for(COND, 1);
1354 if (err)
1355 DRM_ERROR("timeout disabling GT waking\n");
1356 return err;
1357#undef COND
1358}
1359
1360static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1361 bool wait_for_on)
1362{
1363 u32 mask;
1364 u32 val;
1365 int err;
1366
1367 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1368 val = wait_for_on ? mask : 0;
1369#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1370 if (COND)
1371 return 0;
1372
1373 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1374 onoff(wait_for_on),
1375 I915_READ(VLV_GTLC_PW_STATUS));
1376
1377 /*
1378 * RC6 transitioning can be delayed up to 2 msec (see
1379 * valleyview_enable_rps), use 3 msec for safety.
1380 */
1381 err = wait_for(COND, 3);
1382 if (err)
1383 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1384 onoff(wait_for_on));
1385
1386 return err;
1387#undef COND
1388}
1389
1390static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1391{
1392 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1393 return;
1394
1395 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1396 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1397}
1398
1399static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1400{
1401 u32 mask;
1402 int err;
1403
1404 /*
1405 * Bspec defines the following GT well on flags as debug only, so
1406 * don't treat them as hard failures.
1407 */
1408 (void)vlv_wait_for_gt_wells(dev_priv, false);
1409
1410 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1411 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1412
1413 vlv_check_no_gt_access(dev_priv);
1414
1415 err = vlv_force_gfx_clock(dev_priv, true);
1416 if (err)
1417 goto err1;
1418
1419 err = vlv_allow_gt_wake(dev_priv, false);
1420 if (err)
1421 goto err2;
1422
1423 if (!IS_CHERRYVIEW(dev_priv->dev))
1424 vlv_save_gunit_s0ix_state(dev_priv);
1425
1426 err = vlv_force_gfx_clock(dev_priv, false);
1427 if (err)
1428 goto err2;
1429
1430 return 0;
1431
1432err2:
1433 /* For safety always re-enable waking and disable gfx clock forcing */
1434 vlv_allow_gt_wake(dev_priv, true);
1435err1:
1436 vlv_force_gfx_clock(dev_priv, false);
1437
1438 return err;
1439}
1440
1441static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1442 bool rpm_resume)
1443{
1444 struct drm_device *dev = dev_priv->dev;
1445 int err;
1446 int ret;
1447
1448 /*
1449 * If any of the steps fail just try to continue, that's the best we
1450 * can do at this point. Return the first error code (which will also
1451 * leave RPM permanently disabled).
1452 */
1453 ret = vlv_force_gfx_clock(dev_priv, true);
1454
1455 if (!IS_CHERRYVIEW(dev_priv->dev))
1456 vlv_restore_gunit_s0ix_state(dev_priv);
1457
1458 err = vlv_allow_gt_wake(dev_priv, true);
1459 if (!ret)
1460 ret = err;
1461
1462 err = vlv_force_gfx_clock(dev_priv, false);
1463 if (!ret)
1464 ret = err;
1465
1466 vlv_check_no_gt_access(dev_priv);
1467
1468 if (rpm_resume) {
1469 intel_init_clock_gating(dev);
1470 i915_gem_restore_fences(dev);
1471 }
1472
1473 return ret;
1474}
1475
1476static int intel_runtime_suspend(struct device *device)
1477{
1478 struct pci_dev *pdev = to_pci_dev(device);
1479 struct drm_device *dev = pci_get_drvdata(pdev);
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 int ret;
1482
1483 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1484 return -ENODEV;
1485
1486 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1487 return -ENODEV;
1488
1489 DRM_DEBUG_KMS("Suspending device\n");
1490
1491 /*
1492 * We could deadlock here in case another thread holding struct_mutex
1493 * calls RPM suspend concurrently, since the RPM suspend will wait
1494 * first for this RPM suspend to finish. In this case the concurrent
1495 * RPM resume will be followed by its RPM suspend counterpart. Still
1496 * for consistency return -EAGAIN, which will reschedule this suspend.
1497 */
1498 if (!mutex_trylock(&dev->struct_mutex)) {
1499 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1500 /*
1501 * Bump the expiration timestamp, otherwise the suspend won't
1502 * be rescheduled.
1503 */
1504 pm_runtime_mark_last_busy(device);
1505
1506 return -EAGAIN;
1507 }
1508
1509 disable_rpm_wakeref_asserts(dev_priv);
1510
1511 /*
1512 * We are safe here against re-faults, since the fault handler takes
1513 * an RPM reference.
1514 */
1515 i915_gem_release_all_mmaps(dev_priv);
1516 mutex_unlock(&dev->struct_mutex);
1517
1518 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1519
1520 intel_guc_suspend(dev);
1521
1522 intel_suspend_gt_powersave(dev);
1523 intel_runtime_pm_disable_interrupts(dev_priv);
1524
1525 ret = intel_suspend_complete(dev_priv);
1526 if (ret) {
1527 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1528 intel_runtime_pm_enable_interrupts(dev_priv);
1529
1530 enable_rpm_wakeref_asserts(dev_priv);
1531
1532 return ret;
1533 }
1534
1535 intel_uncore_forcewake_reset(dev, false);
1536
1537 enable_rpm_wakeref_asserts(dev_priv);
1538 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1539
1540 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1541 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1542
1543 dev_priv->pm.suspended = true;
1544
1545 /*
1546 * FIXME: We really should find a document that references the arguments
1547 * used below!
1548 */
1549 if (IS_BROADWELL(dev)) {
1550 /*
1551 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1552 * being detected, and the call we do at intel_runtime_resume()
1553 * won't be able to restore them. Since PCI_D3hot matches the
1554 * actual specification and appears to be working, use it.
1555 */
1556 intel_opregion_notify_adapter(dev, PCI_D3hot);
1557 } else {
1558 /*
1559 * current versions of firmware which depend on this opregion
1560 * notification have repurposed the D1 definition to mean
1561 * "runtime suspended" vs. what you would normally expect (D3)
1562 * to distinguish it from notifications that might be sent via
1563 * the suspend path.
1564 */
1565 intel_opregion_notify_adapter(dev, PCI_D1);
1566 }
1567
1568 assert_forcewakes_inactive(dev_priv);
1569
1570 DRM_DEBUG_KMS("Device suspended\n");
1571 return 0;
1572}
1573
1574static int intel_runtime_resume(struct device *device)
1575{
1576 struct pci_dev *pdev = to_pci_dev(device);
1577 struct drm_device *dev = pci_get_drvdata(pdev);
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 int ret = 0;
1580
1581 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1582 return -ENODEV;
1583
1584 DRM_DEBUG_KMS("Resuming device\n");
1585
1586 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1587 disable_rpm_wakeref_asserts(dev_priv);
1588
1589 intel_opregion_notify_adapter(dev, PCI_D0);
1590 dev_priv->pm.suspended = false;
1591 if (intel_uncore_unclaimed_mmio(dev_priv))
1592 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1593
1594 intel_guc_resume(dev);
1595
1596 if (IS_GEN6(dev_priv))
1597 intel_init_pch_refclk(dev);
1598
1599 if (IS_BROXTON(dev))
1600 ret = bxt_resume_prepare(dev_priv);
1601 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1602 hsw_disable_pc8(dev_priv);
1603 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1604 ret = vlv_resume_prepare(dev_priv, true);
1605
1606 /*
1607 * No point of rolling back things in case of an error, as the best
1608 * we can do is to hope that things will still work (and disable RPM).
1609 */
1610 i915_gem_init_swizzling(dev);
1611 gen6_update_ring_freq(dev);
1612
1613 intel_runtime_pm_enable_interrupts(dev_priv);
1614
1615 /*
1616 * On VLV/CHV display interrupts are part of the display
1617 * power well, so hpd is reinitialized from there. For
1618 * everyone else do it here.
1619 */
1620 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1621 intel_hpd_init(dev_priv);
1622
1623 intel_enable_gt_powersave(dev);
1624
1625 enable_rpm_wakeref_asserts(dev_priv);
1626
1627 if (ret)
1628 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1629 else
1630 DRM_DEBUG_KMS("Device resumed\n");
1631
1632 return ret;
1633}
1634
1635/*
1636 * This function implements common functionality of runtime and system
1637 * suspend sequence.
1638 */
1639static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1640{
1641 int ret;
1642
1643 if (IS_BROXTON(dev_priv))
1644 ret = bxt_suspend_complete(dev_priv);
1645 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1646 ret = hsw_suspend_complete(dev_priv);
1647 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1648 ret = vlv_suspend_complete(dev_priv);
1649 else
1650 ret = 0;
1651
1652 return ret;
1653}
1654
1655static const struct dev_pm_ops i915_pm_ops = {
1656 /*
1657 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1658 * PMSG_RESUME]
1659 */
1660 .suspend = i915_pm_suspend,
1661 .suspend_late = i915_pm_suspend_late,
1662 .resume_early = i915_pm_resume_early,
1663 .resume = i915_pm_resume,
1664
1665 /*
1666 * S4 event handlers
1667 * @freeze, @freeze_late : called (1) before creating the
1668 * hibernation image [PMSG_FREEZE] and
1669 * (2) after rebooting, before restoring
1670 * the image [PMSG_QUIESCE]
1671 * @thaw, @thaw_early : called (1) after creating the hibernation
1672 * image, before writing it [PMSG_THAW]
1673 * and (2) after failing to create or
1674 * restore the image [PMSG_RECOVER]
1675 * @poweroff, @poweroff_late: called after writing the hibernation
1676 * image, before rebooting [PMSG_HIBERNATE]
1677 * @restore, @restore_early : called after rebooting and restoring the
1678 * hibernation image [PMSG_RESTORE]
1679 */
1680 .freeze = i915_pm_suspend,
1681 .freeze_late = i915_pm_suspend_late,
1682 .thaw_early = i915_pm_resume_early,
1683 .thaw = i915_pm_resume,
1684 .poweroff = i915_pm_suspend,
1685 .poweroff_late = i915_pm_poweroff_late,
1686 .restore_early = i915_pm_resume_early,
1687 .restore = i915_pm_resume,
1688
1689 /* S0ix (via runtime suspend) event handlers */
1690 .runtime_suspend = intel_runtime_suspend,
1691 .runtime_resume = intel_runtime_resume,
1692};
1693
1694static const struct vm_operations_struct i915_gem_vm_ops = {
1695 .fault = i915_gem_fault,
1696 .open = drm_gem_vm_open,
1697 .close = drm_gem_vm_close,
1698};
1699
1700static const struct file_operations i915_driver_fops = {
1701 .owner = THIS_MODULE,
1702 .open = drm_open,
1703 .release = drm_release,
1704 .unlocked_ioctl = drm_ioctl,
1705 .mmap = drm_gem_mmap,
1706 .poll = drm_poll,
1707 .read = drm_read,
1708#ifdef CONFIG_COMPAT
1709 .compat_ioctl = i915_compat_ioctl,
1710#endif
1711 .llseek = noop_llseek,
1712};
1713
1714static struct drm_driver driver = {
1715 /* Don't use MTRRs here; the Xserver or userspace app should
1716 * deal with them for Intel hardware.
1717 */
1718 .driver_features =
1719 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1720 DRIVER_RENDER | DRIVER_MODESET,
1721 .load = i915_driver_load,
1722 .unload = i915_driver_unload,
1723 .open = i915_driver_open,
1724 .lastclose = i915_driver_lastclose,
1725 .preclose = i915_driver_preclose,
1726 .postclose = i915_driver_postclose,
1727 .set_busid = drm_pci_set_busid,
1728
1729#if defined(CONFIG_DEBUG_FS)
1730 .debugfs_init = i915_debugfs_init,
1731 .debugfs_cleanup = i915_debugfs_cleanup,
1732#endif
1733 .gem_free_object = i915_gem_free_object,
1734 .gem_vm_ops = &i915_gem_vm_ops,
1735
1736 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1737 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1738 .gem_prime_export = i915_gem_prime_export,
1739 .gem_prime_import = i915_gem_prime_import,
1740
1741 .dumb_create = i915_gem_dumb_create,
1742 .dumb_map_offset = i915_gem_mmap_gtt,
1743 .dumb_destroy = drm_gem_dumb_destroy,
1744 .ioctls = i915_ioctls,
1745 .fops = &i915_driver_fops,
1746 .name = DRIVER_NAME,
1747 .desc = DRIVER_DESC,
1748 .date = DRIVER_DATE,
1749 .major = DRIVER_MAJOR,
1750 .minor = DRIVER_MINOR,
1751 .patchlevel = DRIVER_PATCHLEVEL,
1752};
1753
1754static struct pci_driver i915_pci_driver = {
1755 .name = DRIVER_NAME,
1756 .id_table = pciidlist,
1757 .probe = i915_pci_probe,
1758 .remove = i915_pci_remove,
1759 .driver.pm = &i915_pm_ops,
1760};
1761
1762static int __init i915_init(void)
1763{
1764 driver.num_ioctls = i915_max_ioctl;
1765
1766 /*
1767 * Enable KMS by default, unless explicitly overriden by
1768 * either the i915.modeset prarameter or by the
1769 * vga_text_mode_force boot option.
1770 */
1771
1772 if (i915.modeset == 0)
1773 driver.driver_features &= ~DRIVER_MODESET;
1774
1775#ifdef CONFIG_VGA_CONSOLE
1776 if (vgacon_text_force() && i915.modeset == -1)
1777 driver.driver_features &= ~DRIVER_MODESET;
1778#endif
1779
1780 if (!(driver.driver_features & DRIVER_MODESET)) {
1781 /* Silently fail loading to not upset userspace. */
1782 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1783 return 0;
1784 }
1785
1786 if (i915.nuclear_pageflip)
1787 driver.driver_features |= DRIVER_ATOMIC;
1788
1789 return drm_pci_init(&driver, &i915_pci_driver);
1790}
1791
1792static void __exit i915_exit(void)
1793{
1794 if (!(driver.driver_features & DRIVER_MODESET))
1795 return; /* Never loaded a driver. */
1796
1797 drm_pci_exit(&driver, &i915_pci_driver);
1798}
1799
1800module_init(i915_init);
1801module_exit(i915_exit);
1802
1803MODULE_AUTHOR("Tungsten Graphics, Inc.");
1804MODULE_AUTHOR("Intel Corporation");
1805
1806MODULE_DESCRIPTION(DRIVER_DESC);
1807MODULE_LICENSE("GPL and additional rights");
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/acpi.h>
31#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
45#include <drm/drm_crtc_helper.h>
46#include <drm/drm_atomic_helper.h>
47#include <drm/i915_drm.h>
48
49#include "i915_drv.h"
50#include "i915_trace.h"
51#include "i915_pmu.h"
52#include "i915_query.h"
53#include "i915_vgpu.h"
54#include "intel_drv.h"
55#include "intel_uc.h"
56
57static struct drm_driver driver;
58
59#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60static unsigned int i915_load_fail_count;
61
62bool __i915_inject_load_failure(const char *func, int line)
63{
64 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
65 return false;
66
67 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
68 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
69 i915_modparams.inject_load_failure, func, line);
70 return true;
71 }
72
73 return false;
74}
75#endif
76
77#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
78#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
79 "providing the dmesg log by booting with drm.debug=0xf"
80
81void
82__i915_printk(struct drm_i915_private *dev_priv, const char *level,
83 const char *fmt, ...)
84{
85 static bool shown_bug_once;
86 struct device *kdev = dev_priv->drm.dev;
87 bool is_error = level[1] <= KERN_ERR[1];
88 bool is_debug = level[1] == KERN_DEBUG[1];
89 struct va_format vaf;
90 va_list args;
91
92 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
93 return;
94
95 va_start(args, fmt);
96
97 vaf.fmt = fmt;
98 vaf.va = &args;
99
100 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
101 __builtin_return_address(0), &vaf);
102
103 if (is_error && !shown_bug_once) {
104 dev_notice(kdev, "%s", FDO_BUG_MSG);
105 shown_bug_once = true;
106 }
107
108 va_end(args);
109}
110
111static bool i915_error_injected(struct drm_i915_private *dev_priv)
112{
113#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
114 return i915_modparams.inject_load_failure &&
115 i915_load_fail_count == i915_modparams.inject_load_failure;
116#else
117 return false;
118#endif
119}
120
121#define i915_load_error(dev_priv, fmt, ...) \
122 __i915_printk(dev_priv, \
123 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
124 fmt, ##__VA_ARGS__)
125
126/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
127static enum intel_pch
128intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
129{
130 switch (id) {
131 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
132 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
133 WARN_ON(!IS_GEN5(dev_priv));
134 return PCH_IBX;
135 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
136 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
137 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
138 return PCH_CPT;
139 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
140 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
141 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
142 /* PantherPoint is CPT compatible */
143 return PCH_CPT;
144 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
145 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
146 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
147 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
148 return PCH_LPT;
149 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
150 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
151 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
152 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
153 return PCH_LPT;
154 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
155 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
156 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
157 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
158 /* WildcatPoint is LPT compatible */
159 return PCH_LPT;
160 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
161 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
162 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
163 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
164 /* WildcatPoint is LPT compatible */
165 return PCH_LPT;
166 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
167 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
168 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
169 return PCH_SPT;
170 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
171 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
172 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
173 return PCH_SPT;
174 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
175 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
176 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
177 !IS_COFFEELAKE(dev_priv));
178 return PCH_KBP;
179 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
180 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
181 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
182 return PCH_CNP;
183 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
184 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
185 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
186 return PCH_CNP;
187 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
188 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
189 WARN_ON(!IS_ICELAKE(dev_priv));
190 return PCH_ICP;
191 default:
192 return PCH_NONE;
193 }
194}
195
196static bool intel_is_virt_pch(unsigned short id,
197 unsigned short svendor, unsigned short sdevice)
198{
199 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
200 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
201 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
202 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
203 sdevice == PCI_SUBDEVICE_ID_QEMU));
204}
205
206static unsigned short
207intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
208{
209 unsigned short id = 0;
210
211 /*
212 * In a virtualized passthrough environment we can be in a
213 * setup where the ISA bridge is not able to be passed through.
214 * In this case, a south bridge can be emulated and we have to
215 * make an educated guess as to which PCH is really there.
216 */
217
218 if (IS_GEN5(dev_priv))
219 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
220 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
221 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
222 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
223 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
224 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
225 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
226 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
227 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
228 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
229 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
230
231 if (id)
232 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
233 else
234 DRM_DEBUG_KMS("Assuming no PCH\n");
235
236 return id;
237}
238
239static void intel_detect_pch(struct drm_i915_private *dev_priv)
240{
241 struct pci_dev *pch = NULL;
242
243 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
244 * (which really amounts to a PCH but no South Display).
245 */
246 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
247 dev_priv->pch_type = PCH_NOP;
248 return;
249 }
250
251 /*
252 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
253 * make graphics device passthrough work easy for VMM, that only
254 * need to expose ISA bridge to let driver know the real hardware
255 * underneath. This is a requirement from virtualization team.
256 *
257 * In some virtualized environments (e.g. XEN), there is irrelevant
258 * ISA bridge in the system. To work reliably, we should scan trhough
259 * all the ISA bridge devices and check for the first match, instead
260 * of only checking the first one.
261 */
262 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
263 unsigned short id;
264 enum intel_pch pch_type;
265
266 if (pch->vendor != PCI_VENDOR_ID_INTEL)
267 continue;
268
269 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
270
271 pch_type = intel_pch_type(dev_priv, id);
272 if (pch_type != PCH_NONE) {
273 dev_priv->pch_type = pch_type;
274 dev_priv->pch_id = id;
275 break;
276 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
277 pch->subsystem_device)) {
278 id = intel_virt_detect_pch(dev_priv);
279 if (id) {
280 pch_type = intel_pch_type(dev_priv, id);
281 if (WARN_ON(pch_type == PCH_NONE))
282 pch_type = PCH_NOP;
283 } else {
284 pch_type = PCH_NOP;
285 }
286 dev_priv->pch_type = pch_type;
287 dev_priv->pch_id = id;
288 break;
289 }
290 }
291 if (!pch)
292 DRM_DEBUG_KMS("No PCH found.\n");
293
294 pci_dev_put(pch);
295}
296
297static int i915_getparam_ioctl(struct drm_device *dev, void *data,
298 struct drm_file *file_priv)
299{
300 struct drm_i915_private *dev_priv = to_i915(dev);
301 struct pci_dev *pdev = dev_priv->drm.pdev;
302 drm_i915_getparam_t *param = data;
303 int value;
304
305 switch (param->param) {
306 case I915_PARAM_IRQ_ACTIVE:
307 case I915_PARAM_ALLOW_BATCHBUFFER:
308 case I915_PARAM_LAST_DISPATCH:
309 case I915_PARAM_HAS_EXEC_CONSTANTS:
310 /* Reject all old ums/dri params. */
311 return -ENODEV;
312 case I915_PARAM_CHIPSET_ID:
313 value = pdev->device;
314 break;
315 case I915_PARAM_REVISION:
316 value = pdev->revision;
317 break;
318 case I915_PARAM_NUM_FENCES_AVAIL:
319 value = dev_priv->num_fence_regs;
320 break;
321 case I915_PARAM_HAS_OVERLAY:
322 value = dev_priv->overlay ? 1 : 0;
323 break;
324 case I915_PARAM_HAS_BSD:
325 value = !!dev_priv->engine[VCS];
326 break;
327 case I915_PARAM_HAS_BLT:
328 value = !!dev_priv->engine[BCS];
329 break;
330 case I915_PARAM_HAS_VEBOX:
331 value = !!dev_priv->engine[VECS];
332 break;
333 case I915_PARAM_HAS_BSD2:
334 value = !!dev_priv->engine[VCS2];
335 break;
336 case I915_PARAM_HAS_LLC:
337 value = HAS_LLC(dev_priv);
338 break;
339 case I915_PARAM_HAS_WT:
340 value = HAS_WT(dev_priv);
341 break;
342 case I915_PARAM_HAS_ALIASING_PPGTT:
343 value = USES_PPGTT(dev_priv);
344 break;
345 case I915_PARAM_HAS_SEMAPHORES:
346 value = HAS_LEGACY_SEMAPHORES(dev_priv);
347 break;
348 case I915_PARAM_HAS_SECURE_BATCHES:
349 value = capable(CAP_SYS_ADMIN);
350 break;
351 case I915_PARAM_CMD_PARSER_VERSION:
352 value = i915_cmd_parser_get_version(dev_priv);
353 break;
354 case I915_PARAM_SUBSLICE_TOTAL:
355 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
356 if (!value)
357 return -ENODEV;
358 break;
359 case I915_PARAM_EU_TOTAL:
360 value = INTEL_INFO(dev_priv)->sseu.eu_total;
361 if (!value)
362 return -ENODEV;
363 break;
364 case I915_PARAM_HAS_GPU_RESET:
365 value = i915_modparams.enable_hangcheck &&
366 intel_has_gpu_reset(dev_priv);
367 if (value && intel_has_reset_engine(dev_priv))
368 value = 2;
369 break;
370 case I915_PARAM_HAS_RESOURCE_STREAMER:
371 value = HAS_RESOURCE_STREAMER(dev_priv);
372 break;
373 case I915_PARAM_HAS_POOLED_EU:
374 value = HAS_POOLED_EU(dev_priv);
375 break;
376 case I915_PARAM_MIN_EU_IN_POOL:
377 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
378 break;
379 case I915_PARAM_HUC_STATUS:
380 intel_runtime_pm_get(dev_priv);
381 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
382 intel_runtime_pm_put(dev_priv);
383 break;
384 case I915_PARAM_MMAP_GTT_VERSION:
385 /* Though we've started our numbering from 1, and so class all
386 * earlier versions as 0, in effect their value is undefined as
387 * the ioctl will report EINVAL for the unknown param!
388 */
389 value = i915_gem_mmap_gtt_version();
390 break;
391 case I915_PARAM_HAS_SCHEDULER:
392 value = dev_priv->caps.scheduler;
393 break;
394
395 case I915_PARAM_MMAP_VERSION:
396 /* Remember to bump this if the version changes! */
397 case I915_PARAM_HAS_GEM:
398 case I915_PARAM_HAS_PAGEFLIPPING:
399 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
400 case I915_PARAM_HAS_RELAXED_FENCING:
401 case I915_PARAM_HAS_COHERENT_RINGS:
402 case I915_PARAM_HAS_RELAXED_DELTA:
403 case I915_PARAM_HAS_GEN7_SOL_RESET:
404 case I915_PARAM_HAS_WAIT_TIMEOUT:
405 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
406 case I915_PARAM_HAS_PINNED_BATCHES:
407 case I915_PARAM_HAS_EXEC_NO_RELOC:
408 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
409 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
410 case I915_PARAM_HAS_EXEC_SOFTPIN:
411 case I915_PARAM_HAS_EXEC_ASYNC:
412 case I915_PARAM_HAS_EXEC_FENCE:
413 case I915_PARAM_HAS_EXEC_CAPTURE:
414 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
415 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
416 /* For the time being all of these are always true;
417 * if some supported hardware does not have one of these
418 * features this value needs to be provided from
419 * INTEL_INFO(), a feature macro, or similar.
420 */
421 value = 1;
422 break;
423 case I915_PARAM_HAS_CONTEXT_ISOLATION:
424 value = intel_engines_has_context_isolation(dev_priv);
425 break;
426 case I915_PARAM_SLICE_MASK:
427 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
428 if (!value)
429 return -ENODEV;
430 break;
431 case I915_PARAM_SUBSLICE_MASK:
432 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
433 if (!value)
434 return -ENODEV;
435 break;
436 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
437 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
438 break;
439 default:
440 DRM_DEBUG("Unknown parameter %d\n", param->param);
441 return -EINVAL;
442 }
443
444 if (put_user(value, param->value))
445 return -EFAULT;
446
447 return 0;
448}
449
450static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
451{
452 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
453
454 dev_priv->bridge_dev =
455 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
456 if (!dev_priv->bridge_dev) {
457 DRM_ERROR("bridge device not found\n");
458 return -1;
459 }
460 return 0;
461}
462
463/* Allocate space for the MCH regs if needed, return nonzero on error */
464static int
465intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
466{
467 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
468 u32 temp_lo, temp_hi = 0;
469 u64 mchbar_addr;
470 int ret;
471
472 if (INTEL_GEN(dev_priv) >= 4)
473 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
474 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
475 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
476
477 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
478#ifdef CONFIG_PNP
479 if (mchbar_addr &&
480 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
481 return 0;
482#endif
483
484 /* Get some space for it */
485 dev_priv->mch_res.name = "i915 MCHBAR";
486 dev_priv->mch_res.flags = IORESOURCE_MEM;
487 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
488 &dev_priv->mch_res,
489 MCHBAR_SIZE, MCHBAR_SIZE,
490 PCIBIOS_MIN_MEM,
491 0, pcibios_align_resource,
492 dev_priv->bridge_dev);
493 if (ret) {
494 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
495 dev_priv->mch_res.start = 0;
496 return ret;
497 }
498
499 if (INTEL_GEN(dev_priv) >= 4)
500 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
501 upper_32_bits(dev_priv->mch_res.start));
502
503 pci_write_config_dword(dev_priv->bridge_dev, reg,
504 lower_32_bits(dev_priv->mch_res.start));
505 return 0;
506}
507
508/* Setup MCHBAR if possible, return true if we should disable it again */
509static void
510intel_setup_mchbar(struct drm_i915_private *dev_priv)
511{
512 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
513 u32 temp;
514 bool enabled;
515
516 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
517 return;
518
519 dev_priv->mchbar_need_disable = false;
520
521 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
522 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
523 enabled = !!(temp & DEVEN_MCHBAR_EN);
524 } else {
525 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
526 enabled = temp & 1;
527 }
528
529 /* If it's already enabled, don't have to do anything */
530 if (enabled)
531 return;
532
533 if (intel_alloc_mchbar_resource(dev_priv))
534 return;
535
536 dev_priv->mchbar_need_disable = true;
537
538 /* Space is allocated or reserved, so enable it. */
539 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
540 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
541 temp | DEVEN_MCHBAR_EN);
542 } else {
543 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
544 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
545 }
546}
547
548static void
549intel_teardown_mchbar(struct drm_i915_private *dev_priv)
550{
551 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
552
553 if (dev_priv->mchbar_need_disable) {
554 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
555 u32 deven_val;
556
557 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
558 &deven_val);
559 deven_val &= ~DEVEN_MCHBAR_EN;
560 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
561 deven_val);
562 } else {
563 u32 mchbar_val;
564
565 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
566 &mchbar_val);
567 mchbar_val &= ~1;
568 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
569 mchbar_val);
570 }
571 }
572
573 if (dev_priv->mch_res.start)
574 release_resource(&dev_priv->mch_res);
575}
576
577/* true = enable decode, false = disable decoder */
578static unsigned int i915_vga_set_decode(void *cookie, bool state)
579{
580 struct drm_i915_private *dev_priv = cookie;
581
582 intel_modeset_vga_set_state(dev_priv, state);
583 if (state)
584 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
585 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
586 else
587 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
588}
589
590static int i915_resume_switcheroo(struct drm_device *dev);
591static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
592
593static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
594{
595 struct drm_device *dev = pci_get_drvdata(pdev);
596 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
597
598 if (state == VGA_SWITCHEROO_ON) {
599 pr_info("switched on\n");
600 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
601 /* i915 resume handler doesn't set to D0 */
602 pci_set_power_state(pdev, PCI_D0);
603 i915_resume_switcheroo(dev);
604 dev->switch_power_state = DRM_SWITCH_POWER_ON;
605 } else {
606 pr_info("switched off\n");
607 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
608 i915_suspend_switcheroo(dev, pmm);
609 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
610 }
611}
612
613static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
614{
615 struct drm_device *dev = pci_get_drvdata(pdev);
616
617 /*
618 * FIXME: open_count is protected by drm_global_mutex but that would lead to
619 * locking inversion with the driver load path. And the access here is
620 * completely racy anyway. So don't bother with locking for now.
621 */
622 return dev->open_count == 0;
623}
624
625static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
626 .set_gpu_state = i915_switcheroo_set_state,
627 .reprobe = NULL,
628 .can_switch = i915_switcheroo_can_switch,
629};
630
631static void i915_gem_fini(struct drm_i915_private *dev_priv)
632{
633 /* Flush any outstanding unpin_work. */
634 i915_gem_drain_workqueue(dev_priv);
635
636 mutex_lock(&dev_priv->drm.struct_mutex);
637 intel_uc_fini_hw(dev_priv);
638 intel_uc_fini(dev_priv);
639 i915_gem_cleanup_engines(dev_priv);
640 i915_gem_contexts_fini(dev_priv);
641 mutex_unlock(&dev_priv->drm.struct_mutex);
642
643 intel_uc_fini_misc(dev_priv);
644 i915_gem_cleanup_userptr(dev_priv);
645
646 i915_gem_drain_freed_objects(dev_priv);
647
648 WARN_ON(!list_empty(&dev_priv->contexts.list));
649}
650
651static int i915_load_modeset_init(struct drm_device *dev)
652{
653 struct drm_i915_private *dev_priv = to_i915(dev);
654 struct pci_dev *pdev = dev_priv->drm.pdev;
655 int ret;
656
657 if (i915_inject_load_failure())
658 return -ENODEV;
659
660 intel_bios_init(dev_priv);
661
662 /* If we have > 1 VGA cards, then we need to arbitrate access
663 * to the common VGA resources.
664 *
665 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
666 * then we do not take part in VGA arbitration and the
667 * vga_client_register() fails with -ENODEV.
668 */
669 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
670 if (ret && ret != -ENODEV)
671 goto out;
672
673 intel_register_dsm_handler();
674
675 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
676 if (ret)
677 goto cleanup_vga_client;
678
679 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
680 intel_update_rawclk(dev_priv);
681
682 intel_power_domains_init_hw(dev_priv, false);
683
684 intel_csr_ucode_init(dev_priv);
685
686 ret = intel_irq_install(dev_priv);
687 if (ret)
688 goto cleanup_csr;
689
690 intel_setup_gmbus(dev_priv);
691
692 /* Important: The output setup functions called by modeset_init need
693 * working irqs for e.g. gmbus and dp aux transfers. */
694 ret = intel_modeset_init(dev);
695 if (ret)
696 goto cleanup_irq;
697
698 intel_uc_init_fw(dev_priv);
699
700 ret = i915_gem_init(dev_priv);
701 if (ret)
702 goto cleanup_uc;
703
704 intel_setup_overlay(dev_priv);
705
706 if (INTEL_INFO(dev_priv)->num_pipes == 0)
707 return 0;
708
709 ret = intel_fbdev_init(dev);
710 if (ret)
711 goto cleanup_gem;
712
713 /* Only enable hotplug handling once the fbdev is fully set up. */
714 intel_hpd_init(dev_priv);
715
716 return 0;
717
718cleanup_gem:
719 if (i915_gem_suspend(dev_priv))
720 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
721 i915_gem_fini(dev_priv);
722cleanup_uc:
723 intel_uc_fini_fw(dev_priv);
724cleanup_irq:
725 drm_irq_uninstall(dev);
726 intel_teardown_gmbus(dev_priv);
727cleanup_csr:
728 intel_csr_ucode_fini(dev_priv);
729 intel_power_domains_fini(dev_priv);
730 vga_switcheroo_unregister_client(pdev);
731cleanup_vga_client:
732 vga_client_register(pdev, NULL, NULL, NULL);
733out:
734 return ret;
735}
736
737static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
738{
739 struct apertures_struct *ap;
740 struct pci_dev *pdev = dev_priv->drm.pdev;
741 struct i915_ggtt *ggtt = &dev_priv->ggtt;
742 bool primary;
743 int ret;
744
745 ap = alloc_apertures(1);
746 if (!ap)
747 return -ENOMEM;
748
749 ap->ranges[0].base = ggtt->gmadr.start;
750 ap->ranges[0].size = ggtt->mappable_end;
751
752 primary =
753 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
754
755 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
756
757 kfree(ap);
758
759 return ret;
760}
761
762#if !defined(CONFIG_VGA_CONSOLE)
763static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
764{
765 return 0;
766}
767#elif !defined(CONFIG_DUMMY_CONSOLE)
768static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
769{
770 return -ENODEV;
771}
772#else
773static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
774{
775 int ret = 0;
776
777 DRM_INFO("Replacing VGA console driver\n");
778
779 console_lock();
780 if (con_is_bound(&vga_con))
781 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
782 if (ret == 0) {
783 ret = do_unregister_con_driver(&vga_con);
784
785 /* Ignore "already unregistered". */
786 if (ret == -ENODEV)
787 ret = 0;
788 }
789 console_unlock();
790
791 return ret;
792}
793#endif
794
795static void intel_init_dpio(struct drm_i915_private *dev_priv)
796{
797 /*
798 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
799 * CHV x1 PHY (DP/HDMI D)
800 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
801 */
802 if (IS_CHERRYVIEW(dev_priv)) {
803 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
804 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
805 } else if (IS_VALLEYVIEW(dev_priv)) {
806 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
807 }
808}
809
810static int i915_workqueues_init(struct drm_i915_private *dev_priv)
811{
812 /*
813 * The i915 workqueue is primarily used for batched retirement of
814 * requests (and thus managing bo) once the task has been completed
815 * by the GPU. i915_retire_requests() is called directly when we
816 * need high-priority retirement, such as waiting for an explicit
817 * bo.
818 *
819 * It is also used for periodic low-priority events, such as
820 * idle-timers and recording error state.
821 *
822 * All tasks on the workqueue are expected to acquire the dev mutex
823 * so there is no point in running more than one instance of the
824 * workqueue at any time. Use an ordered one.
825 */
826 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
827 if (dev_priv->wq == NULL)
828 goto out_err;
829
830 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
831 if (dev_priv->hotplug.dp_wq == NULL)
832 goto out_free_wq;
833
834 return 0;
835
836out_free_wq:
837 destroy_workqueue(dev_priv->wq);
838out_err:
839 DRM_ERROR("Failed to allocate workqueues.\n");
840
841 return -ENOMEM;
842}
843
844static void i915_engines_cleanup(struct drm_i915_private *i915)
845{
846 struct intel_engine_cs *engine;
847 enum intel_engine_id id;
848
849 for_each_engine(engine, i915, id)
850 kfree(engine);
851}
852
853static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
854{
855 destroy_workqueue(dev_priv->hotplug.dp_wq);
856 destroy_workqueue(dev_priv->wq);
857}
858
859/*
860 * We don't keep the workarounds for pre-production hardware, so we expect our
861 * driver to fail on these machines in one way or another. A little warning on
862 * dmesg may help both the user and the bug triagers.
863 *
864 * Our policy for removing pre-production workarounds is to keep the
865 * current gen workarounds as a guide to the bring-up of the next gen
866 * (workarounds have a habit of persisting!). Anything older than that
867 * should be removed along with the complications they introduce.
868 */
869static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
870{
871 bool pre = false;
872
873 pre |= IS_HSW_EARLY_SDV(dev_priv);
874 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
875 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
876
877 if (pre) {
878 DRM_ERROR("This is a pre-production stepping. "
879 "It may not be fully functional.\n");
880 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
881 }
882}
883
884/**
885 * i915_driver_init_early - setup state not requiring device access
886 * @dev_priv: device private
887 * @ent: the matching pci_device_id
888 *
889 * Initialize everything that is a "SW-only" state, that is state not
890 * requiring accessing the device or exposing the driver via kernel internal
891 * or userspace interfaces. Example steps belonging here: lock initialization,
892 * system memory allocation, setting up device specific attributes and
893 * function hooks not requiring accessing the device.
894 */
895static int i915_driver_init_early(struct drm_i915_private *dev_priv,
896 const struct pci_device_id *ent)
897{
898 const struct intel_device_info *match_info =
899 (struct intel_device_info *)ent->driver_data;
900 struct intel_device_info *device_info;
901 int ret = 0;
902
903 if (i915_inject_load_failure())
904 return -ENODEV;
905
906 /* Setup the write-once "constant" device info */
907 device_info = mkwrite_device_info(dev_priv);
908 memcpy(device_info, match_info, sizeof(*device_info));
909 device_info->device_id = dev_priv->drm.pdev->device;
910
911 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
912 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
913 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
914 spin_lock_init(&dev_priv->irq_lock);
915 spin_lock_init(&dev_priv->gpu_error.lock);
916 mutex_init(&dev_priv->backlight_lock);
917 spin_lock_init(&dev_priv->uncore.lock);
918
919 mutex_init(&dev_priv->sb_lock);
920 mutex_init(&dev_priv->modeset_restore_lock);
921 mutex_init(&dev_priv->av_mutex);
922 mutex_init(&dev_priv->wm.wm_mutex);
923 mutex_init(&dev_priv->pps_mutex);
924
925 intel_uc_init_early(dev_priv);
926 i915_memcpy_init_early(dev_priv);
927
928 ret = i915_workqueues_init(dev_priv);
929 if (ret < 0)
930 goto err_engines;
931
932 /* This must be called before any calls to HAS_PCH_* */
933 intel_detect_pch(dev_priv);
934
935 intel_pm_setup(dev_priv);
936 intel_init_dpio(dev_priv);
937 intel_power_domains_init(dev_priv);
938 intel_irq_init(dev_priv);
939 intel_hangcheck_init(dev_priv);
940 intel_init_display_hooks(dev_priv);
941 intel_init_clock_gating_hooks(dev_priv);
942 intel_init_audio_hooks(dev_priv);
943 ret = i915_gem_load_init(dev_priv);
944 if (ret < 0)
945 goto err_irq;
946
947 intel_display_crc_init(dev_priv);
948
949 intel_detect_preproduction_hw(dev_priv);
950
951 return 0;
952
953err_irq:
954 intel_irq_fini(dev_priv);
955 i915_workqueues_cleanup(dev_priv);
956err_engines:
957 i915_engines_cleanup(dev_priv);
958 return ret;
959}
960
961/**
962 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
963 * @dev_priv: device private
964 */
965static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
966{
967 i915_gem_load_cleanup(dev_priv);
968 intel_irq_fini(dev_priv);
969 i915_workqueues_cleanup(dev_priv);
970 i915_engines_cleanup(dev_priv);
971}
972
973static int i915_mmio_setup(struct drm_i915_private *dev_priv)
974{
975 struct pci_dev *pdev = dev_priv->drm.pdev;
976 int mmio_bar;
977 int mmio_size;
978
979 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
980 /*
981 * Before gen4, the registers and the GTT are behind different BARs.
982 * However, from gen4 onwards, the registers and the GTT are shared
983 * in the same BAR, so we want to restrict this ioremap from
984 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
985 * the register BAR remains the same size for all the earlier
986 * generations up to Ironlake.
987 */
988 if (INTEL_GEN(dev_priv) < 5)
989 mmio_size = 512 * 1024;
990 else
991 mmio_size = 2 * 1024 * 1024;
992 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
993 if (dev_priv->regs == NULL) {
994 DRM_ERROR("failed to map registers\n");
995
996 return -EIO;
997 }
998
999 /* Try to make sure MCHBAR is enabled before poking at it */
1000 intel_setup_mchbar(dev_priv);
1001
1002 return 0;
1003}
1004
1005static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1006{
1007 struct pci_dev *pdev = dev_priv->drm.pdev;
1008
1009 intel_teardown_mchbar(dev_priv);
1010 pci_iounmap(pdev, dev_priv->regs);
1011}
1012
1013/**
1014 * i915_driver_init_mmio - setup device MMIO
1015 * @dev_priv: device private
1016 *
1017 * Setup minimal device state necessary for MMIO accesses later in the
1018 * initialization sequence. The setup here should avoid any other device-wide
1019 * side effects or exposing the driver via kernel internal or user space
1020 * interfaces.
1021 */
1022static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1023{
1024 int ret;
1025
1026 if (i915_inject_load_failure())
1027 return -ENODEV;
1028
1029 if (i915_get_bridge_dev(dev_priv))
1030 return -EIO;
1031
1032 ret = i915_mmio_setup(dev_priv);
1033 if (ret < 0)
1034 goto err_bridge;
1035
1036 intel_uncore_init(dev_priv);
1037
1038 intel_uc_init_mmio(dev_priv);
1039
1040 ret = intel_engines_init_mmio(dev_priv);
1041 if (ret)
1042 goto err_uncore;
1043
1044 i915_gem_init_mmio(dev_priv);
1045
1046 return 0;
1047
1048err_uncore:
1049 intel_uncore_fini(dev_priv);
1050err_bridge:
1051 pci_dev_put(dev_priv->bridge_dev);
1052
1053 return ret;
1054}
1055
1056/**
1057 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1058 * @dev_priv: device private
1059 */
1060static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1061{
1062 intel_uncore_fini(dev_priv);
1063 i915_mmio_cleanup(dev_priv);
1064 pci_dev_put(dev_priv->bridge_dev);
1065}
1066
1067static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1068{
1069 /*
1070 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1071 * user's requested state against the hardware/driver capabilities. We
1072 * do this now so that we can print out any log messages once rather
1073 * than every time we check intel_enable_ppgtt().
1074 */
1075 i915_modparams.enable_ppgtt =
1076 intel_sanitize_enable_ppgtt(dev_priv,
1077 i915_modparams.enable_ppgtt);
1078 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1079
1080 intel_uc_sanitize_options(dev_priv);
1081
1082 intel_gvt_sanitize_options(dev_priv);
1083}
1084
1085/**
1086 * i915_driver_init_hw - setup state requiring device access
1087 * @dev_priv: device private
1088 *
1089 * Setup state that requires accessing the device, but doesn't require
1090 * exposing the driver via kernel internal or userspace interfaces.
1091 */
1092static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1093{
1094 struct pci_dev *pdev = dev_priv->drm.pdev;
1095 int ret;
1096
1097 if (i915_inject_load_failure())
1098 return -ENODEV;
1099
1100 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1101
1102 intel_sanitize_options(dev_priv);
1103
1104 i915_perf_init(dev_priv);
1105
1106 ret = i915_ggtt_probe_hw(dev_priv);
1107 if (ret)
1108 goto err_perf;
1109
1110 /*
1111 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1112 * otherwise the vga fbdev driver falls over.
1113 */
1114 ret = i915_kick_out_firmware_fb(dev_priv);
1115 if (ret) {
1116 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1117 goto err_ggtt;
1118 }
1119
1120 ret = i915_kick_out_vgacon(dev_priv);
1121 if (ret) {
1122 DRM_ERROR("failed to remove conflicting VGA console\n");
1123 goto err_ggtt;
1124 }
1125
1126 ret = i915_ggtt_init_hw(dev_priv);
1127 if (ret)
1128 goto err_ggtt;
1129
1130 ret = i915_ggtt_enable_hw(dev_priv);
1131 if (ret) {
1132 DRM_ERROR("failed to enable GGTT\n");
1133 goto err_ggtt;
1134 }
1135
1136 pci_set_master(pdev);
1137
1138 /* overlay on gen2 is broken and can't address above 1G */
1139 if (IS_GEN2(dev_priv)) {
1140 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1141 if (ret) {
1142 DRM_ERROR("failed to set DMA mask\n");
1143
1144 goto err_ggtt;
1145 }
1146 }
1147
1148 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1149 * using 32bit addressing, overwriting memory if HWS is located
1150 * above 4GB.
1151 *
1152 * The documentation also mentions an issue with undefined
1153 * behaviour if any general state is accessed within a page above 4GB,
1154 * which also needs to be handled carefully.
1155 */
1156 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1157 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1158
1159 if (ret) {
1160 DRM_ERROR("failed to set DMA mask\n");
1161
1162 goto err_ggtt;
1163 }
1164 }
1165
1166 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1167 PM_QOS_DEFAULT_VALUE);
1168
1169 intel_uncore_sanitize(dev_priv);
1170
1171 intel_opregion_setup(dev_priv);
1172
1173 i915_gem_load_init_fences(dev_priv);
1174
1175 /* On the 945G/GM, the chipset reports the MSI capability on the
1176 * integrated graphics even though the support isn't actually there
1177 * according to the published specs. It doesn't appear to function
1178 * correctly in testing on 945G.
1179 * This may be a side effect of MSI having been made available for PEG
1180 * and the registers being closely associated.
1181 *
1182 * According to chipset errata, on the 965GM, MSI interrupts may
1183 * be lost or delayed, and was defeatured. MSI interrupts seem to
1184 * get lost on g4x as well, and interrupt delivery seems to stay
1185 * properly dead afterwards. So we'll just disable them for all
1186 * pre-gen5 chipsets.
1187 */
1188 if (INTEL_GEN(dev_priv) >= 5) {
1189 if (pci_enable_msi(pdev) < 0)
1190 DRM_DEBUG_DRIVER("can't enable MSI");
1191 }
1192
1193 ret = intel_gvt_init(dev_priv);
1194 if (ret)
1195 goto err_ggtt;
1196
1197 return 0;
1198
1199err_ggtt:
1200 i915_ggtt_cleanup_hw(dev_priv);
1201err_perf:
1202 i915_perf_fini(dev_priv);
1203 return ret;
1204}
1205
1206/**
1207 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1208 * @dev_priv: device private
1209 */
1210static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1211{
1212 struct pci_dev *pdev = dev_priv->drm.pdev;
1213
1214 i915_perf_fini(dev_priv);
1215
1216 if (pdev->msi_enabled)
1217 pci_disable_msi(pdev);
1218
1219 pm_qos_remove_request(&dev_priv->pm_qos);
1220 i915_ggtt_cleanup_hw(dev_priv);
1221}
1222
1223/**
1224 * i915_driver_register - register the driver with the rest of the system
1225 * @dev_priv: device private
1226 *
1227 * Perform any steps necessary to make the driver available via kernel
1228 * internal or userspace interfaces.
1229 */
1230static void i915_driver_register(struct drm_i915_private *dev_priv)
1231{
1232 struct drm_device *dev = &dev_priv->drm;
1233
1234 i915_gem_shrinker_register(dev_priv);
1235 i915_pmu_register(dev_priv);
1236
1237 /*
1238 * Notify a valid surface after modesetting,
1239 * when running inside a VM.
1240 */
1241 if (intel_vgpu_active(dev_priv))
1242 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1243
1244 /* Reveal our presence to userspace */
1245 if (drm_dev_register(dev, 0) == 0) {
1246 i915_debugfs_register(dev_priv);
1247 i915_guc_log_register(dev_priv);
1248 i915_setup_sysfs(dev_priv);
1249
1250 /* Depends on sysfs having been initialized */
1251 i915_perf_register(dev_priv);
1252 } else
1253 DRM_ERROR("Failed to register driver for userspace access!\n");
1254
1255 if (INTEL_INFO(dev_priv)->num_pipes) {
1256 /* Must be done after probing outputs */
1257 intel_opregion_register(dev_priv);
1258 acpi_video_register();
1259 }
1260
1261 if (IS_GEN5(dev_priv))
1262 intel_gpu_ips_init(dev_priv);
1263
1264 intel_audio_init(dev_priv);
1265
1266 /*
1267 * Some ports require correctly set-up hpd registers for detection to
1268 * work properly (leading to ghost connected connector status), e.g. VGA
1269 * on gm45. Hence we can only set up the initial fbdev config after hpd
1270 * irqs are fully enabled. We do it last so that the async config
1271 * cannot run before the connectors are registered.
1272 */
1273 intel_fbdev_initial_config_async(dev);
1274
1275 /*
1276 * We need to coordinate the hotplugs with the asynchronous fbdev
1277 * configuration, for which we use the fbdev->async_cookie.
1278 */
1279 if (INTEL_INFO(dev_priv)->num_pipes)
1280 drm_kms_helper_poll_init(dev);
1281}
1282
1283/**
1284 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1285 * @dev_priv: device private
1286 */
1287static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1288{
1289 intel_fbdev_unregister(dev_priv);
1290 intel_audio_deinit(dev_priv);
1291
1292 /*
1293 * After flushing the fbdev (incl. a late async config which will
1294 * have delayed queuing of a hotplug event), then flush the hotplug
1295 * events.
1296 */
1297 drm_kms_helper_poll_fini(&dev_priv->drm);
1298
1299 intel_gpu_ips_teardown();
1300 acpi_video_unregister();
1301 intel_opregion_unregister(dev_priv);
1302
1303 i915_perf_unregister(dev_priv);
1304 i915_pmu_unregister(dev_priv);
1305
1306 i915_teardown_sysfs(dev_priv);
1307 i915_guc_log_unregister(dev_priv);
1308 drm_dev_unregister(&dev_priv->drm);
1309
1310 i915_gem_shrinker_unregister(dev_priv);
1311}
1312
1313static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1314{
1315 if (drm_debug & DRM_UT_DRIVER) {
1316 struct drm_printer p = drm_debug_printer("i915 device info:");
1317
1318 intel_device_info_dump(&dev_priv->info, &p);
1319 intel_device_info_dump_runtime(&dev_priv->info, &p);
1320 }
1321
1322 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1323 DRM_INFO("DRM_I915_DEBUG enabled\n");
1324 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1325 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1326}
1327
1328/**
1329 * i915_driver_load - setup chip and create an initial config
1330 * @pdev: PCI device
1331 * @ent: matching PCI ID entry
1332 *
1333 * The driver load routine has to do several things:
1334 * - drive output discovery via intel_modeset_init()
1335 * - initialize the memory manager
1336 * - allocate initial config memory
1337 * - setup the DRM framebuffer with the allocated memory
1338 */
1339int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1340{
1341 const struct intel_device_info *match_info =
1342 (struct intel_device_info *)ent->driver_data;
1343 struct drm_i915_private *dev_priv;
1344 int ret;
1345
1346 /* Enable nuclear pageflip on ILK+ */
1347 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1348 driver.driver_features &= ~DRIVER_ATOMIC;
1349
1350 ret = -ENOMEM;
1351 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1352 if (dev_priv)
1353 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1354 if (ret) {
1355 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1356 goto out_free;
1357 }
1358
1359 dev_priv->drm.pdev = pdev;
1360 dev_priv->drm.dev_private = dev_priv;
1361
1362 ret = pci_enable_device(pdev);
1363 if (ret)
1364 goto out_fini;
1365
1366 pci_set_drvdata(pdev, &dev_priv->drm);
1367 /*
1368 * Disable the system suspend direct complete optimization, which can
1369 * leave the device suspended skipping the driver's suspend handlers
1370 * if the device was already runtime suspended. This is needed due to
1371 * the difference in our runtime and system suspend sequence and
1372 * becaue the HDA driver may require us to enable the audio power
1373 * domain during system suspend.
1374 */
1375 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1376
1377 ret = i915_driver_init_early(dev_priv, ent);
1378 if (ret < 0)
1379 goto out_pci_disable;
1380
1381 intel_runtime_pm_get(dev_priv);
1382
1383 ret = i915_driver_init_mmio(dev_priv);
1384 if (ret < 0)
1385 goto out_runtime_pm_put;
1386
1387 ret = i915_driver_init_hw(dev_priv);
1388 if (ret < 0)
1389 goto out_cleanup_mmio;
1390
1391 /*
1392 * TODO: move the vblank init and parts of modeset init steps into one
1393 * of the i915_driver_init_/i915_driver_register functions according
1394 * to the role/effect of the given init step.
1395 */
1396 if (INTEL_INFO(dev_priv)->num_pipes) {
1397 ret = drm_vblank_init(&dev_priv->drm,
1398 INTEL_INFO(dev_priv)->num_pipes);
1399 if (ret)
1400 goto out_cleanup_hw;
1401 }
1402
1403 ret = i915_load_modeset_init(&dev_priv->drm);
1404 if (ret < 0)
1405 goto out_cleanup_hw;
1406
1407 i915_driver_register(dev_priv);
1408
1409 intel_runtime_pm_enable(dev_priv);
1410
1411 intel_init_ipc(dev_priv);
1412
1413 intel_runtime_pm_put(dev_priv);
1414
1415 i915_welcome_messages(dev_priv);
1416
1417 return 0;
1418
1419out_cleanup_hw:
1420 i915_driver_cleanup_hw(dev_priv);
1421out_cleanup_mmio:
1422 i915_driver_cleanup_mmio(dev_priv);
1423out_runtime_pm_put:
1424 intel_runtime_pm_put(dev_priv);
1425 i915_driver_cleanup_early(dev_priv);
1426out_pci_disable:
1427 pci_disable_device(pdev);
1428out_fini:
1429 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1430 drm_dev_fini(&dev_priv->drm);
1431out_free:
1432 kfree(dev_priv);
1433 return ret;
1434}
1435
1436void i915_driver_unload(struct drm_device *dev)
1437{
1438 struct drm_i915_private *dev_priv = to_i915(dev);
1439 struct pci_dev *pdev = dev_priv->drm.pdev;
1440
1441 i915_driver_unregister(dev_priv);
1442
1443 if (i915_gem_suspend(dev_priv))
1444 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1445
1446 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1447
1448 drm_atomic_helper_shutdown(dev);
1449
1450 intel_gvt_cleanup(dev_priv);
1451
1452 intel_modeset_cleanup(dev);
1453
1454 intel_bios_cleanup(dev_priv);
1455
1456 vga_switcheroo_unregister_client(pdev);
1457 vga_client_register(pdev, NULL, NULL, NULL);
1458
1459 intel_csr_ucode_fini(dev_priv);
1460
1461 /* Free error state after interrupts are fully disabled. */
1462 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1463 i915_reset_error_state(dev_priv);
1464
1465 i915_gem_fini(dev_priv);
1466 intel_uc_fini_fw(dev_priv);
1467 intel_fbc_cleanup_cfb(dev_priv);
1468
1469 intel_power_domains_fini(dev_priv);
1470
1471 i915_driver_cleanup_hw(dev_priv);
1472 i915_driver_cleanup_mmio(dev_priv);
1473
1474 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1475}
1476
1477static void i915_driver_release(struct drm_device *dev)
1478{
1479 struct drm_i915_private *dev_priv = to_i915(dev);
1480
1481 i915_driver_cleanup_early(dev_priv);
1482 drm_dev_fini(&dev_priv->drm);
1483
1484 kfree(dev_priv);
1485}
1486
1487static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1488{
1489 struct drm_i915_private *i915 = to_i915(dev);
1490 int ret;
1491
1492 ret = i915_gem_open(i915, file);
1493 if (ret)
1494 return ret;
1495
1496 return 0;
1497}
1498
1499/**
1500 * i915_driver_lastclose - clean up after all DRM clients have exited
1501 * @dev: DRM device
1502 *
1503 * Take care of cleaning up after all DRM clients have exited. In the
1504 * mode setting case, we want to restore the kernel's initial mode (just
1505 * in case the last client left us in a bad state).
1506 *
1507 * Additionally, in the non-mode setting case, we'll tear down the GTT
1508 * and DMA structures, since the kernel won't be using them, and clea
1509 * up any GEM state.
1510 */
1511static void i915_driver_lastclose(struct drm_device *dev)
1512{
1513 intel_fbdev_restore_mode(dev);
1514 vga_switcheroo_process_delayed_switch();
1515}
1516
1517static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1518{
1519 struct drm_i915_file_private *file_priv = file->driver_priv;
1520
1521 mutex_lock(&dev->struct_mutex);
1522 i915_gem_context_close(file);
1523 i915_gem_release(dev, file);
1524 mutex_unlock(&dev->struct_mutex);
1525
1526 kfree(file_priv);
1527}
1528
1529static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1530{
1531 struct drm_device *dev = &dev_priv->drm;
1532 struct intel_encoder *encoder;
1533
1534 drm_modeset_lock_all(dev);
1535 for_each_intel_encoder(dev, encoder)
1536 if (encoder->suspend)
1537 encoder->suspend(encoder);
1538 drm_modeset_unlock_all(dev);
1539}
1540
1541static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1542 bool rpm_resume);
1543static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1544
1545static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1546{
1547#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1548 if (acpi_target_system_state() < ACPI_STATE_S3)
1549 return true;
1550#endif
1551 return false;
1552}
1553
1554static int i915_drm_suspend(struct drm_device *dev)
1555{
1556 struct drm_i915_private *dev_priv = to_i915(dev);
1557 struct pci_dev *pdev = dev_priv->drm.pdev;
1558 pci_power_t opregion_target_state;
1559 int error;
1560
1561 /* ignore lid events during suspend */
1562 mutex_lock(&dev_priv->modeset_restore_lock);
1563 dev_priv->modeset_restore = MODESET_SUSPENDED;
1564 mutex_unlock(&dev_priv->modeset_restore_lock);
1565
1566 disable_rpm_wakeref_asserts(dev_priv);
1567
1568 /* We do a lot of poking in a lot of registers, make sure they work
1569 * properly. */
1570 intel_display_set_init_power(dev_priv, true);
1571
1572 drm_kms_helper_poll_disable(dev);
1573
1574 pci_save_state(pdev);
1575
1576 error = i915_gem_suspend(dev_priv);
1577 if (error) {
1578 dev_err(&pdev->dev,
1579 "GEM idle failed, resume might fail\n");
1580 goto out;
1581 }
1582
1583 intel_display_suspend(dev);
1584
1585 intel_dp_mst_suspend(dev);
1586
1587 intel_runtime_pm_disable_interrupts(dev_priv);
1588 intel_hpd_cancel_work(dev_priv);
1589
1590 intel_suspend_encoders(dev_priv);
1591
1592 intel_suspend_hw(dev_priv);
1593
1594 i915_gem_suspend_gtt_mappings(dev_priv);
1595
1596 i915_save_state(dev_priv);
1597
1598 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1599 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1600
1601 intel_uncore_suspend(dev_priv);
1602 intel_opregion_unregister(dev_priv);
1603
1604 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1605
1606 dev_priv->suspend_count++;
1607
1608 intel_csr_ucode_suspend(dev_priv);
1609
1610out:
1611 enable_rpm_wakeref_asserts(dev_priv);
1612
1613 return error;
1614}
1615
1616static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1617{
1618 struct drm_i915_private *dev_priv = to_i915(dev);
1619 struct pci_dev *pdev = dev_priv->drm.pdev;
1620 int ret;
1621
1622 disable_rpm_wakeref_asserts(dev_priv);
1623
1624 intel_display_set_init_power(dev_priv, false);
1625
1626 /*
1627 * In case of firmware assisted context save/restore don't manually
1628 * deinit the power domains. This also means the CSR/DMC firmware will
1629 * stay active, it will power down any HW resources as required and
1630 * also enable deeper system power states that would be blocked if the
1631 * firmware was inactive.
1632 */
1633 if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1634 dev_priv->csr.dmc_payload == NULL) {
1635 intel_power_domains_suspend(dev_priv);
1636 dev_priv->power_domains_suspended = true;
1637 }
1638
1639 ret = 0;
1640 if (IS_GEN9_LP(dev_priv))
1641 bxt_enable_dc9(dev_priv);
1642 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1643 hsw_enable_pc8(dev_priv);
1644 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1645 ret = vlv_suspend_complete(dev_priv);
1646
1647 if (ret) {
1648 DRM_ERROR("Suspend complete failed: %d\n", ret);
1649 if (dev_priv->power_domains_suspended) {
1650 intel_power_domains_init_hw(dev_priv, true);
1651 dev_priv->power_domains_suspended = false;
1652 }
1653
1654 goto out;
1655 }
1656
1657 pci_disable_device(pdev);
1658 /*
1659 * During hibernation on some platforms the BIOS may try to access
1660 * the device even though it's already in D3 and hang the machine. So
1661 * leave the device in D0 on those platforms and hope the BIOS will
1662 * power down the device properly. The issue was seen on multiple old
1663 * GENs with different BIOS vendors, so having an explicit blacklist
1664 * is inpractical; apply the workaround on everything pre GEN6. The
1665 * platforms where the issue was seen:
1666 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1667 * Fujitsu FSC S7110
1668 * Acer Aspire 1830T
1669 */
1670 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1671 pci_set_power_state(pdev, PCI_D3hot);
1672
1673out:
1674 enable_rpm_wakeref_asserts(dev_priv);
1675
1676 return ret;
1677}
1678
1679static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1680{
1681 int error;
1682
1683 if (!dev) {
1684 DRM_ERROR("dev: %p\n", dev);
1685 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1686 return -ENODEV;
1687 }
1688
1689 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1690 state.event != PM_EVENT_FREEZE))
1691 return -EINVAL;
1692
1693 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1694 return 0;
1695
1696 error = i915_drm_suspend(dev);
1697 if (error)
1698 return error;
1699
1700 return i915_drm_suspend_late(dev, false);
1701}
1702
1703static int i915_drm_resume(struct drm_device *dev)
1704{
1705 struct drm_i915_private *dev_priv = to_i915(dev);
1706 int ret;
1707
1708 disable_rpm_wakeref_asserts(dev_priv);
1709 intel_sanitize_gt_powersave(dev_priv);
1710
1711 ret = i915_ggtt_enable_hw(dev_priv);
1712 if (ret)
1713 DRM_ERROR("failed to re-enable GGTT\n");
1714
1715 intel_csr_ucode_resume(dev_priv);
1716
1717 i915_restore_state(dev_priv);
1718 intel_pps_unlock_regs_wa(dev_priv);
1719 intel_opregion_setup(dev_priv);
1720
1721 intel_init_pch_refclk(dev_priv);
1722
1723 /*
1724 * Interrupts have to be enabled before any batches are run. If not the
1725 * GPU will hang. i915_gem_init_hw() will initiate batches to
1726 * update/restore the context.
1727 *
1728 * drm_mode_config_reset() needs AUX interrupts.
1729 *
1730 * Modeset enabling in intel_modeset_init_hw() also needs working
1731 * interrupts.
1732 */
1733 intel_runtime_pm_enable_interrupts(dev_priv);
1734
1735 drm_mode_config_reset(dev);
1736
1737 i915_gem_resume(dev_priv);
1738
1739 intel_modeset_init_hw(dev);
1740 intel_init_clock_gating(dev_priv);
1741
1742 spin_lock_irq(&dev_priv->irq_lock);
1743 if (dev_priv->display.hpd_irq_setup)
1744 dev_priv->display.hpd_irq_setup(dev_priv);
1745 spin_unlock_irq(&dev_priv->irq_lock);
1746
1747 intel_dp_mst_resume(dev);
1748
1749 intel_display_resume(dev);
1750
1751 drm_kms_helper_poll_enable(dev);
1752
1753 /*
1754 * ... but also need to make sure that hotplug processing
1755 * doesn't cause havoc. Like in the driver load code we don't
1756 * bother with the tiny race here where we might loose hotplug
1757 * notifications.
1758 * */
1759 intel_hpd_init(dev_priv);
1760
1761 intel_opregion_register(dev_priv);
1762
1763 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1764
1765 mutex_lock(&dev_priv->modeset_restore_lock);
1766 dev_priv->modeset_restore = MODESET_DONE;
1767 mutex_unlock(&dev_priv->modeset_restore_lock);
1768
1769 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1770
1771 enable_rpm_wakeref_asserts(dev_priv);
1772
1773 return 0;
1774}
1775
1776static int i915_drm_resume_early(struct drm_device *dev)
1777{
1778 struct drm_i915_private *dev_priv = to_i915(dev);
1779 struct pci_dev *pdev = dev_priv->drm.pdev;
1780 int ret;
1781
1782 /*
1783 * We have a resume ordering issue with the snd-hda driver also
1784 * requiring our device to be power up. Due to the lack of a
1785 * parent/child relationship we currently solve this with an early
1786 * resume hook.
1787 *
1788 * FIXME: This should be solved with a special hdmi sink device or
1789 * similar so that power domains can be employed.
1790 */
1791
1792 /*
1793 * Note that we need to set the power state explicitly, since we
1794 * powered off the device during freeze and the PCI core won't power
1795 * it back up for us during thaw. Powering off the device during
1796 * freeze is not a hard requirement though, and during the
1797 * suspend/resume phases the PCI core makes sure we get here with the
1798 * device powered on. So in case we change our freeze logic and keep
1799 * the device powered we can also remove the following set power state
1800 * call.
1801 */
1802 ret = pci_set_power_state(pdev, PCI_D0);
1803 if (ret) {
1804 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1805 goto out;
1806 }
1807
1808 /*
1809 * Note that pci_enable_device() first enables any parent bridge
1810 * device and only then sets the power state for this device. The
1811 * bridge enabling is a nop though, since bridge devices are resumed
1812 * first. The order of enabling power and enabling the device is
1813 * imposed by the PCI core as described above, so here we preserve the
1814 * same order for the freeze/thaw phases.
1815 *
1816 * TODO: eventually we should remove pci_disable_device() /
1817 * pci_enable_enable_device() from suspend/resume. Due to how they
1818 * depend on the device enable refcount we can't anyway depend on them
1819 * disabling/enabling the device.
1820 */
1821 if (pci_enable_device(pdev)) {
1822 ret = -EIO;
1823 goto out;
1824 }
1825
1826 pci_set_master(pdev);
1827
1828 disable_rpm_wakeref_asserts(dev_priv);
1829
1830 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1831 ret = vlv_resume_prepare(dev_priv, false);
1832 if (ret)
1833 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1834 ret);
1835
1836 intel_uncore_resume_early(dev_priv);
1837
1838 if (IS_GEN9_LP(dev_priv)) {
1839 gen9_sanitize_dc_state(dev_priv);
1840 bxt_disable_dc9(dev_priv);
1841 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1842 hsw_disable_pc8(dev_priv);
1843 }
1844
1845 intel_uncore_sanitize(dev_priv);
1846
1847 if (dev_priv->power_domains_suspended)
1848 intel_power_domains_init_hw(dev_priv, true);
1849 else
1850 intel_display_set_init_power(dev_priv, true);
1851
1852 i915_gem_sanitize(dev_priv);
1853
1854 enable_rpm_wakeref_asserts(dev_priv);
1855
1856out:
1857 dev_priv->power_domains_suspended = false;
1858
1859 return ret;
1860}
1861
1862static int i915_resume_switcheroo(struct drm_device *dev)
1863{
1864 int ret;
1865
1866 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1867 return 0;
1868
1869 ret = i915_drm_resume_early(dev);
1870 if (ret)
1871 return ret;
1872
1873 return i915_drm_resume(dev);
1874}
1875
1876/**
1877 * i915_reset - reset chip after a hang
1878 * @i915: #drm_i915_private to reset
1879 * @flags: Instructions
1880 *
1881 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1882 * on failure.
1883 *
1884 * Caller must hold the struct_mutex.
1885 *
1886 * Procedure is fairly simple:
1887 * - reset the chip using the reset reg
1888 * - re-init context state
1889 * - re-init hardware status page
1890 * - re-init ring buffer
1891 * - re-init interrupt state
1892 * - re-init display
1893 */
1894void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1895{
1896 struct i915_gpu_error *error = &i915->gpu_error;
1897 int ret;
1898 int i;
1899
1900 might_sleep();
1901 lockdep_assert_held(&i915->drm.struct_mutex);
1902 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1903
1904 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1905 return;
1906
1907 /* Clear any previous failed attempts at recovery. Time to try again. */
1908 if (!i915_gem_unset_wedged(i915))
1909 goto wakeup;
1910
1911 if (!(flags & I915_RESET_QUIET))
1912 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1913 error->reset_count++;
1914
1915 disable_irq(i915->drm.irq);
1916 ret = i915_gem_reset_prepare(i915);
1917 if (ret) {
1918 dev_err(i915->drm.dev, "GPU recovery failed\n");
1919 goto taint;
1920 }
1921
1922 if (!intel_has_gpu_reset(i915)) {
1923 if (i915_modparams.reset)
1924 dev_err(i915->drm.dev, "GPU reset not supported\n");
1925 else
1926 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1927 goto error;
1928 }
1929
1930 for (i = 0; i < 3; i++) {
1931 ret = intel_gpu_reset(i915, ALL_ENGINES);
1932 if (ret == 0)
1933 break;
1934
1935 msleep(100);
1936 }
1937 if (ret) {
1938 dev_err(i915->drm.dev, "Failed to reset chip\n");
1939 goto taint;
1940 }
1941
1942 /* Ok, now get things going again... */
1943
1944 /*
1945 * Everything depends on having the GTT running, so we need to start
1946 * there.
1947 */
1948 ret = i915_ggtt_enable_hw(i915);
1949 if (ret) {
1950 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1951 ret);
1952 goto error;
1953 }
1954
1955 i915_gem_reset(i915);
1956 intel_overlay_reset(i915);
1957
1958 /*
1959 * Next we need to restore the context, but we don't use those
1960 * yet either...
1961 *
1962 * Ring buffer needs to be re-initialized in the KMS case, or if X
1963 * was running at the time of the reset (i.e. we weren't VT
1964 * switched away).
1965 */
1966 ret = i915_gem_init_hw(i915);
1967 if (ret) {
1968 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1969 ret);
1970 goto error;
1971 }
1972
1973 i915_queue_hangcheck(i915);
1974
1975finish:
1976 i915_gem_reset_finish(i915);
1977 enable_irq(i915->drm.irq);
1978
1979wakeup:
1980 clear_bit(I915_RESET_HANDOFF, &error->flags);
1981 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1982 return;
1983
1984taint:
1985 /*
1986 * History tells us that if we cannot reset the GPU now, we
1987 * never will. This then impacts everything that is run
1988 * subsequently. On failing the reset, we mark the driver
1989 * as wedged, preventing further execution on the GPU.
1990 * We also want to go one step further and add a taint to the
1991 * kernel so that any subsequent faults can be traced back to
1992 * this failure. This is important for CI, where if the
1993 * GPU/driver fails we would like to reboot and restart testing
1994 * rather than continue on into oblivion. For everyone else,
1995 * the system should still plod along, but they have been warned!
1996 */
1997 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1998error:
1999 i915_gem_set_wedged(i915);
2000 i915_retire_requests(i915);
2001 intel_gpu_reset(i915, ALL_ENGINES);
2002 goto finish;
2003}
2004
2005static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2006 struct intel_engine_cs *engine)
2007{
2008 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2009}
2010
2011/**
2012 * i915_reset_engine - reset GPU engine to recover from a hang
2013 * @engine: engine to reset
2014 * @flags: options
2015 *
2016 * Reset a specific GPU engine. Useful if a hang is detected.
2017 * Returns zero on successful reset or otherwise an error code.
2018 *
2019 * Procedure is:
2020 * - identifies the request that caused the hang and it is dropped
2021 * - reset engine (which will force the engine to idle)
2022 * - re-init/configure engine
2023 */
2024int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2025{
2026 struct i915_gpu_error *error = &engine->i915->gpu_error;
2027 struct i915_request *active_request;
2028 int ret;
2029
2030 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2031
2032 active_request = i915_gem_reset_prepare_engine(engine);
2033 if (IS_ERR_OR_NULL(active_request)) {
2034 /* Either the previous reset failed, or we pardon the reset. */
2035 ret = PTR_ERR(active_request);
2036 goto out;
2037 }
2038
2039 if (!(flags & I915_RESET_QUIET)) {
2040 dev_notice(engine->i915->drm.dev,
2041 "Resetting %s after gpu hang\n", engine->name);
2042 }
2043 error->reset_engine_count[engine->id]++;
2044
2045 if (!engine->i915->guc.execbuf_client)
2046 ret = intel_gt_reset_engine(engine->i915, engine);
2047 else
2048 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2049 if (ret) {
2050 /* If we fail here, we expect to fallback to a global reset */
2051 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2052 engine->i915->guc.execbuf_client ? "GuC " : "",
2053 engine->name, ret);
2054 goto out;
2055 }
2056
2057 /*
2058 * The request that caused the hang is stuck on elsp, we know the
2059 * active request and can drop it, adjust head to skip the offending
2060 * request to resume executing remaining requests in the queue.
2061 */
2062 i915_gem_reset_engine(engine, active_request);
2063
2064 /*
2065 * The engine and its registers (and workarounds in case of render)
2066 * have been reset to their default values. Follow the init_ring
2067 * process to program RING_MODE, HWSP and re-enable submission.
2068 */
2069 ret = engine->init_hw(engine);
2070 if (ret)
2071 goto out;
2072
2073out:
2074 i915_gem_reset_finish_engine(engine);
2075 return ret;
2076}
2077
2078static int i915_pm_suspend(struct device *kdev)
2079{
2080 struct pci_dev *pdev = to_pci_dev(kdev);
2081 struct drm_device *dev = pci_get_drvdata(pdev);
2082
2083 if (!dev) {
2084 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2085 return -ENODEV;
2086 }
2087
2088 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2089 return 0;
2090
2091 return i915_drm_suspend(dev);
2092}
2093
2094static int i915_pm_suspend_late(struct device *kdev)
2095{
2096 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2097
2098 /*
2099 * We have a suspend ordering issue with the snd-hda driver also
2100 * requiring our device to be power up. Due to the lack of a
2101 * parent/child relationship we currently solve this with an late
2102 * suspend hook.
2103 *
2104 * FIXME: This should be solved with a special hdmi sink device or
2105 * similar so that power domains can be employed.
2106 */
2107 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2108 return 0;
2109
2110 return i915_drm_suspend_late(dev, false);
2111}
2112
2113static int i915_pm_poweroff_late(struct device *kdev)
2114{
2115 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2116
2117 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2118 return 0;
2119
2120 return i915_drm_suspend_late(dev, true);
2121}
2122
2123static int i915_pm_resume_early(struct device *kdev)
2124{
2125 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2126
2127 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2128 return 0;
2129
2130 return i915_drm_resume_early(dev);
2131}
2132
2133static int i915_pm_resume(struct device *kdev)
2134{
2135 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2136
2137 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2138 return 0;
2139
2140 return i915_drm_resume(dev);
2141}
2142
2143/* freeze: before creating the hibernation_image */
2144static int i915_pm_freeze(struct device *kdev)
2145{
2146 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2147 int ret;
2148
2149 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2150 ret = i915_drm_suspend(dev);
2151 if (ret)
2152 return ret;
2153 }
2154
2155 ret = i915_gem_freeze(kdev_to_i915(kdev));
2156 if (ret)
2157 return ret;
2158
2159 return 0;
2160}
2161
2162static int i915_pm_freeze_late(struct device *kdev)
2163{
2164 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2165 int ret;
2166
2167 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2168 ret = i915_drm_suspend_late(dev, true);
2169 if (ret)
2170 return ret;
2171 }
2172
2173 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2174 if (ret)
2175 return ret;
2176
2177 return 0;
2178}
2179
2180/* thaw: called after creating the hibernation image, but before turning off. */
2181static int i915_pm_thaw_early(struct device *kdev)
2182{
2183 return i915_pm_resume_early(kdev);
2184}
2185
2186static int i915_pm_thaw(struct device *kdev)
2187{
2188 return i915_pm_resume(kdev);
2189}
2190
2191/* restore: called after loading the hibernation image. */
2192static int i915_pm_restore_early(struct device *kdev)
2193{
2194 return i915_pm_resume_early(kdev);
2195}
2196
2197static int i915_pm_restore(struct device *kdev)
2198{
2199 return i915_pm_resume(kdev);
2200}
2201
2202/*
2203 * Save all Gunit registers that may be lost after a D3 and a subsequent
2204 * S0i[R123] transition. The list of registers needing a save/restore is
2205 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2206 * registers in the following way:
2207 * - Driver: saved/restored by the driver
2208 * - Punit : saved/restored by the Punit firmware
2209 * - No, w/o marking: no need to save/restore, since the register is R/O or
2210 * used internally by the HW in a way that doesn't depend
2211 * keeping the content across a suspend/resume.
2212 * - Debug : used for debugging
2213 *
2214 * We save/restore all registers marked with 'Driver', with the following
2215 * exceptions:
2216 * - Registers out of use, including also registers marked with 'Debug'.
2217 * These have no effect on the driver's operation, so we don't save/restore
2218 * them to reduce the overhead.
2219 * - Registers that are fully setup by an initialization function called from
2220 * the resume path. For example many clock gating and RPS/RC6 registers.
2221 * - Registers that provide the right functionality with their reset defaults.
2222 *
2223 * TODO: Except for registers that based on the above 3 criteria can be safely
2224 * ignored, we save/restore all others, practically treating the HW context as
2225 * a black-box for the driver. Further investigation is needed to reduce the
2226 * saved/restored registers even further, by following the same 3 criteria.
2227 */
2228static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2229{
2230 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2231 int i;
2232
2233 /* GAM 0x4000-0x4770 */
2234 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2235 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2236 s->arb_mode = I915_READ(ARB_MODE);
2237 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2238 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2239
2240 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2241 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2242
2243 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2244 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2245
2246 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2247 s->ecochk = I915_READ(GAM_ECOCHK);
2248 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2249 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2250
2251 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2252
2253 /* MBC 0x9024-0x91D0, 0x8500 */
2254 s->g3dctl = I915_READ(VLV_G3DCTL);
2255 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2256 s->mbctl = I915_READ(GEN6_MBCTL);
2257
2258 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2259 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2260 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2261 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2262 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2263 s->rstctl = I915_READ(GEN6_RSTCTL);
2264 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2265
2266 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2267 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2268 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2269 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2270 s->ecobus = I915_READ(ECOBUS);
2271 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2272 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2273 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2274 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2275 s->rcedata = I915_READ(VLV_RCEDATA);
2276 s->spare2gh = I915_READ(VLV_SPAREG2H);
2277
2278 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2279 s->gt_imr = I915_READ(GTIMR);
2280 s->gt_ier = I915_READ(GTIER);
2281 s->pm_imr = I915_READ(GEN6_PMIMR);
2282 s->pm_ier = I915_READ(GEN6_PMIER);
2283
2284 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2285 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2286
2287 /* GT SA CZ domain, 0x100000-0x138124 */
2288 s->tilectl = I915_READ(TILECTL);
2289 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2290 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2291 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2292 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2293
2294 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2295 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2296 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2297 s->pcbr = I915_READ(VLV_PCBR);
2298 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2299
2300 /*
2301 * Not saving any of:
2302 * DFT, 0x9800-0x9EC0
2303 * SARB, 0xB000-0xB1FC
2304 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2305 * PCI CFG
2306 */
2307}
2308
2309static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2310{
2311 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2312 u32 val;
2313 int i;
2314
2315 /* GAM 0x4000-0x4770 */
2316 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2317 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2318 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2319 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2320 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2321
2322 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2323 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2324
2325 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2326 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2327
2328 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2329 I915_WRITE(GAM_ECOCHK, s->ecochk);
2330 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2331 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2332
2333 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2334
2335 /* MBC 0x9024-0x91D0, 0x8500 */
2336 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2337 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2338 I915_WRITE(GEN6_MBCTL, s->mbctl);
2339
2340 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2341 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2342 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2343 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2344 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2345 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2346 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2347
2348 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2349 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2350 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2351 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2352 I915_WRITE(ECOBUS, s->ecobus);
2353 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2354 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2355 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2356 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2357 I915_WRITE(VLV_RCEDATA, s->rcedata);
2358 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2359
2360 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2361 I915_WRITE(GTIMR, s->gt_imr);
2362 I915_WRITE(GTIER, s->gt_ier);
2363 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2364 I915_WRITE(GEN6_PMIER, s->pm_ier);
2365
2366 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2367 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2368
2369 /* GT SA CZ domain, 0x100000-0x138124 */
2370 I915_WRITE(TILECTL, s->tilectl);
2371 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2372 /*
2373 * Preserve the GT allow wake and GFX force clock bit, they are not
2374 * be restored, as they are used to control the s0ix suspend/resume
2375 * sequence by the caller.
2376 */
2377 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2378 val &= VLV_GTLC_ALLOWWAKEREQ;
2379 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2380 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2381
2382 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2383 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2384 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2385 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2386
2387 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2388
2389 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2390 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2391 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2392 I915_WRITE(VLV_PCBR, s->pcbr);
2393 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2394}
2395
2396static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2397 u32 mask, u32 val)
2398{
2399 /* The HW does not like us polling for PW_STATUS frequently, so
2400 * use the sleeping loop rather than risk the busy spin within
2401 * intel_wait_for_register().
2402 *
2403 * Transitioning between RC6 states should be at most 2ms (see
2404 * valleyview_enable_rps) so use a 3ms timeout.
2405 */
2406 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2407 3);
2408}
2409
2410int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2411{
2412 u32 val;
2413 int err;
2414
2415 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2416 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2417 if (force_on)
2418 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2419 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2420
2421 if (!force_on)
2422 return 0;
2423
2424 err = intel_wait_for_register(dev_priv,
2425 VLV_GTLC_SURVIVABILITY_REG,
2426 VLV_GFX_CLK_STATUS_BIT,
2427 VLV_GFX_CLK_STATUS_BIT,
2428 20);
2429 if (err)
2430 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2431 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2432
2433 return err;
2434}
2435
2436static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2437{
2438 u32 mask;
2439 u32 val;
2440 int err;
2441
2442 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2443 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2444 if (allow)
2445 val |= VLV_GTLC_ALLOWWAKEREQ;
2446 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2447 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2448
2449 mask = VLV_GTLC_ALLOWWAKEACK;
2450 val = allow ? mask : 0;
2451
2452 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2453 if (err)
2454 DRM_ERROR("timeout disabling GT waking\n");
2455
2456 return err;
2457}
2458
2459static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2460 bool wait_for_on)
2461{
2462 u32 mask;
2463 u32 val;
2464
2465 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2466 val = wait_for_on ? mask : 0;
2467
2468 /*
2469 * RC6 transitioning can be delayed up to 2 msec (see
2470 * valleyview_enable_rps), use 3 msec for safety.
2471 */
2472 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2473 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2474 onoff(wait_for_on));
2475}
2476
2477static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2478{
2479 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2480 return;
2481
2482 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2483 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2484}
2485
2486static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2487{
2488 u32 mask;
2489 int err;
2490
2491 /*
2492 * Bspec defines the following GT well on flags as debug only, so
2493 * don't treat them as hard failures.
2494 */
2495 vlv_wait_for_gt_wells(dev_priv, false);
2496
2497 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2498 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2499
2500 vlv_check_no_gt_access(dev_priv);
2501
2502 err = vlv_force_gfx_clock(dev_priv, true);
2503 if (err)
2504 goto err1;
2505
2506 err = vlv_allow_gt_wake(dev_priv, false);
2507 if (err)
2508 goto err2;
2509
2510 if (!IS_CHERRYVIEW(dev_priv))
2511 vlv_save_gunit_s0ix_state(dev_priv);
2512
2513 err = vlv_force_gfx_clock(dev_priv, false);
2514 if (err)
2515 goto err2;
2516
2517 return 0;
2518
2519err2:
2520 /* For safety always re-enable waking and disable gfx clock forcing */
2521 vlv_allow_gt_wake(dev_priv, true);
2522err1:
2523 vlv_force_gfx_clock(dev_priv, false);
2524
2525 return err;
2526}
2527
2528static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2529 bool rpm_resume)
2530{
2531 int err;
2532 int ret;
2533
2534 /*
2535 * If any of the steps fail just try to continue, that's the best we
2536 * can do at this point. Return the first error code (which will also
2537 * leave RPM permanently disabled).
2538 */
2539 ret = vlv_force_gfx_clock(dev_priv, true);
2540
2541 if (!IS_CHERRYVIEW(dev_priv))
2542 vlv_restore_gunit_s0ix_state(dev_priv);
2543
2544 err = vlv_allow_gt_wake(dev_priv, true);
2545 if (!ret)
2546 ret = err;
2547
2548 err = vlv_force_gfx_clock(dev_priv, false);
2549 if (!ret)
2550 ret = err;
2551
2552 vlv_check_no_gt_access(dev_priv);
2553
2554 if (rpm_resume)
2555 intel_init_clock_gating(dev_priv);
2556
2557 return ret;
2558}
2559
2560static int intel_runtime_suspend(struct device *kdev)
2561{
2562 struct pci_dev *pdev = to_pci_dev(kdev);
2563 struct drm_device *dev = pci_get_drvdata(pdev);
2564 struct drm_i915_private *dev_priv = to_i915(dev);
2565 int ret;
2566
2567 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2568 return -ENODEV;
2569
2570 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2571 return -ENODEV;
2572
2573 DRM_DEBUG_KMS("Suspending device\n");
2574
2575 disable_rpm_wakeref_asserts(dev_priv);
2576
2577 /*
2578 * We are safe here against re-faults, since the fault handler takes
2579 * an RPM reference.
2580 */
2581 i915_gem_runtime_suspend(dev_priv);
2582
2583 intel_uc_suspend(dev_priv);
2584
2585 intel_runtime_pm_disable_interrupts(dev_priv);
2586
2587 intel_uncore_suspend(dev_priv);
2588
2589 ret = 0;
2590 if (IS_GEN9_LP(dev_priv)) {
2591 bxt_display_core_uninit(dev_priv);
2592 bxt_enable_dc9(dev_priv);
2593 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2594 hsw_enable_pc8(dev_priv);
2595 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2596 ret = vlv_suspend_complete(dev_priv);
2597 }
2598
2599 if (ret) {
2600 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2601 intel_uncore_runtime_resume(dev_priv);
2602
2603 intel_runtime_pm_enable_interrupts(dev_priv);
2604
2605 intel_uc_resume(dev_priv);
2606
2607 i915_gem_init_swizzling(dev_priv);
2608 i915_gem_restore_fences(dev_priv);
2609
2610 enable_rpm_wakeref_asserts(dev_priv);
2611
2612 return ret;
2613 }
2614
2615 enable_rpm_wakeref_asserts(dev_priv);
2616 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2617
2618 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2619 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2620
2621 dev_priv->runtime_pm.suspended = true;
2622
2623 /*
2624 * FIXME: We really should find a document that references the arguments
2625 * used below!
2626 */
2627 if (IS_BROADWELL(dev_priv)) {
2628 /*
2629 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2630 * being detected, and the call we do at intel_runtime_resume()
2631 * won't be able to restore them. Since PCI_D3hot matches the
2632 * actual specification and appears to be working, use it.
2633 */
2634 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2635 } else {
2636 /*
2637 * current versions of firmware which depend on this opregion
2638 * notification have repurposed the D1 definition to mean
2639 * "runtime suspended" vs. what you would normally expect (D3)
2640 * to distinguish it from notifications that might be sent via
2641 * the suspend path.
2642 */
2643 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2644 }
2645
2646 assert_forcewakes_inactive(dev_priv);
2647
2648 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2649 intel_hpd_poll_init(dev_priv);
2650
2651 DRM_DEBUG_KMS("Device suspended\n");
2652 return 0;
2653}
2654
2655static int intel_runtime_resume(struct device *kdev)
2656{
2657 struct pci_dev *pdev = to_pci_dev(kdev);
2658 struct drm_device *dev = pci_get_drvdata(pdev);
2659 struct drm_i915_private *dev_priv = to_i915(dev);
2660 int ret = 0;
2661
2662 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2663 return -ENODEV;
2664
2665 DRM_DEBUG_KMS("Resuming device\n");
2666
2667 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2668 disable_rpm_wakeref_asserts(dev_priv);
2669
2670 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2671 dev_priv->runtime_pm.suspended = false;
2672 if (intel_uncore_unclaimed_mmio(dev_priv))
2673 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2674
2675 if (IS_GEN9_LP(dev_priv)) {
2676 bxt_disable_dc9(dev_priv);
2677 bxt_display_core_init(dev_priv, true);
2678 if (dev_priv->csr.dmc_payload &&
2679 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2680 gen9_enable_dc5(dev_priv);
2681 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2682 hsw_disable_pc8(dev_priv);
2683 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2684 ret = vlv_resume_prepare(dev_priv, true);
2685 }
2686
2687 intel_uncore_runtime_resume(dev_priv);
2688
2689 intel_runtime_pm_enable_interrupts(dev_priv);
2690
2691 intel_uc_resume(dev_priv);
2692
2693 /*
2694 * No point of rolling back things in case of an error, as the best
2695 * we can do is to hope that things will still work (and disable RPM).
2696 */
2697 i915_gem_init_swizzling(dev_priv);
2698 i915_gem_restore_fences(dev_priv);
2699
2700 /*
2701 * On VLV/CHV display interrupts are part of the display
2702 * power well, so hpd is reinitialized from there. For
2703 * everyone else do it here.
2704 */
2705 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2706 intel_hpd_init(dev_priv);
2707
2708 intel_enable_ipc(dev_priv);
2709
2710 enable_rpm_wakeref_asserts(dev_priv);
2711
2712 if (ret)
2713 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2714 else
2715 DRM_DEBUG_KMS("Device resumed\n");
2716
2717 return ret;
2718}
2719
2720const struct dev_pm_ops i915_pm_ops = {
2721 /*
2722 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2723 * PMSG_RESUME]
2724 */
2725 .suspend = i915_pm_suspend,
2726 .suspend_late = i915_pm_suspend_late,
2727 .resume_early = i915_pm_resume_early,
2728 .resume = i915_pm_resume,
2729
2730 /*
2731 * S4 event handlers
2732 * @freeze, @freeze_late : called (1) before creating the
2733 * hibernation image [PMSG_FREEZE] and
2734 * (2) after rebooting, before restoring
2735 * the image [PMSG_QUIESCE]
2736 * @thaw, @thaw_early : called (1) after creating the hibernation
2737 * image, before writing it [PMSG_THAW]
2738 * and (2) after failing to create or
2739 * restore the image [PMSG_RECOVER]
2740 * @poweroff, @poweroff_late: called after writing the hibernation
2741 * image, before rebooting [PMSG_HIBERNATE]
2742 * @restore, @restore_early : called after rebooting and restoring the
2743 * hibernation image [PMSG_RESTORE]
2744 */
2745 .freeze = i915_pm_freeze,
2746 .freeze_late = i915_pm_freeze_late,
2747 .thaw_early = i915_pm_thaw_early,
2748 .thaw = i915_pm_thaw,
2749 .poweroff = i915_pm_suspend,
2750 .poweroff_late = i915_pm_poweroff_late,
2751 .restore_early = i915_pm_restore_early,
2752 .restore = i915_pm_restore,
2753
2754 /* S0ix (via runtime suspend) event handlers */
2755 .runtime_suspend = intel_runtime_suspend,
2756 .runtime_resume = intel_runtime_resume,
2757};
2758
2759static const struct vm_operations_struct i915_gem_vm_ops = {
2760 .fault = i915_gem_fault,
2761 .open = drm_gem_vm_open,
2762 .close = drm_gem_vm_close,
2763};
2764
2765static const struct file_operations i915_driver_fops = {
2766 .owner = THIS_MODULE,
2767 .open = drm_open,
2768 .release = drm_release,
2769 .unlocked_ioctl = drm_ioctl,
2770 .mmap = drm_gem_mmap,
2771 .poll = drm_poll,
2772 .read = drm_read,
2773 .compat_ioctl = i915_compat_ioctl,
2774 .llseek = noop_llseek,
2775};
2776
2777static int
2778i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2779 struct drm_file *file)
2780{
2781 return -ENODEV;
2782}
2783
2784static const struct drm_ioctl_desc i915_ioctls[] = {
2785 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2786 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2787 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2788 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2789 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2790 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2791 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2792 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2793 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2794 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2795 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2796 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2797 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2800 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2801 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2802 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2803 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2804 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2806 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2807 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2808 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2809 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2811 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2812 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2813 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2814 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2815 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2816 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2819 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2824 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2825 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2826 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2827 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2829 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2830 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2831 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2832 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2833 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2834 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2835 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2836 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2837 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2838 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2839 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2840 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2841};
2842
2843static struct drm_driver driver = {
2844 /* Don't use MTRRs here; the Xserver or userspace app should
2845 * deal with them for Intel hardware.
2846 */
2847 .driver_features =
2848 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2849 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2850 .release = i915_driver_release,
2851 .open = i915_driver_open,
2852 .lastclose = i915_driver_lastclose,
2853 .postclose = i915_driver_postclose,
2854
2855 .gem_close_object = i915_gem_close_object,
2856 .gem_free_object_unlocked = i915_gem_free_object,
2857 .gem_vm_ops = &i915_gem_vm_ops,
2858
2859 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2860 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2861 .gem_prime_export = i915_gem_prime_export,
2862 .gem_prime_import = i915_gem_prime_import,
2863
2864 .dumb_create = i915_gem_dumb_create,
2865 .dumb_map_offset = i915_gem_mmap_gtt,
2866 .ioctls = i915_ioctls,
2867 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2868 .fops = &i915_driver_fops,
2869 .name = DRIVER_NAME,
2870 .desc = DRIVER_DESC,
2871 .date = DRIVER_DATE,
2872 .major = DRIVER_MAJOR,
2873 .minor = DRIVER_MINOR,
2874 .patchlevel = DRIVER_PATCHLEVEL,
2875};
2876
2877#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2878#include "selftests/mock_drm.c"
2879#endif