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1/*
2 * Copyright(c) 2016, Analogix Semiconductor.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * Based on anx7808 driver obtained from chromeos with copyright:
14 * Copyright(c) 2013, Google Inc.
15 *
16 */
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of_gpio.h>
24#include <linux/of_irq.h>
25#include <linux/of_platform.h>
26#include <linux/regmap.h>
27#include <linux/types.h>
28#include <linux/gpio/consumer.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_atomic_helper.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_edid.h>
37
38#include "analogix-anx78xx.h"
39
40#define I2C_NUM_ADDRESSES 5
41#define I2C_IDX_TX_P0 0
42#define I2C_IDX_TX_P1 1
43#define I2C_IDX_TX_P2 2
44#define I2C_IDX_RX_P0 3
45#define I2C_IDX_RX_P1 4
46
47#define XTAL_CLK 270 /* 27M */
48#define AUX_CH_BUFFER_SIZE 16
49#define AUX_WAIT_TIMEOUT_MS 15
50
51static const u8 anx78xx_i2c_addresses[] = {
52 [I2C_IDX_TX_P0] = TX_P0,
53 [I2C_IDX_TX_P1] = TX_P1,
54 [I2C_IDX_TX_P2] = TX_P2,
55 [I2C_IDX_RX_P0] = RX_P0,
56 [I2C_IDX_RX_P1] = RX_P1,
57};
58
59struct anx78xx_platform_data {
60 struct regulator *dvdd10;
61 struct gpio_desc *gpiod_hpd;
62 struct gpio_desc *gpiod_pd;
63 struct gpio_desc *gpiod_reset;
64
65 int hpd_irq;
66 int intp_irq;
67};
68
69struct anx78xx {
70 struct drm_dp_aux aux;
71 struct drm_bridge bridge;
72 struct i2c_client *client;
73 struct edid *edid;
74 struct drm_connector connector;
75 struct drm_dp_link link;
76 struct anx78xx_platform_data pdata;
77 struct mutex lock;
78
79 /*
80 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
81 * RX_P0 and RX_P1.
82 */
83 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
84 struct regmap *map[I2C_NUM_ADDRESSES];
85
86 u16 chipid;
87 u8 dpcd[DP_RECEIVER_CAP_SIZE];
88
89 bool powered;
90};
91
92static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
93{
94 return container_of(c, struct anx78xx, connector);
95}
96
97static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
98{
99 return container_of(bridge, struct anx78xx, bridge);
100}
101
102static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
103{
104 return regmap_update_bits(map, reg, mask, mask);
105}
106
107static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
108{
109 return regmap_update_bits(map, reg, mask, 0);
110}
111
112static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
113{
114 unsigned int value;
115 int err;
116
117 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
118 &value);
119 if (err < 0)
120 return false;
121
122 return (value & SP_AUX_EN) == 0;
123}
124
125static int anx78xx_aux_wait(struct anx78xx *anx78xx)
126{
127 unsigned long timeout;
128 unsigned int status;
129 int err;
130
131 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
132
133 while (!anx78xx_aux_op_finished(anx78xx)) {
134 if (time_after(jiffies, timeout)) {
135 if (!anx78xx_aux_op_finished(anx78xx)) {
136 DRM_ERROR("Timed out waiting AUX to finish\n");
137 return -ETIMEDOUT;
138 }
139
140 break;
141 }
142
143 usleep_range(1000, 2000);
144 }
145
146 /* Read the AUX channel access status */
147 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
148 &status);
149 if (err < 0) {
150 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
151 return err;
152 }
153
154 if (status & SP_AUX_STATUS) {
155 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
156 status);
157 return -ETIMEDOUT;
158 }
159
160 return 0;
161}
162
163static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
164{
165 int err;
166
167 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
168 addr & 0xff);
169 if (err)
170 return err;
171
172 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
173 (addr & 0xff00) >> 8);
174 if (err)
175 return err;
176
177 /*
178 * DP AUX CH Address Register #2, only update bits[3:0]
179 * [7:4] RESERVED
180 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
181 */
182 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
183 SP_AUX_ADDR_19_16_REG,
184 SP_AUX_ADDR_19_16_MASK,
185 (addr & 0xf0000) >> 16);
186
187 if (err)
188 return err;
189
190 return 0;
191}
192
193static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
194 struct drm_dp_aux_msg *msg)
195{
196 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
197 u8 ctrl1 = msg->request;
198 u8 ctrl2 = SP_AUX_EN;
199 u8 *buffer = msg->buffer;
200 int err;
201
202 /* The DP AUX transmit and receive buffer has 16 bytes. */
203 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
204 return -E2BIG;
205
206 /* Zero-sized messages specify address-only transactions. */
207 if (msg->size < 1)
208 ctrl2 |= SP_ADDR_ONLY;
209 else /* For non-zero-sized set the length field. */
210 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
211
212 if ((msg->request & DP_AUX_I2C_READ) == 0) {
213 /* When WRITE | MOT write values to data buffer */
214 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
215 SP_DP_BUF_DATA0_REG, buffer,
216 msg->size);
217 if (err)
218 return err;
219 }
220
221 /* Write address and request */
222 err = anx78xx_aux_address(anx78xx, msg->address);
223 if (err)
224 return err;
225
226 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
227 ctrl1);
228 if (err)
229 return err;
230
231 /* Start transaction */
232 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
233 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
234 SP_AUX_EN, ctrl2);
235 if (err)
236 return err;
237
238 err = anx78xx_aux_wait(anx78xx);
239 if (err)
240 return err;
241
242 msg->reply = DP_AUX_I2C_REPLY_ACK;
243
244 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
245 /* Read values from data buffer */
246 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
247 SP_DP_BUF_DATA0_REG, buffer,
248 msg->size);
249 if (err)
250 return err;
251 }
252
253 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
254 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
255 if (err)
256 return err;
257
258 return msg->size;
259}
260
261static int anx78xx_set_hpd(struct anx78xx *anx78xx)
262{
263 int err;
264
265 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
266 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
267 if (err)
268 return err;
269
270 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
271 SP_HPD_OUT);
272 if (err)
273 return err;
274
275 return 0;
276}
277
278static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
279{
280 int err;
281
282 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
283 SP_HPD_OUT);
284 if (err)
285 return err;
286
287 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
288 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
289 if (err)
290 return err;
291
292 return 0;
293}
294
295static const struct reg_sequence tmds_phy_initialization[] = {
296 { SP_TMDS_CTRL_BASE + 1, 0x90 },
297 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
298 { SP_TMDS_CTRL_BASE + 6, 0x92 },
299 { SP_TMDS_CTRL_BASE + 7, 0x80 },
300 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
301 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
302 { SP_TMDS_CTRL_BASE + 23, 0x18 },
303};
304
305static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
306{
307 int err;
308
309 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
310 SP_AUD_MUTE | SP_VID_MUTE);
311 if (err)
312 return err;
313
314 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
315 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
316 SP_DIGITAL_CKDT_EN);
317 if (err)
318 return err;
319
320 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
321 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
322 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
323 if (err)
324 return err;
325
326 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
327 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
328 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
329 if (err)
330 return err;
331
332 /* Sync detect change, GP set mute */
333 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
334 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
335 BIT(6));
336 if (err)
337 return err;
338
339 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
340 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
341 SP_AEC_EN21);
342 if (err)
343 return err;
344
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
346 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
347 if (err)
348 return err;
349
350 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
351 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
352 if (err)
353 return err;
354
355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
356 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
357 if (err)
358 return err;
359
360 /* Enable DDC stretch */
361 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
362 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
363 if (err)
364 return err;
365
366 /* TMDS phy initialization */
367 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
368 tmds_phy_initialization,
369 ARRAY_SIZE(tmds_phy_initialization));
370 if (err)
371 return err;
372
373 err = anx78xx_clear_hpd(anx78xx);
374 if (err)
375 return err;
376
377 return 0;
378}
379
380static const u8 dp_tx_output_precise_tune_bits[20] = {
381 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
382 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
383 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
384};
385
386static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
387{
388 int err;
389
390 /*
391 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
392 * register.
393 */
394 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
395 0x02);
396 if (err)
397 return err;
398
399 /*
400 * Write DP TX output emphasis precise tune bits.
401 */
402 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
403 SP_DP_TX_LT_CTRL0_REG,
404 dp_tx_output_precise_tune_bits,
405 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
406
407 if (err)
408 return err;
409
410 return 0;
411}
412
413static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
414{
415 unsigned int value;
416 int err;
417
418 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
419 SP_ANALOG_DEBUG2_REG,
420 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
421 SP_XTAL_FRQ_27M);
422 if (err)
423 return err;
424
425 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
426 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
427 if (err)
428 return err;
429
430 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
431 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
432 if (err)
433 return err;
434
435 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
436 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
437 if (err)
438 return err;
439
440 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
441 SP_I2C_GEN_10US_TIMER1_REG,
442 (XTAL_CLK & 0xff00) >> 8);
443 if (err)
444 return err;
445
446 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
447 XTAL_CLK / 10 - 1);
448 if (err)
449 return err;
450
451 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
452 SP_HDMI_US_TIMER_CTRL_REG,
453 &value);
454 if (err)
455 return err;
456
457 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
458 SP_HDMI_US_TIMER_CTRL_REG,
459 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
460 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
461 if (err)
462 return err;
463
464 return 0;
465}
466
467static const struct reg_sequence otp_key_protect[] = {
468 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
469 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
470 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
471};
472
473static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
474{
475 int err;
476
477 /* Set terminal resistor to 50 ohm */
478 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
479 0x30);
480 if (err)
481 return err;
482
483 /* Enable aux double diff output */
484 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
485 SP_DP_AUX_CH_CTRL2_REG, 0x08);
486 if (err)
487 return err;
488
489 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
490 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
491 SP_AUTO_START);
492 if (err)
493 return err;
494
495 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
496 otp_key_protect,
497 ARRAY_SIZE(otp_key_protect));
498 if (err)
499 return err;
500
501 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
502 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
503 if (err)
504 return err;
505
506 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
507 SP_VID_VRES_TH);
508 if (err)
509 return err;
510
511 /*
512 * DP HDCP auto authentication wait timer (when downstream starts to
513 * auth, DP side will wait for this period then do auth automatically)
514 */
515 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
516 0x00);
517 if (err)
518 return err;
519
520 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
521 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
522 if (err)
523 return err;
524
525 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
526 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
527 if (err)
528 return err;
529
530 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
531 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
532 if (err)
533 return err;
534
535 err = anx78xx_xtal_clk_sel(anx78xx);
536 if (err)
537 return err;
538
539 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
540 SP_DEFER_CTRL_EN | 0x0c);
541 if (err)
542 return err;
543
544 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
545 SP_DP_POLLING_CTRL_REG,
546 SP_AUTO_POLLING_DISABLE);
547 if (err)
548 return err;
549
550 /*
551 * Short the link integrity check timer to speed up bstatus
552 * polling for HDCP CTS item 1A-07
553 */
554 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
555 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
556 if (err)
557 return err;
558
559 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
560 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
561 if (err)
562 return err;
563
564 /* Power down the main link by default */
565 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
566 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
567 if (err)
568 return err;
569
570 err = anx78xx_link_phy_initialization(anx78xx);
571 if (err)
572 return err;
573
574 /* Gen m_clk with downspreading */
575 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
576 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
577 if (err)
578 return err;
579
580 return 0;
581}
582
583static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
584{
585 int err;
586
587 /*
588 * BIT0: INT pin assertion polarity: 1 = assert high
589 * BIT1: INT pin output type: 0 = push/pull
590 */
591 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
592 if (err)
593 return err;
594
595 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
596 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
597 if (err)
598 return err;
599
600 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
601 SP_TRAINING_FINISH);
602 if (err)
603 return err;
604
605 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
606 SP_CKDT_CHG | SP_SCDT_CHG);
607 if (err)
608 return err;
609
610 return 0;
611}
612
613static void anx78xx_poweron(struct anx78xx *anx78xx)
614{
615 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
616 int err;
617
618 if (WARN_ON(anx78xx->powered))
619 return;
620
621 if (pdata->dvdd10) {
622 err = regulator_enable(pdata->dvdd10);
623 if (err) {
624 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
625 err);
626 return;
627 }
628
629 usleep_range(1000, 2000);
630 }
631
632 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
633 usleep_range(1000, 2000);
634
635 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
636 usleep_range(1000, 2000);
637
638 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
639
640 /* Power on registers module */
641 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
642 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
643 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
644 SP_REGISTER_PD | SP_TOTAL_PD);
645
646 anx78xx->powered = true;
647}
648
649static void anx78xx_poweroff(struct anx78xx *anx78xx)
650{
651 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
652 int err;
653
654 if (WARN_ON(!anx78xx->powered))
655 return;
656
657 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
658 usleep_range(1000, 2000);
659
660 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
661 usleep_range(1000, 2000);
662
663 if (pdata->dvdd10) {
664 err = regulator_disable(pdata->dvdd10);
665 if (err) {
666 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
667 err);
668 return;
669 }
670
671 usleep_range(1000, 2000);
672 }
673
674 anx78xx->powered = false;
675}
676
677static int anx78xx_start(struct anx78xx *anx78xx)
678{
679 int err;
680
681 /* Power on all modules */
682 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
683 SP_POWERDOWN_CTRL_REG,
684 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
685 SP_LINK_PD);
686
687 err = anx78xx_enable_interrupts(anx78xx);
688 if (err) {
689 DRM_ERROR("Failed to enable interrupts: %d\n", err);
690 goto err_poweroff;
691 }
692
693 err = anx78xx_rx_initialization(anx78xx);
694 if (err) {
695 DRM_ERROR("Failed receiver initialization: %d\n", err);
696 goto err_poweroff;
697 }
698
699 err = anx78xx_tx_initialization(anx78xx);
700 if (err) {
701 DRM_ERROR("Failed transmitter initialization: %d\n", err);
702 goto err_poweroff;
703 }
704
705 /*
706 * This delay seems to help keep the hardware in a good state. Without
707 * it, there are times where it fails silently.
708 */
709 usleep_range(10000, 15000);
710
711 return 0;
712
713err_poweroff:
714 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
715 anx78xx_poweroff(anx78xx);
716
717 return err;
718}
719
720static int anx78xx_init_pdata(struct anx78xx *anx78xx)
721{
722 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
723 struct device *dev = &anx78xx->client->dev;
724
725 /* 1.0V digital core power regulator */
726 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
727 if (IS_ERR(pdata->dvdd10)) {
728 DRM_ERROR("DVDD10 regulator not found\n");
729 return PTR_ERR(pdata->dvdd10);
730 }
731
732 /* GPIO for HPD */
733 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
734 if (IS_ERR(pdata->gpiod_hpd))
735 return PTR_ERR(pdata->gpiod_hpd);
736
737 /* GPIO for chip power down */
738 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
739 if (IS_ERR(pdata->gpiod_pd))
740 return PTR_ERR(pdata->gpiod_pd);
741
742 /* GPIO for chip reset */
743 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
744
745 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
746}
747
748static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
749{
750 u8 dp_bw, value;
751 int err;
752
753 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
754 0x0);
755 if (err)
756 return err;
757
758 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
759 SP_POWERDOWN_CTRL_REG,
760 SP_TOTAL_PD);
761 if (err)
762 return err;
763
764 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
765 if (err < 0)
766 return err;
767
768 switch (dp_bw) {
769 case DP_LINK_BW_1_62:
770 case DP_LINK_BW_2_7:
771 case DP_LINK_BW_5_4:
772 break;
773
774 default:
775 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
776 return -EINVAL;
777 }
778
779 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
780 SP_VIDEO_MUTE);
781 if (err)
782 return err;
783
784 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
785 SP_VID_CTRL1_REG, SP_VIDEO_EN);
786 if (err)
787 return err;
788
789 /* Get DPCD info */
790 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
791 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
792 if (err < 0) {
793 DRM_ERROR("Failed to read DPCD: %d\n", err);
794 return err;
795 }
796
797 /* Clear channel x SERDES power down */
798 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
799 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
800 if (err)
801 return err;
802
803 /* Check link capabilities */
804 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
805 if (err < 0) {
806 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
807 return err;
808 }
809
810 /* Power up the sink */
811 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
812 if (err < 0) {
813 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
814 return err;
815 }
816
817 /* Possibly enable downspread on the sink */
818 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
819 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
820 if (err)
821 return err;
822
823 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
824 DRM_DEBUG("Enable downspread on the sink\n");
825 /* 4000PPM */
826 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
827 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
828 if (err)
829 return err;
830
831 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
832 DP_SPREAD_AMP_0_5);
833 if (err < 0)
834 return err;
835 } else {
836 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
837 if (err < 0)
838 return err;
839 }
840
841 /* Set the lane count and the link rate on the sink */
842 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
843 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
844 SP_DP_SYSTEM_CTRL_BASE + 4,
845 SP_ENHANCED_MODE);
846 else
847 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
848 SP_DP_SYSTEM_CTRL_BASE + 4,
849 SP_ENHANCED_MODE);
850 if (err)
851 return err;
852
853 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
854 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
855 SP_DP_MAIN_LINK_BW_SET_REG, value);
856 if (err)
857 return err;
858
859 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
860 if (err < 0) {
861 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
862 return err;
863 }
864
865 /* Start training on the source */
866 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
867 SP_LT_EN);
868 if (err)
869 return err;
870
871 return 0;
872}
873
874static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
875{
876 int err;
877
878 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
879 SP_VIDEO_MUTE);
880 if (err)
881 return err;
882
883 /* Enable DP output */
884 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
885 SP_VIDEO_EN);
886 if (err)
887 return err;
888
889 return 0;
890}
891
892static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
893 struct hdmi_avi_infoframe *frame)
894{
895 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
896 int err;
897
898 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
899 if (err < 0) {
900 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
901 return err;
902 }
903
904 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
905 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
906 if (err)
907 return err;
908
909 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
910 SP_INFOFRAME_AVI_DB1_REG, buffer,
911 frame->length);
912 if (err)
913 return err;
914
915 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
916 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
917 if (err)
918 return err;
919
920 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
921 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
922 if (err)
923 return err;
924
925 return 0;
926}
927
928static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
929{
930 u8 value;
931 int err;
932
933 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
934 if (err < 0) {
935 DRM_ERROR("Get sink count failed %d\n", err);
936 return err;
937 }
938
939 if (!DP_GET_SINK_COUNT(value)) {
940 DRM_ERROR("Downstream disconnected\n");
941 return -EIO;
942 }
943
944 return 0;
945}
946
947static int anx78xx_get_modes(struct drm_connector *connector)
948{
949 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
950 int err, num_modes = 0;
951
952 if (WARN_ON(!anx78xx->powered))
953 return 0;
954
955 if (anx78xx->edid)
956 return drm_add_edid_modes(connector, anx78xx->edid);
957
958 mutex_lock(&anx78xx->lock);
959
960 err = anx78xx_get_downstream_info(anx78xx);
961 if (err) {
962 DRM_ERROR("Failed to get downstream info: %d\n", err);
963 goto unlock;
964 }
965
966 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
967 if (!anx78xx->edid) {
968 DRM_ERROR("Failed to read EDID\n");
969 goto unlock;
970 }
971
972 err = drm_mode_connector_update_edid_property(connector,
973 anx78xx->edid);
974 if (err) {
975 DRM_ERROR("Failed to update EDID property: %d\n", err);
976 goto unlock;
977 }
978
979 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
980
981unlock:
982 mutex_unlock(&anx78xx->lock);
983
984 return num_modes;
985}
986
987static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
988 .get_modes = anx78xx_get_modes,
989};
990
991static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
992 bool force)
993{
994 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
995
996 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
997 return connector_status_disconnected;
998
999 return connector_status_connected;
1000}
1001
1002static const struct drm_connector_funcs anx78xx_connector_funcs = {
1003 .fill_modes = drm_helper_probe_single_connector_modes,
1004 .detect = anx78xx_detect,
1005 .destroy = drm_connector_cleanup,
1006 .reset = drm_atomic_helper_connector_reset,
1007 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1008 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1009};
1010
1011static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1012{
1013 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1014 int err;
1015
1016 if (!bridge->encoder) {
1017 DRM_ERROR("Parent encoder object not found");
1018 return -ENODEV;
1019 }
1020
1021 /* Register aux channel */
1022 anx78xx->aux.name = "DP-AUX";
1023 anx78xx->aux.dev = &anx78xx->client->dev;
1024 anx78xx->aux.transfer = anx78xx_aux_transfer;
1025
1026 err = drm_dp_aux_register(&anx78xx->aux);
1027 if (err < 0) {
1028 DRM_ERROR("Failed to register aux channel: %d\n", err);
1029 return err;
1030 }
1031
1032 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1033 &anx78xx_connector_funcs,
1034 DRM_MODE_CONNECTOR_DisplayPort);
1035 if (err) {
1036 DRM_ERROR("Failed to initialize connector: %d\n", err);
1037 return err;
1038 }
1039
1040 drm_connector_helper_add(&anx78xx->connector,
1041 &anx78xx_connector_helper_funcs);
1042
1043 err = drm_connector_register(&anx78xx->connector);
1044 if (err) {
1045 DRM_ERROR("Failed to register connector: %d\n", err);
1046 return err;
1047 }
1048
1049 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1050
1051 err = drm_mode_connector_attach_encoder(&anx78xx->connector,
1052 bridge->encoder);
1053 if (err) {
1054 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1055 return err;
1056 }
1057
1058 return 0;
1059}
1060
1061static enum drm_mode_status
1062anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1063 const struct drm_display_mode *mode)
1064{
1065 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1066 return MODE_NO_INTERLACE;
1067
1068 /* Max 1200p at 5.4 Ghz, one lane */
1069 if (mode->clock > 154000)
1070 return MODE_CLOCK_HIGH;
1071
1072 return MODE_OK;
1073}
1074
1075static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1076{
1077 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1078
1079 /* Power off all modules except configuration registers access */
1080 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1081 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1082}
1083
1084static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1085 struct drm_display_mode *mode,
1086 struct drm_display_mode *adjusted_mode)
1087{
1088 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1089 struct hdmi_avi_infoframe frame;
1090 int err;
1091
1092 if (WARN_ON(!anx78xx->powered))
1093 return;
1094
1095 mutex_lock(&anx78xx->lock);
1096
1097 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, adjusted_mode,
1098 false);
1099 if (err) {
1100 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1101 goto unlock;
1102 }
1103
1104 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1105 if (err)
1106 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1107
1108unlock:
1109 mutex_unlock(&anx78xx->lock);
1110}
1111
1112static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1113{
1114 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1115 int err;
1116
1117 err = anx78xx_start(anx78xx);
1118 if (err) {
1119 DRM_ERROR("Failed to initialize: %d\n", err);
1120 return;
1121 }
1122
1123 err = anx78xx_set_hpd(anx78xx);
1124 if (err)
1125 DRM_ERROR("Failed to set HPD: %d\n", err);
1126}
1127
1128static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1129 .attach = anx78xx_bridge_attach,
1130 .mode_valid = anx78xx_bridge_mode_valid,
1131 .disable = anx78xx_bridge_disable,
1132 .mode_set = anx78xx_bridge_mode_set,
1133 .enable = anx78xx_bridge_enable,
1134};
1135
1136static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1137{
1138 struct anx78xx *anx78xx = data;
1139 int err;
1140
1141 if (anx78xx->powered)
1142 return IRQ_HANDLED;
1143
1144 mutex_lock(&anx78xx->lock);
1145
1146 /* Cable is pulled, power on the chip */
1147 anx78xx_poweron(anx78xx);
1148
1149 err = anx78xx_enable_interrupts(anx78xx);
1150 if (err)
1151 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1152
1153 mutex_unlock(&anx78xx->lock);
1154
1155 return IRQ_HANDLED;
1156}
1157
1158static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1159{
1160 int err;
1161
1162 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1163
1164 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1165 irq);
1166 if (err)
1167 return err;
1168
1169 if (irq & SP_TRAINING_FINISH) {
1170 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1171 err = anx78xx_config_dp_output(anx78xx);
1172 }
1173
1174 return err;
1175}
1176
1177static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1178{
1179 bool event = false;
1180 int err;
1181
1182 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1183
1184 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1185 SP_COMMON_INT_STATUS4_REG, irq);
1186 if (err) {
1187 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1188 return event;
1189 }
1190
1191 if (irq & SP_HPD_LOST) {
1192 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1193 event = true;
1194 anx78xx_poweroff(anx78xx);
1195 /* Free cached EDID */
1196 kfree(anx78xx->edid);
1197 anx78xx->edid = NULL;
1198 } else if (irq & SP_HPD_PLUG) {
1199 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1200 event = true;
1201 }
1202
1203 return event;
1204}
1205
1206static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1207{
1208 unsigned int value;
1209 int err;
1210
1211 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1212
1213 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1214 irq);
1215 if (err) {
1216 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1217 return;
1218 }
1219
1220 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1221 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1222
1223 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1224 SP_SYSTEM_STATUS_REG, &value);
1225 if (err) {
1226 DRM_ERROR("Read system status reg failed: %d\n", err);
1227 return;
1228 }
1229
1230 if (!(value & SP_TMDS_CLOCK_DET)) {
1231 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1232 return;
1233 }
1234
1235 if (!(value & SP_TMDS_DE_DET)) {
1236 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1237 return;
1238 }
1239
1240 err = anx78xx_dp_link_training(anx78xx);
1241 if (err)
1242 DRM_ERROR("Failed to start link training: %d\n", err);
1243 }
1244}
1245
1246static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1247{
1248 struct anx78xx *anx78xx = data;
1249 bool event = false;
1250 unsigned int irq;
1251 int err;
1252
1253 mutex_lock(&anx78xx->lock);
1254
1255 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1256 &irq);
1257 if (err) {
1258 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1259 goto unlock;
1260 }
1261
1262 if (irq)
1263 anx78xx_handle_dp_int_1(anx78xx, irq);
1264
1265 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1266 SP_COMMON_INT_STATUS4_REG, &irq);
1267 if (err) {
1268 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1269 err);
1270 goto unlock;
1271 }
1272
1273 if (irq)
1274 event = anx78xx_handle_common_int_4(anx78xx, irq);
1275
1276 /* Make sure we are still powered after handle HPD events */
1277 if (!anx78xx->powered)
1278 goto unlock;
1279
1280 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1281 &irq);
1282 if (err) {
1283 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1284 goto unlock;
1285 }
1286
1287 if (irq)
1288 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1289
1290unlock:
1291 mutex_unlock(&anx78xx->lock);
1292
1293 if (event)
1294 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1295
1296 return IRQ_HANDLED;
1297}
1298
1299static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1300{
1301 unsigned int i;
1302
1303 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1304 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1305}
1306
1307static const struct regmap_config anx78xx_regmap_config = {
1308 .reg_bits = 8,
1309 .val_bits = 8,
1310};
1311
1312static const u16 anx78xx_chipid_list[] = {
1313 0x7812,
1314 0x7814,
1315 0x7818,
1316};
1317
1318static int anx78xx_i2c_probe(struct i2c_client *client,
1319 const struct i2c_device_id *id)
1320{
1321 struct anx78xx *anx78xx;
1322 struct anx78xx_platform_data *pdata;
1323 unsigned int i, idl, idh, version;
1324 bool found = false;
1325 int err;
1326
1327 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1328 if (!anx78xx)
1329 return -ENOMEM;
1330
1331 pdata = &anx78xx->pdata;
1332
1333 mutex_init(&anx78xx->lock);
1334
1335#if IS_ENABLED(CONFIG_OF)
1336 anx78xx->bridge.of_node = client->dev.of_node;
1337#endif
1338
1339 anx78xx->client = client;
1340 i2c_set_clientdata(client, anx78xx);
1341
1342 err = anx78xx_init_pdata(anx78xx);
1343 if (err) {
1344 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1345 return err;
1346 }
1347
1348 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1349 if (pdata->hpd_irq < 0) {
1350 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1351 return -ENODEV;
1352 }
1353
1354 pdata->intp_irq = client->irq;
1355 if (!pdata->intp_irq) {
1356 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1357 return -ENODEV;
1358 }
1359
1360 /* Map slave addresses of ANX7814 */
1361 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1362 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1363 anx78xx_i2c_addresses[i] >> 1);
1364 if (!anx78xx->i2c_dummy[i]) {
1365 err = -ENOMEM;
1366 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1367 anx78xx_i2c_addresses[i]);
1368 goto err_unregister_i2c;
1369 }
1370
1371 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1372 &anx78xx_regmap_config);
1373 if (IS_ERR(anx78xx->map[i])) {
1374 err = PTR_ERR(anx78xx->map[i]);
1375 DRM_ERROR("Failed regmap initialization %02x\n",
1376 anx78xx_i2c_addresses[i]);
1377 goto err_unregister_i2c;
1378 }
1379 }
1380
1381 /* Look for supported chip ID */
1382 anx78xx_poweron(anx78xx);
1383
1384 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1385 &idl);
1386 if (err)
1387 goto err_poweroff;
1388
1389 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1390 &idh);
1391 if (err)
1392 goto err_poweroff;
1393
1394 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1395
1396 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1397 &version);
1398 if (err)
1399 goto err_poweroff;
1400
1401 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1402 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1403 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1404 anx78xx->chipid, version);
1405 found = true;
1406 break;
1407 }
1408 }
1409
1410 if (!found) {
1411 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1412 anx78xx->chipid, version);
1413 err = -ENODEV;
1414 goto err_poweroff;
1415 }
1416
1417 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1418 anx78xx_hpd_threaded_handler,
1419 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1420 "anx78xx-hpd", anx78xx);
1421 if (err) {
1422 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1423 err);
1424 goto err_poweroff;
1425 }
1426
1427 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1428 anx78xx_intp_threaded_handler,
1429 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1430 "anx78xx-intp", anx78xx);
1431 if (err) {
1432 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1433 goto err_poweroff;
1434 }
1435
1436 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1437
1438 drm_bridge_add(&anx78xx->bridge);
1439
1440 /* If cable is pulled out, just poweroff and wait for HPD event */
1441 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1442 anx78xx_poweroff(anx78xx);
1443
1444 return 0;
1445
1446err_poweroff:
1447 anx78xx_poweroff(anx78xx);
1448
1449err_unregister_i2c:
1450 unregister_i2c_dummy_clients(anx78xx);
1451 return err;
1452}
1453
1454static int anx78xx_i2c_remove(struct i2c_client *client)
1455{
1456 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1457
1458 drm_bridge_remove(&anx78xx->bridge);
1459
1460 unregister_i2c_dummy_clients(anx78xx);
1461
1462 kfree(anx78xx->edid);
1463
1464 return 0;
1465}
1466
1467static const struct i2c_device_id anx78xx_id[] = {
1468 { "anx7814", 0 },
1469 { /* sentinel */ }
1470};
1471MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1472
1473#if IS_ENABLED(CONFIG_OF)
1474static const struct of_device_id anx78xx_match_table[] = {
1475 { .compatible = "analogix,anx7814", },
1476 { /* sentinel */ },
1477};
1478MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1479#endif
1480
1481static struct i2c_driver anx78xx_driver = {
1482 .driver = {
1483 .name = "anx7814",
1484 .of_match_table = of_match_ptr(anx78xx_match_table),
1485 },
1486 .probe = anx78xx_i2c_probe,
1487 .remove = anx78xx_i2c_remove,
1488 .id_table = anx78xx_id,
1489};
1490module_i2c_driver(anx78xx_driver);
1491
1492MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1493MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1494MODULE_LICENSE("GPL v2");