1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#ifndef _DM_PP_INTERFACE_
 24#define _DM_PP_INTERFACE_
 25
 26#define PP_MAX_CLOCK_LEVELS 16
 27
 28enum amd_pp_display_config_type{
 29	AMD_PP_DisplayConfigType_None = 0,
 30	AMD_PP_DisplayConfigType_DP54 ,
 31	AMD_PP_DisplayConfigType_DP432 ,
 32	AMD_PP_DisplayConfigType_DP324 ,
 33	AMD_PP_DisplayConfigType_DP27,
 34	AMD_PP_DisplayConfigType_DP243,
 35	AMD_PP_DisplayConfigType_DP216,
 36	AMD_PP_DisplayConfigType_DP162,
 37	AMD_PP_DisplayConfigType_HDMI6G ,
 38	AMD_PP_DisplayConfigType_HDMI297 ,
 39	AMD_PP_DisplayConfigType_HDMI162,
 40	AMD_PP_DisplayConfigType_LVDS,
 41	AMD_PP_DisplayConfigType_DVI,
 42	AMD_PP_DisplayConfigType_WIRELESS,
 43	AMD_PP_DisplayConfigType_VGA
 44};
 45
 46struct single_display_configuration
 47{
 48	uint32_t controller_index;
 49	uint32_t controller_id;
 50	uint32_t signal_type;
 51	uint32_t display_state;
 52	/* phy id for the primary internal transmitter */
 53	uint8_t primary_transmitter_phyi_d;
 54	/* bitmap with the active lanes */
 55	uint8_t primary_transmitter_active_lanemap;
 56	/* phy id for the secondary internal transmitter (for dual-link dvi) */
 57	uint8_t secondary_transmitter_phy_id;
 58	/* bitmap with the active lanes */
 59	uint8_t secondary_transmitter_active_lanemap;
 60	/* misc phy settings for SMU. */
 61	uint32_t config_flags;
 62	uint32_t display_type;
 63	uint32_t view_resolution_cx;
 64	uint32_t view_resolution_cy;
 65	enum amd_pp_display_config_type displayconfigtype;
 66	uint32_t vertical_refresh; /* for active display */
 67};
 68
 69#define MAX_NUM_DISPLAY 32
 70
 71struct amd_pp_display_configuration {
 72	bool nb_pstate_switch_disable;/* controls NB PState switch */
 73	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 74	bool cpu_pstate_disable;
 75	uint32_t cpu_pstate_separation_time;
 76
 77	uint32_t num_display;  /* total number of display*/
 78	uint32_t num_path_including_non_display;
 79	uint32_t crossfire_display_index;
 80	uint32_t min_mem_set_clock;
 81	uint32_t min_core_set_clock;
 82	/* unit 10KHz x bit*/
 83	uint32_t min_bus_bandwidth;
 84	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
 85	uint32_t min_core_set_clock_in_sr;
 86
 87	struct single_display_configuration displays[MAX_NUM_DISPLAY];
 88
 89	uint32_t vrefresh; /* for active display*/
 90
 91	uint32_t min_vblank_time; /* for active display*/
 92	bool multi_monitor_in_sync;
 93	/* Controller Index of primary display - used in MCLK SMC switching hang
 94	 * SW Workaround*/
 95	uint32_t crtc_index;
 96	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 97	uint32_t line_time_in_us;
 98	bool invalid_vblank_time;
 99
100	uint32_t display_clk;
101	/*
102	 * for given display configuration if multimonitormnsync == false then
103	 * Memory clock DPMS with this latency or below is allowed, DPMS with
104	 * higher latency not allowed.
105	 */
106	uint32_t dce_tolerable_mclk_in_active_latency;
107	uint32_t min_dcef_set_clk;
108	uint32_t min_dcef_deep_sleep_set_clk;
109};
110
111struct amd_pp_simple_clock_info {
112	uint32_t	engine_max_clock;
113	uint32_t	memory_max_clock;
114	uint32_t	level;
115};
116
117enum PP_DAL_POWERLEVEL {
118	PP_DAL_POWERLEVEL_INVALID = 0,
119	PP_DAL_POWERLEVEL_ULTRALOW,
120	PP_DAL_POWERLEVEL_LOW,
121	PP_DAL_POWERLEVEL_NOMINAL,
122	PP_DAL_POWERLEVEL_PERFORMANCE,
123
124	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
125	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
126	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
127	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
128	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
129	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
130	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
131	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
132};
133
134struct amd_pp_clock_info {
135	uint32_t min_engine_clock;
136	uint32_t max_engine_clock;
137	uint32_t min_memory_clock;
138	uint32_t max_memory_clock;
139	uint32_t min_bus_bandwidth;
140	uint32_t max_bus_bandwidth;
141	uint32_t max_engine_clock_in_sr;
142	uint32_t min_engine_clock_in_sr;
143	enum PP_DAL_POWERLEVEL max_clocks_state;
144};
145
146enum amd_pp_clock_type {
147	amd_pp_disp_clock = 1,
148	amd_pp_sys_clock,
149	amd_pp_mem_clock,
150	amd_pp_dcef_clock,
151	amd_pp_soc_clock,
152	amd_pp_pixel_clock,
153	amd_pp_phy_clock,
154	amd_pp_dcf_clock,
155	amd_pp_dpp_clock,
156	amd_pp_f_clock = amd_pp_dcef_clock,
157};
158
159#define MAX_NUM_CLOCKS 16
160
161struct amd_pp_clocks {
162	uint32_t count;
163	uint32_t clock[MAX_NUM_CLOCKS];
164	uint32_t latency[MAX_NUM_CLOCKS];
165};
166
167struct pp_clock_with_latency {
168	uint32_t clocks_in_khz;
169	uint32_t latency_in_us;
170};
171
172struct pp_clock_levels_with_latency {
173	uint32_t num_levels;
174	struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
175};
176
177struct pp_clock_with_voltage {
178	uint32_t clocks_in_khz;
179	uint32_t voltage_in_mv;
180};
181
182struct pp_clock_levels_with_voltage {
183	uint32_t num_levels;
184	struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
185};
186
187struct pp_display_clock_request {
188	enum amd_pp_clock_type clock_type;
189	uint32_t clock_freq_in_khz;
190};
191
192#define PP_MAX_WM_SETS 4
193
194enum pp_wm_set_id {
195	DC_WM_SET_A = 0,
196	DC_WM_SET_B,
197	DC_WM_SET_C,
198	DC_WM_SET_D,
199	DC_WM_SET_INVALID = 0xffff,
200};
201
202struct pp_wm_set_with_dmif_clock_range_soc15 {
203	enum pp_wm_set_id wm_set_id;
204	uint32_t wm_min_dcefclk_in_khz;
205	uint32_t wm_max_dcefclk_in_khz;
206	uint32_t wm_min_memclk_in_khz;
207	uint32_t wm_max_memclk_in_khz;
208};
209
210struct pp_wm_set_with_mcif_clock_range_soc15 {
211	enum pp_wm_set_id wm_set_id;
212	uint32_t wm_min_socclk_in_khz;
213	uint32_t wm_max_socclk_in_khz;
214	uint32_t wm_min_memclk_in_khz;
215	uint32_t wm_max_memclk_in_khz;
216};
217
218struct pp_wm_sets_with_clock_ranges_soc15 {
219	uint32_t num_wm_sets_dmif;
220	uint32_t num_wm_sets_mcif;
221	struct pp_wm_set_with_dmif_clock_range_soc15
222		wm_sets_dmif[PP_MAX_WM_SETS];
223	struct pp_wm_set_with_mcif_clock_range_soc15
224		wm_sets_mcif[PP_MAX_WM_SETS];
225};
226
227#endif /* _DM_PP_INTERFACE_ */