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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_uvd.h"
29#include "vid.h"
30#include "uvd/uvd_5_0_d.h"
31#include "uvd/uvd_5_0_sh_mask.h"
32#include "oss/oss_2_0_d.h"
33#include "oss/oss_2_0_sh_mask.h"
34
35static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
36static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
37static int uvd_v5_0_start(struct amdgpu_device *adev);
38static void uvd_v5_0_stop(struct amdgpu_device *adev);
39
40/**
41 * uvd_v5_0_ring_get_rptr - get read pointer
42 *
43 * @ring: amdgpu_ring pointer
44 *
45 * Returns the current hardware read pointer
46 */
47static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
48{
49 struct amdgpu_device *adev = ring->adev;
50
51 return RREG32(mmUVD_RBC_RB_RPTR);
52}
53
54/**
55 * uvd_v5_0_ring_get_wptr - get write pointer
56 *
57 * @ring: amdgpu_ring pointer
58 *
59 * Returns the current hardware write pointer
60 */
61static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
62{
63 struct amdgpu_device *adev = ring->adev;
64
65 return RREG32(mmUVD_RBC_RB_WPTR);
66}
67
68/**
69 * uvd_v5_0_ring_set_wptr - set write pointer
70 *
71 * @ring: amdgpu_ring pointer
72 *
73 * Commits the write pointer to the hardware
74 */
75static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
76{
77 struct amdgpu_device *adev = ring->adev;
78
79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
80}
81
82static int uvd_v5_0_early_init(void *handle)
83{
84 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85
86 uvd_v5_0_set_ring_funcs(adev);
87 uvd_v5_0_set_irq_funcs(adev);
88
89 return 0;
90}
91
92static int uvd_v5_0_sw_init(void *handle)
93{
94 struct amdgpu_ring *ring;
95 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
96 int r;
97
98 /* UVD TRAP */
99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
100 if (r)
101 return r;
102
103 r = amdgpu_uvd_sw_init(adev);
104 if (r)
105 return r;
106
107 r = amdgpu_uvd_resume(adev);
108 if (r)
109 return r;
110
111 ring = &adev->uvd.ring;
112 sprintf(ring->name, "uvd");
113 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
115
116 return r;
117}
118
119static int uvd_v5_0_sw_fini(void *handle)
120{
121 int r;
122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
123
124 r = amdgpu_uvd_suspend(adev);
125 if (r)
126 return r;
127
128 r = amdgpu_uvd_sw_fini(adev);
129 if (r)
130 return r;
131
132 return r;
133}
134
135/**
136 * uvd_v5_0_hw_init - start and test UVD block
137 *
138 * @adev: amdgpu_device pointer
139 *
140 * Initialize the hardware, boot up the VCPU and do some testing
141 */
142static int uvd_v5_0_hw_init(void *handle)
143{
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
145 struct amdgpu_ring *ring = &adev->uvd.ring;
146 uint32_t tmp;
147 int r;
148
149 /* raise clocks while booting up the VCPU */
150 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
151
152 r = uvd_v5_0_start(adev);
153 if (r)
154 goto done;
155
156 ring->ready = true;
157 r = amdgpu_ring_test_ring(ring);
158 if (r) {
159 ring->ready = false;
160 goto done;
161 }
162
163 r = amdgpu_ring_alloc(ring, 10);
164 if (r) {
165 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
166 goto done;
167 }
168
169 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
170 amdgpu_ring_write(ring, tmp);
171 amdgpu_ring_write(ring, 0xFFFFF);
172
173 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
174 amdgpu_ring_write(ring, tmp);
175 amdgpu_ring_write(ring, 0xFFFFF);
176
177 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
178 amdgpu_ring_write(ring, tmp);
179 amdgpu_ring_write(ring, 0xFFFFF);
180
181 /* Clear timeout status bits */
182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
183 amdgpu_ring_write(ring, 0x8);
184
185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
186 amdgpu_ring_write(ring, 3);
187
188 amdgpu_ring_commit(ring);
189
190done:
191 /* lower clocks again */
192 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
193
194 if (!r)
195 DRM_INFO("UVD initialized successfully.\n");
196
197 return r;
198}
199
200/**
201 * uvd_v5_0_hw_fini - stop the hardware block
202 *
203 * @adev: amdgpu_device pointer
204 *
205 * Stop the UVD block, mark ring as not ready any more
206 */
207static int uvd_v5_0_hw_fini(void *handle)
208{
209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
210 struct amdgpu_ring *ring = &adev->uvd.ring;
211
212 uvd_v5_0_stop(adev);
213 ring->ready = false;
214
215 return 0;
216}
217
218static int uvd_v5_0_suspend(void *handle)
219{
220 int r;
221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
222
223 r = uvd_v5_0_hw_fini(adev);
224 if (r)
225 return r;
226
227 r = amdgpu_uvd_suspend(adev);
228 if (r)
229 return r;
230
231 return r;
232}
233
234static int uvd_v5_0_resume(void *handle)
235{
236 int r;
237 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
238
239 r = amdgpu_uvd_resume(adev);
240 if (r)
241 return r;
242
243 r = uvd_v5_0_hw_init(adev);
244 if (r)
245 return r;
246
247 return r;
248}
249
250/**
251 * uvd_v5_0_mc_resume - memory controller programming
252 *
253 * @adev: amdgpu_device pointer
254 *
255 * Let the UVD memory controller know it's offsets
256 */
257static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
258{
259 uint64_t offset;
260 uint32_t size;
261
262 /* programm memory controller bits 0-27 */
263 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
264 lower_32_bits(adev->uvd.gpu_addr));
265 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
266 upper_32_bits(adev->uvd.gpu_addr));
267
268 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
269 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
270 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
271 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
272
273 offset += size;
274 size = AMDGPU_UVD_STACK_SIZE;
275 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
276 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
277
278 offset += size;
279 size = AMDGPU_UVD_HEAP_SIZE;
280 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
281 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
282
283 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
284 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
285 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
286}
287
288/**
289 * uvd_v5_0_start - start UVD block
290 *
291 * @adev: amdgpu_device pointer
292 *
293 * Setup and start the UVD block
294 */
295static int uvd_v5_0_start(struct amdgpu_device *adev)
296{
297 struct amdgpu_ring *ring = &adev->uvd.ring;
298 uint32_t rb_bufsz, tmp;
299 uint32_t lmi_swap_cntl;
300 uint32_t mp_swap_cntl;
301 int i, j, r;
302
303 /*disable DPG */
304 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
305
306 /* disable byte swapping */
307 lmi_swap_cntl = 0;
308 mp_swap_cntl = 0;
309
310 uvd_v5_0_mc_resume(adev);
311
312 /* disable clock gating */
313 WREG32(mmUVD_CGC_GATE, 0);
314
315 /* disable interupt */
316 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
317
318 /* stall UMC and register bus before resetting VCPU */
319 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
320 mdelay(1);
321
322 /* put LMI, VCPU, RBC etc... into reset */
323 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
324 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
325 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
326 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
327 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
328 mdelay(5);
329
330 /* take UVD block out of reset */
331 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
332 mdelay(5);
333
334 /* initialize UVD memory controller */
335 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
336 (1 << 21) | (1 << 9) | (1 << 20));
337
338#ifdef __BIG_ENDIAN
339 /* swap (8 in 32) RB and IB */
340 lmi_swap_cntl = 0xa;
341 mp_swap_cntl = 0;
342#endif
343 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
344 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
345
346 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
347 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
348 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
349 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
350 WREG32(mmUVD_MPC_SET_ALU, 0);
351 WREG32(mmUVD_MPC_SET_MUX, 0x88);
352
353 /* take all subblocks out of reset, except VCPU */
354 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
355 mdelay(5);
356
357 /* enable VCPU clock */
358 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
359
360 /* enable UMC */
361 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
362
363 /* boot up the VCPU */
364 WREG32(mmUVD_SOFT_RESET, 0);
365 mdelay(10);
366
367 for (i = 0; i < 10; ++i) {
368 uint32_t status;
369 for (j = 0; j < 100; ++j) {
370 status = RREG32(mmUVD_STATUS);
371 if (status & 2)
372 break;
373 mdelay(10);
374 }
375 r = 0;
376 if (status & 2)
377 break;
378
379 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
380 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
381 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
382 mdelay(10);
383 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
384 mdelay(10);
385 r = -1;
386 }
387
388 if (r) {
389 DRM_ERROR("UVD not responding, giving up!!!\n");
390 return r;
391 }
392 /* enable master interrupt */
393 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
394
395 /* clear the bit 4 of UVD_STATUS */
396 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
397
398 rb_bufsz = order_base_2(ring->ring_size);
399 tmp = 0;
400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
401 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
402 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
403 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
404 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
405 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
406 /* force RBC into idle state */
407 WREG32(mmUVD_RBC_RB_CNTL, tmp);
408
409 /* set the write pointer delay */
410 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
411
412 /* set the wb address */
413 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
414
415 /* programm the RB_BASE for ring buffer */
416 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
417 lower_32_bits(ring->gpu_addr));
418 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
419 upper_32_bits(ring->gpu_addr));
420
421 /* Initialize the ring buffer's read and write pointers */
422 WREG32(mmUVD_RBC_RB_RPTR, 0);
423
424 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
425 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
426
427 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
428
429 return 0;
430}
431
432/**
433 * uvd_v5_0_stop - stop UVD block
434 *
435 * @adev: amdgpu_device pointer
436 *
437 * stop the UVD block
438 */
439static void uvd_v5_0_stop(struct amdgpu_device *adev)
440{
441 /* force RBC into idle state */
442 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
443
444 /* Stall UMC and register bus before resetting VCPU */
445 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
446 mdelay(1);
447
448 /* put VCPU into reset */
449 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
450 mdelay(5);
451
452 /* disable VCPU clock */
453 WREG32(mmUVD_VCPU_CNTL, 0x0);
454
455 /* Unstall UMC and register bus */
456 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
457}
458
459/**
460 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
461 *
462 * @ring: amdgpu_ring pointer
463 * @fence: fence to emit
464 *
465 * Write a fence and a trap command to the ring.
466 */
467static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
468 unsigned flags)
469{
470 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
471
472 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
473 amdgpu_ring_write(ring, seq);
474 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
475 amdgpu_ring_write(ring, addr & 0xffffffff);
476 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
477 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
478 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
479 amdgpu_ring_write(ring, 0);
480
481 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
482 amdgpu_ring_write(ring, 0);
483 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
484 amdgpu_ring_write(ring, 0);
485 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
486 amdgpu_ring_write(ring, 2);
487}
488
489/**
490 * uvd_v5_0_ring_test_ring - register write test
491 *
492 * @ring: amdgpu_ring pointer
493 *
494 * Test if we can successfully write to the context register
495 */
496static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
497{
498 struct amdgpu_device *adev = ring->adev;
499 uint32_t tmp = 0;
500 unsigned i;
501 int r;
502
503 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
504 r = amdgpu_ring_alloc(ring, 3);
505 if (r) {
506 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
507 ring->idx, r);
508 return r;
509 }
510 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
511 amdgpu_ring_write(ring, 0xDEADBEEF);
512 amdgpu_ring_commit(ring);
513 for (i = 0; i < adev->usec_timeout; i++) {
514 tmp = RREG32(mmUVD_CONTEXT_ID);
515 if (tmp == 0xDEADBEEF)
516 break;
517 DRM_UDELAY(1);
518 }
519
520 if (i < adev->usec_timeout) {
521 DRM_INFO("ring test on %d succeeded in %d usecs\n",
522 ring->idx, i);
523 } else {
524 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
525 ring->idx, tmp);
526 r = -EINVAL;
527 }
528 return r;
529}
530
531/**
532 * uvd_v5_0_ring_emit_ib - execute indirect buffer
533 *
534 * @ring: amdgpu_ring pointer
535 * @ib: indirect buffer to execute
536 *
537 * Write ring commands to execute the indirect buffer
538 */
539static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
540 struct amdgpu_ib *ib)
541{
542 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
543 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
544 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
545 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
546 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
547 amdgpu_ring_write(ring, ib->length_dw);
548}
549
550/**
551 * uvd_v5_0_ring_test_ib - test ib execution
552 *
553 * @ring: amdgpu_ring pointer
554 *
555 * Test if we can successfully execute an IB
556 */
557static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring)
558{
559 struct amdgpu_device *adev = ring->adev;
560 struct fence *fence = NULL;
561 int r;
562
563 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
564 if (r) {
565 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
566 return r;
567 }
568
569 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
570 if (r) {
571 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
572 goto error;
573 }
574
575 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
576 if (r) {
577 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
578 goto error;
579 }
580
581 r = fence_wait(fence, false);
582 if (r) {
583 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
584 goto error;
585 }
586 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
587error:
588 fence_put(fence);
589 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
590 return r;
591}
592
593static bool uvd_v5_0_is_idle(void *handle)
594{
595 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
596
597 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
598}
599
600static int uvd_v5_0_wait_for_idle(void *handle)
601{
602 unsigned i;
603 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
604
605 for (i = 0; i < adev->usec_timeout; i++) {
606 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
607 return 0;
608 }
609 return -ETIMEDOUT;
610}
611
612static int uvd_v5_0_soft_reset(void *handle)
613{
614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
615
616 uvd_v5_0_stop(adev);
617
618 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
619 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
620 mdelay(5);
621
622 return uvd_v5_0_start(adev);
623}
624
625static void uvd_v5_0_print_status(void *handle)
626{
627 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
628 dev_info(adev->dev, "UVD 5.0 registers\n");
629 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
630 RREG32(mmUVD_SEMA_ADDR_LOW));
631 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
632 RREG32(mmUVD_SEMA_ADDR_HIGH));
633 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
634 RREG32(mmUVD_SEMA_CMD));
635 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
636 RREG32(mmUVD_GPCOM_VCPU_CMD));
637 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
638 RREG32(mmUVD_GPCOM_VCPU_DATA0));
639 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
640 RREG32(mmUVD_GPCOM_VCPU_DATA1));
641 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
642 RREG32(mmUVD_ENGINE_CNTL));
643 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
644 RREG32(mmUVD_UDEC_ADDR_CONFIG));
645 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
646 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
647 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
648 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
649 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
650 RREG32(mmUVD_SEMA_CNTL));
651 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
652 RREG32(mmUVD_LMI_EXT40_ADDR));
653 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
654 RREG32(mmUVD_CTX_INDEX));
655 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
656 RREG32(mmUVD_CTX_DATA));
657 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
658 RREG32(mmUVD_CGC_GATE));
659 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
660 RREG32(mmUVD_CGC_CTRL));
661 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
662 RREG32(mmUVD_LMI_CTRL2));
663 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
664 RREG32(mmUVD_MASTINT_EN));
665 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
666 RREG32(mmUVD_LMI_ADDR_EXT));
667 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
668 RREG32(mmUVD_LMI_CTRL));
669 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
670 RREG32(mmUVD_LMI_SWAP_CNTL));
671 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
672 RREG32(mmUVD_MP_SWAP_CNTL));
673 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
674 RREG32(mmUVD_MPC_SET_MUXA0));
675 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
676 RREG32(mmUVD_MPC_SET_MUXA1));
677 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
678 RREG32(mmUVD_MPC_SET_MUXB0));
679 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
680 RREG32(mmUVD_MPC_SET_MUXB1));
681 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
682 RREG32(mmUVD_MPC_SET_MUX));
683 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
684 RREG32(mmUVD_MPC_SET_ALU));
685 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
686 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
687 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
688 RREG32(mmUVD_VCPU_CACHE_SIZE0));
689 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
690 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
691 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
692 RREG32(mmUVD_VCPU_CACHE_SIZE1));
693 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
694 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
695 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
696 RREG32(mmUVD_VCPU_CACHE_SIZE2));
697 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
698 RREG32(mmUVD_VCPU_CNTL));
699 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
700 RREG32(mmUVD_SOFT_RESET));
701 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
702 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));
703 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
704 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));
705 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
706 RREG32(mmUVD_RBC_IB_SIZE));
707 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
708 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));
709 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
710 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));
711 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
712 RREG32(mmUVD_RBC_RB_RPTR));
713 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
714 RREG32(mmUVD_RBC_RB_WPTR));
715 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
716 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
717 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
718 RREG32(mmUVD_RBC_RB_CNTL));
719 dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
720 RREG32(mmUVD_STATUS));
721 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
722 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
723 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
724 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
725 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
726 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
727 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
728 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
729 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
730 RREG32(mmUVD_CONTEXT_ID));
731 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
732 RREG32(mmUVD_UDEC_ADDR_CONFIG));
733 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
734 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
735 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
736 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
737}
738
739static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
740 struct amdgpu_irq_src *source,
741 unsigned type,
742 enum amdgpu_interrupt_state state)
743{
744 // TODO
745 return 0;
746}
747
748static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
749 struct amdgpu_irq_src *source,
750 struct amdgpu_iv_entry *entry)
751{
752 DRM_DEBUG("IH: UVD TRAP\n");
753 amdgpu_fence_process(&adev->uvd.ring);
754 return 0;
755}
756
757static int uvd_v5_0_set_clockgating_state(void *handle,
758 enum amd_clockgating_state state)
759{
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
761
762 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
763 return 0;
764
765 return 0;
766}
767
768static int uvd_v5_0_set_powergating_state(void *handle,
769 enum amd_powergating_state state)
770{
771 /* This doesn't actually powergate the UVD block.
772 * That's done in the dpm code via the SMC. This
773 * just re-inits the block as necessary. The actual
774 * gating still happens in the dpm code. We should
775 * revisit this when there is a cleaner line between
776 * the smc and the hw blocks
777 */
778 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
779
780 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
781 return 0;
782
783 if (state == AMD_PG_STATE_GATE) {
784 uvd_v5_0_stop(adev);
785 return 0;
786 } else {
787 return uvd_v5_0_start(adev);
788 }
789}
790
791const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
792 .early_init = uvd_v5_0_early_init,
793 .late_init = NULL,
794 .sw_init = uvd_v5_0_sw_init,
795 .sw_fini = uvd_v5_0_sw_fini,
796 .hw_init = uvd_v5_0_hw_init,
797 .hw_fini = uvd_v5_0_hw_fini,
798 .suspend = uvd_v5_0_suspend,
799 .resume = uvd_v5_0_resume,
800 .is_idle = uvd_v5_0_is_idle,
801 .wait_for_idle = uvd_v5_0_wait_for_idle,
802 .soft_reset = uvd_v5_0_soft_reset,
803 .print_status = uvd_v5_0_print_status,
804 .set_clockgating_state = uvd_v5_0_set_clockgating_state,
805 .set_powergating_state = uvd_v5_0_set_powergating_state,
806};
807
808static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
809 .get_rptr = uvd_v5_0_ring_get_rptr,
810 .get_wptr = uvd_v5_0_ring_get_wptr,
811 .set_wptr = uvd_v5_0_ring_set_wptr,
812 .parse_cs = amdgpu_uvd_ring_parse_cs,
813 .emit_ib = uvd_v5_0_ring_emit_ib,
814 .emit_fence = uvd_v5_0_ring_emit_fence,
815 .test_ring = uvd_v5_0_ring_test_ring,
816 .test_ib = uvd_v5_0_ring_test_ib,
817 .insert_nop = amdgpu_ring_insert_nop,
818 .pad_ib = amdgpu_ring_generic_pad_ib,
819};
820
821static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
822{
823 adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
824}
825
826static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
827 .set = uvd_v5_0_set_interrupt_state,
828 .process = uvd_v5_0_process_interrupt,
829};
830
831static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
832{
833 adev->uvd.irq.num_types = 1;
834 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
835}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_uvd.h"
29#include "vid.h"
30#include "uvd/uvd_5_0_d.h"
31#include "uvd/uvd_5_0_sh_mask.h"
32#include "oss/oss_2_0_d.h"
33#include "oss/oss_2_0_sh_mask.h"
34#include "bif/bif_5_0_d.h"
35#include "vi.h"
36#include "smu/smu_7_1_2_d.h"
37#include "smu/smu_7_1_2_sh_mask.h"
38
39static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
40static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
41static int uvd_v5_0_start(struct amdgpu_device *adev);
42static void uvd_v5_0_stop(struct amdgpu_device *adev);
43static int uvd_v5_0_set_clockgating_state(void *handle,
44 enum amd_clockgating_state state);
45static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
46 bool enable);
47/**
48 * uvd_v5_0_ring_get_rptr - get read pointer
49 *
50 * @ring: amdgpu_ring pointer
51 *
52 * Returns the current hardware read pointer
53 */
54static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
55{
56 struct amdgpu_device *adev = ring->adev;
57
58 return RREG32(mmUVD_RBC_RB_RPTR);
59}
60
61/**
62 * uvd_v5_0_ring_get_wptr - get write pointer
63 *
64 * @ring: amdgpu_ring pointer
65 *
66 * Returns the current hardware write pointer
67 */
68static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
69{
70 struct amdgpu_device *adev = ring->adev;
71
72 return RREG32(mmUVD_RBC_RB_WPTR);
73}
74
75/**
76 * uvd_v5_0_ring_set_wptr - set write pointer
77 *
78 * @ring: amdgpu_ring pointer
79 *
80 * Commits the write pointer to the hardware
81 */
82static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
83{
84 struct amdgpu_device *adev = ring->adev;
85
86 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
87}
88
89static int uvd_v5_0_early_init(void *handle)
90{
91 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
92
93 uvd_v5_0_set_ring_funcs(adev);
94 uvd_v5_0_set_irq_funcs(adev);
95
96 return 0;
97}
98
99static int uvd_v5_0_sw_init(void *handle)
100{
101 struct amdgpu_ring *ring;
102 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
103 int r;
104
105 /* UVD TRAP */
106 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
107 if (r)
108 return r;
109
110 r = amdgpu_uvd_sw_init(adev);
111 if (r)
112 return r;
113
114 r = amdgpu_uvd_resume(adev);
115 if (r)
116 return r;
117
118 ring = &adev->uvd.ring;
119 sprintf(ring->name, "uvd");
120 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
121
122 return r;
123}
124
125static int uvd_v5_0_sw_fini(void *handle)
126{
127 int r;
128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
129
130 r = amdgpu_uvd_suspend(adev);
131 if (r)
132 return r;
133
134 return amdgpu_uvd_sw_fini(adev);
135}
136
137/**
138 * uvd_v5_0_hw_init - start and test UVD block
139 *
140 * @adev: amdgpu_device pointer
141 *
142 * Initialize the hardware, boot up the VCPU and do some testing
143 */
144static int uvd_v5_0_hw_init(void *handle)
145{
146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
147 struct amdgpu_ring *ring = &adev->uvd.ring;
148 uint32_t tmp;
149 int r;
150
151 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
152 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
153 uvd_v5_0_enable_mgcg(adev, true);
154
155 ring->ready = true;
156 r = amdgpu_ring_test_ring(ring);
157 if (r) {
158 ring->ready = false;
159 goto done;
160 }
161
162 r = amdgpu_ring_alloc(ring, 10);
163 if (r) {
164 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
165 goto done;
166 }
167
168 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
169 amdgpu_ring_write(ring, tmp);
170 amdgpu_ring_write(ring, 0xFFFFF);
171
172 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
173 amdgpu_ring_write(ring, tmp);
174 amdgpu_ring_write(ring, 0xFFFFF);
175
176 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
177 amdgpu_ring_write(ring, tmp);
178 amdgpu_ring_write(ring, 0xFFFFF);
179
180 /* Clear timeout status bits */
181 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
182 amdgpu_ring_write(ring, 0x8);
183
184 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
185 amdgpu_ring_write(ring, 3);
186
187 amdgpu_ring_commit(ring);
188
189done:
190 if (!r)
191 DRM_INFO("UVD initialized successfully.\n");
192
193 return r;
194
195}
196
197/**
198 * uvd_v5_0_hw_fini - stop the hardware block
199 *
200 * @adev: amdgpu_device pointer
201 *
202 * Stop the UVD block, mark ring as not ready any more
203 */
204static int uvd_v5_0_hw_fini(void *handle)
205{
206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
207 struct amdgpu_ring *ring = &adev->uvd.ring;
208
209 if (RREG32(mmUVD_STATUS) != 0)
210 uvd_v5_0_stop(adev);
211
212 ring->ready = false;
213
214 return 0;
215}
216
217static int uvd_v5_0_suspend(void *handle)
218{
219 int r;
220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
221
222 r = uvd_v5_0_hw_fini(adev);
223 if (r)
224 return r;
225 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
226
227 return amdgpu_uvd_suspend(adev);
228}
229
230static int uvd_v5_0_resume(void *handle)
231{
232 int r;
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 r = amdgpu_uvd_resume(adev);
236 if (r)
237 return r;
238
239 return uvd_v5_0_hw_init(adev);
240}
241
242/**
243 * uvd_v5_0_mc_resume - memory controller programming
244 *
245 * @adev: amdgpu_device pointer
246 *
247 * Let the UVD memory controller know it's offsets
248 */
249static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
250{
251 uint64_t offset;
252 uint32_t size;
253
254 /* programm memory controller bits 0-27 */
255 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
256 lower_32_bits(adev->uvd.gpu_addr));
257 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
258 upper_32_bits(adev->uvd.gpu_addr));
259
260 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
261 size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
262 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
263 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
264
265 offset += size;
266 size = AMDGPU_UVD_HEAP_SIZE;
267 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
268 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
269
270 offset += size;
271 size = AMDGPU_UVD_STACK_SIZE +
272 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
273 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
274 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
275
276 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
277 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
278 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
279}
280
281/**
282 * uvd_v5_0_start - start UVD block
283 *
284 * @adev: amdgpu_device pointer
285 *
286 * Setup and start the UVD block
287 */
288static int uvd_v5_0_start(struct amdgpu_device *adev)
289{
290 struct amdgpu_ring *ring = &adev->uvd.ring;
291 uint32_t rb_bufsz, tmp;
292 uint32_t lmi_swap_cntl;
293 uint32_t mp_swap_cntl;
294 int i, j, r;
295
296 /*disable DPG */
297 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
298
299 /* disable byte swapping */
300 lmi_swap_cntl = 0;
301 mp_swap_cntl = 0;
302
303 uvd_v5_0_mc_resume(adev);
304
305 /* disable interupt */
306 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
307
308 /* stall UMC and register bus before resetting VCPU */
309 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
310 mdelay(1);
311
312 /* put LMI, VCPU, RBC etc... into reset */
313 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
314 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
315 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
316 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
317 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
318 mdelay(5);
319
320 /* take UVD block out of reset */
321 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
322 mdelay(5);
323
324 /* initialize UVD memory controller */
325 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
326 (1 << 21) | (1 << 9) | (1 << 20));
327
328#ifdef __BIG_ENDIAN
329 /* swap (8 in 32) RB and IB */
330 lmi_swap_cntl = 0xa;
331 mp_swap_cntl = 0;
332#endif
333 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
334 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
335
336 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
337 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
338 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
339 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
340 WREG32(mmUVD_MPC_SET_ALU, 0);
341 WREG32(mmUVD_MPC_SET_MUX, 0x88);
342
343 /* take all subblocks out of reset, except VCPU */
344 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
345 mdelay(5);
346
347 /* enable VCPU clock */
348 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
349
350 /* enable UMC */
351 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
352
353 /* boot up the VCPU */
354 WREG32(mmUVD_SOFT_RESET, 0);
355 mdelay(10);
356
357 for (i = 0; i < 10; ++i) {
358 uint32_t status;
359 for (j = 0; j < 100; ++j) {
360 status = RREG32(mmUVD_STATUS);
361 if (status & 2)
362 break;
363 mdelay(10);
364 }
365 r = 0;
366 if (status & 2)
367 break;
368
369 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
370 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
371 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
372 mdelay(10);
373 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
374 mdelay(10);
375 r = -1;
376 }
377
378 if (r) {
379 DRM_ERROR("UVD not responding, giving up!!!\n");
380 return r;
381 }
382 /* enable master interrupt */
383 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
384
385 /* clear the bit 4 of UVD_STATUS */
386 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
387
388 rb_bufsz = order_base_2(ring->ring_size);
389 tmp = 0;
390 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
391 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
392 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
393 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
394 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
395 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
396 /* force RBC into idle state */
397 WREG32(mmUVD_RBC_RB_CNTL, tmp);
398
399 /* set the write pointer delay */
400 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
401
402 /* set the wb address */
403 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
404
405 /* programm the RB_BASE for ring buffer */
406 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
407 lower_32_bits(ring->gpu_addr));
408 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
409 upper_32_bits(ring->gpu_addr));
410
411 /* Initialize the ring buffer's read and write pointers */
412 WREG32(mmUVD_RBC_RB_RPTR, 0);
413
414 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
415 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
416
417 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
418
419 return 0;
420}
421
422/**
423 * uvd_v5_0_stop - stop UVD block
424 *
425 * @adev: amdgpu_device pointer
426 *
427 * stop the UVD block
428 */
429static void uvd_v5_0_stop(struct amdgpu_device *adev)
430{
431 /* force RBC into idle state */
432 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
433
434 /* Stall UMC and register bus before resetting VCPU */
435 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
436 mdelay(1);
437
438 /* put VCPU into reset */
439 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
440 mdelay(5);
441
442 /* disable VCPU clock */
443 WREG32(mmUVD_VCPU_CNTL, 0x0);
444
445 /* Unstall UMC and register bus */
446 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
447
448 WREG32(mmUVD_STATUS, 0);
449}
450
451/**
452 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
453 *
454 * @ring: amdgpu_ring pointer
455 * @fence: fence to emit
456 *
457 * Write a fence and a trap command to the ring.
458 */
459static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
460 unsigned flags)
461{
462 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
463
464 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
465 amdgpu_ring_write(ring, seq);
466 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
467 amdgpu_ring_write(ring, addr & 0xffffffff);
468 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
469 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
471 amdgpu_ring_write(ring, 0);
472
473 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
474 amdgpu_ring_write(ring, 0);
475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
476 amdgpu_ring_write(ring, 0);
477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
478 amdgpu_ring_write(ring, 2);
479}
480
481/**
482 * uvd_v5_0_ring_test_ring - register write test
483 *
484 * @ring: amdgpu_ring pointer
485 *
486 * Test if we can successfully write to the context register
487 */
488static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
489{
490 struct amdgpu_device *adev = ring->adev;
491 uint32_t tmp = 0;
492 unsigned i;
493 int r;
494
495 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
496 r = amdgpu_ring_alloc(ring, 3);
497 if (r) {
498 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
499 ring->idx, r);
500 return r;
501 }
502 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
503 amdgpu_ring_write(ring, 0xDEADBEEF);
504 amdgpu_ring_commit(ring);
505 for (i = 0; i < adev->usec_timeout; i++) {
506 tmp = RREG32(mmUVD_CONTEXT_ID);
507 if (tmp == 0xDEADBEEF)
508 break;
509 DRM_UDELAY(1);
510 }
511
512 if (i < adev->usec_timeout) {
513 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
514 ring->idx, i);
515 } else {
516 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
517 ring->idx, tmp);
518 r = -EINVAL;
519 }
520 return r;
521}
522
523/**
524 * uvd_v5_0_ring_emit_ib - execute indirect buffer
525 *
526 * @ring: amdgpu_ring pointer
527 * @ib: indirect buffer to execute
528 *
529 * Write ring commands to execute the indirect buffer
530 */
531static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
532 struct amdgpu_ib *ib,
533 unsigned vmid, bool ctx_switch)
534{
535 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
536 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
537 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
538 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
539 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
540 amdgpu_ring_write(ring, ib->length_dw);
541}
542
543static bool uvd_v5_0_is_idle(void *handle)
544{
545 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
546
547 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
548}
549
550static int uvd_v5_0_wait_for_idle(void *handle)
551{
552 unsigned i;
553 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
554
555 for (i = 0; i < adev->usec_timeout; i++) {
556 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
557 return 0;
558 }
559 return -ETIMEDOUT;
560}
561
562static int uvd_v5_0_soft_reset(void *handle)
563{
564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
565
566 uvd_v5_0_stop(adev);
567
568 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
569 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
570 mdelay(5);
571
572 return uvd_v5_0_start(adev);
573}
574
575static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
576 struct amdgpu_irq_src *source,
577 unsigned type,
578 enum amdgpu_interrupt_state state)
579{
580 // TODO
581 return 0;
582}
583
584static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
585 struct amdgpu_irq_src *source,
586 struct amdgpu_iv_entry *entry)
587{
588 DRM_DEBUG("IH: UVD TRAP\n");
589 amdgpu_fence_process(&adev->uvd.ring);
590 return 0;
591}
592
593static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
594{
595 uint32_t data1, data3, suvd_flags;
596
597 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
598 data3 = RREG32(mmUVD_CGC_GATE);
599
600 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
601 UVD_SUVD_CGC_GATE__SIT_MASK |
602 UVD_SUVD_CGC_GATE__SMP_MASK |
603 UVD_SUVD_CGC_GATE__SCM_MASK |
604 UVD_SUVD_CGC_GATE__SDB_MASK;
605
606 if (enable) {
607 data3 |= (UVD_CGC_GATE__SYS_MASK |
608 UVD_CGC_GATE__UDEC_MASK |
609 UVD_CGC_GATE__MPEG2_MASK |
610 UVD_CGC_GATE__RBC_MASK |
611 UVD_CGC_GATE__LMI_MC_MASK |
612 UVD_CGC_GATE__IDCT_MASK |
613 UVD_CGC_GATE__MPRD_MASK |
614 UVD_CGC_GATE__MPC_MASK |
615 UVD_CGC_GATE__LBSI_MASK |
616 UVD_CGC_GATE__LRBBM_MASK |
617 UVD_CGC_GATE__UDEC_RE_MASK |
618 UVD_CGC_GATE__UDEC_CM_MASK |
619 UVD_CGC_GATE__UDEC_IT_MASK |
620 UVD_CGC_GATE__UDEC_DB_MASK |
621 UVD_CGC_GATE__UDEC_MP_MASK |
622 UVD_CGC_GATE__WCB_MASK |
623 UVD_CGC_GATE__JPEG_MASK |
624 UVD_CGC_GATE__SCPU_MASK);
625 /* only in pg enabled, we can gate clock to vcpu*/
626 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
627 data3 |= UVD_CGC_GATE__VCPU_MASK;
628 data3 &= ~UVD_CGC_GATE__REGS_MASK;
629 data1 |= suvd_flags;
630 } else {
631 data3 = 0;
632 data1 = 0;
633 }
634
635 WREG32(mmUVD_SUVD_CGC_GATE, data1);
636 WREG32(mmUVD_CGC_GATE, data3);
637}
638
639static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
640{
641 uint32_t data, data2;
642
643 data = RREG32(mmUVD_CGC_CTRL);
644 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
645
646
647 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
648 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
649
650
651 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
652 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
653 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
654
655 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
656 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
657 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
658 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
659 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
660 UVD_CGC_CTRL__SYS_MODE_MASK |
661 UVD_CGC_CTRL__UDEC_MODE_MASK |
662 UVD_CGC_CTRL__MPEG2_MODE_MASK |
663 UVD_CGC_CTRL__REGS_MODE_MASK |
664 UVD_CGC_CTRL__RBC_MODE_MASK |
665 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
666 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
667 UVD_CGC_CTRL__IDCT_MODE_MASK |
668 UVD_CGC_CTRL__MPRD_MODE_MASK |
669 UVD_CGC_CTRL__MPC_MODE_MASK |
670 UVD_CGC_CTRL__LBSI_MODE_MASK |
671 UVD_CGC_CTRL__LRBBM_MODE_MASK |
672 UVD_CGC_CTRL__WCB_MODE_MASK |
673 UVD_CGC_CTRL__VCPU_MODE_MASK |
674 UVD_CGC_CTRL__JPEG_MODE_MASK |
675 UVD_CGC_CTRL__SCPU_MODE_MASK);
676 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
677 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
678 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
679 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
680 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
681
682 WREG32(mmUVD_CGC_CTRL, data);
683 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
684}
685
686#if 0
687static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
688{
689 uint32_t data, data1, cgc_flags, suvd_flags;
690
691 data = RREG32(mmUVD_CGC_GATE);
692 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
693
694 cgc_flags = UVD_CGC_GATE__SYS_MASK |
695 UVD_CGC_GATE__UDEC_MASK |
696 UVD_CGC_GATE__MPEG2_MASK |
697 UVD_CGC_GATE__RBC_MASK |
698 UVD_CGC_GATE__LMI_MC_MASK |
699 UVD_CGC_GATE__IDCT_MASK |
700 UVD_CGC_GATE__MPRD_MASK |
701 UVD_CGC_GATE__MPC_MASK |
702 UVD_CGC_GATE__LBSI_MASK |
703 UVD_CGC_GATE__LRBBM_MASK |
704 UVD_CGC_GATE__UDEC_RE_MASK |
705 UVD_CGC_GATE__UDEC_CM_MASK |
706 UVD_CGC_GATE__UDEC_IT_MASK |
707 UVD_CGC_GATE__UDEC_DB_MASK |
708 UVD_CGC_GATE__UDEC_MP_MASK |
709 UVD_CGC_GATE__WCB_MASK |
710 UVD_CGC_GATE__VCPU_MASK |
711 UVD_CGC_GATE__SCPU_MASK;
712
713 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
714 UVD_SUVD_CGC_GATE__SIT_MASK |
715 UVD_SUVD_CGC_GATE__SMP_MASK |
716 UVD_SUVD_CGC_GATE__SCM_MASK |
717 UVD_SUVD_CGC_GATE__SDB_MASK;
718
719 data |= cgc_flags;
720 data1 |= suvd_flags;
721
722 WREG32(mmUVD_CGC_GATE, data);
723 WREG32(mmUVD_SUVD_CGC_GATE, data1);
724}
725#endif
726
727static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
728 bool enable)
729{
730 u32 orig, data;
731
732 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
733 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
734 data |= 0xfff;
735 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
736
737 orig = data = RREG32(mmUVD_CGC_CTRL);
738 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
739 if (orig != data)
740 WREG32(mmUVD_CGC_CTRL, data);
741 } else {
742 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
743 data &= ~0xfff;
744 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
745
746 orig = data = RREG32(mmUVD_CGC_CTRL);
747 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
748 if (orig != data)
749 WREG32(mmUVD_CGC_CTRL, data);
750 }
751}
752
753static int uvd_v5_0_set_clockgating_state(void *handle,
754 enum amd_clockgating_state state)
755{
756 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
757 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
758
759 if (enable) {
760 /* wait for STATUS to clear */
761 if (uvd_v5_0_wait_for_idle(handle))
762 return -EBUSY;
763 uvd_v5_0_enable_clock_gating(adev, true);
764
765 /* enable HW gates because UVD is idle */
766/* uvd_v5_0_set_hw_clock_gating(adev); */
767 } else {
768 uvd_v5_0_enable_clock_gating(adev, false);
769 }
770
771 uvd_v5_0_set_sw_clock_gating(adev);
772 return 0;
773}
774
775static int uvd_v5_0_set_powergating_state(void *handle,
776 enum amd_powergating_state state)
777{
778 /* This doesn't actually powergate the UVD block.
779 * That's done in the dpm code via the SMC. This
780 * just re-inits the block as necessary. The actual
781 * gating still happens in the dpm code. We should
782 * revisit this when there is a cleaner line between
783 * the smc and the hw blocks
784 */
785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
786 int ret = 0;
787
788 if (state == AMD_PG_STATE_GATE) {
789 uvd_v5_0_stop(adev);
790 } else {
791 ret = uvd_v5_0_start(adev);
792 if (ret)
793 goto out;
794 }
795
796out:
797 return ret;
798}
799
800static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
801{
802 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
803 int data;
804
805 mutex_lock(&adev->pm.mutex);
806
807 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
808 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
809 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
810 goto out;
811 }
812
813 /* AMD_CG_SUPPORT_UVD_MGCG */
814 data = RREG32(mmUVD_CGC_CTRL);
815 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
816 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
817
818out:
819 mutex_unlock(&adev->pm.mutex);
820}
821
822static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
823 .name = "uvd_v5_0",
824 .early_init = uvd_v5_0_early_init,
825 .late_init = NULL,
826 .sw_init = uvd_v5_0_sw_init,
827 .sw_fini = uvd_v5_0_sw_fini,
828 .hw_init = uvd_v5_0_hw_init,
829 .hw_fini = uvd_v5_0_hw_fini,
830 .suspend = uvd_v5_0_suspend,
831 .resume = uvd_v5_0_resume,
832 .is_idle = uvd_v5_0_is_idle,
833 .wait_for_idle = uvd_v5_0_wait_for_idle,
834 .soft_reset = uvd_v5_0_soft_reset,
835 .set_clockgating_state = uvd_v5_0_set_clockgating_state,
836 .set_powergating_state = uvd_v5_0_set_powergating_state,
837 .get_clockgating_state = uvd_v5_0_get_clockgating_state,
838};
839
840static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
841 .type = AMDGPU_RING_TYPE_UVD,
842 .align_mask = 0xf,
843 .nop = PACKET0(mmUVD_NO_OP, 0),
844 .support_64bit_ptrs = false,
845 .get_rptr = uvd_v5_0_ring_get_rptr,
846 .get_wptr = uvd_v5_0_ring_get_wptr,
847 .set_wptr = uvd_v5_0_ring_set_wptr,
848 .parse_cs = amdgpu_uvd_ring_parse_cs,
849 .emit_frame_size =
850 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */
851 .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
852 .emit_ib = uvd_v5_0_ring_emit_ib,
853 .emit_fence = uvd_v5_0_ring_emit_fence,
854 .test_ring = uvd_v5_0_ring_test_ring,
855 .test_ib = amdgpu_uvd_ring_test_ib,
856 .insert_nop = amdgpu_ring_insert_nop,
857 .pad_ib = amdgpu_ring_generic_pad_ib,
858 .begin_use = amdgpu_uvd_ring_begin_use,
859 .end_use = amdgpu_uvd_ring_end_use,
860};
861
862static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
863{
864 adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
865}
866
867static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
868 .set = uvd_v5_0_set_interrupt_state,
869 .process = uvd_v5_0_process_interrupt,
870};
871
872static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
873{
874 adev->uvd.irq.num_types = 1;
875 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
876}
877
878const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
879{
880 .type = AMD_IP_BLOCK_TYPE_UVD,
881 .major = 5,
882 .minor = 0,
883 .rev = 0,
884 .funcs = &uvd_v5_0_ip_funcs,
885};