1/*
  2 * r2300_switch.S: R2300 specific task switching code.
  3 *
  4 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
  5 * Copyright (C) 1994, 1995, 1996 by Andreas Busse
  6 *
  7 * Multi-cpu abstraction and macros for easier reading:
  8 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  9 *
 10 * Further modifications to make this work:
 11 * Copyright (c) 1998-2000 Harald Koerfgen
 12 */
 13#include <asm/asm.h>
 14#include <asm/cachectl.h>
 
 15#include <asm/fpregdef.h>
 16#include <asm/mipsregs.h>
 17#include <asm/asm-offsets.h>
 18#include <asm/regdef.h>
 19#include <asm/stackframe.h>
 20#include <asm/thread_info.h>
 21
 22#include <asm/asmmacro.h>
 23
 24	.set	mips1
 25	.align	5
 26
 27/*
 28 * Offset to the current process status flags, the first 32 bytes of the
 29 * stack are not used.
 30 */
 31#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
 32
 33/*
 34 * task_struct *resume(task_struct *prev, task_struct *next,
 35 *		       struct thread_info *next_ti)
 36 */
 37LEAF(resume)
 38	mfc0	t1, CP0_STATUS
 39	sw	t1, THREAD_STATUS(a0)
 40	cpu_save_nonscratch a0
 41	sw	ra, THREAD_REG31(a0)
 42
 43#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 44	PTR_LA	t8, __stack_chk_guard
 45	LONG_L	t9, TASK_STACK_CANARY(a1)
 46	LONG_S	t9, 0(t8)
 47#endif
 48
 49	/*
 50	 * The order of restoring the registers takes care of the race
 51	 * updating $28, $29 and kernelsp without disabling ints.
 52	 */
 53	move	$28, a2
 54	cpu_restore_nonscratch a1
 55
 56	addiu	t1, $28, _THREAD_SIZE - 32
 57	sw	t1, kernelsp
 58
 59	mfc0	t1, CP0_STATUS		/* Do we really need this? */
 60	li	a3, 0xff01
 61	and	t1, a3
 62	lw	a2, THREAD_STATUS(a1)
 63	nor	a3, $0, a3
 64	and	a2, a3
 65	or	a2, t1
 66	mtc0	a2, CP0_STATUS
 67	move	v0, a0
 68	jr	ra
 69	END(resume)
 70
 71/*
 72 * Save a thread's fp context.
 73 */
 74LEAF(_save_fp)
 75	fpu_save_single a0, t1			# clobbers t1
 76	jr	ra
 77	END(_save_fp)
 78
 79/*
 80 * Restore a thread's fp context.
 81 */
 82LEAF(_restore_fp)
 83	fpu_restore_single a0, t1		# clobbers t1
 84	jr	ra
 85	END(_restore_fp)
 86
 87/*
 88 * Load the FPU with signalling NANS.  This bit pattern we're using has
 89 * the property that no matter whether considered as single or as double
 90 * precision represents signaling NANS.
 91 *
 92 * The value to initialize fcr31 to comes in $a0.
 93 */
 94
 95	.set push
 96	SET_HARDFLOAT
 97
 98LEAF(_init_fpu)
 99	mfc0	t0, CP0_STATUS
100	li	t1, ST0_CU1
101	or	t0, t1
102	mtc0	t0, CP0_STATUS
103
104	ctc1	a0, fcr31
105
106	li	t0, -1
107
108	mtc1	t0, $f0
109	mtc1	t0, $f1
110	mtc1	t0, $f2
111	mtc1	t0, $f3
112	mtc1	t0, $f4
113	mtc1	t0, $f5
114	mtc1	t0, $f6
115	mtc1	t0, $f7
116	mtc1	t0, $f8
117	mtc1	t0, $f9
118	mtc1	t0, $f10
119	mtc1	t0, $f11
120	mtc1	t0, $f12
121	mtc1	t0, $f13
122	mtc1	t0, $f14
123	mtc1	t0, $f15
124	mtc1	t0, $f16
125	mtc1	t0, $f17
126	mtc1	t0, $f18
127	mtc1	t0, $f19
128	mtc1	t0, $f20
129	mtc1	t0, $f21
130	mtc1	t0, $f22
131	mtc1	t0, $f23
132	mtc1	t0, $f24
133	mtc1	t0, $f25
134	mtc1	t0, $f26
135	mtc1	t0, $f27
136	mtc1	t0, $f28
137	mtc1	t0, $f29
138	mtc1	t0, $f30
139	mtc1	t0, $f31
140	jr	ra
141	END(_init_fpu)
142
143	.set pop

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * r2300_switch.S: R2300 specific task switching code.
 4 *
 5 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
 6 * Copyright (C) 1994, 1995, 1996 by Andreas Busse
 7 *
 8 * Multi-cpu abstraction and macros for easier reading:
 9 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
10 *
11 * Further modifications to make this work:
12 * Copyright (c) 1998-2000 Harald Koerfgen
13 */
14#include <asm/asm.h>
15#include <asm/cachectl.h>
16#include <asm/export.h>
17#include <asm/fpregdef.h>
18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h>
20#include <asm/regdef.h>
21#include <asm/stackframe.h>
22#include <asm/thread_info.h>
23
24#include <asm/asmmacro.h>
25
26	.set	mips1
27	.align	5
28
29/*
 
 
 
 
 
 
30 * task_struct *resume(task_struct *prev, task_struct *next,
31 *		       struct thread_info *next_ti)
32 */
33LEAF(resume)
34	mfc0	t1, CP0_STATUS
35	sw	t1, THREAD_STATUS(a0)
36	cpu_save_nonscratch a0
37	sw	ra, THREAD_REG31(a0)
38
39#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
40	PTR_LA	t8, __stack_chk_guard
41	LONG_L	t9, TASK_STACK_CANARY(a1)
42	LONG_S	t9, 0(t8)
43#endif
44
45	/*
46	 * The order of restoring the registers takes care of the race
47	 * updating $28, $29 and kernelsp without disabling ints.
48	 */
49	move	$28, a2
50	cpu_restore_nonscratch a1
51
52	addiu	t1, $28, _THREAD_SIZE - 32
53	sw	t1, kernelsp
54
55	mfc0	t1, CP0_STATUS		/* Do we really need this? */
56	li	a3, 0xff01
57	and	t1, a3
58	lw	a2, THREAD_STATUS(a1)
59	nor	a3, $0, a3
60	and	a2, a3
61	or	a2, t1
62	mtc0	a2, CP0_STATUS
63	move	v0, a0
64	jr	ra
65	END(resume)