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1/*
2 * ARMv5 [xscale] Performance counter handling code.
3 *
4 * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
5 *
6 * Based on the previous xscale OProfile code.
7 *
8 * There are two variants of the xscale PMU that we support:
9 * - xscale1pmu: 2 event counters and a cycle counter
10 * - xscale2pmu: 4 event counters and a cycle counter
11 * The two variants share event definitions, but have different
12 * PMU structures.
13 */
14
15#ifdef CONFIG_CPU_XSCALE
16
17#include <asm/cputype.h>
18#include <asm/irq_regs.h>
19
20#include <linux/of.h>
21#include <linux/perf/arm_pmu.h>
22#include <linux/platform_device.h>
23
24enum xscale_perf_types {
25 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
26 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
27 XSCALE_PERFCTR_DATA_STALL = 0x02,
28 XSCALE_PERFCTR_ITLB_MISS = 0x03,
29 XSCALE_PERFCTR_DTLB_MISS = 0x04,
30 XSCALE_PERFCTR_BRANCH = 0x05,
31 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
32 XSCALE_PERFCTR_INSTRUCTION = 0x07,
33 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
34 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
35 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
36 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
37 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
38 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
39 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
40 XSCALE_PERFCTR_BCU_FULL = 0x11,
41 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
42 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
43 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
44 XSCALE_PERFCTR_RMW = 0x16,
45 /* XSCALE_PERFCTR_CCNT is not hardware defined */
46 XSCALE_PERFCTR_CCNT = 0xFE,
47 XSCALE_PERFCTR_UNUSED = 0xFF,
48};
49
50enum xscale_counters {
51 XSCALE_CYCLE_COUNTER = 0,
52 XSCALE_COUNTER0,
53 XSCALE_COUNTER1,
54 XSCALE_COUNTER2,
55 XSCALE_COUNTER3,
56};
57
58static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
59 PERF_MAP_ALL_UNSUPPORTED,
60 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
61 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
62 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
63 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
64 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
65};
66
67static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
68 [PERF_COUNT_HW_CACHE_OP_MAX]
69 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
70 PERF_CACHE_MAP_ALL_UNSUPPORTED,
71
72 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
73 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
74 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
75 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
76
77 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
78
79 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
80 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
81
82 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
83 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
84};
85
86#define XSCALE_PMU_ENABLE 0x001
87#define XSCALE_PMN_RESET 0x002
88#define XSCALE_CCNT_RESET 0x004
89#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
90#define XSCALE_PMU_CNT64 0x008
91
92#define XSCALE1_OVERFLOWED_MASK 0x700
93#define XSCALE1_CCOUNT_OVERFLOW 0x400
94#define XSCALE1_COUNT0_OVERFLOW 0x100
95#define XSCALE1_COUNT1_OVERFLOW 0x200
96#define XSCALE1_CCOUNT_INT_EN 0x040
97#define XSCALE1_COUNT0_INT_EN 0x010
98#define XSCALE1_COUNT1_INT_EN 0x020
99#define XSCALE1_COUNT0_EVT_SHFT 12
100#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
101#define XSCALE1_COUNT1_EVT_SHFT 20
102#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
103
104static inline u32
105xscale1pmu_read_pmnc(void)
106{
107 u32 val;
108 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
109 return val;
110}
111
112static inline void
113xscale1pmu_write_pmnc(u32 val)
114{
115 /* upper 4bits and 7, 11 are write-as-0 */
116 val &= 0xffff77f;
117 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
118}
119
120static inline int
121xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
122 enum xscale_counters counter)
123{
124 int ret = 0;
125
126 switch (counter) {
127 case XSCALE_CYCLE_COUNTER:
128 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
129 break;
130 case XSCALE_COUNTER0:
131 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
132 break;
133 case XSCALE_COUNTER1:
134 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
135 break;
136 default:
137 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
138 }
139
140 return ret;
141}
142
143static irqreturn_t
144xscale1pmu_handle_irq(int irq_num, void *dev)
145{
146 unsigned long pmnc;
147 struct perf_sample_data data;
148 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
149 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
150 struct pt_regs *regs;
151 int idx;
152
153 /*
154 * NOTE: there's an A stepping erratum that states if an overflow
155 * bit already exists and another occurs, the previous
156 * Overflow bit gets cleared. There's no workaround.
157 * Fixed in B stepping or later.
158 */
159 pmnc = xscale1pmu_read_pmnc();
160
161 /*
162 * Write the value back to clear the overflow flags. Overflow
163 * flags remain in pmnc for use below. We also disable the PMU
164 * while we process the interrupt.
165 */
166 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
167
168 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
169 return IRQ_NONE;
170
171 regs = get_irq_regs();
172
173 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
174 struct perf_event *event = cpuc->events[idx];
175 struct hw_perf_event *hwc;
176
177 if (!event)
178 continue;
179
180 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
181 continue;
182
183 hwc = &event->hw;
184 armpmu_event_update(event);
185 perf_sample_data_init(&data, 0, hwc->last_period);
186 if (!armpmu_event_set_period(event))
187 continue;
188
189 if (perf_event_overflow(event, &data, regs))
190 cpu_pmu->disable(event);
191 }
192
193 irq_work_run();
194
195 /*
196 * Re-enable the PMU.
197 */
198 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
199 xscale1pmu_write_pmnc(pmnc);
200
201 return IRQ_HANDLED;
202}
203
204static void xscale1pmu_enable_event(struct perf_event *event)
205{
206 unsigned long val, mask, evt, flags;
207 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
208 struct hw_perf_event *hwc = &event->hw;
209 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
210 int idx = hwc->idx;
211
212 switch (idx) {
213 case XSCALE_CYCLE_COUNTER:
214 mask = 0;
215 evt = XSCALE1_CCOUNT_INT_EN;
216 break;
217 case XSCALE_COUNTER0:
218 mask = XSCALE1_COUNT0_EVT_MASK;
219 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
220 XSCALE1_COUNT0_INT_EN;
221 break;
222 case XSCALE_COUNTER1:
223 mask = XSCALE1_COUNT1_EVT_MASK;
224 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
225 XSCALE1_COUNT1_INT_EN;
226 break;
227 default:
228 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
229 return;
230 }
231
232 raw_spin_lock_irqsave(&events->pmu_lock, flags);
233 val = xscale1pmu_read_pmnc();
234 val &= ~mask;
235 val |= evt;
236 xscale1pmu_write_pmnc(val);
237 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
238}
239
240static void xscale1pmu_disable_event(struct perf_event *event)
241{
242 unsigned long val, mask, evt, flags;
243 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
244 struct hw_perf_event *hwc = &event->hw;
245 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
246 int idx = hwc->idx;
247
248 switch (idx) {
249 case XSCALE_CYCLE_COUNTER:
250 mask = XSCALE1_CCOUNT_INT_EN;
251 evt = 0;
252 break;
253 case XSCALE_COUNTER0:
254 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
255 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
256 break;
257 case XSCALE_COUNTER1:
258 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
259 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
260 break;
261 default:
262 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
263 return;
264 }
265
266 raw_spin_lock_irqsave(&events->pmu_lock, flags);
267 val = xscale1pmu_read_pmnc();
268 val &= ~mask;
269 val |= evt;
270 xscale1pmu_write_pmnc(val);
271 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
272}
273
274static int
275xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
276 struct perf_event *event)
277{
278 struct hw_perf_event *hwc = &event->hw;
279 if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
280 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
281 return -EAGAIN;
282
283 return XSCALE_CYCLE_COUNTER;
284 } else {
285 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
286 return XSCALE_COUNTER1;
287
288 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
289 return XSCALE_COUNTER0;
290
291 return -EAGAIN;
292 }
293}
294
295static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
296{
297 unsigned long flags, val;
298 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
299
300 raw_spin_lock_irqsave(&events->pmu_lock, flags);
301 val = xscale1pmu_read_pmnc();
302 val |= XSCALE_PMU_ENABLE;
303 xscale1pmu_write_pmnc(val);
304 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
305}
306
307static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
308{
309 unsigned long flags, val;
310 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
311
312 raw_spin_lock_irqsave(&events->pmu_lock, flags);
313 val = xscale1pmu_read_pmnc();
314 val &= ~XSCALE_PMU_ENABLE;
315 xscale1pmu_write_pmnc(val);
316 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
317}
318
319static inline u32 xscale1pmu_read_counter(struct perf_event *event)
320{
321 struct hw_perf_event *hwc = &event->hw;
322 int counter = hwc->idx;
323 u32 val = 0;
324
325 switch (counter) {
326 case XSCALE_CYCLE_COUNTER:
327 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
328 break;
329 case XSCALE_COUNTER0:
330 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
331 break;
332 case XSCALE_COUNTER1:
333 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
334 break;
335 }
336
337 return val;
338}
339
340static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val)
341{
342 struct hw_perf_event *hwc = &event->hw;
343 int counter = hwc->idx;
344
345 switch (counter) {
346 case XSCALE_CYCLE_COUNTER:
347 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
348 break;
349 case XSCALE_COUNTER0:
350 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
351 break;
352 case XSCALE_COUNTER1:
353 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
354 break;
355 }
356}
357
358static int xscale_map_event(struct perf_event *event)
359{
360 return armpmu_map_event(event, &xscale_perf_map,
361 &xscale_perf_cache_map, 0xFF);
362}
363
364static int xscale1pmu_init(struct arm_pmu *cpu_pmu)
365{
366 cpu_pmu->name = "armv5_xscale1";
367 cpu_pmu->handle_irq = xscale1pmu_handle_irq;
368 cpu_pmu->enable = xscale1pmu_enable_event;
369 cpu_pmu->disable = xscale1pmu_disable_event;
370 cpu_pmu->read_counter = xscale1pmu_read_counter;
371 cpu_pmu->write_counter = xscale1pmu_write_counter;
372 cpu_pmu->get_event_idx = xscale1pmu_get_event_idx;
373 cpu_pmu->start = xscale1pmu_start;
374 cpu_pmu->stop = xscale1pmu_stop;
375 cpu_pmu->map_event = xscale_map_event;
376 cpu_pmu->num_events = 3;
377 cpu_pmu->max_period = (1LLU << 32) - 1;
378
379 return 0;
380}
381
382#define XSCALE2_OVERFLOWED_MASK 0x01f
383#define XSCALE2_CCOUNT_OVERFLOW 0x001
384#define XSCALE2_COUNT0_OVERFLOW 0x002
385#define XSCALE2_COUNT1_OVERFLOW 0x004
386#define XSCALE2_COUNT2_OVERFLOW 0x008
387#define XSCALE2_COUNT3_OVERFLOW 0x010
388#define XSCALE2_CCOUNT_INT_EN 0x001
389#define XSCALE2_COUNT0_INT_EN 0x002
390#define XSCALE2_COUNT1_INT_EN 0x004
391#define XSCALE2_COUNT2_INT_EN 0x008
392#define XSCALE2_COUNT3_INT_EN 0x010
393#define XSCALE2_COUNT0_EVT_SHFT 0
394#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
395#define XSCALE2_COUNT1_EVT_SHFT 8
396#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
397#define XSCALE2_COUNT2_EVT_SHFT 16
398#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
399#define XSCALE2_COUNT3_EVT_SHFT 24
400#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
401
402static inline u32
403xscale2pmu_read_pmnc(void)
404{
405 u32 val;
406 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
407 /* bits 1-2 and 4-23 are read-unpredictable */
408 return val & 0xff000009;
409}
410
411static inline void
412xscale2pmu_write_pmnc(u32 val)
413{
414 /* bits 4-23 are write-as-0, 24-31 are write ignored */
415 val &= 0xf;
416 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
417}
418
419static inline u32
420xscale2pmu_read_overflow_flags(void)
421{
422 u32 val;
423 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
424 return val;
425}
426
427static inline void
428xscale2pmu_write_overflow_flags(u32 val)
429{
430 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
431}
432
433static inline u32
434xscale2pmu_read_event_select(void)
435{
436 u32 val;
437 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
438 return val;
439}
440
441static inline void
442xscale2pmu_write_event_select(u32 val)
443{
444 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
445}
446
447static inline u32
448xscale2pmu_read_int_enable(void)
449{
450 u32 val;
451 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
452 return val;
453}
454
455static void
456xscale2pmu_write_int_enable(u32 val)
457{
458 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
459}
460
461static inline int
462xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
463 enum xscale_counters counter)
464{
465 int ret = 0;
466
467 switch (counter) {
468 case XSCALE_CYCLE_COUNTER:
469 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
470 break;
471 case XSCALE_COUNTER0:
472 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
473 break;
474 case XSCALE_COUNTER1:
475 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
476 break;
477 case XSCALE_COUNTER2:
478 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
479 break;
480 case XSCALE_COUNTER3:
481 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
482 break;
483 default:
484 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
485 }
486
487 return ret;
488}
489
490static irqreturn_t
491xscale2pmu_handle_irq(int irq_num, void *dev)
492{
493 unsigned long pmnc, of_flags;
494 struct perf_sample_data data;
495 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
496 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
497 struct pt_regs *regs;
498 int idx;
499
500 /* Disable the PMU. */
501 pmnc = xscale2pmu_read_pmnc();
502 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
503
504 /* Check the overflow flag register. */
505 of_flags = xscale2pmu_read_overflow_flags();
506 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
507 return IRQ_NONE;
508
509 /* Clear the overflow bits. */
510 xscale2pmu_write_overflow_flags(of_flags);
511
512 regs = get_irq_regs();
513
514 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
515 struct perf_event *event = cpuc->events[idx];
516 struct hw_perf_event *hwc;
517
518 if (!event)
519 continue;
520
521 if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
522 continue;
523
524 hwc = &event->hw;
525 armpmu_event_update(event);
526 perf_sample_data_init(&data, 0, hwc->last_period);
527 if (!armpmu_event_set_period(event))
528 continue;
529
530 if (perf_event_overflow(event, &data, regs))
531 cpu_pmu->disable(event);
532 }
533
534 irq_work_run();
535
536 /*
537 * Re-enable the PMU.
538 */
539 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
540 xscale2pmu_write_pmnc(pmnc);
541
542 return IRQ_HANDLED;
543}
544
545static void xscale2pmu_enable_event(struct perf_event *event)
546{
547 unsigned long flags, ien, evtsel;
548 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
549 struct hw_perf_event *hwc = &event->hw;
550 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
551 int idx = hwc->idx;
552
553 ien = xscale2pmu_read_int_enable();
554 evtsel = xscale2pmu_read_event_select();
555
556 switch (idx) {
557 case XSCALE_CYCLE_COUNTER:
558 ien |= XSCALE2_CCOUNT_INT_EN;
559 break;
560 case XSCALE_COUNTER0:
561 ien |= XSCALE2_COUNT0_INT_EN;
562 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
563 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
564 break;
565 case XSCALE_COUNTER1:
566 ien |= XSCALE2_COUNT1_INT_EN;
567 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
568 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
569 break;
570 case XSCALE_COUNTER2:
571 ien |= XSCALE2_COUNT2_INT_EN;
572 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
573 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
574 break;
575 case XSCALE_COUNTER3:
576 ien |= XSCALE2_COUNT3_INT_EN;
577 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
578 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
579 break;
580 default:
581 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
582 return;
583 }
584
585 raw_spin_lock_irqsave(&events->pmu_lock, flags);
586 xscale2pmu_write_event_select(evtsel);
587 xscale2pmu_write_int_enable(ien);
588 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
589}
590
591static void xscale2pmu_disable_event(struct perf_event *event)
592{
593 unsigned long flags, ien, evtsel, of_flags;
594 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
595 struct hw_perf_event *hwc = &event->hw;
596 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
597 int idx = hwc->idx;
598
599 ien = xscale2pmu_read_int_enable();
600 evtsel = xscale2pmu_read_event_select();
601
602 switch (idx) {
603 case XSCALE_CYCLE_COUNTER:
604 ien &= ~XSCALE2_CCOUNT_INT_EN;
605 of_flags = XSCALE2_CCOUNT_OVERFLOW;
606 break;
607 case XSCALE_COUNTER0:
608 ien &= ~XSCALE2_COUNT0_INT_EN;
609 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
610 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
611 of_flags = XSCALE2_COUNT0_OVERFLOW;
612 break;
613 case XSCALE_COUNTER1:
614 ien &= ~XSCALE2_COUNT1_INT_EN;
615 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
616 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
617 of_flags = XSCALE2_COUNT1_OVERFLOW;
618 break;
619 case XSCALE_COUNTER2:
620 ien &= ~XSCALE2_COUNT2_INT_EN;
621 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
622 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
623 of_flags = XSCALE2_COUNT2_OVERFLOW;
624 break;
625 case XSCALE_COUNTER3:
626 ien &= ~XSCALE2_COUNT3_INT_EN;
627 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
628 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
629 of_flags = XSCALE2_COUNT3_OVERFLOW;
630 break;
631 default:
632 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
633 return;
634 }
635
636 raw_spin_lock_irqsave(&events->pmu_lock, flags);
637 xscale2pmu_write_event_select(evtsel);
638 xscale2pmu_write_int_enable(ien);
639 xscale2pmu_write_overflow_flags(of_flags);
640 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
641}
642
643static int
644xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
645 struct perf_event *event)
646{
647 int idx = xscale1pmu_get_event_idx(cpuc, event);
648 if (idx >= 0)
649 goto out;
650
651 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
652 idx = XSCALE_COUNTER3;
653 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
654 idx = XSCALE_COUNTER2;
655out:
656 return idx;
657}
658
659static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
660{
661 unsigned long flags, val;
662 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
663
664 raw_spin_lock_irqsave(&events->pmu_lock, flags);
665 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
666 val |= XSCALE_PMU_ENABLE;
667 xscale2pmu_write_pmnc(val);
668 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
669}
670
671static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
672{
673 unsigned long flags, val;
674 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
675
676 raw_spin_lock_irqsave(&events->pmu_lock, flags);
677 val = xscale2pmu_read_pmnc();
678 val &= ~XSCALE_PMU_ENABLE;
679 xscale2pmu_write_pmnc(val);
680 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
681}
682
683static inline u32 xscale2pmu_read_counter(struct perf_event *event)
684{
685 struct hw_perf_event *hwc = &event->hw;
686 int counter = hwc->idx;
687 u32 val = 0;
688
689 switch (counter) {
690 case XSCALE_CYCLE_COUNTER:
691 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
692 break;
693 case XSCALE_COUNTER0:
694 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
695 break;
696 case XSCALE_COUNTER1:
697 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
698 break;
699 case XSCALE_COUNTER2:
700 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
701 break;
702 case XSCALE_COUNTER3:
703 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
704 break;
705 }
706
707 return val;
708}
709
710static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
711{
712 struct hw_perf_event *hwc = &event->hw;
713 int counter = hwc->idx;
714
715 switch (counter) {
716 case XSCALE_CYCLE_COUNTER:
717 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
718 break;
719 case XSCALE_COUNTER0:
720 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
721 break;
722 case XSCALE_COUNTER1:
723 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
724 break;
725 case XSCALE_COUNTER2:
726 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
727 break;
728 case XSCALE_COUNTER3:
729 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
730 break;
731 }
732}
733
734static int xscale2pmu_init(struct arm_pmu *cpu_pmu)
735{
736 cpu_pmu->name = "armv5_xscale2";
737 cpu_pmu->handle_irq = xscale2pmu_handle_irq;
738 cpu_pmu->enable = xscale2pmu_enable_event;
739 cpu_pmu->disable = xscale2pmu_disable_event;
740 cpu_pmu->read_counter = xscale2pmu_read_counter;
741 cpu_pmu->write_counter = xscale2pmu_write_counter;
742 cpu_pmu->get_event_idx = xscale2pmu_get_event_idx;
743 cpu_pmu->start = xscale2pmu_start;
744 cpu_pmu->stop = xscale2pmu_stop;
745 cpu_pmu->map_event = xscale_map_event;
746 cpu_pmu->num_events = 5;
747 cpu_pmu->max_period = (1LLU << 32) - 1;
748
749 return 0;
750}
751
752static const struct pmu_probe_info xscale_pmu_probe_table[] = {
753 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init),
754 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init),
755 { /* sentinel value */ }
756};
757
758static int xscale_pmu_device_probe(struct platform_device *pdev)
759{
760 return arm_pmu_device_probe(pdev, NULL, xscale_pmu_probe_table);
761}
762
763static struct platform_driver xscale_pmu_driver = {
764 .driver = {
765 .name = "xscale-pmu",
766 },
767 .probe = xscale_pmu_device_probe,
768};
769
770static int __init register_xscale_pmu_driver(void)
771{
772 return platform_driver_register(&xscale_pmu_driver);
773}
774device_initcall(register_xscale_pmu_driver);
775#endif /* CONFIG_CPU_XSCALE */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARMv5 [xscale] Performance counter handling code.
4 *
5 * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
6 *
7 * Based on the previous xscale OProfile code.
8 *
9 * There are two variants of the xscale PMU that we support:
10 * - xscale1pmu: 2 event counters and a cycle counter
11 * - xscale2pmu: 4 event counters and a cycle counter
12 * The two variants share event definitions, but have different
13 * PMU structures.
14 */
15
16#ifdef CONFIG_CPU_XSCALE
17
18#include <asm/cputype.h>
19#include <asm/irq_regs.h>
20
21#include <linux/of.h>
22#include <linux/perf/arm_pmu.h>
23#include <linux/platform_device.h>
24
25enum xscale_perf_types {
26 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
27 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
28 XSCALE_PERFCTR_DATA_STALL = 0x02,
29 XSCALE_PERFCTR_ITLB_MISS = 0x03,
30 XSCALE_PERFCTR_DTLB_MISS = 0x04,
31 XSCALE_PERFCTR_BRANCH = 0x05,
32 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
33 XSCALE_PERFCTR_INSTRUCTION = 0x07,
34 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
35 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
36 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
37 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
38 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
39 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
40 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
41 XSCALE_PERFCTR_BCU_FULL = 0x11,
42 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
43 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
44 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
45 XSCALE_PERFCTR_RMW = 0x16,
46 /* XSCALE_PERFCTR_CCNT is not hardware defined */
47 XSCALE_PERFCTR_CCNT = 0xFE,
48 XSCALE_PERFCTR_UNUSED = 0xFF,
49};
50
51enum xscale_counters {
52 XSCALE_CYCLE_COUNTER = 0,
53 XSCALE_COUNTER0,
54 XSCALE_COUNTER1,
55 XSCALE_COUNTER2,
56 XSCALE_COUNTER3,
57};
58
59static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
60 PERF_MAP_ALL_UNSUPPORTED,
61 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
62 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
63 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
64 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
65 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
66};
67
68static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
69 [PERF_COUNT_HW_CACHE_OP_MAX]
70 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
71 PERF_CACHE_MAP_ALL_UNSUPPORTED,
72
73 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
74 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
75 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
76 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
77
78 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
79
80 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
81 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
82
83 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
84 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
85};
86
87#define XSCALE_PMU_ENABLE 0x001
88#define XSCALE_PMN_RESET 0x002
89#define XSCALE_CCNT_RESET 0x004
90#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
91#define XSCALE_PMU_CNT64 0x008
92
93#define XSCALE1_OVERFLOWED_MASK 0x700
94#define XSCALE1_CCOUNT_OVERFLOW 0x400
95#define XSCALE1_COUNT0_OVERFLOW 0x100
96#define XSCALE1_COUNT1_OVERFLOW 0x200
97#define XSCALE1_CCOUNT_INT_EN 0x040
98#define XSCALE1_COUNT0_INT_EN 0x010
99#define XSCALE1_COUNT1_INT_EN 0x020
100#define XSCALE1_COUNT0_EVT_SHFT 12
101#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
102#define XSCALE1_COUNT1_EVT_SHFT 20
103#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
104
105static inline u32
106xscale1pmu_read_pmnc(void)
107{
108 u32 val;
109 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
110 return val;
111}
112
113static inline void
114xscale1pmu_write_pmnc(u32 val)
115{
116 /* upper 4bits and 7, 11 are write-as-0 */
117 val &= 0xffff77f;
118 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
119}
120
121static inline int
122xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
123 enum xscale_counters counter)
124{
125 int ret = 0;
126
127 switch (counter) {
128 case XSCALE_CYCLE_COUNTER:
129 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
130 break;
131 case XSCALE_COUNTER0:
132 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
133 break;
134 case XSCALE_COUNTER1:
135 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
136 break;
137 default:
138 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
139 }
140
141 return ret;
142}
143
144static irqreturn_t
145xscale1pmu_handle_irq(int irq_num, void *dev)
146{
147 unsigned long pmnc;
148 struct perf_sample_data data;
149 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
150 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
151 struct pt_regs *regs;
152 int idx;
153
154 /*
155 * NOTE: there's an A stepping erratum that states if an overflow
156 * bit already exists and another occurs, the previous
157 * Overflow bit gets cleared. There's no workaround.
158 * Fixed in B stepping or later.
159 */
160 pmnc = xscale1pmu_read_pmnc();
161
162 /*
163 * Write the value back to clear the overflow flags. Overflow
164 * flags remain in pmnc for use below. We also disable the PMU
165 * while we process the interrupt.
166 */
167 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
168
169 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
170 return IRQ_NONE;
171
172 regs = get_irq_regs();
173
174 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
175 struct perf_event *event = cpuc->events[idx];
176 struct hw_perf_event *hwc;
177
178 if (!event)
179 continue;
180
181 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
182 continue;
183
184 hwc = &event->hw;
185 armpmu_event_update(event);
186 perf_sample_data_init(&data, 0, hwc->last_period);
187 if (!armpmu_event_set_period(event))
188 continue;
189
190 if (perf_event_overflow(event, &data, regs))
191 cpu_pmu->disable(event);
192 }
193
194 irq_work_run();
195
196 /*
197 * Re-enable the PMU.
198 */
199 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
200 xscale1pmu_write_pmnc(pmnc);
201
202 return IRQ_HANDLED;
203}
204
205static void xscale1pmu_enable_event(struct perf_event *event)
206{
207 unsigned long val, mask, evt, flags;
208 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
209 struct hw_perf_event *hwc = &event->hw;
210 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
211 int idx = hwc->idx;
212
213 switch (idx) {
214 case XSCALE_CYCLE_COUNTER:
215 mask = 0;
216 evt = XSCALE1_CCOUNT_INT_EN;
217 break;
218 case XSCALE_COUNTER0:
219 mask = XSCALE1_COUNT0_EVT_MASK;
220 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
221 XSCALE1_COUNT0_INT_EN;
222 break;
223 case XSCALE_COUNTER1:
224 mask = XSCALE1_COUNT1_EVT_MASK;
225 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
226 XSCALE1_COUNT1_INT_EN;
227 break;
228 default:
229 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
230 return;
231 }
232
233 raw_spin_lock_irqsave(&events->pmu_lock, flags);
234 val = xscale1pmu_read_pmnc();
235 val &= ~mask;
236 val |= evt;
237 xscale1pmu_write_pmnc(val);
238 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
239}
240
241static void xscale1pmu_disable_event(struct perf_event *event)
242{
243 unsigned long val, mask, evt, flags;
244 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
245 struct hw_perf_event *hwc = &event->hw;
246 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
247 int idx = hwc->idx;
248
249 switch (idx) {
250 case XSCALE_CYCLE_COUNTER:
251 mask = XSCALE1_CCOUNT_INT_EN;
252 evt = 0;
253 break;
254 case XSCALE_COUNTER0:
255 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
256 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
257 break;
258 case XSCALE_COUNTER1:
259 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
260 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
261 break;
262 default:
263 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
264 return;
265 }
266
267 raw_spin_lock_irqsave(&events->pmu_lock, flags);
268 val = xscale1pmu_read_pmnc();
269 val &= ~mask;
270 val |= evt;
271 xscale1pmu_write_pmnc(val);
272 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
273}
274
275static int
276xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
277 struct perf_event *event)
278{
279 struct hw_perf_event *hwc = &event->hw;
280 if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
281 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
282 return -EAGAIN;
283
284 return XSCALE_CYCLE_COUNTER;
285 } else {
286 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
287 return XSCALE_COUNTER1;
288
289 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
290 return XSCALE_COUNTER0;
291
292 return -EAGAIN;
293 }
294}
295
296static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
297{
298 unsigned long flags, val;
299 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
300
301 raw_spin_lock_irqsave(&events->pmu_lock, flags);
302 val = xscale1pmu_read_pmnc();
303 val |= XSCALE_PMU_ENABLE;
304 xscale1pmu_write_pmnc(val);
305 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
306}
307
308static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
309{
310 unsigned long flags, val;
311 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
312
313 raw_spin_lock_irqsave(&events->pmu_lock, flags);
314 val = xscale1pmu_read_pmnc();
315 val &= ~XSCALE_PMU_ENABLE;
316 xscale1pmu_write_pmnc(val);
317 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
318}
319
320static inline u32 xscale1pmu_read_counter(struct perf_event *event)
321{
322 struct hw_perf_event *hwc = &event->hw;
323 int counter = hwc->idx;
324 u32 val = 0;
325
326 switch (counter) {
327 case XSCALE_CYCLE_COUNTER:
328 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
329 break;
330 case XSCALE_COUNTER0:
331 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
332 break;
333 case XSCALE_COUNTER1:
334 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
335 break;
336 }
337
338 return val;
339}
340
341static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val)
342{
343 struct hw_perf_event *hwc = &event->hw;
344 int counter = hwc->idx;
345
346 switch (counter) {
347 case XSCALE_CYCLE_COUNTER:
348 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
349 break;
350 case XSCALE_COUNTER0:
351 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
352 break;
353 case XSCALE_COUNTER1:
354 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
355 break;
356 }
357}
358
359static int xscale_map_event(struct perf_event *event)
360{
361 return armpmu_map_event(event, &xscale_perf_map,
362 &xscale_perf_cache_map, 0xFF);
363}
364
365static int xscale1pmu_init(struct arm_pmu *cpu_pmu)
366{
367 cpu_pmu->name = "armv5_xscale1";
368 cpu_pmu->handle_irq = xscale1pmu_handle_irq;
369 cpu_pmu->enable = xscale1pmu_enable_event;
370 cpu_pmu->disable = xscale1pmu_disable_event;
371 cpu_pmu->read_counter = xscale1pmu_read_counter;
372 cpu_pmu->write_counter = xscale1pmu_write_counter;
373 cpu_pmu->get_event_idx = xscale1pmu_get_event_idx;
374 cpu_pmu->start = xscale1pmu_start;
375 cpu_pmu->stop = xscale1pmu_stop;
376 cpu_pmu->map_event = xscale_map_event;
377 cpu_pmu->num_events = 3;
378 cpu_pmu->max_period = (1LLU << 32) - 1;
379
380 return 0;
381}
382
383#define XSCALE2_OVERFLOWED_MASK 0x01f
384#define XSCALE2_CCOUNT_OVERFLOW 0x001
385#define XSCALE2_COUNT0_OVERFLOW 0x002
386#define XSCALE2_COUNT1_OVERFLOW 0x004
387#define XSCALE2_COUNT2_OVERFLOW 0x008
388#define XSCALE2_COUNT3_OVERFLOW 0x010
389#define XSCALE2_CCOUNT_INT_EN 0x001
390#define XSCALE2_COUNT0_INT_EN 0x002
391#define XSCALE2_COUNT1_INT_EN 0x004
392#define XSCALE2_COUNT2_INT_EN 0x008
393#define XSCALE2_COUNT3_INT_EN 0x010
394#define XSCALE2_COUNT0_EVT_SHFT 0
395#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
396#define XSCALE2_COUNT1_EVT_SHFT 8
397#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
398#define XSCALE2_COUNT2_EVT_SHFT 16
399#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
400#define XSCALE2_COUNT3_EVT_SHFT 24
401#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
402
403static inline u32
404xscale2pmu_read_pmnc(void)
405{
406 u32 val;
407 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
408 /* bits 1-2 and 4-23 are read-unpredictable */
409 return val & 0xff000009;
410}
411
412static inline void
413xscale2pmu_write_pmnc(u32 val)
414{
415 /* bits 4-23 are write-as-0, 24-31 are write ignored */
416 val &= 0xf;
417 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
418}
419
420static inline u32
421xscale2pmu_read_overflow_flags(void)
422{
423 u32 val;
424 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
425 return val;
426}
427
428static inline void
429xscale2pmu_write_overflow_flags(u32 val)
430{
431 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
432}
433
434static inline u32
435xscale2pmu_read_event_select(void)
436{
437 u32 val;
438 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
439 return val;
440}
441
442static inline void
443xscale2pmu_write_event_select(u32 val)
444{
445 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
446}
447
448static inline u32
449xscale2pmu_read_int_enable(void)
450{
451 u32 val;
452 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
453 return val;
454}
455
456static void
457xscale2pmu_write_int_enable(u32 val)
458{
459 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
460}
461
462static inline int
463xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
464 enum xscale_counters counter)
465{
466 int ret = 0;
467
468 switch (counter) {
469 case XSCALE_CYCLE_COUNTER:
470 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
471 break;
472 case XSCALE_COUNTER0:
473 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
474 break;
475 case XSCALE_COUNTER1:
476 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
477 break;
478 case XSCALE_COUNTER2:
479 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
480 break;
481 case XSCALE_COUNTER3:
482 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
483 break;
484 default:
485 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
486 }
487
488 return ret;
489}
490
491static irqreturn_t
492xscale2pmu_handle_irq(int irq_num, void *dev)
493{
494 unsigned long pmnc, of_flags;
495 struct perf_sample_data data;
496 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
497 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
498 struct pt_regs *regs;
499 int idx;
500
501 /* Disable the PMU. */
502 pmnc = xscale2pmu_read_pmnc();
503 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
504
505 /* Check the overflow flag register. */
506 of_flags = xscale2pmu_read_overflow_flags();
507 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
508 return IRQ_NONE;
509
510 /* Clear the overflow bits. */
511 xscale2pmu_write_overflow_flags(of_flags);
512
513 regs = get_irq_regs();
514
515 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
516 struct perf_event *event = cpuc->events[idx];
517 struct hw_perf_event *hwc;
518
519 if (!event)
520 continue;
521
522 if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
523 continue;
524
525 hwc = &event->hw;
526 armpmu_event_update(event);
527 perf_sample_data_init(&data, 0, hwc->last_period);
528 if (!armpmu_event_set_period(event))
529 continue;
530
531 if (perf_event_overflow(event, &data, regs))
532 cpu_pmu->disable(event);
533 }
534
535 irq_work_run();
536
537 /*
538 * Re-enable the PMU.
539 */
540 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
541 xscale2pmu_write_pmnc(pmnc);
542
543 return IRQ_HANDLED;
544}
545
546static void xscale2pmu_enable_event(struct perf_event *event)
547{
548 unsigned long flags, ien, evtsel;
549 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
550 struct hw_perf_event *hwc = &event->hw;
551 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
552 int idx = hwc->idx;
553
554 ien = xscale2pmu_read_int_enable();
555 evtsel = xscale2pmu_read_event_select();
556
557 switch (idx) {
558 case XSCALE_CYCLE_COUNTER:
559 ien |= XSCALE2_CCOUNT_INT_EN;
560 break;
561 case XSCALE_COUNTER0:
562 ien |= XSCALE2_COUNT0_INT_EN;
563 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
564 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
565 break;
566 case XSCALE_COUNTER1:
567 ien |= XSCALE2_COUNT1_INT_EN;
568 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
569 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
570 break;
571 case XSCALE_COUNTER2:
572 ien |= XSCALE2_COUNT2_INT_EN;
573 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
574 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
575 break;
576 case XSCALE_COUNTER3:
577 ien |= XSCALE2_COUNT3_INT_EN;
578 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
579 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
580 break;
581 default:
582 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
583 return;
584 }
585
586 raw_spin_lock_irqsave(&events->pmu_lock, flags);
587 xscale2pmu_write_event_select(evtsel);
588 xscale2pmu_write_int_enable(ien);
589 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
590}
591
592static void xscale2pmu_disable_event(struct perf_event *event)
593{
594 unsigned long flags, ien, evtsel, of_flags;
595 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
596 struct hw_perf_event *hwc = &event->hw;
597 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
598 int idx = hwc->idx;
599
600 ien = xscale2pmu_read_int_enable();
601 evtsel = xscale2pmu_read_event_select();
602
603 switch (idx) {
604 case XSCALE_CYCLE_COUNTER:
605 ien &= ~XSCALE2_CCOUNT_INT_EN;
606 of_flags = XSCALE2_CCOUNT_OVERFLOW;
607 break;
608 case XSCALE_COUNTER0:
609 ien &= ~XSCALE2_COUNT0_INT_EN;
610 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
611 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
612 of_flags = XSCALE2_COUNT0_OVERFLOW;
613 break;
614 case XSCALE_COUNTER1:
615 ien &= ~XSCALE2_COUNT1_INT_EN;
616 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
617 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
618 of_flags = XSCALE2_COUNT1_OVERFLOW;
619 break;
620 case XSCALE_COUNTER2:
621 ien &= ~XSCALE2_COUNT2_INT_EN;
622 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
623 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
624 of_flags = XSCALE2_COUNT2_OVERFLOW;
625 break;
626 case XSCALE_COUNTER3:
627 ien &= ~XSCALE2_COUNT3_INT_EN;
628 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
629 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
630 of_flags = XSCALE2_COUNT3_OVERFLOW;
631 break;
632 default:
633 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
634 return;
635 }
636
637 raw_spin_lock_irqsave(&events->pmu_lock, flags);
638 xscale2pmu_write_event_select(evtsel);
639 xscale2pmu_write_int_enable(ien);
640 xscale2pmu_write_overflow_flags(of_flags);
641 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
642}
643
644static int
645xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
646 struct perf_event *event)
647{
648 int idx = xscale1pmu_get_event_idx(cpuc, event);
649 if (idx >= 0)
650 goto out;
651
652 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
653 idx = XSCALE_COUNTER3;
654 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
655 idx = XSCALE_COUNTER2;
656out:
657 return idx;
658}
659
660static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
661{
662 unsigned long flags, val;
663 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
664
665 raw_spin_lock_irqsave(&events->pmu_lock, flags);
666 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
667 val |= XSCALE_PMU_ENABLE;
668 xscale2pmu_write_pmnc(val);
669 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
670}
671
672static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
673{
674 unsigned long flags, val;
675 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
676
677 raw_spin_lock_irqsave(&events->pmu_lock, flags);
678 val = xscale2pmu_read_pmnc();
679 val &= ~XSCALE_PMU_ENABLE;
680 xscale2pmu_write_pmnc(val);
681 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
682}
683
684static inline u32 xscale2pmu_read_counter(struct perf_event *event)
685{
686 struct hw_perf_event *hwc = &event->hw;
687 int counter = hwc->idx;
688 u32 val = 0;
689
690 switch (counter) {
691 case XSCALE_CYCLE_COUNTER:
692 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
693 break;
694 case XSCALE_COUNTER0:
695 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
696 break;
697 case XSCALE_COUNTER1:
698 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
699 break;
700 case XSCALE_COUNTER2:
701 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
702 break;
703 case XSCALE_COUNTER3:
704 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
705 break;
706 }
707
708 return val;
709}
710
711static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
712{
713 struct hw_perf_event *hwc = &event->hw;
714 int counter = hwc->idx;
715
716 switch (counter) {
717 case XSCALE_CYCLE_COUNTER:
718 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
719 break;
720 case XSCALE_COUNTER0:
721 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
722 break;
723 case XSCALE_COUNTER1:
724 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
725 break;
726 case XSCALE_COUNTER2:
727 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
728 break;
729 case XSCALE_COUNTER3:
730 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
731 break;
732 }
733}
734
735static int xscale2pmu_init(struct arm_pmu *cpu_pmu)
736{
737 cpu_pmu->name = "armv5_xscale2";
738 cpu_pmu->handle_irq = xscale2pmu_handle_irq;
739 cpu_pmu->enable = xscale2pmu_enable_event;
740 cpu_pmu->disable = xscale2pmu_disable_event;
741 cpu_pmu->read_counter = xscale2pmu_read_counter;
742 cpu_pmu->write_counter = xscale2pmu_write_counter;
743 cpu_pmu->get_event_idx = xscale2pmu_get_event_idx;
744 cpu_pmu->start = xscale2pmu_start;
745 cpu_pmu->stop = xscale2pmu_stop;
746 cpu_pmu->map_event = xscale_map_event;
747 cpu_pmu->num_events = 5;
748 cpu_pmu->max_period = (1LLU << 32) - 1;
749
750 return 0;
751}
752
753static const struct pmu_probe_info xscale_pmu_probe_table[] = {
754 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init),
755 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init),
756 { /* sentinel value */ }
757};
758
759static int xscale_pmu_device_probe(struct platform_device *pdev)
760{
761 return arm_pmu_device_probe(pdev, NULL, xscale_pmu_probe_table);
762}
763
764static struct platform_driver xscale_pmu_driver = {
765 .driver = {
766 .name = "xscale-pmu",
767 },
768 .probe = xscale_pmu_device_probe,
769};
770
771builtin_platform_driver(xscale_pmu_driver);
772#endif /* CONFIG_CPU_XSCALE */