Loading...
1/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/watchdog.h>
21
22#define WDT_RST 0x38
23#define WDT_EN 0x40
24#define WDT_BITE_TIME 0x5C
25
26struct qcom_wdt {
27 struct watchdog_device wdd;
28 struct clk *clk;
29 unsigned long rate;
30 void __iomem *base;
31};
32
33static inline
34struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
35{
36 return container_of(wdd, struct qcom_wdt, wdd);
37}
38
39static int qcom_wdt_start(struct watchdog_device *wdd)
40{
41 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
42
43 writel(0, wdt->base + WDT_EN);
44 writel(1, wdt->base + WDT_RST);
45 writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
46 writel(1, wdt->base + WDT_EN);
47 return 0;
48}
49
50static int qcom_wdt_stop(struct watchdog_device *wdd)
51{
52 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
53
54 writel(0, wdt->base + WDT_EN);
55 return 0;
56}
57
58static int qcom_wdt_ping(struct watchdog_device *wdd)
59{
60 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
61
62 writel(1, wdt->base + WDT_RST);
63 return 0;
64}
65
66static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
67 unsigned int timeout)
68{
69 wdd->timeout = timeout;
70 return qcom_wdt_start(wdd);
71}
72
73static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
74 void *data)
75{
76 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
77 u32 timeout;
78
79 /*
80 * Trigger watchdog bite:
81 * Setup BITE_TIME to be 128ms, and enable WDT.
82 */
83 timeout = 128 * wdt->rate / 1000;
84
85 writel(0, wdt->base + WDT_EN);
86 writel(1, wdt->base + WDT_RST);
87 writel(timeout, wdt->base + WDT_BITE_TIME);
88 writel(1, wdt->base + WDT_EN);
89
90 /*
91 * Actually make sure the above sequence hits hardware before sleeping.
92 */
93 wmb();
94
95 msleep(150);
96 return 0;
97}
98
99static const struct watchdog_ops qcom_wdt_ops = {
100 .start = qcom_wdt_start,
101 .stop = qcom_wdt_stop,
102 .ping = qcom_wdt_ping,
103 .set_timeout = qcom_wdt_set_timeout,
104 .restart = qcom_wdt_restart,
105 .owner = THIS_MODULE,
106};
107
108static const struct watchdog_info qcom_wdt_info = {
109 .options = WDIOF_KEEPALIVEPING
110 | WDIOF_MAGICCLOSE
111 | WDIOF_SETTIMEOUT,
112 .identity = KBUILD_MODNAME,
113};
114
115static int qcom_wdt_probe(struct platform_device *pdev)
116{
117 struct qcom_wdt *wdt;
118 struct resource *res;
119 struct device_node *np = pdev->dev.of_node;
120 u32 percpu_offset;
121 int ret;
122
123 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
124 if (!wdt)
125 return -ENOMEM;
126
127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128
129 /* We use CPU0's DGT for the watchdog */
130 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
131 percpu_offset = 0;
132
133 res->start += percpu_offset;
134 res->end += percpu_offset;
135
136 wdt->base = devm_ioremap_resource(&pdev->dev, res);
137 if (IS_ERR(wdt->base))
138 return PTR_ERR(wdt->base);
139
140 wdt->clk = devm_clk_get(&pdev->dev, NULL);
141 if (IS_ERR(wdt->clk)) {
142 dev_err(&pdev->dev, "failed to get input clock\n");
143 return PTR_ERR(wdt->clk);
144 }
145
146 ret = clk_prepare_enable(wdt->clk);
147 if (ret) {
148 dev_err(&pdev->dev, "failed to setup clock\n");
149 return ret;
150 }
151
152 /*
153 * We use the clock rate to calculate the max timeout, so ensure it's
154 * not zero to avoid a divide-by-zero exception.
155 *
156 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
157 * that it would bite before a second elapses it's usefulness is
158 * limited. Bail if this is the case.
159 */
160 wdt->rate = clk_get_rate(wdt->clk);
161 if (wdt->rate == 0 ||
162 wdt->rate > 0x10000000U) {
163 dev_err(&pdev->dev, "invalid clock rate\n");
164 ret = -EINVAL;
165 goto err_clk_unprepare;
166 }
167
168 wdt->wdd.info = &qcom_wdt_info;
169 wdt->wdd.ops = &qcom_wdt_ops;
170 wdt->wdd.min_timeout = 1;
171 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
172 wdt->wdd.parent = &pdev->dev;
173
174 /*
175 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
176 * default, unless the max timeout is less than 30 seconds, then use
177 * the max instead.
178 */
179 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
180 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
181
182 ret = watchdog_register_device(&wdt->wdd);
183 if (ret) {
184 dev_err(&pdev->dev, "failed to register watchdog\n");
185 goto err_clk_unprepare;
186 }
187
188 platform_set_drvdata(pdev, wdt);
189 return 0;
190
191err_clk_unprepare:
192 clk_disable_unprepare(wdt->clk);
193 return ret;
194}
195
196static int qcom_wdt_remove(struct platform_device *pdev)
197{
198 struct qcom_wdt *wdt = platform_get_drvdata(pdev);
199
200 watchdog_unregister_device(&wdt->wdd);
201 clk_disable_unprepare(wdt->clk);
202 return 0;
203}
204
205static const struct of_device_id qcom_wdt_of_table[] = {
206 { .compatible = "qcom,kpss-timer" },
207 { .compatible = "qcom,scss-timer" },
208 { },
209};
210MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
211
212static struct platform_driver qcom_watchdog_driver = {
213 .probe = qcom_wdt_probe,
214 .remove = qcom_wdt_remove,
215 .driver = {
216 .name = KBUILD_MODNAME,
217 .of_match_table = qcom_wdt_of_table,
218 },
219};
220module_platform_driver(qcom_watchdog_driver);
221
222MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
223MODULE_LICENSE("GPL v2");
1/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/watchdog.h>
21#include <linux/of_device.h>
22
23enum wdt_reg {
24 WDT_RST,
25 WDT_EN,
26 WDT_STS,
27 WDT_BARK_TIME,
28 WDT_BITE_TIME,
29};
30
31static const u32 reg_offset_data_apcs_tmr[] = {
32 [WDT_RST] = 0x38,
33 [WDT_EN] = 0x40,
34 [WDT_STS] = 0x44,
35 [WDT_BARK_TIME] = 0x4C,
36 [WDT_BITE_TIME] = 0x5C,
37};
38
39static const u32 reg_offset_data_kpss[] = {
40 [WDT_RST] = 0x4,
41 [WDT_EN] = 0x8,
42 [WDT_STS] = 0xC,
43 [WDT_BARK_TIME] = 0x10,
44 [WDT_BITE_TIME] = 0x14,
45};
46
47struct qcom_wdt {
48 struct watchdog_device wdd;
49 struct clk *clk;
50 unsigned long rate;
51 void __iomem *base;
52 const u32 *layout;
53};
54
55static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
56{
57 return wdt->base + wdt->layout[reg];
58}
59
60static inline
61struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
62{
63 return container_of(wdd, struct qcom_wdt, wdd);
64}
65
66static int qcom_wdt_start(struct watchdog_device *wdd)
67{
68 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
69
70 writel(0, wdt_addr(wdt, WDT_EN));
71 writel(1, wdt_addr(wdt, WDT_RST));
72 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
73 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
74 writel(1, wdt_addr(wdt, WDT_EN));
75 return 0;
76}
77
78static int qcom_wdt_stop(struct watchdog_device *wdd)
79{
80 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
81
82 writel(0, wdt_addr(wdt, WDT_EN));
83 return 0;
84}
85
86static int qcom_wdt_ping(struct watchdog_device *wdd)
87{
88 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
89
90 writel(1, wdt_addr(wdt, WDT_RST));
91 return 0;
92}
93
94static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
95 unsigned int timeout)
96{
97 wdd->timeout = timeout;
98 return qcom_wdt_start(wdd);
99}
100
101static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
102 void *data)
103{
104 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
105 u32 timeout;
106
107 /*
108 * Trigger watchdog bite:
109 * Setup BITE_TIME to be 128ms, and enable WDT.
110 */
111 timeout = 128 * wdt->rate / 1000;
112
113 writel(0, wdt_addr(wdt, WDT_EN));
114 writel(1, wdt_addr(wdt, WDT_RST));
115 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
116 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
117 writel(1, wdt_addr(wdt, WDT_EN));
118
119 /*
120 * Actually make sure the above sequence hits hardware before sleeping.
121 */
122 wmb();
123
124 msleep(150);
125 return 0;
126}
127
128static const struct watchdog_ops qcom_wdt_ops = {
129 .start = qcom_wdt_start,
130 .stop = qcom_wdt_stop,
131 .ping = qcom_wdt_ping,
132 .set_timeout = qcom_wdt_set_timeout,
133 .restart = qcom_wdt_restart,
134 .owner = THIS_MODULE,
135};
136
137static const struct watchdog_info qcom_wdt_info = {
138 .options = WDIOF_KEEPALIVEPING
139 | WDIOF_MAGICCLOSE
140 | WDIOF_SETTIMEOUT
141 | WDIOF_CARDRESET,
142 .identity = KBUILD_MODNAME,
143};
144
145static int qcom_wdt_probe(struct platform_device *pdev)
146{
147 struct qcom_wdt *wdt;
148 struct resource *res;
149 struct device_node *np = pdev->dev.of_node;
150 const u32 *regs;
151 u32 percpu_offset;
152 int ret;
153
154 regs = of_device_get_match_data(&pdev->dev);
155 if (!regs) {
156 dev_err(&pdev->dev, "Unsupported QCOM WDT module\n");
157 return -ENODEV;
158 }
159
160 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
161 if (!wdt)
162 return -ENOMEM;
163
164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
165 if (!res)
166 return -ENOMEM;
167
168 /* We use CPU0's DGT for the watchdog */
169 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
170 percpu_offset = 0;
171
172 res->start += percpu_offset;
173 res->end += percpu_offset;
174
175 wdt->base = devm_ioremap_resource(&pdev->dev, res);
176 if (IS_ERR(wdt->base))
177 return PTR_ERR(wdt->base);
178
179 wdt->clk = devm_clk_get(&pdev->dev, NULL);
180 if (IS_ERR(wdt->clk)) {
181 dev_err(&pdev->dev, "failed to get input clock\n");
182 return PTR_ERR(wdt->clk);
183 }
184
185 ret = clk_prepare_enable(wdt->clk);
186 if (ret) {
187 dev_err(&pdev->dev, "failed to setup clock\n");
188 return ret;
189 }
190
191 /*
192 * We use the clock rate to calculate the max timeout, so ensure it's
193 * not zero to avoid a divide-by-zero exception.
194 *
195 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
196 * that it would bite before a second elapses it's usefulness is
197 * limited. Bail if this is the case.
198 */
199 wdt->rate = clk_get_rate(wdt->clk);
200 if (wdt->rate == 0 ||
201 wdt->rate > 0x10000000U) {
202 dev_err(&pdev->dev, "invalid clock rate\n");
203 ret = -EINVAL;
204 goto err_clk_unprepare;
205 }
206
207 wdt->wdd.info = &qcom_wdt_info;
208 wdt->wdd.ops = &qcom_wdt_ops;
209 wdt->wdd.min_timeout = 1;
210 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
211 wdt->wdd.parent = &pdev->dev;
212 wdt->layout = regs;
213
214 if (readl(wdt_addr(wdt, WDT_STS)) & 1)
215 wdt->wdd.bootstatus = WDIOF_CARDRESET;
216
217 /*
218 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
219 * default, unless the max timeout is less than 30 seconds, then use
220 * the max instead.
221 */
222 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
223 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
224
225 ret = watchdog_register_device(&wdt->wdd);
226 if (ret) {
227 dev_err(&pdev->dev, "failed to register watchdog\n");
228 goto err_clk_unprepare;
229 }
230
231 platform_set_drvdata(pdev, wdt);
232 return 0;
233
234err_clk_unprepare:
235 clk_disable_unprepare(wdt->clk);
236 return ret;
237}
238
239static int qcom_wdt_remove(struct platform_device *pdev)
240{
241 struct qcom_wdt *wdt = platform_get_drvdata(pdev);
242
243 watchdog_unregister_device(&wdt->wdd);
244 clk_disable_unprepare(wdt->clk);
245 return 0;
246}
247
248static const struct of_device_id qcom_wdt_of_table[] = {
249 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
250 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
251 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
252 { },
253};
254MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
255
256static struct platform_driver qcom_watchdog_driver = {
257 .probe = qcom_wdt_probe,
258 .remove = qcom_wdt_remove,
259 .driver = {
260 .name = KBUILD_MODNAME,
261 .of_match_table = qcom_wdt_of_table,
262 },
263};
264module_platform_driver(qcom_watchdog_driver);
265
266MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
267MODULE_LICENSE("GPL v2");