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1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#undef DEBUG
16#undef VERBOSE
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/ioport.h>
21#include <linux/types.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/timer.h>
26#include <linux/list.h>
27#include <linux/interrupt.h>
28#include <linux/proc_fs.h>
29#include <linux/mm.h>
30#include <linux/moduleparam.h>
31#include <linux/platform_device.h>
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
34#include <linux/usb/otg.h>
35#include <linux/dma-mapping.h>
36#include <linux/clk.h>
37#include <linux/err.h>
38#include <linux/prefetch.h>
39#include <linux/io.h>
40
41#include <asm/byteorder.h>
42#include <asm/irq.h>
43#include <asm/unaligned.h>
44#include <asm/mach-types.h>
45
46#include <linux/omap-dma.h>
47
48#include <mach/usb.h>
49
50#include "omap_udc.h"
51
52#undef USB_TRACE
53
54/* bulk DMA seems to be behaving for both IN and OUT */
55#define USE_DMA
56
57/* ISO too */
58#define USE_ISO
59
60#define DRIVER_DESC "OMAP UDC driver"
61#define DRIVER_VERSION "4 October 2004"
62
63#define OMAP_DMA_USB_W2FC_TX0 29
64#define OMAP_DMA_USB_W2FC_RX0 26
65
66/*
67 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
68 * D+ pullup to allow enumeration. That's too early for the gadget
69 * framework to use from usb_endpoint_enable(), which happens after
70 * enumeration as part of activating an interface. (But if we add an
71 * optional new "UDC not yet running" state to the gadget driver model,
72 * even just during driver binding, the endpoint autoconfig logic is the
73 * natural spot to manufacture new endpoints.)
74 *
75 * So instead of using endpoint enable calls to control the hardware setup,
76 * this driver defines a "fifo mode" parameter. It's used during driver
77 * initialization to choose among a set of pre-defined endpoint configs.
78 * See omap_udc_setup() for available modes, or to add others. That code
79 * lives in an init section, so use this driver as a module if you need
80 * to change the fifo mode after the kernel boots.
81 *
82 * Gadget drivers normally ignore endpoints they don't care about, and
83 * won't include them in configuration descriptors. That means only
84 * misbehaving hosts would even notice they exist.
85 */
86#ifdef USE_ISO
87static unsigned fifo_mode = 3;
88#else
89static unsigned fifo_mode;
90#endif
91
92/* "modprobe omap_udc fifo_mode=42", or else as a kernel
93 * boot parameter "omap_udc:fifo_mode=42"
94 */
95module_param(fifo_mode, uint, 0);
96MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
97
98#ifdef USE_DMA
99static bool use_dma = 1;
100
101/* "modprobe omap_udc use_dma=y", or else as a kernel
102 * boot parameter "omap_udc:use_dma=y"
103 */
104module_param(use_dma, bool, 0);
105MODULE_PARM_DESC(use_dma, "enable/disable DMA");
106#else /* !USE_DMA */
107
108/* save a bit of code */
109#define use_dma 0
110#endif /* !USE_DMA */
111
112
113static const char driver_name[] = "omap_udc";
114static const char driver_desc[] = DRIVER_DESC;
115
116/*-------------------------------------------------------------------------*/
117
118/* there's a notion of "current endpoint" for modifying endpoint
119 * state, and PIO access to its FIFO.
120 */
121
122static void use_ep(struct omap_ep *ep, u16 select)
123{
124 u16 num = ep->bEndpointAddress & 0x0f;
125
126 if (ep->bEndpointAddress & USB_DIR_IN)
127 num |= UDC_EP_DIR;
128 omap_writew(num | select, UDC_EP_NUM);
129 /* when select, MUST deselect later !! */
130}
131
132static inline void deselect_ep(void)
133{
134 u16 w;
135
136 w = omap_readw(UDC_EP_NUM);
137 w &= ~UDC_EP_SEL;
138 omap_writew(w, UDC_EP_NUM);
139 /* 6 wait states before TX will happen */
140}
141
142static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
143
144/*-------------------------------------------------------------------------*/
145
146static int omap_ep_enable(struct usb_ep *_ep,
147 const struct usb_endpoint_descriptor *desc)
148{
149 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
150 struct omap_udc *udc;
151 unsigned long flags;
152 u16 maxp;
153
154 /* catch various bogus parameters */
155 if (!_ep || !desc
156 || desc->bDescriptorType != USB_DT_ENDPOINT
157 || ep->bEndpointAddress != desc->bEndpointAddress
158 || ep->maxpacket < usb_endpoint_maxp(desc)) {
159 DBG("%s, bad ep or descriptor\n", __func__);
160 return -EINVAL;
161 }
162 maxp = usb_endpoint_maxp(desc);
163 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
164 && maxp != ep->maxpacket)
165 || usb_endpoint_maxp(desc) > ep->maxpacket
166 || !desc->wMaxPacketSize) {
167 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
168 return -ERANGE;
169 }
170
171#ifdef USE_ISO
172 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
173 && desc->bInterval != 1)) {
174 /* hardware wants period = 1; USB allows 2^(Interval-1) */
175 DBG("%s, unsupported ISO period %dms\n", _ep->name,
176 1 << (desc->bInterval - 1));
177 return -EDOM;
178 }
179#else
180 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
181 DBG("%s, ISO nyet\n", _ep->name);
182 return -EDOM;
183 }
184#endif
185
186 /* xfer types must match, except that interrupt ~= bulk */
187 if (ep->bmAttributes != desc->bmAttributes
188 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
189 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
190 DBG("%s, %s type mismatch\n", __func__, _ep->name);
191 return -EINVAL;
192 }
193
194 udc = ep->udc;
195 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
196 DBG("%s, bogus device state\n", __func__);
197 return -ESHUTDOWN;
198 }
199
200 spin_lock_irqsave(&udc->lock, flags);
201
202 ep->ep.desc = desc;
203 ep->irqs = 0;
204 ep->stopped = 0;
205 ep->ep.maxpacket = maxp;
206
207 /* set endpoint to initial state */
208 ep->dma_channel = 0;
209 ep->has_dma = 0;
210 ep->lch = -1;
211 use_ep(ep, UDC_EP_SEL);
212 omap_writew(udc->clr_halt, UDC_CTRL);
213 ep->ackwait = 0;
214 deselect_ep();
215
216 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
217 list_add(&ep->iso, &udc->iso);
218
219 /* maybe assign a DMA channel to this endpoint */
220 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
221 /* FIXME ISO can dma, but prefers first channel */
222 dma_channel_claim(ep, 0);
223
224 /* PIO OUT may RX packets */
225 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
226 && !ep->has_dma
227 && !(ep->bEndpointAddress & USB_DIR_IN)) {
228 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
229 ep->ackwait = 1 + ep->double_buf;
230 }
231
232 spin_unlock_irqrestore(&udc->lock, flags);
233 VDBG("%s enabled\n", _ep->name);
234 return 0;
235}
236
237static void nuke(struct omap_ep *, int status);
238
239static int omap_ep_disable(struct usb_ep *_ep)
240{
241 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
242 unsigned long flags;
243
244 if (!_ep || !ep->ep.desc) {
245 DBG("%s, %s not enabled\n", __func__,
246 _ep ? ep->ep.name : NULL);
247 return -EINVAL;
248 }
249
250 spin_lock_irqsave(&ep->udc->lock, flags);
251 ep->ep.desc = NULL;
252 nuke(ep, -ESHUTDOWN);
253 ep->ep.maxpacket = ep->maxpacket;
254 ep->has_dma = 0;
255 omap_writew(UDC_SET_HALT, UDC_CTRL);
256 list_del_init(&ep->iso);
257 del_timer(&ep->timer);
258
259 spin_unlock_irqrestore(&ep->udc->lock, flags);
260
261 VDBG("%s disabled\n", _ep->name);
262 return 0;
263}
264
265/*-------------------------------------------------------------------------*/
266
267static struct usb_request *
268omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
269{
270 struct omap_req *req;
271
272 req = kzalloc(sizeof(*req), gfp_flags);
273 if (!req)
274 return NULL;
275
276 INIT_LIST_HEAD(&req->queue);
277
278 return &req->req;
279}
280
281static void
282omap_free_request(struct usb_ep *ep, struct usb_request *_req)
283{
284 struct omap_req *req = container_of(_req, struct omap_req, req);
285
286 kfree(req);
287}
288
289/*-------------------------------------------------------------------------*/
290
291static void
292done(struct omap_ep *ep, struct omap_req *req, int status)
293{
294 struct omap_udc *udc = ep->udc;
295 unsigned stopped = ep->stopped;
296
297 list_del_init(&req->queue);
298
299 if (req->req.status == -EINPROGRESS)
300 req->req.status = status;
301 else
302 status = req->req.status;
303
304 if (use_dma && ep->has_dma)
305 usb_gadget_unmap_request(&udc->gadget, &req->req,
306 (ep->bEndpointAddress & USB_DIR_IN));
307
308#ifndef USB_TRACE
309 if (status && status != -ESHUTDOWN)
310#endif
311 VDBG("complete %s req %p stat %d len %u/%u\n",
312 ep->ep.name, &req->req, status,
313 req->req.actual, req->req.length);
314
315 /* don't modify queue heads during completion callback */
316 ep->stopped = 1;
317 spin_unlock(&ep->udc->lock);
318 usb_gadget_giveback_request(&ep->ep, &req->req);
319 spin_lock(&ep->udc->lock);
320 ep->stopped = stopped;
321}
322
323/*-------------------------------------------------------------------------*/
324
325#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
326#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
327
328#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
329#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
330
331static inline int
332write_packet(u8 *buf, struct omap_req *req, unsigned max)
333{
334 unsigned len;
335 u16 *wp;
336
337 len = min(req->req.length - req->req.actual, max);
338 req->req.actual += len;
339
340 max = len;
341 if (likely((((int)buf) & 1) == 0)) {
342 wp = (u16 *)buf;
343 while (max >= 2) {
344 omap_writew(*wp++, UDC_DATA);
345 max -= 2;
346 }
347 buf = (u8 *)wp;
348 }
349 while (max--)
350 omap_writeb(*buf++, UDC_DATA);
351 return len;
352}
353
354/* FIXME change r/w fifo calling convention */
355
356
357/* return: 0 = still running, 1 = completed, negative = errno */
358static int write_fifo(struct omap_ep *ep, struct omap_req *req)
359{
360 u8 *buf;
361 unsigned count;
362 int is_last;
363 u16 ep_stat;
364
365 buf = req->req.buf + req->req.actual;
366 prefetch(buf);
367
368 /* PIO-IN isn't double buffered except for iso */
369 ep_stat = omap_readw(UDC_STAT_FLG);
370 if (ep_stat & UDC_FIFO_UNWRITABLE)
371 return 0;
372
373 count = ep->ep.maxpacket;
374 count = write_packet(buf, req, count);
375 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
376 ep->ackwait = 1;
377
378 /* last packet is often short (sometimes a zlp) */
379 if (count != ep->ep.maxpacket)
380 is_last = 1;
381 else if (req->req.length == req->req.actual
382 && !req->req.zero)
383 is_last = 1;
384 else
385 is_last = 0;
386
387 /* NOTE: requests complete when all IN data is in a
388 * FIFO (or sometimes later, if a zlp was needed).
389 * Use usb_ep_fifo_status() where needed.
390 */
391 if (is_last)
392 done(ep, req, 0);
393 return is_last;
394}
395
396static inline int
397read_packet(u8 *buf, struct omap_req *req, unsigned avail)
398{
399 unsigned len;
400 u16 *wp;
401
402 len = min(req->req.length - req->req.actual, avail);
403 req->req.actual += len;
404 avail = len;
405
406 if (likely((((int)buf) & 1) == 0)) {
407 wp = (u16 *)buf;
408 while (avail >= 2) {
409 *wp++ = omap_readw(UDC_DATA);
410 avail -= 2;
411 }
412 buf = (u8 *)wp;
413 }
414 while (avail--)
415 *buf++ = omap_readb(UDC_DATA);
416 return len;
417}
418
419/* return: 0 = still running, 1 = queue empty, negative = errno */
420static int read_fifo(struct omap_ep *ep, struct omap_req *req)
421{
422 u8 *buf;
423 unsigned count, avail;
424 int is_last;
425
426 buf = req->req.buf + req->req.actual;
427 prefetchw(buf);
428
429 for (;;) {
430 u16 ep_stat = omap_readw(UDC_STAT_FLG);
431
432 is_last = 0;
433 if (ep_stat & FIFO_EMPTY) {
434 if (!ep->double_buf)
435 break;
436 ep->fnf = 1;
437 }
438 if (ep_stat & UDC_EP_HALTED)
439 break;
440
441 if (ep_stat & UDC_FIFO_FULL)
442 avail = ep->ep.maxpacket;
443 else {
444 avail = omap_readw(UDC_RXFSTAT);
445 ep->fnf = ep->double_buf;
446 }
447 count = read_packet(buf, req, avail);
448
449 /* partial packet reads may not be errors */
450 if (count < ep->ep.maxpacket) {
451 is_last = 1;
452 /* overflowed this request? flush extra data */
453 if (count != avail) {
454 req->req.status = -EOVERFLOW;
455 avail -= count;
456 while (avail--)
457 omap_readw(UDC_DATA);
458 }
459 } else if (req->req.length == req->req.actual)
460 is_last = 1;
461 else
462 is_last = 0;
463
464 if (!ep->bEndpointAddress)
465 break;
466 if (is_last)
467 done(ep, req, 0);
468 break;
469 }
470 return is_last;
471}
472
473/*-------------------------------------------------------------------------*/
474
475static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
476{
477 dma_addr_t end;
478
479 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
480 * the last transfer's bytecount by more than a FIFO's worth.
481 */
482 if (cpu_is_omap15xx())
483 return 0;
484
485 end = omap_get_dma_src_pos(ep->lch);
486 if (end == ep->dma_counter)
487 return 0;
488
489 end |= start & (0xffff << 16);
490 if (end < start)
491 end += 0x10000;
492 return end - start;
493}
494
495static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
496{
497 dma_addr_t end;
498
499 end = omap_get_dma_dst_pos(ep->lch);
500 if (end == ep->dma_counter)
501 return 0;
502
503 end |= start & (0xffff << 16);
504 if (cpu_is_omap15xx())
505 end++;
506 if (end < start)
507 end += 0x10000;
508 return end - start;
509}
510
511
512/* Each USB transfer request using DMA maps to one or more DMA transfers.
513 * When DMA completion isn't request completion, the UDC continues with
514 * the next DMA transfer for that USB transfer.
515 */
516
517static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
518{
519 u16 txdma_ctrl, w;
520 unsigned length = req->req.length - req->req.actual;
521 const int sync_mode = cpu_is_omap15xx()
522 ? OMAP_DMA_SYNC_FRAME
523 : OMAP_DMA_SYNC_ELEMENT;
524 int dma_trigger = 0;
525
526 /* measure length in either bytes or packets */
527 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
528 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
529 txdma_ctrl = UDC_TXN_EOT | length;
530 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
531 length, 1, sync_mode, dma_trigger, 0);
532 } else {
533 length = min(length / ep->maxpacket,
534 (unsigned) UDC_TXN_TSC + 1);
535 txdma_ctrl = length;
536 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
537 ep->ep.maxpacket >> 1, length, sync_mode,
538 dma_trigger, 0);
539 length *= ep->maxpacket;
540 }
541 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
542 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
543 0, 0);
544
545 omap_start_dma(ep->lch);
546 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
547 w = omap_readw(UDC_DMA_IRQ_EN);
548 w |= UDC_TX_DONE_IE(ep->dma_channel);
549 omap_writew(w, UDC_DMA_IRQ_EN);
550 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
551 req->dma_bytes = length;
552}
553
554static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
555{
556 u16 w;
557
558 if (status == 0) {
559 req->req.actual += req->dma_bytes;
560
561 /* return if this request needs to send data or zlp */
562 if (req->req.actual < req->req.length)
563 return;
564 if (req->req.zero
565 && req->dma_bytes != 0
566 && (req->req.actual % ep->maxpacket) == 0)
567 return;
568 } else
569 req->req.actual += dma_src_len(ep, req->req.dma
570 + req->req.actual);
571
572 /* tx completion */
573 omap_stop_dma(ep->lch);
574 w = omap_readw(UDC_DMA_IRQ_EN);
575 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
576 omap_writew(w, UDC_DMA_IRQ_EN);
577 done(ep, req, status);
578}
579
580static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
581{
582 unsigned packets = req->req.length - req->req.actual;
583 int dma_trigger = 0;
584 u16 w;
585
586 /* set up this DMA transfer, enable the fifo, start */
587 packets /= ep->ep.maxpacket;
588 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
589 req->dma_bytes = packets * ep->ep.maxpacket;
590 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
591 ep->ep.maxpacket >> 1, packets,
592 OMAP_DMA_SYNC_ELEMENT,
593 dma_trigger, 0);
594 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
595 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
596 0, 0);
597 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
598
599 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
600 w = omap_readw(UDC_DMA_IRQ_EN);
601 w |= UDC_RX_EOT_IE(ep->dma_channel);
602 omap_writew(w, UDC_DMA_IRQ_EN);
603 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
604 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
605
606 omap_start_dma(ep->lch);
607}
608
609static void
610finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
611{
612 u16 count, w;
613
614 if (status == 0)
615 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
616 count = dma_dest_len(ep, req->req.dma + req->req.actual);
617 count += req->req.actual;
618 if (one)
619 count--;
620 if (count <= req->req.length)
621 req->req.actual = count;
622
623 if (count != req->dma_bytes || status)
624 omap_stop_dma(ep->lch);
625
626 /* if this wasn't short, request may need another transfer */
627 else if (req->req.actual < req->req.length)
628 return;
629
630 /* rx completion */
631 w = omap_readw(UDC_DMA_IRQ_EN);
632 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
633 omap_writew(w, UDC_DMA_IRQ_EN);
634 done(ep, req, status);
635}
636
637static void dma_irq(struct omap_udc *udc, u16 irq_src)
638{
639 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
640 struct omap_ep *ep;
641 struct omap_req *req;
642
643 /* IN dma: tx to host */
644 if (irq_src & UDC_TXN_DONE) {
645 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
646 ep->irqs++;
647 /* can see TXN_DONE after dma abort */
648 if (!list_empty(&ep->queue)) {
649 req = container_of(ep->queue.next,
650 struct omap_req, queue);
651 finish_in_dma(ep, req, 0);
652 }
653 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
654
655 if (!list_empty(&ep->queue)) {
656 req = container_of(ep->queue.next,
657 struct omap_req, queue);
658 next_in_dma(ep, req);
659 }
660 }
661
662 /* OUT dma: rx from host */
663 if (irq_src & UDC_RXN_EOT) {
664 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
665 ep->irqs++;
666 /* can see RXN_EOT after dma abort */
667 if (!list_empty(&ep->queue)) {
668 req = container_of(ep->queue.next,
669 struct omap_req, queue);
670 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
671 }
672 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
673
674 if (!list_empty(&ep->queue)) {
675 req = container_of(ep->queue.next,
676 struct omap_req, queue);
677 next_out_dma(ep, req);
678 }
679 }
680
681 if (irq_src & UDC_RXN_CNT) {
682 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
683 ep->irqs++;
684 /* omap15xx does this unasked... */
685 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
686 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
687 }
688}
689
690static void dma_error(int lch, u16 ch_status, void *data)
691{
692 struct omap_ep *ep = data;
693
694 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
695 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
696 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
697
698 /* complete current transfer ... */
699}
700
701static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
702{
703 u16 reg;
704 int status, restart, is_in;
705 int dma_channel;
706
707 is_in = ep->bEndpointAddress & USB_DIR_IN;
708 if (is_in)
709 reg = omap_readw(UDC_TXDMA_CFG);
710 else
711 reg = omap_readw(UDC_RXDMA_CFG);
712 reg |= UDC_DMA_REQ; /* "pulse" activated */
713
714 ep->dma_channel = 0;
715 ep->lch = -1;
716 if (channel == 0 || channel > 3) {
717 if ((reg & 0x0f00) == 0)
718 channel = 3;
719 else if ((reg & 0x00f0) == 0)
720 channel = 2;
721 else if ((reg & 0x000f) == 0) /* preferred for ISO */
722 channel = 1;
723 else {
724 status = -EMLINK;
725 goto just_restart;
726 }
727 }
728 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
729 ep->dma_channel = channel;
730
731 if (is_in) {
732 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
733 status = omap_request_dma(dma_channel,
734 ep->ep.name, dma_error, ep, &ep->lch);
735 if (status == 0) {
736 omap_writew(reg, UDC_TXDMA_CFG);
737 /* EMIFF or SDRC */
738 omap_set_dma_src_burst_mode(ep->lch,
739 OMAP_DMA_DATA_BURST_4);
740 omap_set_dma_src_data_pack(ep->lch, 1);
741 /* TIPB */
742 omap_set_dma_dest_params(ep->lch,
743 OMAP_DMA_PORT_TIPB,
744 OMAP_DMA_AMODE_CONSTANT,
745 UDC_DATA_DMA,
746 0, 0);
747 }
748 } else {
749 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
750 status = omap_request_dma(dma_channel,
751 ep->ep.name, dma_error, ep, &ep->lch);
752 if (status == 0) {
753 omap_writew(reg, UDC_RXDMA_CFG);
754 /* TIPB */
755 omap_set_dma_src_params(ep->lch,
756 OMAP_DMA_PORT_TIPB,
757 OMAP_DMA_AMODE_CONSTANT,
758 UDC_DATA_DMA,
759 0, 0);
760 /* EMIFF or SDRC */
761 omap_set_dma_dest_burst_mode(ep->lch,
762 OMAP_DMA_DATA_BURST_4);
763 omap_set_dma_dest_data_pack(ep->lch, 1);
764 }
765 }
766 if (status)
767 ep->dma_channel = 0;
768 else {
769 ep->has_dma = 1;
770 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
771
772 /* channel type P: hw synch (fifo) */
773 if (!cpu_is_omap15xx())
774 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
775 }
776
777just_restart:
778 /* restart any queue, even if the claim failed */
779 restart = !ep->stopped && !list_empty(&ep->queue);
780
781 if (status)
782 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
783 restart ? " (restart)" : "");
784 else
785 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
786 is_in ? 't' : 'r',
787 ep->dma_channel - 1, ep->lch,
788 restart ? " (restart)" : "");
789
790 if (restart) {
791 struct omap_req *req;
792 req = container_of(ep->queue.next, struct omap_req, queue);
793 if (ep->has_dma)
794 (is_in ? next_in_dma : next_out_dma)(ep, req);
795 else {
796 use_ep(ep, UDC_EP_SEL);
797 (is_in ? write_fifo : read_fifo)(ep, req);
798 deselect_ep();
799 if (!is_in) {
800 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
801 ep->ackwait = 1 + ep->double_buf;
802 }
803 /* IN: 6 wait states before it'll tx */
804 }
805 }
806}
807
808static void dma_channel_release(struct omap_ep *ep)
809{
810 int shift = 4 * (ep->dma_channel - 1);
811 u16 mask = 0x0f << shift;
812 struct omap_req *req;
813 int active;
814
815 /* abort any active usb transfer request */
816 if (!list_empty(&ep->queue))
817 req = container_of(ep->queue.next, struct omap_req, queue);
818 else
819 req = NULL;
820
821 active = omap_get_dma_active_status(ep->lch);
822
823 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
824 active ? "active" : "idle",
825 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
826 ep->dma_channel - 1, req);
827
828 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
829 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
830 */
831
832 /* wait till current packet DMA finishes, and fifo empties */
833 if (ep->bEndpointAddress & USB_DIR_IN) {
834 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
835 UDC_TXDMA_CFG);
836
837 if (req) {
838 finish_in_dma(ep, req, -ECONNRESET);
839
840 /* clear FIFO; hosts probably won't empty it */
841 use_ep(ep, UDC_EP_SEL);
842 omap_writew(UDC_CLR_EP, UDC_CTRL);
843 deselect_ep();
844 }
845 while (omap_readw(UDC_TXDMA_CFG) & mask)
846 udelay(10);
847 } else {
848 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
849 UDC_RXDMA_CFG);
850
851 /* dma empties the fifo */
852 while (omap_readw(UDC_RXDMA_CFG) & mask)
853 udelay(10);
854 if (req)
855 finish_out_dma(ep, req, -ECONNRESET, 0);
856 }
857 omap_free_dma(ep->lch);
858 ep->dma_channel = 0;
859 ep->lch = -1;
860 /* has_dma still set, till endpoint is fully quiesced */
861}
862
863
864/*-------------------------------------------------------------------------*/
865
866static int
867omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
868{
869 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
870 struct omap_req *req = container_of(_req, struct omap_req, req);
871 struct omap_udc *udc;
872 unsigned long flags;
873 int is_iso = 0;
874
875 /* catch various bogus parameters */
876 if (!_req || !req->req.complete || !req->req.buf
877 || !list_empty(&req->queue)) {
878 DBG("%s, bad params\n", __func__);
879 return -EINVAL;
880 }
881 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
882 DBG("%s, bad ep\n", __func__);
883 return -EINVAL;
884 }
885 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
886 if (req->req.length > ep->ep.maxpacket)
887 return -EMSGSIZE;
888 is_iso = 1;
889 }
890
891 /* this isn't bogus, but OMAP DMA isn't the only hardware to
892 * have a hard time with partial packet reads... reject it.
893 */
894 if (use_dma
895 && ep->has_dma
896 && ep->bEndpointAddress != 0
897 && (ep->bEndpointAddress & USB_DIR_IN) == 0
898 && (req->req.length % ep->ep.maxpacket) != 0) {
899 DBG("%s, no partial packet OUT reads\n", __func__);
900 return -EMSGSIZE;
901 }
902
903 udc = ep->udc;
904 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
905 return -ESHUTDOWN;
906
907 if (use_dma && ep->has_dma)
908 usb_gadget_map_request(&udc->gadget, &req->req,
909 (ep->bEndpointAddress & USB_DIR_IN));
910
911 VDBG("%s queue req %p, len %d buf %p\n",
912 ep->ep.name, _req, _req->length, _req->buf);
913
914 spin_lock_irqsave(&udc->lock, flags);
915
916 req->req.status = -EINPROGRESS;
917 req->req.actual = 0;
918
919 /* maybe kickstart non-iso i/o queues */
920 if (is_iso) {
921 u16 w;
922
923 w = omap_readw(UDC_IRQ_EN);
924 w |= UDC_SOF_IE;
925 omap_writew(w, UDC_IRQ_EN);
926 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
927 int is_in;
928
929 if (ep->bEndpointAddress == 0) {
930 if (!udc->ep0_pending || !list_empty(&ep->queue)) {
931 spin_unlock_irqrestore(&udc->lock, flags);
932 return -EL2HLT;
933 }
934
935 /* empty DATA stage? */
936 is_in = udc->ep0_in;
937 if (!req->req.length) {
938
939 /* chip became CONFIGURED or ADDRESSED
940 * earlier; drivers may already have queued
941 * requests to non-control endpoints
942 */
943 if (udc->ep0_set_config) {
944 u16 irq_en = omap_readw(UDC_IRQ_EN);
945
946 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
947 if (!udc->ep0_reset_config)
948 irq_en |= UDC_EPN_RX_IE
949 | UDC_EPN_TX_IE;
950 omap_writew(irq_en, UDC_IRQ_EN);
951 }
952
953 /* STATUS for zero length DATA stages is
954 * always an IN ... even for IN transfers,
955 * a weird case which seem to stall OMAP.
956 */
957 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
958 UDC_EP_NUM);
959 omap_writew(UDC_CLR_EP, UDC_CTRL);
960 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
961 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
962
963 /* cleanup */
964 udc->ep0_pending = 0;
965 done(ep, req, 0);
966 req = NULL;
967
968 /* non-empty DATA stage */
969 } else if (is_in) {
970 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
971 UDC_EP_NUM);
972 } else {
973 if (udc->ep0_setup)
974 goto irq_wait;
975 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
976 }
977 } else {
978 is_in = ep->bEndpointAddress & USB_DIR_IN;
979 if (!ep->has_dma)
980 use_ep(ep, UDC_EP_SEL);
981 /* if ISO: SOF IRQs must be enabled/disabled! */
982 }
983
984 if (ep->has_dma)
985 (is_in ? next_in_dma : next_out_dma)(ep, req);
986 else if (req) {
987 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
988 req = NULL;
989 deselect_ep();
990 if (!is_in) {
991 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
992 ep->ackwait = 1 + ep->double_buf;
993 }
994 /* IN: 6 wait states before it'll tx */
995 }
996 }
997
998irq_wait:
999 /* irq handler advances the queue */
1000 if (req != NULL)
1001 list_add_tail(&req->queue, &ep->queue);
1002 spin_unlock_irqrestore(&udc->lock, flags);
1003
1004 return 0;
1005}
1006
1007static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1008{
1009 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1010 struct omap_req *req;
1011 unsigned long flags;
1012
1013 if (!_ep || !_req)
1014 return -EINVAL;
1015
1016 spin_lock_irqsave(&ep->udc->lock, flags);
1017
1018 /* make sure it's actually queued on this endpoint */
1019 list_for_each_entry(req, &ep->queue, queue) {
1020 if (&req->req == _req)
1021 break;
1022 }
1023 if (&req->req != _req) {
1024 spin_unlock_irqrestore(&ep->udc->lock, flags);
1025 return -EINVAL;
1026 }
1027
1028 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029 int channel = ep->dma_channel;
1030
1031 /* releasing the channel cancels the request,
1032 * reclaiming the channel restarts the queue
1033 */
1034 dma_channel_release(ep);
1035 dma_channel_claim(ep, channel);
1036 } else
1037 done(ep, req, -ECONNRESET);
1038 spin_unlock_irqrestore(&ep->udc->lock, flags);
1039 return 0;
1040}
1041
1042/*-------------------------------------------------------------------------*/
1043
1044static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045{
1046 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1047 unsigned long flags;
1048 int status = -EOPNOTSUPP;
1049
1050 spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052 /* just use protocol stalls for ep0; real halts are annoying */
1053 if (ep->bEndpointAddress == 0) {
1054 if (!ep->udc->ep0_pending)
1055 status = -EINVAL;
1056 else if (value) {
1057 if (ep->udc->ep0_set_config) {
1058 WARNING("error changing config?\n");
1059 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060 }
1061 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062 ep->udc->ep0_pending = 0;
1063 status = 0;
1064 } else /* NOP */
1065 status = 0;
1066
1067 /* otherwise, all active non-ISO endpoints can halt */
1068 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070 /* IN endpoints must already be idle */
1071 if ((ep->bEndpointAddress & USB_DIR_IN)
1072 && !list_empty(&ep->queue)) {
1073 status = -EAGAIN;
1074 goto done;
1075 }
1076
1077 if (value) {
1078 int channel;
1079
1080 if (use_dma && ep->dma_channel
1081 && !list_empty(&ep->queue)) {
1082 channel = ep->dma_channel;
1083 dma_channel_release(ep);
1084 } else
1085 channel = 0;
1086
1087 use_ep(ep, UDC_EP_SEL);
1088 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089 omap_writew(UDC_SET_HALT, UDC_CTRL);
1090 status = 0;
1091 } else
1092 status = -EAGAIN;
1093 deselect_ep();
1094
1095 if (channel)
1096 dma_channel_claim(ep, channel);
1097 } else {
1098 use_ep(ep, 0);
1099 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100 ep->ackwait = 0;
1101 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103 ep->ackwait = 1 + ep->double_buf;
1104 }
1105 }
1106 }
1107done:
1108 VDBG("%s %s halt stat %d\n", ep->ep.name,
1109 value ? "set" : "clear", status);
1110
1111 spin_unlock_irqrestore(&ep->udc->lock, flags);
1112 return status;
1113}
1114
1115static struct usb_ep_ops omap_ep_ops = {
1116 .enable = omap_ep_enable,
1117 .disable = omap_ep_disable,
1118
1119 .alloc_request = omap_alloc_request,
1120 .free_request = omap_free_request,
1121
1122 .queue = omap_ep_queue,
1123 .dequeue = omap_ep_dequeue,
1124
1125 .set_halt = omap_ep_set_halt,
1126 /* fifo_status ... report bytes in fifo */
1127 /* fifo_flush ... flush fifo */
1128};
1129
1130/*-------------------------------------------------------------------------*/
1131
1132static int omap_get_frame(struct usb_gadget *gadget)
1133{
1134 u16 sof = omap_readw(UDC_SOF);
1135 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136}
1137
1138static int omap_wakeup(struct usb_gadget *gadget)
1139{
1140 struct omap_udc *udc;
1141 unsigned long flags;
1142 int retval = -EHOSTUNREACH;
1143
1144 udc = container_of(gadget, struct omap_udc, gadget);
1145
1146 spin_lock_irqsave(&udc->lock, flags);
1147 if (udc->devstat & UDC_SUS) {
1148 /* NOTE: OTG spec erratum says that OTG devices may
1149 * issue wakeups without host enable.
1150 */
1151 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152 DBG("remote wakeup...\n");
1153 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154 retval = 0;
1155 }
1156
1157 /* NOTE: non-OTG systems may use SRP TOO... */
1158 } else if (!(udc->devstat & UDC_ATT)) {
1159 if (!IS_ERR_OR_NULL(udc->transceiver))
1160 retval = otg_start_srp(udc->transceiver->otg);
1161 }
1162 spin_unlock_irqrestore(&udc->lock, flags);
1163
1164 return retval;
1165}
1166
1167static int
1168omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169{
1170 struct omap_udc *udc;
1171 unsigned long flags;
1172 u16 syscon1;
1173
1174 gadget->is_selfpowered = (is_selfpowered != 0);
1175 udc = container_of(gadget, struct omap_udc, gadget);
1176 spin_lock_irqsave(&udc->lock, flags);
1177 syscon1 = omap_readw(UDC_SYSCON1);
1178 if (is_selfpowered)
1179 syscon1 |= UDC_SELF_PWR;
1180 else
1181 syscon1 &= ~UDC_SELF_PWR;
1182 omap_writew(syscon1, UDC_SYSCON1);
1183 spin_unlock_irqrestore(&udc->lock, flags);
1184
1185 return 0;
1186}
1187
1188static int can_pullup(struct omap_udc *udc)
1189{
1190 return udc->driver && udc->softconnect && udc->vbus_active;
1191}
1192
1193static void pullup_enable(struct omap_udc *udc)
1194{
1195 u16 w;
1196
1197 w = omap_readw(UDC_SYSCON1);
1198 w |= UDC_PULLUP_EN;
1199 omap_writew(w, UDC_SYSCON1);
1200 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1201 u32 l;
1202
1203 l = omap_readl(OTG_CTRL);
1204 l |= OTG_BSESSVLD;
1205 omap_writel(l, OTG_CTRL);
1206 }
1207 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1208}
1209
1210static void pullup_disable(struct omap_udc *udc)
1211{
1212 u16 w;
1213
1214 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1215 u32 l;
1216
1217 l = omap_readl(OTG_CTRL);
1218 l &= ~OTG_BSESSVLD;
1219 omap_writel(l, OTG_CTRL);
1220 }
1221 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1222 w = omap_readw(UDC_SYSCON1);
1223 w &= ~UDC_PULLUP_EN;
1224 omap_writew(w, UDC_SYSCON1);
1225}
1226
1227static struct omap_udc *udc;
1228
1229static void omap_udc_enable_clock(int enable)
1230{
1231 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1232 return;
1233
1234 if (enable) {
1235 clk_enable(udc->dc_clk);
1236 clk_enable(udc->hhc_clk);
1237 udelay(100);
1238 } else {
1239 clk_disable(udc->hhc_clk);
1240 clk_disable(udc->dc_clk);
1241 }
1242}
1243
1244/*
1245 * Called by whatever detects VBUS sessions: external transceiver
1246 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1247 */
1248static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1249{
1250 struct omap_udc *udc;
1251 unsigned long flags;
1252 u32 l;
1253
1254 udc = container_of(gadget, struct omap_udc, gadget);
1255 spin_lock_irqsave(&udc->lock, flags);
1256 VDBG("VBUS %s\n", is_active ? "on" : "off");
1257 udc->vbus_active = (is_active != 0);
1258 if (cpu_is_omap15xx()) {
1259 /* "software" detect, ignored if !VBUS_MODE_1510 */
1260 l = omap_readl(FUNC_MUX_CTRL_0);
1261 if (is_active)
1262 l |= VBUS_CTRL_1510;
1263 else
1264 l &= ~VBUS_CTRL_1510;
1265 omap_writel(l, FUNC_MUX_CTRL_0);
1266 }
1267 if (udc->dc_clk != NULL && is_active) {
1268 if (!udc->clk_requested) {
1269 omap_udc_enable_clock(1);
1270 udc->clk_requested = 1;
1271 }
1272 }
1273 if (can_pullup(udc))
1274 pullup_enable(udc);
1275 else
1276 pullup_disable(udc);
1277 if (udc->dc_clk != NULL && !is_active) {
1278 if (udc->clk_requested) {
1279 omap_udc_enable_clock(0);
1280 udc->clk_requested = 0;
1281 }
1282 }
1283 spin_unlock_irqrestore(&udc->lock, flags);
1284 return 0;
1285}
1286
1287static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1288{
1289 struct omap_udc *udc;
1290
1291 udc = container_of(gadget, struct omap_udc, gadget);
1292 if (!IS_ERR_OR_NULL(udc->transceiver))
1293 return usb_phy_set_power(udc->transceiver, mA);
1294 return -EOPNOTSUPP;
1295}
1296
1297static int omap_pullup(struct usb_gadget *gadget, int is_on)
1298{
1299 struct omap_udc *udc;
1300 unsigned long flags;
1301
1302 udc = container_of(gadget, struct omap_udc, gadget);
1303 spin_lock_irqsave(&udc->lock, flags);
1304 udc->softconnect = (is_on != 0);
1305 if (can_pullup(udc))
1306 pullup_enable(udc);
1307 else
1308 pullup_disable(udc);
1309 spin_unlock_irqrestore(&udc->lock, flags);
1310 return 0;
1311}
1312
1313static int omap_udc_start(struct usb_gadget *g,
1314 struct usb_gadget_driver *driver);
1315static int omap_udc_stop(struct usb_gadget *g);
1316
1317static const struct usb_gadget_ops omap_gadget_ops = {
1318 .get_frame = omap_get_frame,
1319 .wakeup = omap_wakeup,
1320 .set_selfpowered = omap_set_selfpowered,
1321 .vbus_session = omap_vbus_session,
1322 .vbus_draw = omap_vbus_draw,
1323 .pullup = omap_pullup,
1324 .udc_start = omap_udc_start,
1325 .udc_stop = omap_udc_stop,
1326};
1327
1328/*-------------------------------------------------------------------------*/
1329
1330/* dequeue ALL requests; caller holds udc->lock */
1331static void nuke(struct omap_ep *ep, int status)
1332{
1333 struct omap_req *req;
1334
1335 ep->stopped = 1;
1336
1337 if (use_dma && ep->dma_channel)
1338 dma_channel_release(ep);
1339
1340 use_ep(ep, 0);
1341 omap_writew(UDC_CLR_EP, UDC_CTRL);
1342 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1343 omap_writew(UDC_SET_HALT, UDC_CTRL);
1344
1345 while (!list_empty(&ep->queue)) {
1346 req = list_entry(ep->queue.next, struct omap_req, queue);
1347 done(ep, req, status);
1348 }
1349}
1350
1351/* caller holds udc->lock */
1352static void udc_quiesce(struct omap_udc *udc)
1353{
1354 struct omap_ep *ep;
1355
1356 udc->gadget.speed = USB_SPEED_UNKNOWN;
1357 nuke(&udc->ep[0], -ESHUTDOWN);
1358 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1359 nuke(ep, -ESHUTDOWN);
1360}
1361
1362/*-------------------------------------------------------------------------*/
1363
1364static void update_otg(struct omap_udc *udc)
1365{
1366 u16 devstat;
1367
1368 if (!gadget_is_otg(&udc->gadget))
1369 return;
1370
1371 if (omap_readl(OTG_CTRL) & OTG_ID)
1372 devstat = omap_readw(UDC_DEVSTAT);
1373 else
1374 devstat = 0;
1375
1376 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1377 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1378 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1379
1380 /* Enable HNP early, avoiding races on suspend irq path.
1381 * ASSUMES OTG state machine B_BUS_REQ input is true.
1382 */
1383 if (udc->gadget.b_hnp_enable) {
1384 u32 l;
1385
1386 l = omap_readl(OTG_CTRL);
1387 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1388 l &= ~OTG_PULLUP;
1389 omap_writel(l, OTG_CTRL);
1390 }
1391}
1392
1393static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1394{
1395 struct omap_ep *ep0 = &udc->ep[0];
1396 struct omap_req *req = NULL;
1397
1398 ep0->irqs++;
1399
1400 /* Clear any pending requests and then scrub any rx/tx state
1401 * before starting to handle the SETUP request.
1402 */
1403 if (irq_src & UDC_SETUP) {
1404 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1405
1406 nuke(ep0, 0);
1407 if (ack) {
1408 omap_writew(ack, UDC_IRQ_SRC);
1409 irq_src = UDC_SETUP;
1410 }
1411 }
1412
1413 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1414 * This driver uses only uses protocol stalls (ep0 never halts),
1415 * and if we got this far the gadget driver already had a
1416 * chance to stall. Tries to be forgiving of host oddities.
1417 *
1418 * NOTE: the last chance gadget drivers have to stall control
1419 * requests is during their request completion callback.
1420 */
1421 if (!list_empty(&ep0->queue))
1422 req = container_of(ep0->queue.next, struct omap_req, queue);
1423
1424 /* IN == TX to host */
1425 if (irq_src & UDC_EP0_TX) {
1426 int stat;
1427
1428 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1429 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1430 stat = omap_readw(UDC_STAT_FLG);
1431 if (stat & UDC_ACK) {
1432 if (udc->ep0_in) {
1433 /* write next IN packet from response,
1434 * or set up the status stage.
1435 */
1436 if (req)
1437 stat = write_fifo(ep0, req);
1438 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1439 if (!req && udc->ep0_pending) {
1440 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1441 omap_writew(UDC_CLR_EP, UDC_CTRL);
1442 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1443 omap_writew(0, UDC_EP_NUM);
1444 udc->ep0_pending = 0;
1445 } /* else: 6 wait states before it'll tx */
1446 } else {
1447 /* ack status stage of OUT transfer */
1448 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1449 if (req)
1450 done(ep0, req, 0);
1451 }
1452 req = NULL;
1453 } else if (stat & UDC_STALL) {
1454 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1455 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1456 } else {
1457 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1458 }
1459 }
1460
1461 /* OUT == RX from host */
1462 if (irq_src & UDC_EP0_RX) {
1463 int stat;
1464
1465 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1466 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467 stat = omap_readw(UDC_STAT_FLG);
1468 if (stat & UDC_ACK) {
1469 if (!udc->ep0_in) {
1470 stat = 0;
1471 /* read next OUT packet of request, maybe
1472 * reactiviting the fifo; stall on errors.
1473 */
1474 stat = read_fifo(ep0, req);
1475 if (!req || stat < 0) {
1476 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1477 udc->ep0_pending = 0;
1478 stat = 0;
1479 } else if (stat == 0)
1480 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1481 omap_writew(0, UDC_EP_NUM);
1482
1483 /* activate status stage */
1484 if (stat == 1) {
1485 done(ep0, req, 0);
1486 /* that may have STALLed ep0... */
1487 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1488 UDC_EP_NUM);
1489 omap_writew(UDC_CLR_EP, UDC_CTRL);
1490 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1491 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1492 udc->ep0_pending = 0;
1493 }
1494 } else {
1495 /* ack status stage of IN transfer */
1496 omap_writew(0, UDC_EP_NUM);
1497 if (req)
1498 done(ep0, req, 0);
1499 }
1500 } else if (stat & UDC_STALL) {
1501 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1502 omap_writew(0, UDC_EP_NUM);
1503 } else {
1504 omap_writew(0, UDC_EP_NUM);
1505 }
1506 }
1507
1508 /* SETUP starts all control transfers */
1509 if (irq_src & UDC_SETUP) {
1510 union u {
1511 u16 word[4];
1512 struct usb_ctrlrequest r;
1513 } u;
1514 int status = -EINVAL;
1515 struct omap_ep *ep;
1516
1517 /* read the (latest) SETUP message */
1518 do {
1519 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1520 /* two bytes at a time */
1521 u.word[0] = omap_readw(UDC_DATA);
1522 u.word[1] = omap_readw(UDC_DATA);
1523 u.word[2] = omap_readw(UDC_DATA);
1524 u.word[3] = omap_readw(UDC_DATA);
1525 omap_writew(0, UDC_EP_NUM);
1526 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1527
1528#define w_value le16_to_cpu(u.r.wValue)
1529#define w_index le16_to_cpu(u.r.wIndex)
1530#define w_length le16_to_cpu(u.r.wLength)
1531
1532 /* Delegate almost all control requests to the gadget driver,
1533 * except for a handful of ch9 status/feature requests that
1534 * hardware doesn't autodecode _and_ the gadget API hides.
1535 */
1536 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1537 udc->ep0_set_config = 0;
1538 udc->ep0_pending = 1;
1539 ep0->stopped = 0;
1540 ep0->ackwait = 0;
1541 switch (u.r.bRequest) {
1542 case USB_REQ_SET_CONFIGURATION:
1543 /* udc needs to know when ep != 0 is valid */
1544 if (u.r.bRequestType != USB_RECIP_DEVICE)
1545 goto delegate;
1546 if (w_length != 0)
1547 goto do_stall;
1548 udc->ep0_set_config = 1;
1549 udc->ep0_reset_config = (w_value == 0);
1550 VDBG("set config %d\n", w_value);
1551
1552 /* update udc NOW since gadget driver may start
1553 * queueing requests immediately; clear config
1554 * later if it fails the request.
1555 */
1556 if (udc->ep0_reset_config)
1557 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1558 else
1559 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1560 update_otg(udc);
1561 goto delegate;
1562 case USB_REQ_CLEAR_FEATURE:
1563 /* clear endpoint halt */
1564 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1565 goto delegate;
1566 if (w_value != USB_ENDPOINT_HALT
1567 || w_length != 0)
1568 goto do_stall;
1569 ep = &udc->ep[w_index & 0xf];
1570 if (ep != ep0) {
1571 if (w_index & USB_DIR_IN)
1572 ep += 16;
1573 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1574 || !ep->ep.desc)
1575 goto do_stall;
1576 use_ep(ep, 0);
1577 omap_writew(udc->clr_halt, UDC_CTRL);
1578 ep->ackwait = 0;
1579 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1580 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1581 ep->ackwait = 1 + ep->double_buf;
1582 }
1583 /* NOTE: assumes the host behaves sanely,
1584 * only clearing real halts. Else we may
1585 * need to kill pending transfers and then
1586 * restart the queue... very messy for DMA!
1587 */
1588 }
1589 VDBG("%s halt cleared by host\n", ep->name);
1590 goto ep0out_status_stage;
1591 case USB_REQ_SET_FEATURE:
1592 /* set endpoint halt */
1593 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594 goto delegate;
1595 if (w_value != USB_ENDPOINT_HALT
1596 || w_length != 0)
1597 goto do_stall;
1598 ep = &udc->ep[w_index & 0xf];
1599 if (w_index & USB_DIR_IN)
1600 ep += 16;
1601 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1602 || ep == ep0 || !ep->ep.desc)
1603 goto do_stall;
1604 if (use_dma && ep->has_dma) {
1605 /* this has rude side-effects (aborts) and
1606 * can't really work if DMA-IN is active
1607 */
1608 DBG("%s host set_halt, NYET\n", ep->name);
1609 goto do_stall;
1610 }
1611 use_ep(ep, 0);
1612 /* can't halt if fifo isn't empty... */
1613 omap_writew(UDC_CLR_EP, UDC_CTRL);
1614 omap_writew(UDC_SET_HALT, UDC_CTRL);
1615 VDBG("%s halted by host\n", ep->name);
1616ep0out_status_stage:
1617 status = 0;
1618 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1619 omap_writew(UDC_CLR_EP, UDC_CTRL);
1620 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1621 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1622 udc->ep0_pending = 0;
1623 break;
1624 case USB_REQ_GET_STATUS:
1625 /* USB_ENDPOINT_HALT status? */
1626 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1627 goto intf_status;
1628
1629 /* ep0 never stalls */
1630 if (!(w_index & 0xf))
1631 goto zero_status;
1632
1633 /* only active endpoints count */
1634 ep = &udc->ep[w_index & 0xf];
1635 if (w_index & USB_DIR_IN)
1636 ep += 16;
1637 if (!ep->ep.desc)
1638 goto do_stall;
1639
1640 /* iso never stalls */
1641 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1642 goto zero_status;
1643
1644 /* FIXME don't assume non-halted endpoints!! */
1645 ERR("%s status, can't report\n", ep->ep.name);
1646 goto do_stall;
1647
1648intf_status:
1649 /* return interface status. if we were pedantic,
1650 * we'd detect non-existent interfaces, and stall.
1651 */
1652 if (u.r.bRequestType
1653 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1654 goto delegate;
1655
1656zero_status:
1657 /* return two zero bytes */
1658 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1659 omap_writew(0, UDC_DATA);
1660 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1661 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1662 status = 0;
1663 VDBG("GET_STATUS, interface %d\n", w_index);
1664 /* next, status stage */
1665 break;
1666 default:
1667delegate:
1668 /* activate the ep0out fifo right away */
1669 if (!udc->ep0_in && w_length) {
1670 omap_writew(0, UDC_EP_NUM);
1671 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1672 }
1673
1674 /* gadget drivers see class/vendor specific requests,
1675 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1676 * and more
1677 */
1678 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1679 u.r.bRequestType, u.r.bRequest,
1680 w_value, w_index, w_length);
1681
1682#undef w_value
1683#undef w_index
1684#undef w_length
1685
1686 /* The gadget driver may return an error here,
1687 * causing an immediate protocol stall.
1688 *
1689 * Else it must issue a response, either queueing a
1690 * response buffer for the DATA stage, or halting ep0
1691 * (causing a protocol stall, not a real halt). A
1692 * zero length buffer means no DATA stage.
1693 *
1694 * It's fine to issue that response after the setup()
1695 * call returns, and this IRQ was handled.
1696 */
1697 udc->ep0_setup = 1;
1698 spin_unlock(&udc->lock);
1699 status = udc->driver->setup(&udc->gadget, &u.r);
1700 spin_lock(&udc->lock);
1701 udc->ep0_setup = 0;
1702 }
1703
1704 if (status < 0) {
1705do_stall:
1706 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1707 u.r.bRequestType, u.r.bRequest, status);
1708 if (udc->ep0_set_config) {
1709 if (udc->ep0_reset_config)
1710 WARNING("error resetting config?\n");
1711 else
1712 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1713 }
1714 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1715 udc->ep0_pending = 0;
1716 }
1717 }
1718}
1719
1720/*-------------------------------------------------------------------------*/
1721
1722#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1723
1724static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1725{
1726 u16 devstat, change;
1727
1728 devstat = omap_readw(UDC_DEVSTAT);
1729 change = devstat ^ udc->devstat;
1730 udc->devstat = devstat;
1731
1732 if (change & (UDC_USB_RESET|UDC_ATT)) {
1733 udc_quiesce(udc);
1734
1735 if (change & UDC_ATT) {
1736 /* driver for any external transceiver will
1737 * have called omap_vbus_session() already
1738 */
1739 if (devstat & UDC_ATT) {
1740 udc->gadget.speed = USB_SPEED_FULL;
1741 VDBG("connect\n");
1742 if (IS_ERR_OR_NULL(udc->transceiver))
1743 pullup_enable(udc);
1744 /* if (driver->connect) call it */
1745 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1746 udc->gadget.speed = USB_SPEED_UNKNOWN;
1747 if (IS_ERR_OR_NULL(udc->transceiver))
1748 pullup_disable(udc);
1749 DBG("disconnect, gadget %s\n",
1750 udc->driver->driver.name);
1751 if (udc->driver->disconnect) {
1752 spin_unlock(&udc->lock);
1753 udc->driver->disconnect(&udc->gadget);
1754 spin_lock(&udc->lock);
1755 }
1756 }
1757 change &= ~UDC_ATT;
1758 }
1759
1760 if (change & UDC_USB_RESET) {
1761 if (devstat & UDC_USB_RESET) {
1762 VDBG("RESET=1\n");
1763 } else {
1764 udc->gadget.speed = USB_SPEED_FULL;
1765 INFO("USB reset done, gadget %s\n",
1766 udc->driver->driver.name);
1767 /* ep0 traffic is legal from now on */
1768 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1769 UDC_IRQ_EN);
1770 }
1771 change &= ~UDC_USB_RESET;
1772 }
1773 }
1774 if (change & UDC_SUS) {
1775 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1776 /* FIXME tell isp1301 to suspend/resume (?) */
1777 if (devstat & UDC_SUS) {
1778 VDBG("suspend\n");
1779 update_otg(udc);
1780 /* HNP could be under way already */
1781 if (udc->gadget.speed == USB_SPEED_FULL
1782 && udc->driver->suspend) {
1783 spin_unlock(&udc->lock);
1784 udc->driver->suspend(&udc->gadget);
1785 spin_lock(&udc->lock);
1786 }
1787 if (!IS_ERR_OR_NULL(udc->transceiver))
1788 usb_phy_set_suspend(
1789 udc->transceiver, 1);
1790 } else {
1791 VDBG("resume\n");
1792 if (!IS_ERR_OR_NULL(udc->transceiver))
1793 usb_phy_set_suspend(
1794 udc->transceiver, 0);
1795 if (udc->gadget.speed == USB_SPEED_FULL
1796 && udc->driver->resume) {
1797 spin_unlock(&udc->lock);
1798 udc->driver->resume(&udc->gadget);
1799 spin_lock(&udc->lock);
1800 }
1801 }
1802 }
1803 change &= ~UDC_SUS;
1804 }
1805 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806 update_otg(udc);
1807 change &= ~OTG_FLAGS;
1808 }
1809
1810 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811 if (change)
1812 VDBG("devstat %03x, ignore change %03x\n",
1813 devstat, change);
1814
1815 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1816}
1817
1818static irqreturn_t omap_udc_irq(int irq, void *_udc)
1819{
1820 struct omap_udc *udc = _udc;
1821 u16 irq_src;
1822 irqreturn_t status = IRQ_NONE;
1823 unsigned long flags;
1824
1825 spin_lock_irqsave(&udc->lock, flags);
1826 irq_src = omap_readw(UDC_IRQ_SRC);
1827
1828 /* Device state change (usb ch9 stuff) */
1829 if (irq_src & UDC_DS_CHG) {
1830 devstate_irq(_udc, irq_src);
1831 status = IRQ_HANDLED;
1832 irq_src &= ~UDC_DS_CHG;
1833 }
1834
1835 /* EP0 control transfers */
1836 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1837 ep0_irq(_udc, irq_src);
1838 status = IRQ_HANDLED;
1839 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1840 }
1841
1842 /* DMA transfer completion */
1843 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1844 dma_irq(_udc, irq_src);
1845 status = IRQ_HANDLED;
1846 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1847 }
1848
1849 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1850 if (irq_src)
1851 DBG("udc_irq, unhandled %03x\n", irq_src);
1852 spin_unlock_irqrestore(&udc->lock, flags);
1853
1854 return status;
1855}
1856
1857/* workaround for seemingly-lost IRQs for RX ACKs... */
1858#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1859#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1860
1861static void pio_out_timer(unsigned long _ep)
1862{
1863 struct omap_ep *ep = (void *) _ep;
1864 unsigned long flags;
1865 u16 stat_flg;
1866
1867 spin_lock_irqsave(&ep->udc->lock, flags);
1868 if (!list_empty(&ep->queue) && ep->ackwait) {
1869 use_ep(ep, UDC_EP_SEL);
1870 stat_flg = omap_readw(UDC_STAT_FLG);
1871
1872 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1873 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1874 struct omap_req *req;
1875
1876 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1877 req = container_of(ep->queue.next,
1878 struct omap_req, queue);
1879 (void) read_fifo(ep, req);
1880 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1881 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1882 ep->ackwait = 1 + ep->double_buf;
1883 } else
1884 deselect_ep();
1885 }
1886 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1887 spin_unlock_irqrestore(&ep->udc->lock, flags);
1888}
1889
1890static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1891{
1892 u16 epn_stat, irq_src;
1893 irqreturn_t status = IRQ_NONE;
1894 struct omap_ep *ep;
1895 int epnum;
1896 struct omap_udc *udc = _dev;
1897 struct omap_req *req;
1898 unsigned long flags;
1899
1900 spin_lock_irqsave(&udc->lock, flags);
1901 epn_stat = omap_readw(UDC_EPN_STAT);
1902 irq_src = omap_readw(UDC_IRQ_SRC);
1903
1904 /* handle OUT first, to avoid some wasteful NAKs */
1905 if (irq_src & UDC_EPN_RX) {
1906 epnum = (epn_stat >> 8) & 0x0f;
1907 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1908 status = IRQ_HANDLED;
1909 ep = &udc->ep[epnum];
1910 ep->irqs++;
1911
1912 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1913 ep->fnf = 0;
1914 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1915 ep->ackwait--;
1916 if (!list_empty(&ep->queue)) {
1917 int stat;
1918 req = container_of(ep->queue.next,
1919 struct omap_req, queue);
1920 stat = read_fifo(ep, req);
1921 if (!ep->double_buf)
1922 ep->fnf = 1;
1923 }
1924 }
1925 /* min 6 clock delay before clearing EP_SEL ... */
1926 epn_stat = omap_readw(UDC_EPN_STAT);
1927 epn_stat = omap_readw(UDC_EPN_STAT);
1928 omap_writew(epnum, UDC_EP_NUM);
1929
1930 /* enabling fifo _after_ clearing ACK, contrary to docs,
1931 * reduces lossage; timer still needed though (sigh).
1932 */
1933 if (ep->fnf) {
1934 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935 ep->ackwait = 1 + ep->double_buf;
1936 }
1937 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1938 }
1939
1940 /* then IN transfers */
1941 else if (irq_src & UDC_EPN_TX) {
1942 epnum = epn_stat & 0x0f;
1943 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1944 status = IRQ_HANDLED;
1945 ep = &udc->ep[16 + epnum];
1946 ep->irqs++;
1947
1948 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1949 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1950 ep->ackwait = 0;
1951 if (!list_empty(&ep->queue)) {
1952 req = container_of(ep->queue.next,
1953 struct omap_req, queue);
1954 (void) write_fifo(ep, req);
1955 }
1956 }
1957 /* min 6 clock delay before clearing EP_SEL ... */
1958 epn_stat = omap_readw(UDC_EPN_STAT);
1959 epn_stat = omap_readw(UDC_EPN_STAT);
1960 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1961 /* then 6 clocks before it'd tx */
1962 }
1963
1964 spin_unlock_irqrestore(&udc->lock, flags);
1965 return status;
1966}
1967
1968#ifdef USE_ISO
1969static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1970{
1971 struct omap_udc *udc = _dev;
1972 struct omap_ep *ep;
1973 int pending = 0;
1974 unsigned long flags;
1975
1976 spin_lock_irqsave(&udc->lock, flags);
1977
1978 /* handle all non-DMA ISO transfers */
1979 list_for_each_entry(ep, &udc->iso, iso) {
1980 u16 stat;
1981 struct omap_req *req;
1982
1983 if (ep->has_dma || list_empty(&ep->queue))
1984 continue;
1985 req = list_entry(ep->queue.next, struct omap_req, queue);
1986
1987 use_ep(ep, UDC_EP_SEL);
1988 stat = omap_readw(UDC_STAT_FLG);
1989
1990 /* NOTE: like the other controller drivers, this isn't
1991 * currently reporting lost or damaged frames.
1992 */
1993 if (ep->bEndpointAddress & USB_DIR_IN) {
1994 if (stat & UDC_MISS_IN)
1995 /* done(ep, req, -EPROTO) */;
1996 else
1997 write_fifo(ep, req);
1998 } else {
1999 int status = 0;
2000
2001 if (stat & UDC_NO_RXPACKET)
2002 status = -EREMOTEIO;
2003 else if (stat & UDC_ISO_ERR)
2004 status = -EILSEQ;
2005 else if (stat & UDC_DATA_FLUSH)
2006 status = -ENOSR;
2007
2008 if (status)
2009 /* done(ep, req, status) */;
2010 else
2011 read_fifo(ep, req);
2012 }
2013 deselect_ep();
2014 /* 6 wait states before next EP */
2015
2016 ep->irqs++;
2017 if (!list_empty(&ep->queue))
2018 pending = 1;
2019 }
2020 if (!pending) {
2021 u16 w;
2022
2023 w = omap_readw(UDC_IRQ_EN);
2024 w &= ~UDC_SOF_IE;
2025 omap_writew(w, UDC_IRQ_EN);
2026 }
2027 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2028
2029 spin_unlock_irqrestore(&udc->lock, flags);
2030 return IRQ_HANDLED;
2031}
2032#endif
2033
2034/*-------------------------------------------------------------------------*/
2035
2036static inline int machine_without_vbus_sense(void)
2037{
2038 return machine_is_omap_innovator()
2039 || machine_is_omap_osk()
2040 || machine_is_sx1()
2041 /* No known omap7xx boards with vbus sense */
2042 || cpu_is_omap7xx();
2043}
2044
2045static int omap_udc_start(struct usb_gadget *g,
2046 struct usb_gadget_driver *driver)
2047{
2048 int status = -ENODEV;
2049 struct omap_ep *ep;
2050 unsigned long flags;
2051
2052
2053 spin_lock_irqsave(&udc->lock, flags);
2054 /* reset state */
2055 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2056 ep->irqs = 0;
2057 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2058 continue;
2059 use_ep(ep, 0);
2060 omap_writew(UDC_SET_HALT, UDC_CTRL);
2061 }
2062 udc->ep0_pending = 0;
2063 udc->ep[0].irqs = 0;
2064 udc->softconnect = 1;
2065
2066 /* hook up the driver */
2067 driver->driver.bus = NULL;
2068 udc->driver = driver;
2069 spin_unlock_irqrestore(&udc->lock, flags);
2070
2071 if (udc->dc_clk != NULL)
2072 omap_udc_enable_clock(1);
2073
2074 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2075
2076 /* connect to bus through transceiver */
2077 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2078 status = otg_set_peripheral(udc->transceiver->otg,
2079 &udc->gadget);
2080 if (status < 0) {
2081 ERR("can't bind to transceiver\n");
2082 udc->driver = NULL;
2083 goto done;
2084 }
2085 } else {
2086 if (can_pullup(udc))
2087 pullup_enable(udc);
2088 else
2089 pullup_disable(udc);
2090 }
2091
2092 /* boards that don't have VBUS sensing can't autogate 48MHz;
2093 * can't enter deep sleep while a gadget driver is active.
2094 */
2095 if (machine_without_vbus_sense())
2096 omap_vbus_session(&udc->gadget, 1);
2097
2098done:
2099 if (udc->dc_clk != NULL)
2100 omap_udc_enable_clock(0);
2101
2102 return status;
2103}
2104
2105static int omap_udc_stop(struct usb_gadget *g)
2106{
2107 unsigned long flags;
2108 int status = -ENODEV;
2109
2110 if (udc->dc_clk != NULL)
2111 omap_udc_enable_clock(1);
2112
2113 if (machine_without_vbus_sense())
2114 omap_vbus_session(&udc->gadget, 0);
2115
2116 if (!IS_ERR_OR_NULL(udc->transceiver))
2117 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2118 else
2119 pullup_disable(udc);
2120
2121 spin_lock_irqsave(&udc->lock, flags);
2122 udc_quiesce(udc);
2123 spin_unlock_irqrestore(&udc->lock, flags);
2124
2125 udc->driver = NULL;
2126
2127 if (udc->dc_clk != NULL)
2128 omap_udc_enable_clock(0);
2129
2130 return status;
2131}
2132
2133/*-------------------------------------------------------------------------*/
2134
2135#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2136
2137#include <linux/seq_file.h>
2138
2139static const char proc_filename[] = "driver/udc";
2140
2141#define FOURBITS "%s%s%s%s"
2142#define EIGHTBITS "%s%s%s%s%s%s%s%s"
2143
2144static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2145{
2146 u16 stat_flg;
2147 struct omap_req *req;
2148 char buf[20];
2149
2150 use_ep(ep, 0);
2151
2152 if (use_dma && ep->has_dma)
2153 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2154 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2155 ep->dma_channel - 1, ep->lch);
2156 else
2157 buf[0] = 0;
2158
2159 stat_flg = omap_readw(UDC_STAT_FLG);
2160 seq_printf(s,
2161 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2162 ep->name, buf,
2163 ep->double_buf ? "dbuf " : "",
2164 ({ char *s;
2165 switch (ep->ackwait) {
2166 case 0:
2167 s = "";
2168 break;
2169 case 1:
2170 s = "(ackw) ";
2171 break;
2172 case 2:
2173 s = "(ackw2) ";
2174 break;
2175 default:
2176 s = "(?) ";
2177 break;
2178 } s; }),
2179 ep->irqs, stat_flg,
2180 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2181 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2182 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2183 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2184 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2185 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2186 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2187 (stat_flg & UDC_STALL) ? "STALL " : "",
2188 (stat_flg & UDC_NAK) ? "NAK " : "",
2189 (stat_flg & UDC_ACK) ? "ACK " : "",
2190 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2191 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2192 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2193
2194 if (list_empty(&ep->queue))
2195 seq_printf(s, "\t(queue empty)\n");
2196 else
2197 list_for_each_entry(req, &ep->queue, queue) {
2198 unsigned length = req->req.actual;
2199
2200 if (use_dma && buf[0]) {
2201 length += ((ep->bEndpointAddress & USB_DIR_IN)
2202 ? dma_src_len : dma_dest_len)
2203 (ep, req->req.dma + length);
2204 buf[0] = 0;
2205 }
2206 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2207 &req->req, length,
2208 req->req.length, req->req.buf);
2209 }
2210}
2211
2212static char *trx_mode(unsigned m, int enabled)
2213{
2214 switch (m) {
2215 case 0:
2216 return enabled ? "*6wire" : "unused";
2217 case 1:
2218 return "4wire";
2219 case 2:
2220 return "3wire";
2221 case 3:
2222 return "6wire";
2223 default:
2224 return "unknown";
2225 }
2226}
2227
2228static int proc_otg_show(struct seq_file *s)
2229{
2230 u32 tmp;
2231 u32 trans = 0;
2232 char *ctrl_name = "(UNKNOWN)";
2233
2234 tmp = omap_readl(OTG_REV);
2235 ctrl_name = "tranceiver_ctrl";
2236 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2237 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2238 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2239 tmp = omap_readw(OTG_SYSCON_1);
2240 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2241 FOURBITS "\n", tmp,
2242 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2243 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2244 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2245 ? "internal"
2246 : trx_mode(USB0_TRX_MODE(tmp), 1),
2247 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2248 (tmp & HST_IDLE_EN) ? " !host" : "",
2249 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2250 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2251 tmp = omap_readl(OTG_SYSCON_2);
2252 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2253 " b_ase_brst=%d hmc=%d\n", tmp,
2254 (tmp & OTG_EN) ? " otg_en" : "",
2255 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2256 /* much more SRP stuff */
2257 (tmp & SRP_DATA) ? " srp_data" : "",
2258 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2259 (tmp & OTG_PADEN) ? " otg_paden" : "",
2260 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2261 (tmp & UHOST_EN) ? " uhost_en" : "",
2262 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2263 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2264 B_ASE_BRST(tmp),
2265 OTG_HMC(tmp));
2266 tmp = omap_readl(OTG_CTRL);
2267 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2268 (tmp & OTG_ASESSVLD) ? " asess" : "",
2269 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2270 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2271 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2272 (tmp & OTG_ID) ? " id" : "",
2273 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2274 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2275 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2276 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2277 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2278 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2279 (tmp & OTG_PULLDOWN) ? " down" : "",
2280 (tmp & OTG_PULLUP) ? " up" : "",
2281 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2282 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2283 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2284 (tmp & OTG_PU_ID) ? " pu_id" : ""
2285 );
2286 tmp = omap_readw(OTG_IRQ_EN);
2287 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2288 tmp = omap_readw(OTG_IRQ_SRC);
2289 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2290 tmp = omap_readw(OTG_OUTCTRL);
2291 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2292 tmp = omap_readw(OTG_TEST);
2293 seq_printf(s, "otg_test %04x" "\n", tmp);
2294 return 0;
2295}
2296
2297static int proc_udc_show(struct seq_file *s, void *_)
2298{
2299 u32 tmp;
2300 struct omap_ep *ep;
2301 unsigned long flags;
2302
2303 spin_lock_irqsave(&udc->lock, flags);
2304
2305 seq_printf(s, "%s, version: " DRIVER_VERSION
2306#ifdef USE_ISO
2307 " (iso)"
2308#endif
2309 "%s\n",
2310 driver_desc,
2311 use_dma ? " (dma)" : "");
2312
2313 tmp = omap_readw(UDC_REV) & 0xff;
2314 seq_printf(s,
2315 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2316 "hmc %d, transceiver %s\n",
2317 tmp >> 4, tmp & 0xf,
2318 fifo_mode,
2319 udc->driver ? udc->driver->driver.name : "(none)",
2320 HMC,
2321 udc->transceiver
2322 ? udc->transceiver->label
2323 : (cpu_is_omap1710()
2324 ? "external" : "(none)"));
2325 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2326 omap_readw(ULPD_CLOCK_CTRL),
2327 omap_readw(ULPD_SOFT_REQ),
2328 omap_readw(ULPD_STATUS_REQ));
2329
2330 /* OTG controller registers */
2331 if (!cpu_is_omap15xx())
2332 proc_otg_show(s);
2333
2334 tmp = omap_readw(UDC_SYSCON1);
2335 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2336 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2337 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2338 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2339 (tmp & UDC_NAK_EN) ? " nak" : "",
2340 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2341 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2342 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2343 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2344 /* syscon2 is write-only */
2345
2346 /* UDC controller registers */
2347 if (!(tmp & UDC_PULLUP_EN)) {
2348 seq_printf(s, "(suspended)\n");
2349 spin_unlock_irqrestore(&udc->lock, flags);
2350 return 0;
2351 }
2352
2353 tmp = omap_readw(UDC_DEVSTAT);
2354 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2355 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2356 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2357 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2358 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2359 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2360 (tmp & UDC_SUS) ? " SUS" : "",
2361 (tmp & UDC_CFG) ? " CFG" : "",
2362 (tmp & UDC_ADD) ? " ADD" : "",
2363 (tmp & UDC_DEF) ? " DEF" : "",
2364 (tmp & UDC_ATT) ? " ATT" : "");
2365 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2366 tmp = omap_readw(UDC_IRQ_EN);
2367 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2368 (tmp & UDC_SOF_IE) ? " sof" : "",
2369 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2370 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2371 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2372 (tmp & UDC_EP0_IE) ? " ep0" : "");
2373 tmp = omap_readw(UDC_IRQ_SRC);
2374 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2375 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2376 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2377 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2378 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2379 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2380 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2381 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2382 (tmp & UDC_SETUP) ? " setup" : "",
2383 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2384 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2385 if (use_dma) {
2386 unsigned i;
2387
2388 tmp = omap_readw(UDC_DMA_IRQ_EN);
2389 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2390 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2391 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2392 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2393
2394 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2395 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2396 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2397
2398 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2399 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2400 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2401
2402 tmp = omap_readw(UDC_RXDMA_CFG);
2403 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2404 if (tmp) {
2405 for (i = 0; i < 3; i++) {
2406 if ((tmp & (0x0f << (i * 4))) == 0)
2407 continue;
2408 seq_printf(s, "rxdma[%d] %04x\n", i,
2409 omap_readw(UDC_RXDMA(i + 1)));
2410 }
2411 }
2412 tmp = omap_readw(UDC_TXDMA_CFG);
2413 seq_printf(s, "txdma_cfg %04x\n", tmp);
2414 if (tmp) {
2415 for (i = 0; i < 3; i++) {
2416 if (!(tmp & (0x0f << (i * 4))))
2417 continue;
2418 seq_printf(s, "txdma[%d] %04x\n", i,
2419 omap_readw(UDC_TXDMA(i + 1)));
2420 }
2421 }
2422 }
2423
2424 tmp = omap_readw(UDC_DEVSTAT);
2425 if (tmp & UDC_ATT) {
2426 proc_ep_show(s, &udc->ep[0]);
2427 if (tmp & UDC_ADD) {
2428 list_for_each_entry(ep, &udc->gadget.ep_list,
2429 ep.ep_list) {
2430 if (ep->ep.desc)
2431 proc_ep_show(s, ep);
2432 }
2433 }
2434 }
2435 spin_unlock_irqrestore(&udc->lock, flags);
2436 return 0;
2437}
2438
2439static int proc_udc_open(struct inode *inode, struct file *file)
2440{
2441 return single_open(file, proc_udc_show, NULL);
2442}
2443
2444static const struct file_operations proc_ops = {
2445 .owner = THIS_MODULE,
2446 .open = proc_udc_open,
2447 .read = seq_read,
2448 .llseek = seq_lseek,
2449 .release = single_release,
2450};
2451
2452static void create_proc_file(void)
2453{
2454 proc_create(proc_filename, 0, NULL, &proc_ops);
2455}
2456
2457static void remove_proc_file(void)
2458{
2459 remove_proc_entry(proc_filename, NULL);
2460}
2461
2462#else
2463
2464static inline void create_proc_file(void) {}
2465static inline void remove_proc_file(void) {}
2466
2467#endif
2468
2469/*-------------------------------------------------------------------------*/
2470
2471/* Before this controller can enumerate, we need to pick an endpoint
2472 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2473 * buffer space among the endpoints we'll be operating.
2474 *
2475 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2476 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2477 * capability yet though.
2478 */
2479static unsigned
2480omap_ep_setup(char *name, u8 addr, u8 type,
2481 unsigned buf, unsigned maxp, int dbuf)
2482{
2483 struct omap_ep *ep;
2484 u16 epn_rxtx = 0;
2485
2486 /* OUT endpoints first, then IN */
2487 ep = &udc->ep[addr & 0xf];
2488 if (addr & USB_DIR_IN)
2489 ep += 16;
2490
2491 /* in case of ep init table bugs */
2492 BUG_ON(ep->name[0]);
2493
2494 /* chip setup ... bit values are same for IN, OUT */
2495 if (type == USB_ENDPOINT_XFER_ISOC) {
2496 switch (maxp) {
2497 case 8:
2498 epn_rxtx = 0 << 12;
2499 break;
2500 case 16:
2501 epn_rxtx = 1 << 12;
2502 break;
2503 case 32:
2504 epn_rxtx = 2 << 12;
2505 break;
2506 case 64:
2507 epn_rxtx = 3 << 12;
2508 break;
2509 case 128:
2510 epn_rxtx = 4 << 12;
2511 break;
2512 case 256:
2513 epn_rxtx = 5 << 12;
2514 break;
2515 case 512:
2516 epn_rxtx = 6 << 12;
2517 break;
2518 default:
2519 BUG();
2520 }
2521 epn_rxtx |= UDC_EPN_RX_ISO;
2522 dbuf = 1;
2523 } else {
2524 /* double-buffering "not supported" on 15xx,
2525 * and ignored for PIO-IN on newer chips
2526 * (for more reliable behavior)
2527 */
2528 if (!use_dma || cpu_is_omap15xx())
2529 dbuf = 0;
2530
2531 switch (maxp) {
2532 case 8:
2533 epn_rxtx = 0 << 12;
2534 break;
2535 case 16:
2536 epn_rxtx = 1 << 12;
2537 break;
2538 case 32:
2539 epn_rxtx = 2 << 12;
2540 break;
2541 case 64:
2542 epn_rxtx = 3 << 12;
2543 break;
2544 default:
2545 BUG();
2546 }
2547 if (dbuf && addr)
2548 epn_rxtx |= UDC_EPN_RX_DB;
2549 init_timer(&ep->timer);
2550 ep->timer.function = pio_out_timer;
2551 ep->timer.data = (unsigned long) ep;
2552 }
2553 if (addr)
2554 epn_rxtx |= UDC_EPN_RX_VALID;
2555 BUG_ON(buf & 0x07);
2556 epn_rxtx |= buf >> 3;
2557
2558 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2559 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2560
2561 if (addr & USB_DIR_IN)
2562 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2563 else
2564 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2565
2566 /* next endpoint's buffer starts after this one's */
2567 buf += maxp;
2568 if (dbuf)
2569 buf += maxp;
2570 BUG_ON(buf > 2048);
2571
2572 /* set up driver data structures */
2573 BUG_ON(strlen(name) >= sizeof ep->name);
2574 strlcpy(ep->name, name, sizeof ep->name);
2575 INIT_LIST_HEAD(&ep->queue);
2576 INIT_LIST_HEAD(&ep->iso);
2577 ep->bEndpointAddress = addr;
2578 ep->bmAttributes = type;
2579 ep->double_buf = dbuf;
2580 ep->udc = udc;
2581
2582 switch (type) {
2583 case USB_ENDPOINT_XFER_CONTROL:
2584 ep->ep.caps.type_control = true;
2585 ep->ep.caps.dir_in = true;
2586 ep->ep.caps.dir_out = true;
2587 break;
2588 case USB_ENDPOINT_XFER_ISOC:
2589 ep->ep.caps.type_iso = true;
2590 break;
2591 case USB_ENDPOINT_XFER_BULK:
2592 ep->ep.caps.type_bulk = true;
2593 break;
2594 case USB_ENDPOINT_XFER_INT:
2595 ep->ep.caps.type_int = true;
2596 break;
2597 };
2598
2599 if (addr & USB_DIR_IN)
2600 ep->ep.caps.dir_in = true;
2601 else
2602 ep->ep.caps.dir_out = true;
2603
2604 ep->ep.name = ep->name;
2605 ep->ep.ops = &omap_ep_ops;
2606 ep->maxpacket = maxp;
2607 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2608 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2609
2610 return buf;
2611}
2612
2613static void omap_udc_release(struct device *dev)
2614{
2615 complete(udc->done);
2616 kfree(udc);
2617 udc = NULL;
2618}
2619
2620static int
2621omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2622{
2623 unsigned tmp, buf;
2624
2625 /* abolish any previous hardware state */
2626 omap_writew(0, UDC_SYSCON1);
2627 omap_writew(0, UDC_IRQ_EN);
2628 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2629 omap_writew(0, UDC_DMA_IRQ_EN);
2630 omap_writew(0, UDC_RXDMA_CFG);
2631 omap_writew(0, UDC_TXDMA_CFG);
2632
2633 /* UDC_PULLUP_EN gates the chip clock */
2634 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2635
2636 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2637 if (!udc)
2638 return -ENOMEM;
2639
2640 spin_lock_init(&udc->lock);
2641
2642 udc->gadget.ops = &omap_gadget_ops;
2643 udc->gadget.ep0 = &udc->ep[0].ep;
2644 INIT_LIST_HEAD(&udc->gadget.ep_list);
2645 INIT_LIST_HEAD(&udc->iso);
2646 udc->gadget.speed = USB_SPEED_UNKNOWN;
2647 udc->gadget.max_speed = USB_SPEED_FULL;
2648 udc->gadget.name = driver_name;
2649 udc->transceiver = xceiv;
2650
2651 /* ep0 is special; put it right after the SETUP buffer */
2652 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2653 8 /* after SETUP */, 64 /* maxpacket */, 0);
2654 list_del_init(&udc->ep[0].ep.ep_list);
2655
2656 /* initially disable all non-ep0 endpoints */
2657 for (tmp = 1; tmp < 15; tmp++) {
2658 omap_writew(0, UDC_EP_RX(tmp));
2659 omap_writew(0, UDC_EP_TX(tmp));
2660 }
2661
2662#define OMAP_BULK_EP(name, addr) \
2663 buf = omap_ep_setup(name "-bulk", addr, \
2664 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2665#define OMAP_INT_EP(name, addr, maxp) \
2666 buf = omap_ep_setup(name "-int", addr, \
2667 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2668#define OMAP_ISO_EP(name, addr, maxp) \
2669 buf = omap_ep_setup(name "-iso", addr, \
2670 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2671
2672 switch (fifo_mode) {
2673 case 0:
2674 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2675 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2676 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2677 break;
2678 case 1:
2679 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2680 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2681 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2682
2683 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2684 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2685 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2686
2687 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2688 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2689 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2690
2691 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2692 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2693 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2694
2695 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2696 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2697 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2698 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2699
2700 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2701 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2702 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2703 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2704
2705 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2706 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2707
2708 break;
2709
2710#ifdef USE_ISO
2711 case 2: /* mixed iso/bulk */
2712 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2713 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2714 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2715 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2716
2717 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2718
2719 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2720 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2721 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2722 break;
2723 case 3: /* mixed bulk/iso */
2724 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2725 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2726 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2727
2728 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2729 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2730 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2731
2732 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2733 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2734 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2735 break;
2736#endif
2737
2738 /* add more modes as needed */
2739
2740 default:
2741 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2742 return -ENODEV;
2743 }
2744 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2745 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2746 return 0;
2747}
2748
2749static int omap_udc_probe(struct platform_device *pdev)
2750{
2751 int status = -ENODEV;
2752 int hmc;
2753 struct usb_phy *xceiv = NULL;
2754 const char *type = NULL;
2755 struct omap_usb_config *config = dev_get_platdata(&pdev->dev);
2756 struct clk *dc_clk = NULL;
2757 struct clk *hhc_clk = NULL;
2758
2759 if (cpu_is_omap7xx())
2760 use_dma = 0;
2761
2762 /* NOTE: "knows" the order of the resources! */
2763 if (!request_mem_region(pdev->resource[0].start,
2764 pdev->resource[0].end - pdev->resource[0].start + 1,
2765 driver_name)) {
2766 DBG("request_mem_region failed\n");
2767 return -EBUSY;
2768 }
2769
2770 if (cpu_is_omap16xx()) {
2771 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2772 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2773 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2774 /* can't use omap_udc_enable_clock yet */
2775 clk_enable(dc_clk);
2776 clk_enable(hhc_clk);
2777 udelay(100);
2778 }
2779
2780 if (cpu_is_omap7xx()) {
2781 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2782 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2783 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2784 /* can't use omap_udc_enable_clock yet */
2785 clk_enable(dc_clk);
2786 clk_enable(hhc_clk);
2787 udelay(100);
2788 }
2789
2790 INFO("OMAP UDC rev %d.%d%s\n",
2791 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2792 config->otg ? ", Mini-AB" : "");
2793
2794 /* use the mode given to us by board init code */
2795 if (cpu_is_omap15xx()) {
2796 hmc = HMC_1510;
2797 type = "(unknown)";
2798
2799 if (machine_without_vbus_sense()) {
2800 /* just set up software VBUS detect, and then
2801 * later rig it so we always report VBUS.
2802 * FIXME without really sensing VBUS, we can't
2803 * know when to turn PULLUP_EN on/off; and that
2804 * means we always "need" the 48MHz clock.
2805 */
2806 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2807 tmp &= ~VBUS_CTRL_1510;
2808 omap_writel(tmp, FUNC_MUX_CTRL_0);
2809 tmp |= VBUS_MODE_1510;
2810 tmp &= ~VBUS_CTRL_1510;
2811 omap_writel(tmp, FUNC_MUX_CTRL_0);
2812 }
2813 } else {
2814 /* The transceiver may package some GPIO logic or handle
2815 * loopback and/or transceiverless setup; if we find one,
2816 * use it. Except for OTG, we don't _need_ to talk to one;
2817 * but not having one probably means no VBUS detection.
2818 */
2819 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2820 if (!IS_ERR_OR_NULL(xceiv))
2821 type = xceiv->label;
2822 else if (config->otg) {
2823 DBG("OTG requires external transceiver!\n");
2824 goto cleanup0;
2825 }
2826
2827 hmc = HMC_1610;
2828
2829 switch (hmc) {
2830 case 0: /* POWERUP DEFAULT == 0 */
2831 case 4:
2832 case 12:
2833 case 20:
2834 if (!cpu_is_omap1710()) {
2835 type = "integrated";
2836 break;
2837 }
2838 /* FALL THROUGH */
2839 case 3:
2840 case 11:
2841 case 16:
2842 case 19:
2843 case 25:
2844 if (IS_ERR_OR_NULL(xceiv)) {
2845 DBG("external transceiver not registered!\n");
2846 type = "unknown";
2847 }
2848 break;
2849 case 21: /* internal loopback */
2850 type = "loopback";
2851 break;
2852 case 14: /* transceiverless */
2853 if (cpu_is_omap1710())
2854 goto bad_on_1710;
2855 /* FALL THROUGH */
2856 case 13:
2857 case 15:
2858 type = "no";
2859 break;
2860
2861 default:
2862bad_on_1710:
2863 ERR("unrecognized UDC HMC mode %d\n", hmc);
2864 goto cleanup0;
2865 }
2866 }
2867
2868 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2869
2870 /* a "gadget" abstracts/virtualizes the controller */
2871 status = omap_udc_setup(pdev, xceiv);
2872 if (status)
2873 goto cleanup0;
2874
2875 xceiv = NULL;
2876 /* "udc" is now valid */
2877 pullup_disable(udc);
2878#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2879 udc->gadget.is_otg = (config->otg != 0);
2880#endif
2881
2882 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2883 if (omap_readw(UDC_REV) >= 0x61)
2884 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2885 else
2886 udc->clr_halt = UDC_RESET_EP;
2887
2888 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2889 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2890 0, driver_name, udc);
2891 if (status != 0) {
2892 ERR("can't get irq %d, err %d\n",
2893 (int) pdev->resource[1].start, status);
2894 goto cleanup1;
2895 }
2896
2897 /* USB "non-iso" IRQ (PIO for all but ep0) */
2898 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2899 0, "omap_udc pio", udc);
2900 if (status != 0) {
2901 ERR("can't get irq %d, err %d\n",
2902 (int) pdev->resource[2].start, status);
2903 goto cleanup2;
2904 }
2905#ifdef USE_ISO
2906 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2907 0, "omap_udc iso", udc);
2908 if (status != 0) {
2909 ERR("can't get irq %d, err %d\n",
2910 (int) pdev->resource[3].start, status);
2911 goto cleanup3;
2912 }
2913#endif
2914 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2915 udc->dc_clk = dc_clk;
2916 udc->hhc_clk = hhc_clk;
2917 clk_disable(hhc_clk);
2918 clk_disable(dc_clk);
2919 }
2920
2921 create_proc_file();
2922 status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2923 omap_udc_release);
2924 if (status)
2925 goto cleanup4;
2926
2927 return 0;
2928
2929cleanup4:
2930 remove_proc_file();
2931
2932#ifdef USE_ISO
2933cleanup3:
2934 free_irq(pdev->resource[2].start, udc);
2935#endif
2936
2937cleanup2:
2938 free_irq(pdev->resource[1].start, udc);
2939
2940cleanup1:
2941 kfree(udc);
2942 udc = NULL;
2943
2944cleanup0:
2945 if (!IS_ERR_OR_NULL(xceiv))
2946 usb_put_phy(xceiv);
2947
2948 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2949 clk_disable(hhc_clk);
2950 clk_disable(dc_clk);
2951 clk_put(hhc_clk);
2952 clk_put(dc_clk);
2953 }
2954
2955 release_mem_region(pdev->resource[0].start,
2956 pdev->resource[0].end - pdev->resource[0].start + 1);
2957
2958 return status;
2959}
2960
2961static int omap_udc_remove(struct platform_device *pdev)
2962{
2963 DECLARE_COMPLETION_ONSTACK(done);
2964
2965 if (!udc)
2966 return -ENODEV;
2967
2968 usb_del_gadget_udc(&udc->gadget);
2969 if (udc->driver)
2970 return -EBUSY;
2971
2972 udc->done = &done;
2973
2974 pullup_disable(udc);
2975 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2976 usb_put_phy(udc->transceiver);
2977 udc->transceiver = NULL;
2978 }
2979 omap_writew(0, UDC_SYSCON1);
2980
2981 remove_proc_file();
2982
2983#ifdef USE_ISO
2984 free_irq(pdev->resource[3].start, udc);
2985#endif
2986 free_irq(pdev->resource[2].start, udc);
2987 free_irq(pdev->resource[1].start, udc);
2988
2989 if (udc->dc_clk) {
2990 if (udc->clk_requested)
2991 omap_udc_enable_clock(0);
2992 clk_put(udc->hhc_clk);
2993 clk_put(udc->dc_clk);
2994 }
2995
2996 release_mem_region(pdev->resource[0].start,
2997 pdev->resource[0].end - pdev->resource[0].start + 1);
2998
2999 wait_for_completion(&done);
3000
3001 return 0;
3002}
3003
3004/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3005 * system is forced into deep sleep
3006 *
3007 * REVISIT we should probably reject suspend requests when there's a host
3008 * session active, rather than disconnecting, at least on boards that can
3009 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3010 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3011 * may involve talking to an external transceiver (e.g. isp1301).
3012 */
3013
3014static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3015{
3016 u32 devstat;
3017
3018 devstat = omap_readw(UDC_DEVSTAT);
3019
3020 /* we're requesting 48 MHz clock if the pullup is enabled
3021 * (== we're attached to the host) and we're not suspended,
3022 * which would prevent entry to deep sleep...
3023 */
3024 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3025 WARNING("session active; suspend requires disconnect\n");
3026 omap_pullup(&udc->gadget, 0);
3027 }
3028
3029 return 0;
3030}
3031
3032static int omap_udc_resume(struct platform_device *dev)
3033{
3034 DBG("resume + wakeup/SRP\n");
3035 omap_pullup(&udc->gadget, 1);
3036
3037 /* maybe the host would enumerate us if we nudged it */
3038 msleep(100);
3039 return omap_wakeup(&udc->gadget);
3040}
3041
3042/*-------------------------------------------------------------------------*/
3043
3044static struct platform_driver udc_driver = {
3045 .probe = omap_udc_probe,
3046 .remove = omap_udc_remove,
3047 .suspend = omap_udc_suspend,
3048 .resume = omap_udc_resume,
3049 .driver = {
3050 .name = (char *) driver_name,
3051 },
3052};
3053
3054module_platform_driver(udc_driver);
3055
3056MODULE_DESCRIPTION(DRIVER_DESC);
3057MODULE_LICENSE("GPL");
3058MODULE_ALIAS("platform:omap_udc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
4 *
5 * Copyright (C) 2004 Texas Instruments, Inc.
6 * Copyright (C) 2004-2005 David Brownell
7 *
8 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
9 */
10
11#undef DEBUG
12#undef VERBOSE
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/ioport.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21#include <linux/timer.h>
22#include <linux/list.h>
23#include <linux/interrupt.h>
24#include <linux/proc_fs.h>
25#include <linux/mm.h>
26#include <linux/moduleparam.h>
27#include <linux/platform_device.h>
28#include <linux/usb/ch9.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/otg.h>
31#include <linux/dma-mapping.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/prefetch.h>
35#include <linux/io.h>
36
37#include <asm/byteorder.h>
38#include <asm/irq.h>
39#include <asm/unaligned.h>
40#include <asm/mach-types.h>
41
42#include <linux/omap-dma.h>
43
44#include <mach/usb.h>
45
46#include "omap_udc.h"
47
48#undef USB_TRACE
49
50/* bulk DMA seems to be behaving for both IN and OUT */
51#define USE_DMA
52
53/* ISO too */
54#define USE_ISO
55
56#define DRIVER_DESC "OMAP UDC driver"
57#define DRIVER_VERSION "4 October 2004"
58
59#define OMAP_DMA_USB_W2FC_TX0 29
60#define OMAP_DMA_USB_W2FC_RX0 26
61
62/*
63 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
64 * D+ pullup to allow enumeration. That's too early for the gadget
65 * framework to use from usb_endpoint_enable(), which happens after
66 * enumeration as part of activating an interface. (But if we add an
67 * optional new "UDC not yet running" state to the gadget driver model,
68 * even just during driver binding, the endpoint autoconfig logic is the
69 * natural spot to manufacture new endpoints.)
70 *
71 * So instead of using endpoint enable calls to control the hardware setup,
72 * this driver defines a "fifo mode" parameter. It's used during driver
73 * initialization to choose among a set of pre-defined endpoint configs.
74 * See omap_udc_setup() for available modes, or to add others. That code
75 * lives in an init section, so use this driver as a module if you need
76 * to change the fifo mode after the kernel boots.
77 *
78 * Gadget drivers normally ignore endpoints they don't care about, and
79 * won't include them in configuration descriptors. That means only
80 * misbehaving hosts would even notice they exist.
81 */
82#ifdef USE_ISO
83static unsigned fifo_mode = 3;
84#else
85static unsigned fifo_mode;
86#endif
87
88/* "modprobe omap_udc fifo_mode=42", or else as a kernel
89 * boot parameter "omap_udc:fifo_mode=42"
90 */
91module_param(fifo_mode, uint, 0);
92MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
93
94#ifdef USE_DMA
95static bool use_dma = 1;
96
97/* "modprobe omap_udc use_dma=y", or else as a kernel
98 * boot parameter "omap_udc:use_dma=y"
99 */
100module_param(use_dma, bool, 0);
101MODULE_PARM_DESC(use_dma, "enable/disable DMA");
102#else /* !USE_DMA */
103
104/* save a bit of code */
105#define use_dma 0
106#endif /* !USE_DMA */
107
108
109static const char driver_name[] = "omap_udc";
110static const char driver_desc[] = DRIVER_DESC;
111
112/*-------------------------------------------------------------------------*/
113
114/* there's a notion of "current endpoint" for modifying endpoint
115 * state, and PIO access to its FIFO.
116 */
117
118static void use_ep(struct omap_ep *ep, u16 select)
119{
120 u16 num = ep->bEndpointAddress & 0x0f;
121
122 if (ep->bEndpointAddress & USB_DIR_IN)
123 num |= UDC_EP_DIR;
124 omap_writew(num | select, UDC_EP_NUM);
125 /* when select, MUST deselect later !! */
126}
127
128static inline void deselect_ep(void)
129{
130 u16 w;
131
132 w = omap_readw(UDC_EP_NUM);
133 w &= ~UDC_EP_SEL;
134 omap_writew(w, UDC_EP_NUM);
135 /* 6 wait states before TX will happen */
136}
137
138static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
139
140/*-------------------------------------------------------------------------*/
141
142static int omap_ep_enable(struct usb_ep *_ep,
143 const struct usb_endpoint_descriptor *desc)
144{
145 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
146 struct omap_udc *udc;
147 unsigned long flags;
148 u16 maxp;
149
150 /* catch various bogus parameters */
151 if (!_ep || !desc
152 || desc->bDescriptorType != USB_DT_ENDPOINT
153 || ep->bEndpointAddress != desc->bEndpointAddress
154 || ep->maxpacket < usb_endpoint_maxp(desc)) {
155 DBG("%s, bad ep or descriptor\n", __func__);
156 return -EINVAL;
157 }
158 maxp = usb_endpoint_maxp(desc);
159 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
160 && maxp != ep->maxpacket)
161 || usb_endpoint_maxp(desc) > ep->maxpacket
162 || !desc->wMaxPacketSize) {
163 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
164 return -ERANGE;
165 }
166
167#ifdef USE_ISO
168 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
169 && desc->bInterval != 1)) {
170 /* hardware wants period = 1; USB allows 2^(Interval-1) */
171 DBG("%s, unsupported ISO period %dms\n", _ep->name,
172 1 << (desc->bInterval - 1));
173 return -EDOM;
174 }
175#else
176 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
177 DBG("%s, ISO nyet\n", _ep->name);
178 return -EDOM;
179 }
180#endif
181
182 /* xfer types must match, except that interrupt ~= bulk */
183 if (ep->bmAttributes != desc->bmAttributes
184 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
185 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
186 DBG("%s, %s type mismatch\n", __func__, _ep->name);
187 return -EINVAL;
188 }
189
190 udc = ep->udc;
191 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
192 DBG("%s, bogus device state\n", __func__);
193 return -ESHUTDOWN;
194 }
195
196 spin_lock_irqsave(&udc->lock, flags);
197
198 ep->ep.desc = desc;
199 ep->irqs = 0;
200 ep->stopped = 0;
201 ep->ep.maxpacket = maxp;
202
203 /* set endpoint to initial state */
204 ep->dma_channel = 0;
205 ep->has_dma = 0;
206 ep->lch = -1;
207 use_ep(ep, UDC_EP_SEL);
208 omap_writew(udc->clr_halt, UDC_CTRL);
209 ep->ackwait = 0;
210 deselect_ep();
211
212 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
213 list_add(&ep->iso, &udc->iso);
214
215 /* maybe assign a DMA channel to this endpoint */
216 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
217 /* FIXME ISO can dma, but prefers first channel */
218 dma_channel_claim(ep, 0);
219
220 /* PIO OUT may RX packets */
221 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
222 && !ep->has_dma
223 && !(ep->bEndpointAddress & USB_DIR_IN)) {
224 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
225 ep->ackwait = 1 + ep->double_buf;
226 }
227
228 spin_unlock_irqrestore(&udc->lock, flags);
229 VDBG("%s enabled\n", _ep->name);
230 return 0;
231}
232
233static void nuke(struct omap_ep *, int status);
234
235static int omap_ep_disable(struct usb_ep *_ep)
236{
237 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
238 unsigned long flags;
239
240 if (!_ep || !ep->ep.desc) {
241 DBG("%s, %s not enabled\n", __func__,
242 _ep ? ep->ep.name : NULL);
243 return -EINVAL;
244 }
245
246 spin_lock_irqsave(&ep->udc->lock, flags);
247 ep->ep.desc = NULL;
248 nuke(ep, -ESHUTDOWN);
249 ep->ep.maxpacket = ep->maxpacket;
250 ep->has_dma = 0;
251 omap_writew(UDC_SET_HALT, UDC_CTRL);
252 list_del_init(&ep->iso);
253 del_timer(&ep->timer);
254
255 spin_unlock_irqrestore(&ep->udc->lock, flags);
256
257 VDBG("%s disabled\n", _ep->name);
258 return 0;
259}
260
261/*-------------------------------------------------------------------------*/
262
263static struct usb_request *
264omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
265{
266 struct omap_req *req;
267
268 req = kzalloc(sizeof(*req), gfp_flags);
269 if (!req)
270 return NULL;
271
272 INIT_LIST_HEAD(&req->queue);
273
274 return &req->req;
275}
276
277static void
278omap_free_request(struct usb_ep *ep, struct usb_request *_req)
279{
280 struct omap_req *req = container_of(_req, struct omap_req, req);
281
282 kfree(req);
283}
284
285/*-------------------------------------------------------------------------*/
286
287static void
288done(struct omap_ep *ep, struct omap_req *req, int status)
289{
290 struct omap_udc *udc = ep->udc;
291 unsigned stopped = ep->stopped;
292
293 list_del_init(&req->queue);
294
295 if (req->req.status == -EINPROGRESS)
296 req->req.status = status;
297 else
298 status = req->req.status;
299
300 if (use_dma && ep->has_dma)
301 usb_gadget_unmap_request(&udc->gadget, &req->req,
302 (ep->bEndpointAddress & USB_DIR_IN));
303
304#ifndef USB_TRACE
305 if (status && status != -ESHUTDOWN)
306#endif
307 VDBG("complete %s req %p stat %d len %u/%u\n",
308 ep->ep.name, &req->req, status,
309 req->req.actual, req->req.length);
310
311 /* don't modify queue heads during completion callback */
312 ep->stopped = 1;
313 spin_unlock(&ep->udc->lock);
314 usb_gadget_giveback_request(&ep->ep, &req->req);
315 spin_lock(&ep->udc->lock);
316 ep->stopped = stopped;
317}
318
319/*-------------------------------------------------------------------------*/
320
321#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
322#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
323
324#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
325#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
326
327static inline int
328write_packet(u8 *buf, struct omap_req *req, unsigned max)
329{
330 unsigned len;
331 u16 *wp;
332
333 len = min(req->req.length - req->req.actual, max);
334 req->req.actual += len;
335
336 max = len;
337 if (likely((((int)buf) & 1) == 0)) {
338 wp = (u16 *)buf;
339 while (max >= 2) {
340 omap_writew(*wp++, UDC_DATA);
341 max -= 2;
342 }
343 buf = (u8 *)wp;
344 }
345 while (max--)
346 omap_writeb(*buf++, UDC_DATA);
347 return len;
348}
349
350/* FIXME change r/w fifo calling convention */
351
352
353/* return: 0 = still running, 1 = completed, negative = errno */
354static int write_fifo(struct omap_ep *ep, struct omap_req *req)
355{
356 u8 *buf;
357 unsigned count;
358 int is_last;
359 u16 ep_stat;
360
361 buf = req->req.buf + req->req.actual;
362 prefetch(buf);
363
364 /* PIO-IN isn't double buffered except for iso */
365 ep_stat = omap_readw(UDC_STAT_FLG);
366 if (ep_stat & UDC_FIFO_UNWRITABLE)
367 return 0;
368
369 count = ep->ep.maxpacket;
370 count = write_packet(buf, req, count);
371 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
372 ep->ackwait = 1;
373
374 /* last packet is often short (sometimes a zlp) */
375 if (count != ep->ep.maxpacket)
376 is_last = 1;
377 else if (req->req.length == req->req.actual
378 && !req->req.zero)
379 is_last = 1;
380 else
381 is_last = 0;
382
383 /* NOTE: requests complete when all IN data is in a
384 * FIFO (or sometimes later, if a zlp was needed).
385 * Use usb_ep_fifo_status() where needed.
386 */
387 if (is_last)
388 done(ep, req, 0);
389 return is_last;
390}
391
392static inline int
393read_packet(u8 *buf, struct omap_req *req, unsigned avail)
394{
395 unsigned len;
396 u16 *wp;
397
398 len = min(req->req.length - req->req.actual, avail);
399 req->req.actual += len;
400 avail = len;
401
402 if (likely((((int)buf) & 1) == 0)) {
403 wp = (u16 *)buf;
404 while (avail >= 2) {
405 *wp++ = omap_readw(UDC_DATA);
406 avail -= 2;
407 }
408 buf = (u8 *)wp;
409 }
410 while (avail--)
411 *buf++ = omap_readb(UDC_DATA);
412 return len;
413}
414
415/* return: 0 = still running, 1 = queue empty, negative = errno */
416static int read_fifo(struct omap_ep *ep, struct omap_req *req)
417{
418 u8 *buf;
419 unsigned count, avail;
420 int is_last;
421
422 buf = req->req.buf + req->req.actual;
423 prefetchw(buf);
424
425 for (;;) {
426 u16 ep_stat = omap_readw(UDC_STAT_FLG);
427
428 is_last = 0;
429 if (ep_stat & FIFO_EMPTY) {
430 if (!ep->double_buf)
431 break;
432 ep->fnf = 1;
433 }
434 if (ep_stat & UDC_EP_HALTED)
435 break;
436
437 if (ep_stat & UDC_FIFO_FULL)
438 avail = ep->ep.maxpacket;
439 else {
440 avail = omap_readw(UDC_RXFSTAT);
441 ep->fnf = ep->double_buf;
442 }
443 count = read_packet(buf, req, avail);
444
445 /* partial packet reads may not be errors */
446 if (count < ep->ep.maxpacket) {
447 is_last = 1;
448 /* overflowed this request? flush extra data */
449 if (count != avail) {
450 req->req.status = -EOVERFLOW;
451 avail -= count;
452 while (avail--)
453 omap_readw(UDC_DATA);
454 }
455 } else if (req->req.length == req->req.actual)
456 is_last = 1;
457 else
458 is_last = 0;
459
460 if (!ep->bEndpointAddress)
461 break;
462 if (is_last)
463 done(ep, req, 0);
464 break;
465 }
466 return is_last;
467}
468
469/*-------------------------------------------------------------------------*/
470
471static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
472{
473 dma_addr_t end;
474
475 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
476 * the last transfer's bytecount by more than a FIFO's worth.
477 */
478 if (cpu_is_omap15xx())
479 return 0;
480
481 end = omap_get_dma_src_pos(ep->lch);
482 if (end == ep->dma_counter)
483 return 0;
484
485 end |= start & (0xffff << 16);
486 if (end < start)
487 end += 0x10000;
488 return end - start;
489}
490
491static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
492{
493 dma_addr_t end;
494
495 end = omap_get_dma_dst_pos(ep->lch);
496 if (end == ep->dma_counter)
497 return 0;
498
499 end |= start & (0xffff << 16);
500 if (cpu_is_omap15xx())
501 end++;
502 if (end < start)
503 end += 0x10000;
504 return end - start;
505}
506
507
508/* Each USB transfer request using DMA maps to one or more DMA transfers.
509 * When DMA completion isn't request completion, the UDC continues with
510 * the next DMA transfer for that USB transfer.
511 */
512
513static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
514{
515 u16 txdma_ctrl, w;
516 unsigned length = req->req.length - req->req.actual;
517 const int sync_mode = cpu_is_omap15xx()
518 ? OMAP_DMA_SYNC_FRAME
519 : OMAP_DMA_SYNC_ELEMENT;
520 int dma_trigger = 0;
521
522 /* measure length in either bytes or packets */
523 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
524 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
525 txdma_ctrl = UDC_TXN_EOT | length;
526 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
527 length, 1, sync_mode, dma_trigger, 0);
528 } else {
529 length = min(length / ep->maxpacket,
530 (unsigned) UDC_TXN_TSC + 1);
531 txdma_ctrl = length;
532 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
533 ep->ep.maxpacket >> 1, length, sync_mode,
534 dma_trigger, 0);
535 length *= ep->maxpacket;
536 }
537 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
538 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
539 0, 0);
540
541 omap_start_dma(ep->lch);
542 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
543 w = omap_readw(UDC_DMA_IRQ_EN);
544 w |= UDC_TX_DONE_IE(ep->dma_channel);
545 omap_writew(w, UDC_DMA_IRQ_EN);
546 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
547 req->dma_bytes = length;
548}
549
550static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
551{
552 u16 w;
553
554 if (status == 0) {
555 req->req.actual += req->dma_bytes;
556
557 /* return if this request needs to send data or zlp */
558 if (req->req.actual < req->req.length)
559 return;
560 if (req->req.zero
561 && req->dma_bytes != 0
562 && (req->req.actual % ep->maxpacket) == 0)
563 return;
564 } else
565 req->req.actual += dma_src_len(ep, req->req.dma
566 + req->req.actual);
567
568 /* tx completion */
569 omap_stop_dma(ep->lch);
570 w = omap_readw(UDC_DMA_IRQ_EN);
571 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
572 omap_writew(w, UDC_DMA_IRQ_EN);
573 done(ep, req, status);
574}
575
576static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
577{
578 unsigned packets = req->req.length - req->req.actual;
579 int dma_trigger = 0;
580 u16 w;
581
582 /* set up this DMA transfer, enable the fifo, start */
583 packets /= ep->ep.maxpacket;
584 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
585 req->dma_bytes = packets * ep->ep.maxpacket;
586 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
587 ep->ep.maxpacket >> 1, packets,
588 OMAP_DMA_SYNC_ELEMENT,
589 dma_trigger, 0);
590 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
591 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
592 0, 0);
593 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
594
595 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
596 w = omap_readw(UDC_DMA_IRQ_EN);
597 w |= UDC_RX_EOT_IE(ep->dma_channel);
598 omap_writew(w, UDC_DMA_IRQ_EN);
599 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
600 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
601
602 omap_start_dma(ep->lch);
603}
604
605static void
606finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
607{
608 u16 count, w;
609
610 if (status == 0)
611 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
612 count = dma_dest_len(ep, req->req.dma + req->req.actual);
613 count += req->req.actual;
614 if (one)
615 count--;
616 if (count <= req->req.length)
617 req->req.actual = count;
618
619 if (count != req->dma_bytes || status)
620 omap_stop_dma(ep->lch);
621
622 /* if this wasn't short, request may need another transfer */
623 else if (req->req.actual < req->req.length)
624 return;
625
626 /* rx completion */
627 w = omap_readw(UDC_DMA_IRQ_EN);
628 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
629 omap_writew(w, UDC_DMA_IRQ_EN);
630 done(ep, req, status);
631}
632
633static void dma_irq(struct omap_udc *udc, u16 irq_src)
634{
635 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
636 struct omap_ep *ep;
637 struct omap_req *req;
638
639 /* IN dma: tx to host */
640 if (irq_src & UDC_TXN_DONE) {
641 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
642 ep->irqs++;
643 /* can see TXN_DONE after dma abort */
644 if (!list_empty(&ep->queue)) {
645 req = container_of(ep->queue.next,
646 struct omap_req, queue);
647 finish_in_dma(ep, req, 0);
648 }
649 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
650
651 if (!list_empty(&ep->queue)) {
652 req = container_of(ep->queue.next,
653 struct omap_req, queue);
654 next_in_dma(ep, req);
655 }
656 }
657
658 /* OUT dma: rx from host */
659 if (irq_src & UDC_RXN_EOT) {
660 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
661 ep->irqs++;
662 /* can see RXN_EOT after dma abort */
663 if (!list_empty(&ep->queue)) {
664 req = container_of(ep->queue.next,
665 struct omap_req, queue);
666 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
667 }
668 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
669
670 if (!list_empty(&ep->queue)) {
671 req = container_of(ep->queue.next,
672 struct omap_req, queue);
673 next_out_dma(ep, req);
674 }
675 }
676
677 if (irq_src & UDC_RXN_CNT) {
678 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
679 ep->irqs++;
680 /* omap15xx does this unasked... */
681 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
682 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
683 }
684}
685
686static void dma_error(int lch, u16 ch_status, void *data)
687{
688 struct omap_ep *ep = data;
689
690 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
691 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
692 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
693
694 /* complete current transfer ... */
695}
696
697static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
698{
699 u16 reg;
700 int status, restart, is_in;
701 int dma_channel;
702
703 is_in = ep->bEndpointAddress & USB_DIR_IN;
704 if (is_in)
705 reg = omap_readw(UDC_TXDMA_CFG);
706 else
707 reg = omap_readw(UDC_RXDMA_CFG);
708 reg |= UDC_DMA_REQ; /* "pulse" activated */
709
710 ep->dma_channel = 0;
711 ep->lch = -1;
712 if (channel == 0 || channel > 3) {
713 if ((reg & 0x0f00) == 0)
714 channel = 3;
715 else if ((reg & 0x00f0) == 0)
716 channel = 2;
717 else if ((reg & 0x000f) == 0) /* preferred for ISO */
718 channel = 1;
719 else {
720 status = -EMLINK;
721 goto just_restart;
722 }
723 }
724 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
725 ep->dma_channel = channel;
726
727 if (is_in) {
728 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
729 status = omap_request_dma(dma_channel,
730 ep->ep.name, dma_error, ep, &ep->lch);
731 if (status == 0) {
732 omap_writew(reg, UDC_TXDMA_CFG);
733 /* EMIFF or SDRC */
734 omap_set_dma_src_burst_mode(ep->lch,
735 OMAP_DMA_DATA_BURST_4);
736 omap_set_dma_src_data_pack(ep->lch, 1);
737 /* TIPB */
738 omap_set_dma_dest_params(ep->lch,
739 OMAP_DMA_PORT_TIPB,
740 OMAP_DMA_AMODE_CONSTANT,
741 UDC_DATA_DMA,
742 0, 0);
743 }
744 } else {
745 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
746 status = omap_request_dma(dma_channel,
747 ep->ep.name, dma_error, ep, &ep->lch);
748 if (status == 0) {
749 omap_writew(reg, UDC_RXDMA_CFG);
750 /* TIPB */
751 omap_set_dma_src_params(ep->lch,
752 OMAP_DMA_PORT_TIPB,
753 OMAP_DMA_AMODE_CONSTANT,
754 UDC_DATA_DMA,
755 0, 0);
756 /* EMIFF or SDRC */
757 omap_set_dma_dest_burst_mode(ep->lch,
758 OMAP_DMA_DATA_BURST_4);
759 omap_set_dma_dest_data_pack(ep->lch, 1);
760 }
761 }
762 if (status)
763 ep->dma_channel = 0;
764 else {
765 ep->has_dma = 1;
766 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
767
768 /* channel type P: hw synch (fifo) */
769 if (!cpu_is_omap15xx())
770 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
771 }
772
773just_restart:
774 /* restart any queue, even if the claim failed */
775 restart = !ep->stopped && !list_empty(&ep->queue);
776
777 if (status)
778 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
779 restart ? " (restart)" : "");
780 else
781 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
782 is_in ? 't' : 'r',
783 ep->dma_channel - 1, ep->lch,
784 restart ? " (restart)" : "");
785
786 if (restart) {
787 struct omap_req *req;
788 req = container_of(ep->queue.next, struct omap_req, queue);
789 if (ep->has_dma)
790 (is_in ? next_in_dma : next_out_dma)(ep, req);
791 else {
792 use_ep(ep, UDC_EP_SEL);
793 (is_in ? write_fifo : read_fifo)(ep, req);
794 deselect_ep();
795 if (!is_in) {
796 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
797 ep->ackwait = 1 + ep->double_buf;
798 }
799 /* IN: 6 wait states before it'll tx */
800 }
801 }
802}
803
804static void dma_channel_release(struct omap_ep *ep)
805{
806 int shift = 4 * (ep->dma_channel - 1);
807 u16 mask = 0x0f << shift;
808 struct omap_req *req;
809 int active;
810
811 /* abort any active usb transfer request */
812 if (!list_empty(&ep->queue))
813 req = container_of(ep->queue.next, struct omap_req, queue);
814 else
815 req = NULL;
816
817 active = omap_get_dma_active_status(ep->lch);
818
819 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
820 active ? "active" : "idle",
821 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
822 ep->dma_channel - 1, req);
823
824 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
825 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
826 */
827
828 /* wait till current packet DMA finishes, and fifo empties */
829 if (ep->bEndpointAddress & USB_DIR_IN) {
830 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
831 UDC_TXDMA_CFG);
832
833 if (req) {
834 finish_in_dma(ep, req, -ECONNRESET);
835
836 /* clear FIFO; hosts probably won't empty it */
837 use_ep(ep, UDC_EP_SEL);
838 omap_writew(UDC_CLR_EP, UDC_CTRL);
839 deselect_ep();
840 }
841 while (omap_readw(UDC_TXDMA_CFG) & mask)
842 udelay(10);
843 } else {
844 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
845 UDC_RXDMA_CFG);
846
847 /* dma empties the fifo */
848 while (omap_readw(UDC_RXDMA_CFG) & mask)
849 udelay(10);
850 if (req)
851 finish_out_dma(ep, req, -ECONNRESET, 0);
852 }
853 omap_free_dma(ep->lch);
854 ep->dma_channel = 0;
855 ep->lch = -1;
856 /* has_dma still set, till endpoint is fully quiesced */
857}
858
859
860/*-------------------------------------------------------------------------*/
861
862static int
863omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
864{
865 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
866 struct omap_req *req = container_of(_req, struct omap_req, req);
867 struct omap_udc *udc;
868 unsigned long flags;
869 int is_iso = 0;
870
871 /* catch various bogus parameters */
872 if (!_req || !req->req.complete || !req->req.buf
873 || !list_empty(&req->queue)) {
874 DBG("%s, bad params\n", __func__);
875 return -EINVAL;
876 }
877 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
878 DBG("%s, bad ep\n", __func__);
879 return -EINVAL;
880 }
881 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
882 if (req->req.length > ep->ep.maxpacket)
883 return -EMSGSIZE;
884 is_iso = 1;
885 }
886
887 /* this isn't bogus, but OMAP DMA isn't the only hardware to
888 * have a hard time with partial packet reads... reject it.
889 */
890 if (use_dma
891 && ep->has_dma
892 && ep->bEndpointAddress != 0
893 && (ep->bEndpointAddress & USB_DIR_IN) == 0
894 && (req->req.length % ep->ep.maxpacket) != 0) {
895 DBG("%s, no partial packet OUT reads\n", __func__);
896 return -EMSGSIZE;
897 }
898
899 udc = ep->udc;
900 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
901 return -ESHUTDOWN;
902
903 if (use_dma && ep->has_dma)
904 usb_gadget_map_request(&udc->gadget, &req->req,
905 (ep->bEndpointAddress & USB_DIR_IN));
906
907 VDBG("%s queue req %p, len %d buf %p\n",
908 ep->ep.name, _req, _req->length, _req->buf);
909
910 spin_lock_irqsave(&udc->lock, flags);
911
912 req->req.status = -EINPROGRESS;
913 req->req.actual = 0;
914
915 /* maybe kickstart non-iso i/o queues */
916 if (is_iso) {
917 u16 w;
918
919 w = omap_readw(UDC_IRQ_EN);
920 w |= UDC_SOF_IE;
921 omap_writew(w, UDC_IRQ_EN);
922 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
923 int is_in;
924
925 if (ep->bEndpointAddress == 0) {
926 if (!udc->ep0_pending || !list_empty(&ep->queue)) {
927 spin_unlock_irqrestore(&udc->lock, flags);
928 return -EL2HLT;
929 }
930
931 /* empty DATA stage? */
932 is_in = udc->ep0_in;
933 if (!req->req.length) {
934
935 /* chip became CONFIGURED or ADDRESSED
936 * earlier; drivers may already have queued
937 * requests to non-control endpoints
938 */
939 if (udc->ep0_set_config) {
940 u16 irq_en = omap_readw(UDC_IRQ_EN);
941
942 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
943 if (!udc->ep0_reset_config)
944 irq_en |= UDC_EPN_RX_IE
945 | UDC_EPN_TX_IE;
946 omap_writew(irq_en, UDC_IRQ_EN);
947 }
948
949 /* STATUS for zero length DATA stages is
950 * always an IN ... even for IN transfers,
951 * a weird case which seem to stall OMAP.
952 */
953 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
954 UDC_EP_NUM);
955 omap_writew(UDC_CLR_EP, UDC_CTRL);
956 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
957 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
958
959 /* cleanup */
960 udc->ep0_pending = 0;
961 done(ep, req, 0);
962 req = NULL;
963
964 /* non-empty DATA stage */
965 } else if (is_in) {
966 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
967 UDC_EP_NUM);
968 } else {
969 if (udc->ep0_setup)
970 goto irq_wait;
971 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
972 }
973 } else {
974 is_in = ep->bEndpointAddress & USB_DIR_IN;
975 if (!ep->has_dma)
976 use_ep(ep, UDC_EP_SEL);
977 /* if ISO: SOF IRQs must be enabled/disabled! */
978 }
979
980 if (ep->has_dma)
981 (is_in ? next_in_dma : next_out_dma)(ep, req);
982 else if (req) {
983 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
984 req = NULL;
985 deselect_ep();
986 if (!is_in) {
987 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
988 ep->ackwait = 1 + ep->double_buf;
989 }
990 /* IN: 6 wait states before it'll tx */
991 }
992 }
993
994irq_wait:
995 /* irq handler advances the queue */
996 if (req != NULL)
997 list_add_tail(&req->queue, &ep->queue);
998 spin_unlock_irqrestore(&udc->lock, flags);
999
1000 return 0;
1001}
1002
1003static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1004{
1005 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1006 struct omap_req *req;
1007 unsigned long flags;
1008
1009 if (!_ep || !_req)
1010 return -EINVAL;
1011
1012 spin_lock_irqsave(&ep->udc->lock, flags);
1013
1014 /* make sure it's actually queued on this endpoint */
1015 list_for_each_entry(req, &ep->queue, queue) {
1016 if (&req->req == _req)
1017 break;
1018 }
1019 if (&req->req != _req) {
1020 spin_unlock_irqrestore(&ep->udc->lock, flags);
1021 return -EINVAL;
1022 }
1023
1024 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1025 int channel = ep->dma_channel;
1026
1027 /* releasing the channel cancels the request,
1028 * reclaiming the channel restarts the queue
1029 */
1030 dma_channel_release(ep);
1031 dma_channel_claim(ep, channel);
1032 } else
1033 done(ep, req, -ECONNRESET);
1034 spin_unlock_irqrestore(&ep->udc->lock, flags);
1035 return 0;
1036}
1037
1038/*-------------------------------------------------------------------------*/
1039
1040static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1041{
1042 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1043 unsigned long flags;
1044 int status = -EOPNOTSUPP;
1045
1046 spin_lock_irqsave(&ep->udc->lock, flags);
1047
1048 /* just use protocol stalls for ep0; real halts are annoying */
1049 if (ep->bEndpointAddress == 0) {
1050 if (!ep->udc->ep0_pending)
1051 status = -EINVAL;
1052 else if (value) {
1053 if (ep->udc->ep0_set_config) {
1054 WARNING("error changing config?\n");
1055 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1056 }
1057 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1058 ep->udc->ep0_pending = 0;
1059 status = 0;
1060 } else /* NOP */
1061 status = 0;
1062
1063 /* otherwise, all active non-ISO endpoints can halt */
1064 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1065
1066 /* IN endpoints must already be idle */
1067 if ((ep->bEndpointAddress & USB_DIR_IN)
1068 && !list_empty(&ep->queue)) {
1069 status = -EAGAIN;
1070 goto done;
1071 }
1072
1073 if (value) {
1074 int channel;
1075
1076 if (use_dma && ep->dma_channel
1077 && !list_empty(&ep->queue)) {
1078 channel = ep->dma_channel;
1079 dma_channel_release(ep);
1080 } else
1081 channel = 0;
1082
1083 use_ep(ep, UDC_EP_SEL);
1084 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1085 omap_writew(UDC_SET_HALT, UDC_CTRL);
1086 status = 0;
1087 } else
1088 status = -EAGAIN;
1089 deselect_ep();
1090
1091 if (channel)
1092 dma_channel_claim(ep, channel);
1093 } else {
1094 use_ep(ep, 0);
1095 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1096 ep->ackwait = 0;
1097 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1098 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1099 ep->ackwait = 1 + ep->double_buf;
1100 }
1101 }
1102 }
1103done:
1104 VDBG("%s %s halt stat %d\n", ep->ep.name,
1105 value ? "set" : "clear", status);
1106
1107 spin_unlock_irqrestore(&ep->udc->lock, flags);
1108 return status;
1109}
1110
1111static const struct usb_ep_ops omap_ep_ops = {
1112 .enable = omap_ep_enable,
1113 .disable = omap_ep_disable,
1114
1115 .alloc_request = omap_alloc_request,
1116 .free_request = omap_free_request,
1117
1118 .queue = omap_ep_queue,
1119 .dequeue = omap_ep_dequeue,
1120
1121 .set_halt = omap_ep_set_halt,
1122 /* fifo_status ... report bytes in fifo */
1123 /* fifo_flush ... flush fifo */
1124};
1125
1126/*-------------------------------------------------------------------------*/
1127
1128static int omap_get_frame(struct usb_gadget *gadget)
1129{
1130 u16 sof = omap_readw(UDC_SOF);
1131 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1132}
1133
1134static int omap_wakeup(struct usb_gadget *gadget)
1135{
1136 struct omap_udc *udc;
1137 unsigned long flags;
1138 int retval = -EHOSTUNREACH;
1139
1140 udc = container_of(gadget, struct omap_udc, gadget);
1141
1142 spin_lock_irqsave(&udc->lock, flags);
1143 if (udc->devstat & UDC_SUS) {
1144 /* NOTE: OTG spec erratum says that OTG devices may
1145 * issue wakeups without host enable.
1146 */
1147 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1148 DBG("remote wakeup...\n");
1149 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1150 retval = 0;
1151 }
1152
1153 /* NOTE: non-OTG systems may use SRP TOO... */
1154 } else if (!(udc->devstat & UDC_ATT)) {
1155 if (!IS_ERR_OR_NULL(udc->transceiver))
1156 retval = otg_start_srp(udc->transceiver->otg);
1157 }
1158 spin_unlock_irqrestore(&udc->lock, flags);
1159
1160 return retval;
1161}
1162
1163static int
1164omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1165{
1166 struct omap_udc *udc;
1167 unsigned long flags;
1168 u16 syscon1;
1169
1170 gadget->is_selfpowered = (is_selfpowered != 0);
1171 udc = container_of(gadget, struct omap_udc, gadget);
1172 spin_lock_irqsave(&udc->lock, flags);
1173 syscon1 = omap_readw(UDC_SYSCON1);
1174 if (is_selfpowered)
1175 syscon1 |= UDC_SELF_PWR;
1176 else
1177 syscon1 &= ~UDC_SELF_PWR;
1178 omap_writew(syscon1, UDC_SYSCON1);
1179 spin_unlock_irqrestore(&udc->lock, flags);
1180
1181 return 0;
1182}
1183
1184static int can_pullup(struct omap_udc *udc)
1185{
1186 return udc->driver && udc->softconnect && udc->vbus_active;
1187}
1188
1189static void pullup_enable(struct omap_udc *udc)
1190{
1191 u16 w;
1192
1193 w = omap_readw(UDC_SYSCON1);
1194 w |= UDC_PULLUP_EN;
1195 omap_writew(w, UDC_SYSCON1);
1196 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1197 u32 l;
1198
1199 l = omap_readl(OTG_CTRL);
1200 l |= OTG_BSESSVLD;
1201 omap_writel(l, OTG_CTRL);
1202 }
1203 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1204}
1205
1206static void pullup_disable(struct omap_udc *udc)
1207{
1208 u16 w;
1209
1210 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1211 u32 l;
1212
1213 l = omap_readl(OTG_CTRL);
1214 l &= ~OTG_BSESSVLD;
1215 omap_writel(l, OTG_CTRL);
1216 }
1217 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1218 w = omap_readw(UDC_SYSCON1);
1219 w &= ~UDC_PULLUP_EN;
1220 omap_writew(w, UDC_SYSCON1);
1221}
1222
1223static struct omap_udc *udc;
1224
1225static void omap_udc_enable_clock(int enable)
1226{
1227 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1228 return;
1229
1230 if (enable) {
1231 clk_enable(udc->dc_clk);
1232 clk_enable(udc->hhc_clk);
1233 udelay(100);
1234 } else {
1235 clk_disable(udc->hhc_clk);
1236 clk_disable(udc->dc_clk);
1237 }
1238}
1239
1240/*
1241 * Called by whatever detects VBUS sessions: external transceiver
1242 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1243 */
1244static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1245{
1246 struct omap_udc *udc;
1247 unsigned long flags;
1248 u32 l;
1249
1250 udc = container_of(gadget, struct omap_udc, gadget);
1251 spin_lock_irqsave(&udc->lock, flags);
1252 VDBG("VBUS %s\n", is_active ? "on" : "off");
1253 udc->vbus_active = (is_active != 0);
1254 if (cpu_is_omap15xx()) {
1255 /* "software" detect, ignored if !VBUS_MODE_1510 */
1256 l = omap_readl(FUNC_MUX_CTRL_0);
1257 if (is_active)
1258 l |= VBUS_CTRL_1510;
1259 else
1260 l &= ~VBUS_CTRL_1510;
1261 omap_writel(l, FUNC_MUX_CTRL_0);
1262 }
1263 if (udc->dc_clk != NULL && is_active) {
1264 if (!udc->clk_requested) {
1265 omap_udc_enable_clock(1);
1266 udc->clk_requested = 1;
1267 }
1268 }
1269 if (can_pullup(udc))
1270 pullup_enable(udc);
1271 else
1272 pullup_disable(udc);
1273 if (udc->dc_clk != NULL && !is_active) {
1274 if (udc->clk_requested) {
1275 omap_udc_enable_clock(0);
1276 udc->clk_requested = 0;
1277 }
1278 }
1279 spin_unlock_irqrestore(&udc->lock, flags);
1280 return 0;
1281}
1282
1283static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1284{
1285 struct omap_udc *udc;
1286
1287 udc = container_of(gadget, struct omap_udc, gadget);
1288 if (!IS_ERR_OR_NULL(udc->transceiver))
1289 return usb_phy_set_power(udc->transceiver, mA);
1290 return -EOPNOTSUPP;
1291}
1292
1293static int omap_pullup(struct usb_gadget *gadget, int is_on)
1294{
1295 struct omap_udc *udc;
1296 unsigned long flags;
1297
1298 udc = container_of(gadget, struct omap_udc, gadget);
1299 spin_lock_irqsave(&udc->lock, flags);
1300 udc->softconnect = (is_on != 0);
1301 if (can_pullup(udc))
1302 pullup_enable(udc);
1303 else
1304 pullup_disable(udc);
1305 spin_unlock_irqrestore(&udc->lock, flags);
1306 return 0;
1307}
1308
1309static int omap_udc_start(struct usb_gadget *g,
1310 struct usb_gadget_driver *driver);
1311static int omap_udc_stop(struct usb_gadget *g);
1312
1313static const struct usb_gadget_ops omap_gadget_ops = {
1314 .get_frame = omap_get_frame,
1315 .wakeup = omap_wakeup,
1316 .set_selfpowered = omap_set_selfpowered,
1317 .vbus_session = omap_vbus_session,
1318 .vbus_draw = omap_vbus_draw,
1319 .pullup = omap_pullup,
1320 .udc_start = omap_udc_start,
1321 .udc_stop = omap_udc_stop,
1322};
1323
1324/*-------------------------------------------------------------------------*/
1325
1326/* dequeue ALL requests; caller holds udc->lock */
1327static void nuke(struct omap_ep *ep, int status)
1328{
1329 struct omap_req *req;
1330
1331 ep->stopped = 1;
1332
1333 if (use_dma && ep->dma_channel)
1334 dma_channel_release(ep);
1335
1336 use_ep(ep, 0);
1337 omap_writew(UDC_CLR_EP, UDC_CTRL);
1338 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1339 omap_writew(UDC_SET_HALT, UDC_CTRL);
1340
1341 while (!list_empty(&ep->queue)) {
1342 req = list_entry(ep->queue.next, struct omap_req, queue);
1343 done(ep, req, status);
1344 }
1345}
1346
1347/* caller holds udc->lock */
1348static void udc_quiesce(struct omap_udc *udc)
1349{
1350 struct omap_ep *ep;
1351
1352 udc->gadget.speed = USB_SPEED_UNKNOWN;
1353 nuke(&udc->ep[0], -ESHUTDOWN);
1354 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1355 nuke(ep, -ESHUTDOWN);
1356}
1357
1358/*-------------------------------------------------------------------------*/
1359
1360static void update_otg(struct omap_udc *udc)
1361{
1362 u16 devstat;
1363
1364 if (!gadget_is_otg(&udc->gadget))
1365 return;
1366
1367 if (omap_readl(OTG_CTRL) & OTG_ID)
1368 devstat = omap_readw(UDC_DEVSTAT);
1369 else
1370 devstat = 0;
1371
1372 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1373 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1374 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1375
1376 /* Enable HNP early, avoiding races on suspend irq path.
1377 * ASSUMES OTG state machine B_BUS_REQ input is true.
1378 */
1379 if (udc->gadget.b_hnp_enable) {
1380 u32 l;
1381
1382 l = omap_readl(OTG_CTRL);
1383 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1384 l &= ~OTG_PULLUP;
1385 omap_writel(l, OTG_CTRL);
1386 }
1387}
1388
1389static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1390{
1391 struct omap_ep *ep0 = &udc->ep[0];
1392 struct omap_req *req = NULL;
1393
1394 ep0->irqs++;
1395
1396 /* Clear any pending requests and then scrub any rx/tx state
1397 * before starting to handle the SETUP request.
1398 */
1399 if (irq_src & UDC_SETUP) {
1400 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1401
1402 nuke(ep0, 0);
1403 if (ack) {
1404 omap_writew(ack, UDC_IRQ_SRC);
1405 irq_src = UDC_SETUP;
1406 }
1407 }
1408
1409 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1410 * This driver uses only uses protocol stalls (ep0 never halts),
1411 * and if we got this far the gadget driver already had a
1412 * chance to stall. Tries to be forgiving of host oddities.
1413 *
1414 * NOTE: the last chance gadget drivers have to stall control
1415 * requests is during their request completion callback.
1416 */
1417 if (!list_empty(&ep0->queue))
1418 req = container_of(ep0->queue.next, struct omap_req, queue);
1419
1420 /* IN == TX to host */
1421 if (irq_src & UDC_EP0_TX) {
1422 int stat;
1423
1424 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1425 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1426 stat = omap_readw(UDC_STAT_FLG);
1427 if (stat & UDC_ACK) {
1428 if (udc->ep0_in) {
1429 /* write next IN packet from response,
1430 * or set up the status stage.
1431 */
1432 if (req)
1433 stat = write_fifo(ep0, req);
1434 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1435 if (!req && udc->ep0_pending) {
1436 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1437 omap_writew(UDC_CLR_EP, UDC_CTRL);
1438 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1439 omap_writew(0, UDC_EP_NUM);
1440 udc->ep0_pending = 0;
1441 } /* else: 6 wait states before it'll tx */
1442 } else {
1443 /* ack status stage of OUT transfer */
1444 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1445 if (req)
1446 done(ep0, req, 0);
1447 }
1448 req = NULL;
1449 } else if (stat & UDC_STALL) {
1450 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1451 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1452 } else {
1453 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1454 }
1455 }
1456
1457 /* OUT == RX from host */
1458 if (irq_src & UDC_EP0_RX) {
1459 int stat;
1460
1461 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1462 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1463 stat = omap_readw(UDC_STAT_FLG);
1464 if (stat & UDC_ACK) {
1465 if (!udc->ep0_in) {
1466 stat = 0;
1467 /* read next OUT packet of request, maybe
1468 * reactiviting the fifo; stall on errors.
1469 */
1470 stat = read_fifo(ep0, req);
1471 if (!req || stat < 0) {
1472 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1473 udc->ep0_pending = 0;
1474 stat = 0;
1475 } else if (stat == 0)
1476 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1477 omap_writew(0, UDC_EP_NUM);
1478
1479 /* activate status stage */
1480 if (stat == 1) {
1481 done(ep0, req, 0);
1482 /* that may have STALLed ep0... */
1483 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1484 UDC_EP_NUM);
1485 omap_writew(UDC_CLR_EP, UDC_CTRL);
1486 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1487 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1488 udc->ep0_pending = 0;
1489 }
1490 } else {
1491 /* ack status stage of IN transfer */
1492 omap_writew(0, UDC_EP_NUM);
1493 if (req)
1494 done(ep0, req, 0);
1495 }
1496 } else if (stat & UDC_STALL) {
1497 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1498 omap_writew(0, UDC_EP_NUM);
1499 } else {
1500 omap_writew(0, UDC_EP_NUM);
1501 }
1502 }
1503
1504 /* SETUP starts all control transfers */
1505 if (irq_src & UDC_SETUP) {
1506 union u {
1507 u16 word[4];
1508 struct usb_ctrlrequest r;
1509 } u;
1510 int status = -EINVAL;
1511 struct omap_ep *ep;
1512
1513 /* read the (latest) SETUP message */
1514 do {
1515 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1516 /* two bytes at a time */
1517 u.word[0] = omap_readw(UDC_DATA);
1518 u.word[1] = omap_readw(UDC_DATA);
1519 u.word[2] = omap_readw(UDC_DATA);
1520 u.word[3] = omap_readw(UDC_DATA);
1521 omap_writew(0, UDC_EP_NUM);
1522 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1523
1524#define w_value le16_to_cpu(u.r.wValue)
1525#define w_index le16_to_cpu(u.r.wIndex)
1526#define w_length le16_to_cpu(u.r.wLength)
1527
1528 /* Delegate almost all control requests to the gadget driver,
1529 * except for a handful of ch9 status/feature requests that
1530 * hardware doesn't autodecode _and_ the gadget API hides.
1531 */
1532 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1533 udc->ep0_set_config = 0;
1534 udc->ep0_pending = 1;
1535 ep0->stopped = 0;
1536 ep0->ackwait = 0;
1537 switch (u.r.bRequest) {
1538 case USB_REQ_SET_CONFIGURATION:
1539 /* udc needs to know when ep != 0 is valid */
1540 if (u.r.bRequestType != USB_RECIP_DEVICE)
1541 goto delegate;
1542 if (w_length != 0)
1543 goto do_stall;
1544 udc->ep0_set_config = 1;
1545 udc->ep0_reset_config = (w_value == 0);
1546 VDBG("set config %d\n", w_value);
1547
1548 /* update udc NOW since gadget driver may start
1549 * queueing requests immediately; clear config
1550 * later if it fails the request.
1551 */
1552 if (udc->ep0_reset_config)
1553 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1554 else
1555 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1556 update_otg(udc);
1557 goto delegate;
1558 case USB_REQ_CLEAR_FEATURE:
1559 /* clear endpoint halt */
1560 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1561 goto delegate;
1562 if (w_value != USB_ENDPOINT_HALT
1563 || w_length != 0)
1564 goto do_stall;
1565 ep = &udc->ep[w_index & 0xf];
1566 if (ep != ep0) {
1567 if (w_index & USB_DIR_IN)
1568 ep += 16;
1569 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1570 || !ep->ep.desc)
1571 goto do_stall;
1572 use_ep(ep, 0);
1573 omap_writew(udc->clr_halt, UDC_CTRL);
1574 ep->ackwait = 0;
1575 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1576 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1577 ep->ackwait = 1 + ep->double_buf;
1578 }
1579 /* NOTE: assumes the host behaves sanely,
1580 * only clearing real halts. Else we may
1581 * need to kill pending transfers and then
1582 * restart the queue... very messy for DMA!
1583 */
1584 }
1585 VDBG("%s halt cleared by host\n", ep->name);
1586 goto ep0out_status_stage;
1587 case USB_REQ_SET_FEATURE:
1588 /* set endpoint halt */
1589 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1590 goto delegate;
1591 if (w_value != USB_ENDPOINT_HALT
1592 || w_length != 0)
1593 goto do_stall;
1594 ep = &udc->ep[w_index & 0xf];
1595 if (w_index & USB_DIR_IN)
1596 ep += 16;
1597 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1598 || ep == ep0 || !ep->ep.desc)
1599 goto do_stall;
1600 if (use_dma && ep->has_dma) {
1601 /* this has rude side-effects (aborts) and
1602 * can't really work if DMA-IN is active
1603 */
1604 DBG("%s host set_halt, NYET\n", ep->name);
1605 goto do_stall;
1606 }
1607 use_ep(ep, 0);
1608 /* can't halt if fifo isn't empty... */
1609 omap_writew(UDC_CLR_EP, UDC_CTRL);
1610 omap_writew(UDC_SET_HALT, UDC_CTRL);
1611 VDBG("%s halted by host\n", ep->name);
1612ep0out_status_stage:
1613 status = 0;
1614 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1615 omap_writew(UDC_CLR_EP, UDC_CTRL);
1616 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1617 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1618 udc->ep0_pending = 0;
1619 break;
1620 case USB_REQ_GET_STATUS:
1621 /* USB_ENDPOINT_HALT status? */
1622 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1623 goto intf_status;
1624
1625 /* ep0 never stalls */
1626 if (!(w_index & 0xf))
1627 goto zero_status;
1628
1629 /* only active endpoints count */
1630 ep = &udc->ep[w_index & 0xf];
1631 if (w_index & USB_DIR_IN)
1632 ep += 16;
1633 if (!ep->ep.desc)
1634 goto do_stall;
1635
1636 /* iso never stalls */
1637 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1638 goto zero_status;
1639
1640 /* FIXME don't assume non-halted endpoints!! */
1641 ERR("%s status, can't report\n", ep->ep.name);
1642 goto do_stall;
1643
1644intf_status:
1645 /* return interface status. if we were pedantic,
1646 * we'd detect non-existent interfaces, and stall.
1647 */
1648 if (u.r.bRequestType
1649 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1650 goto delegate;
1651
1652zero_status:
1653 /* return two zero bytes */
1654 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1655 omap_writew(0, UDC_DATA);
1656 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1657 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1658 status = 0;
1659 VDBG("GET_STATUS, interface %d\n", w_index);
1660 /* next, status stage */
1661 break;
1662 default:
1663delegate:
1664 /* activate the ep0out fifo right away */
1665 if (!udc->ep0_in && w_length) {
1666 omap_writew(0, UDC_EP_NUM);
1667 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1668 }
1669
1670 /* gadget drivers see class/vendor specific requests,
1671 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1672 * and more
1673 */
1674 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1675 u.r.bRequestType, u.r.bRequest,
1676 w_value, w_index, w_length);
1677
1678#undef w_value
1679#undef w_index
1680#undef w_length
1681
1682 /* The gadget driver may return an error here,
1683 * causing an immediate protocol stall.
1684 *
1685 * Else it must issue a response, either queueing a
1686 * response buffer for the DATA stage, or halting ep0
1687 * (causing a protocol stall, not a real halt). A
1688 * zero length buffer means no DATA stage.
1689 *
1690 * It's fine to issue that response after the setup()
1691 * call returns, and this IRQ was handled.
1692 */
1693 udc->ep0_setup = 1;
1694 spin_unlock(&udc->lock);
1695 status = udc->driver->setup(&udc->gadget, &u.r);
1696 spin_lock(&udc->lock);
1697 udc->ep0_setup = 0;
1698 }
1699
1700 if (status < 0) {
1701do_stall:
1702 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1703 u.r.bRequestType, u.r.bRequest, status);
1704 if (udc->ep0_set_config) {
1705 if (udc->ep0_reset_config)
1706 WARNING("error resetting config?\n");
1707 else
1708 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1709 }
1710 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1711 udc->ep0_pending = 0;
1712 }
1713 }
1714}
1715
1716/*-------------------------------------------------------------------------*/
1717
1718#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1719
1720static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1721{
1722 u16 devstat, change;
1723
1724 devstat = omap_readw(UDC_DEVSTAT);
1725 change = devstat ^ udc->devstat;
1726 udc->devstat = devstat;
1727
1728 if (change & (UDC_USB_RESET|UDC_ATT)) {
1729 udc_quiesce(udc);
1730
1731 if (change & UDC_ATT) {
1732 /* driver for any external transceiver will
1733 * have called omap_vbus_session() already
1734 */
1735 if (devstat & UDC_ATT) {
1736 udc->gadget.speed = USB_SPEED_FULL;
1737 VDBG("connect\n");
1738 if (IS_ERR_OR_NULL(udc->transceiver))
1739 pullup_enable(udc);
1740 /* if (driver->connect) call it */
1741 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1742 udc->gadget.speed = USB_SPEED_UNKNOWN;
1743 if (IS_ERR_OR_NULL(udc->transceiver))
1744 pullup_disable(udc);
1745 DBG("disconnect, gadget %s\n",
1746 udc->driver->driver.name);
1747 if (udc->driver->disconnect) {
1748 spin_unlock(&udc->lock);
1749 udc->driver->disconnect(&udc->gadget);
1750 spin_lock(&udc->lock);
1751 }
1752 }
1753 change &= ~UDC_ATT;
1754 }
1755
1756 if (change & UDC_USB_RESET) {
1757 if (devstat & UDC_USB_RESET) {
1758 VDBG("RESET=1\n");
1759 } else {
1760 udc->gadget.speed = USB_SPEED_FULL;
1761 INFO("USB reset done, gadget %s\n",
1762 udc->driver->driver.name);
1763 /* ep0 traffic is legal from now on */
1764 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1765 UDC_IRQ_EN);
1766 }
1767 change &= ~UDC_USB_RESET;
1768 }
1769 }
1770 if (change & UDC_SUS) {
1771 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1772 /* FIXME tell isp1301 to suspend/resume (?) */
1773 if (devstat & UDC_SUS) {
1774 VDBG("suspend\n");
1775 update_otg(udc);
1776 /* HNP could be under way already */
1777 if (udc->gadget.speed == USB_SPEED_FULL
1778 && udc->driver->suspend) {
1779 spin_unlock(&udc->lock);
1780 udc->driver->suspend(&udc->gadget);
1781 spin_lock(&udc->lock);
1782 }
1783 if (!IS_ERR_OR_NULL(udc->transceiver))
1784 usb_phy_set_suspend(
1785 udc->transceiver, 1);
1786 } else {
1787 VDBG("resume\n");
1788 if (!IS_ERR_OR_NULL(udc->transceiver))
1789 usb_phy_set_suspend(
1790 udc->transceiver, 0);
1791 if (udc->gadget.speed == USB_SPEED_FULL
1792 && udc->driver->resume) {
1793 spin_unlock(&udc->lock);
1794 udc->driver->resume(&udc->gadget);
1795 spin_lock(&udc->lock);
1796 }
1797 }
1798 }
1799 change &= ~UDC_SUS;
1800 }
1801 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1802 update_otg(udc);
1803 change &= ~OTG_FLAGS;
1804 }
1805
1806 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1807 if (change)
1808 VDBG("devstat %03x, ignore change %03x\n",
1809 devstat, change);
1810
1811 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1812}
1813
1814static irqreturn_t omap_udc_irq(int irq, void *_udc)
1815{
1816 struct omap_udc *udc = _udc;
1817 u16 irq_src;
1818 irqreturn_t status = IRQ_NONE;
1819 unsigned long flags;
1820
1821 spin_lock_irqsave(&udc->lock, flags);
1822 irq_src = omap_readw(UDC_IRQ_SRC);
1823
1824 /* Device state change (usb ch9 stuff) */
1825 if (irq_src & UDC_DS_CHG) {
1826 devstate_irq(_udc, irq_src);
1827 status = IRQ_HANDLED;
1828 irq_src &= ~UDC_DS_CHG;
1829 }
1830
1831 /* EP0 control transfers */
1832 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1833 ep0_irq(_udc, irq_src);
1834 status = IRQ_HANDLED;
1835 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1836 }
1837
1838 /* DMA transfer completion */
1839 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1840 dma_irq(_udc, irq_src);
1841 status = IRQ_HANDLED;
1842 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1843 }
1844
1845 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1846 if (irq_src)
1847 DBG("udc_irq, unhandled %03x\n", irq_src);
1848 spin_unlock_irqrestore(&udc->lock, flags);
1849
1850 return status;
1851}
1852
1853/* workaround for seemingly-lost IRQs for RX ACKs... */
1854#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1855#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1856
1857static void pio_out_timer(struct timer_list *t)
1858{
1859 struct omap_ep *ep = from_timer(ep, t, timer);
1860 unsigned long flags;
1861 u16 stat_flg;
1862
1863 spin_lock_irqsave(&ep->udc->lock, flags);
1864 if (!list_empty(&ep->queue) && ep->ackwait) {
1865 use_ep(ep, UDC_EP_SEL);
1866 stat_flg = omap_readw(UDC_STAT_FLG);
1867
1868 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1869 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1870 struct omap_req *req;
1871
1872 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1873 req = container_of(ep->queue.next,
1874 struct omap_req, queue);
1875 (void) read_fifo(ep, req);
1876 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1877 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1878 ep->ackwait = 1 + ep->double_buf;
1879 } else
1880 deselect_ep();
1881 }
1882 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1883 spin_unlock_irqrestore(&ep->udc->lock, flags);
1884}
1885
1886static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1887{
1888 u16 epn_stat, irq_src;
1889 irqreturn_t status = IRQ_NONE;
1890 struct omap_ep *ep;
1891 int epnum;
1892 struct omap_udc *udc = _dev;
1893 struct omap_req *req;
1894 unsigned long flags;
1895
1896 spin_lock_irqsave(&udc->lock, flags);
1897 epn_stat = omap_readw(UDC_EPN_STAT);
1898 irq_src = omap_readw(UDC_IRQ_SRC);
1899
1900 /* handle OUT first, to avoid some wasteful NAKs */
1901 if (irq_src & UDC_EPN_RX) {
1902 epnum = (epn_stat >> 8) & 0x0f;
1903 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1904 status = IRQ_HANDLED;
1905 ep = &udc->ep[epnum];
1906 ep->irqs++;
1907
1908 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1909 ep->fnf = 0;
1910 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1911 ep->ackwait--;
1912 if (!list_empty(&ep->queue)) {
1913 int stat;
1914 req = container_of(ep->queue.next,
1915 struct omap_req, queue);
1916 stat = read_fifo(ep, req);
1917 if (!ep->double_buf)
1918 ep->fnf = 1;
1919 }
1920 }
1921 /* min 6 clock delay before clearing EP_SEL ... */
1922 epn_stat = omap_readw(UDC_EPN_STAT);
1923 epn_stat = omap_readw(UDC_EPN_STAT);
1924 omap_writew(epnum, UDC_EP_NUM);
1925
1926 /* enabling fifo _after_ clearing ACK, contrary to docs,
1927 * reduces lossage; timer still needed though (sigh).
1928 */
1929 if (ep->fnf) {
1930 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1931 ep->ackwait = 1 + ep->double_buf;
1932 }
1933 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1934 }
1935
1936 /* then IN transfers */
1937 else if (irq_src & UDC_EPN_TX) {
1938 epnum = epn_stat & 0x0f;
1939 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1940 status = IRQ_HANDLED;
1941 ep = &udc->ep[16 + epnum];
1942 ep->irqs++;
1943
1944 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1945 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1946 ep->ackwait = 0;
1947 if (!list_empty(&ep->queue)) {
1948 req = container_of(ep->queue.next,
1949 struct omap_req, queue);
1950 (void) write_fifo(ep, req);
1951 }
1952 }
1953 /* min 6 clock delay before clearing EP_SEL ... */
1954 epn_stat = omap_readw(UDC_EPN_STAT);
1955 epn_stat = omap_readw(UDC_EPN_STAT);
1956 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1957 /* then 6 clocks before it'd tx */
1958 }
1959
1960 spin_unlock_irqrestore(&udc->lock, flags);
1961 return status;
1962}
1963
1964#ifdef USE_ISO
1965static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1966{
1967 struct omap_udc *udc = _dev;
1968 struct omap_ep *ep;
1969 int pending = 0;
1970 unsigned long flags;
1971
1972 spin_lock_irqsave(&udc->lock, flags);
1973
1974 /* handle all non-DMA ISO transfers */
1975 list_for_each_entry(ep, &udc->iso, iso) {
1976 u16 stat;
1977 struct omap_req *req;
1978
1979 if (ep->has_dma || list_empty(&ep->queue))
1980 continue;
1981 req = list_entry(ep->queue.next, struct omap_req, queue);
1982
1983 use_ep(ep, UDC_EP_SEL);
1984 stat = omap_readw(UDC_STAT_FLG);
1985
1986 /* NOTE: like the other controller drivers, this isn't
1987 * currently reporting lost or damaged frames.
1988 */
1989 if (ep->bEndpointAddress & USB_DIR_IN) {
1990 if (stat & UDC_MISS_IN)
1991 /* done(ep, req, -EPROTO) */;
1992 else
1993 write_fifo(ep, req);
1994 } else {
1995 int status = 0;
1996
1997 if (stat & UDC_NO_RXPACKET)
1998 status = -EREMOTEIO;
1999 else if (stat & UDC_ISO_ERR)
2000 status = -EILSEQ;
2001 else if (stat & UDC_DATA_FLUSH)
2002 status = -ENOSR;
2003
2004 if (status)
2005 /* done(ep, req, status) */;
2006 else
2007 read_fifo(ep, req);
2008 }
2009 deselect_ep();
2010 /* 6 wait states before next EP */
2011
2012 ep->irqs++;
2013 if (!list_empty(&ep->queue))
2014 pending = 1;
2015 }
2016 if (!pending) {
2017 u16 w;
2018
2019 w = omap_readw(UDC_IRQ_EN);
2020 w &= ~UDC_SOF_IE;
2021 omap_writew(w, UDC_IRQ_EN);
2022 }
2023 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2024
2025 spin_unlock_irqrestore(&udc->lock, flags);
2026 return IRQ_HANDLED;
2027}
2028#endif
2029
2030/*-------------------------------------------------------------------------*/
2031
2032static inline int machine_without_vbus_sense(void)
2033{
2034 return machine_is_omap_innovator()
2035 || machine_is_omap_osk()
2036 || machine_is_sx1()
2037 /* No known omap7xx boards with vbus sense */
2038 || cpu_is_omap7xx();
2039}
2040
2041static int omap_udc_start(struct usb_gadget *g,
2042 struct usb_gadget_driver *driver)
2043{
2044 int status = -ENODEV;
2045 struct omap_ep *ep;
2046 unsigned long flags;
2047
2048
2049 spin_lock_irqsave(&udc->lock, flags);
2050 /* reset state */
2051 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2052 ep->irqs = 0;
2053 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2054 continue;
2055 use_ep(ep, 0);
2056 omap_writew(UDC_SET_HALT, UDC_CTRL);
2057 }
2058 udc->ep0_pending = 0;
2059 udc->ep[0].irqs = 0;
2060 udc->softconnect = 1;
2061
2062 /* hook up the driver */
2063 driver->driver.bus = NULL;
2064 udc->driver = driver;
2065 spin_unlock_irqrestore(&udc->lock, flags);
2066
2067 if (udc->dc_clk != NULL)
2068 omap_udc_enable_clock(1);
2069
2070 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2071
2072 /* connect to bus through transceiver */
2073 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2074 status = otg_set_peripheral(udc->transceiver->otg,
2075 &udc->gadget);
2076 if (status < 0) {
2077 ERR("can't bind to transceiver\n");
2078 udc->driver = NULL;
2079 goto done;
2080 }
2081 } else {
2082 if (can_pullup(udc))
2083 pullup_enable(udc);
2084 else
2085 pullup_disable(udc);
2086 }
2087
2088 /* boards that don't have VBUS sensing can't autogate 48MHz;
2089 * can't enter deep sleep while a gadget driver is active.
2090 */
2091 if (machine_without_vbus_sense())
2092 omap_vbus_session(&udc->gadget, 1);
2093
2094done:
2095 if (udc->dc_clk != NULL)
2096 omap_udc_enable_clock(0);
2097
2098 return status;
2099}
2100
2101static int omap_udc_stop(struct usb_gadget *g)
2102{
2103 unsigned long flags;
2104 int status = -ENODEV;
2105
2106 if (udc->dc_clk != NULL)
2107 omap_udc_enable_clock(1);
2108
2109 if (machine_without_vbus_sense())
2110 omap_vbus_session(&udc->gadget, 0);
2111
2112 if (!IS_ERR_OR_NULL(udc->transceiver))
2113 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2114 else
2115 pullup_disable(udc);
2116
2117 spin_lock_irqsave(&udc->lock, flags);
2118 udc_quiesce(udc);
2119 spin_unlock_irqrestore(&udc->lock, flags);
2120
2121 udc->driver = NULL;
2122
2123 if (udc->dc_clk != NULL)
2124 omap_udc_enable_clock(0);
2125
2126 return status;
2127}
2128
2129/*-------------------------------------------------------------------------*/
2130
2131#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2132
2133#include <linux/seq_file.h>
2134
2135static const char proc_filename[] = "driver/udc";
2136
2137#define FOURBITS "%s%s%s%s"
2138#define EIGHTBITS "%s%s%s%s%s%s%s%s"
2139
2140static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2141{
2142 u16 stat_flg;
2143 struct omap_req *req;
2144 char buf[20];
2145
2146 use_ep(ep, 0);
2147
2148 if (use_dma && ep->has_dma)
2149 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2150 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2151 ep->dma_channel - 1, ep->lch);
2152 else
2153 buf[0] = 0;
2154
2155 stat_flg = omap_readw(UDC_STAT_FLG);
2156 seq_printf(s,
2157 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2158 ep->name, buf,
2159 ep->double_buf ? "dbuf " : "",
2160 ({ char *s;
2161 switch (ep->ackwait) {
2162 case 0:
2163 s = "";
2164 break;
2165 case 1:
2166 s = "(ackw) ";
2167 break;
2168 case 2:
2169 s = "(ackw2) ";
2170 break;
2171 default:
2172 s = "(?) ";
2173 break;
2174 } s; }),
2175 ep->irqs, stat_flg,
2176 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2177 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2178 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2179 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2180 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2181 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2182 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2183 (stat_flg & UDC_STALL) ? "STALL " : "",
2184 (stat_flg & UDC_NAK) ? "NAK " : "",
2185 (stat_flg & UDC_ACK) ? "ACK " : "",
2186 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2187 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2188 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2189
2190 if (list_empty(&ep->queue))
2191 seq_printf(s, "\t(queue empty)\n");
2192 else
2193 list_for_each_entry(req, &ep->queue, queue) {
2194 unsigned length = req->req.actual;
2195
2196 if (use_dma && buf[0]) {
2197 length += ((ep->bEndpointAddress & USB_DIR_IN)
2198 ? dma_src_len : dma_dest_len)
2199 (ep, req->req.dma + length);
2200 buf[0] = 0;
2201 }
2202 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2203 &req->req, length,
2204 req->req.length, req->req.buf);
2205 }
2206}
2207
2208static char *trx_mode(unsigned m, int enabled)
2209{
2210 switch (m) {
2211 case 0:
2212 return enabled ? "*6wire" : "unused";
2213 case 1:
2214 return "4wire";
2215 case 2:
2216 return "3wire";
2217 case 3:
2218 return "6wire";
2219 default:
2220 return "unknown";
2221 }
2222}
2223
2224static int proc_otg_show(struct seq_file *s)
2225{
2226 u32 tmp;
2227 u32 trans = 0;
2228 char *ctrl_name = "(UNKNOWN)";
2229
2230 tmp = omap_readl(OTG_REV);
2231 ctrl_name = "tranceiver_ctrl";
2232 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2233 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2234 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2235 tmp = omap_readw(OTG_SYSCON_1);
2236 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2237 FOURBITS "\n", tmp,
2238 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2239 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2240 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2241 ? "internal"
2242 : trx_mode(USB0_TRX_MODE(tmp), 1),
2243 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2244 (tmp & HST_IDLE_EN) ? " !host" : "",
2245 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2246 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2247 tmp = omap_readl(OTG_SYSCON_2);
2248 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2249 " b_ase_brst=%d hmc=%d\n", tmp,
2250 (tmp & OTG_EN) ? " otg_en" : "",
2251 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2252 /* much more SRP stuff */
2253 (tmp & SRP_DATA) ? " srp_data" : "",
2254 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2255 (tmp & OTG_PADEN) ? " otg_paden" : "",
2256 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2257 (tmp & UHOST_EN) ? " uhost_en" : "",
2258 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2259 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2260 B_ASE_BRST(tmp),
2261 OTG_HMC(tmp));
2262 tmp = omap_readl(OTG_CTRL);
2263 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2264 (tmp & OTG_ASESSVLD) ? " asess" : "",
2265 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2266 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2267 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2268 (tmp & OTG_ID) ? " id" : "",
2269 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2270 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2271 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2272 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2273 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2274 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2275 (tmp & OTG_PULLDOWN) ? " down" : "",
2276 (tmp & OTG_PULLUP) ? " up" : "",
2277 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2278 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2279 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2280 (tmp & OTG_PU_ID) ? " pu_id" : ""
2281 );
2282 tmp = omap_readw(OTG_IRQ_EN);
2283 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2284 tmp = omap_readw(OTG_IRQ_SRC);
2285 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2286 tmp = omap_readw(OTG_OUTCTRL);
2287 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2288 tmp = omap_readw(OTG_TEST);
2289 seq_printf(s, "otg_test %04x" "\n", tmp);
2290 return 0;
2291}
2292
2293static int proc_udc_show(struct seq_file *s, void *_)
2294{
2295 u32 tmp;
2296 struct omap_ep *ep;
2297 unsigned long flags;
2298
2299 spin_lock_irqsave(&udc->lock, flags);
2300
2301 seq_printf(s, "%s, version: " DRIVER_VERSION
2302#ifdef USE_ISO
2303 " (iso)"
2304#endif
2305 "%s\n",
2306 driver_desc,
2307 use_dma ? " (dma)" : "");
2308
2309 tmp = omap_readw(UDC_REV) & 0xff;
2310 seq_printf(s,
2311 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2312 "hmc %d, transceiver %s\n",
2313 tmp >> 4, tmp & 0xf,
2314 fifo_mode,
2315 udc->driver ? udc->driver->driver.name : "(none)",
2316 HMC,
2317 udc->transceiver
2318 ? udc->transceiver->label
2319 : (cpu_is_omap1710()
2320 ? "external" : "(none)"));
2321 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2322 omap_readw(ULPD_CLOCK_CTRL),
2323 omap_readw(ULPD_SOFT_REQ),
2324 omap_readw(ULPD_STATUS_REQ));
2325
2326 /* OTG controller registers */
2327 if (!cpu_is_omap15xx())
2328 proc_otg_show(s);
2329
2330 tmp = omap_readw(UDC_SYSCON1);
2331 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2332 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2333 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2334 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2335 (tmp & UDC_NAK_EN) ? " nak" : "",
2336 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2337 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2338 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2339 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2340 /* syscon2 is write-only */
2341
2342 /* UDC controller registers */
2343 if (!(tmp & UDC_PULLUP_EN)) {
2344 seq_printf(s, "(suspended)\n");
2345 spin_unlock_irqrestore(&udc->lock, flags);
2346 return 0;
2347 }
2348
2349 tmp = omap_readw(UDC_DEVSTAT);
2350 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2351 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2352 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2353 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2354 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2355 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2356 (tmp & UDC_SUS) ? " SUS" : "",
2357 (tmp & UDC_CFG) ? " CFG" : "",
2358 (tmp & UDC_ADD) ? " ADD" : "",
2359 (tmp & UDC_DEF) ? " DEF" : "",
2360 (tmp & UDC_ATT) ? " ATT" : "");
2361 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2362 tmp = omap_readw(UDC_IRQ_EN);
2363 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2364 (tmp & UDC_SOF_IE) ? " sof" : "",
2365 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2366 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2367 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2368 (tmp & UDC_EP0_IE) ? " ep0" : "");
2369 tmp = omap_readw(UDC_IRQ_SRC);
2370 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2371 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2372 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2373 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2374 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2375 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2376 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2377 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2378 (tmp & UDC_SETUP) ? " setup" : "",
2379 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2380 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2381 if (use_dma) {
2382 unsigned i;
2383
2384 tmp = omap_readw(UDC_DMA_IRQ_EN);
2385 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2386 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2387 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2388 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2389
2390 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2391 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2392 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2393
2394 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2395 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2396 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2397
2398 tmp = omap_readw(UDC_RXDMA_CFG);
2399 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2400 if (tmp) {
2401 for (i = 0; i < 3; i++) {
2402 if ((tmp & (0x0f << (i * 4))) == 0)
2403 continue;
2404 seq_printf(s, "rxdma[%d] %04x\n", i,
2405 omap_readw(UDC_RXDMA(i + 1)));
2406 }
2407 }
2408 tmp = omap_readw(UDC_TXDMA_CFG);
2409 seq_printf(s, "txdma_cfg %04x\n", tmp);
2410 if (tmp) {
2411 for (i = 0; i < 3; i++) {
2412 if (!(tmp & (0x0f << (i * 4))))
2413 continue;
2414 seq_printf(s, "txdma[%d] %04x\n", i,
2415 omap_readw(UDC_TXDMA(i + 1)));
2416 }
2417 }
2418 }
2419
2420 tmp = omap_readw(UDC_DEVSTAT);
2421 if (tmp & UDC_ATT) {
2422 proc_ep_show(s, &udc->ep[0]);
2423 if (tmp & UDC_ADD) {
2424 list_for_each_entry(ep, &udc->gadget.ep_list,
2425 ep.ep_list) {
2426 if (ep->ep.desc)
2427 proc_ep_show(s, ep);
2428 }
2429 }
2430 }
2431 spin_unlock_irqrestore(&udc->lock, flags);
2432 return 0;
2433}
2434
2435static int proc_udc_open(struct inode *inode, struct file *file)
2436{
2437 return single_open(file, proc_udc_show, NULL);
2438}
2439
2440static const struct file_operations proc_ops = {
2441 .owner = THIS_MODULE,
2442 .open = proc_udc_open,
2443 .read = seq_read,
2444 .llseek = seq_lseek,
2445 .release = single_release,
2446};
2447
2448static void create_proc_file(void)
2449{
2450 proc_create(proc_filename, 0, NULL, &proc_ops);
2451}
2452
2453static void remove_proc_file(void)
2454{
2455 remove_proc_entry(proc_filename, NULL);
2456}
2457
2458#else
2459
2460static inline void create_proc_file(void) {}
2461static inline void remove_proc_file(void) {}
2462
2463#endif
2464
2465/*-------------------------------------------------------------------------*/
2466
2467/* Before this controller can enumerate, we need to pick an endpoint
2468 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2469 * buffer space among the endpoints we'll be operating.
2470 *
2471 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2472 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2473 * capability yet though.
2474 */
2475static unsigned
2476omap_ep_setup(char *name, u8 addr, u8 type,
2477 unsigned buf, unsigned maxp, int dbuf)
2478{
2479 struct omap_ep *ep;
2480 u16 epn_rxtx = 0;
2481
2482 /* OUT endpoints first, then IN */
2483 ep = &udc->ep[addr & 0xf];
2484 if (addr & USB_DIR_IN)
2485 ep += 16;
2486
2487 /* in case of ep init table bugs */
2488 BUG_ON(ep->name[0]);
2489
2490 /* chip setup ... bit values are same for IN, OUT */
2491 if (type == USB_ENDPOINT_XFER_ISOC) {
2492 switch (maxp) {
2493 case 8:
2494 epn_rxtx = 0 << 12;
2495 break;
2496 case 16:
2497 epn_rxtx = 1 << 12;
2498 break;
2499 case 32:
2500 epn_rxtx = 2 << 12;
2501 break;
2502 case 64:
2503 epn_rxtx = 3 << 12;
2504 break;
2505 case 128:
2506 epn_rxtx = 4 << 12;
2507 break;
2508 case 256:
2509 epn_rxtx = 5 << 12;
2510 break;
2511 case 512:
2512 epn_rxtx = 6 << 12;
2513 break;
2514 default:
2515 BUG();
2516 }
2517 epn_rxtx |= UDC_EPN_RX_ISO;
2518 dbuf = 1;
2519 } else {
2520 /* double-buffering "not supported" on 15xx,
2521 * and ignored for PIO-IN on newer chips
2522 * (for more reliable behavior)
2523 */
2524 if (!use_dma || cpu_is_omap15xx())
2525 dbuf = 0;
2526
2527 switch (maxp) {
2528 case 8:
2529 epn_rxtx = 0 << 12;
2530 break;
2531 case 16:
2532 epn_rxtx = 1 << 12;
2533 break;
2534 case 32:
2535 epn_rxtx = 2 << 12;
2536 break;
2537 case 64:
2538 epn_rxtx = 3 << 12;
2539 break;
2540 default:
2541 BUG();
2542 }
2543 if (dbuf && addr)
2544 epn_rxtx |= UDC_EPN_RX_DB;
2545 timer_setup(&ep->timer, pio_out_timer, 0);
2546 }
2547 if (addr)
2548 epn_rxtx |= UDC_EPN_RX_VALID;
2549 BUG_ON(buf & 0x07);
2550 epn_rxtx |= buf >> 3;
2551
2552 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2553 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2554
2555 if (addr & USB_DIR_IN)
2556 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2557 else
2558 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2559
2560 /* next endpoint's buffer starts after this one's */
2561 buf += maxp;
2562 if (dbuf)
2563 buf += maxp;
2564 BUG_ON(buf > 2048);
2565
2566 /* set up driver data structures */
2567 BUG_ON(strlen(name) >= sizeof ep->name);
2568 strlcpy(ep->name, name, sizeof ep->name);
2569 INIT_LIST_HEAD(&ep->queue);
2570 INIT_LIST_HEAD(&ep->iso);
2571 ep->bEndpointAddress = addr;
2572 ep->bmAttributes = type;
2573 ep->double_buf = dbuf;
2574 ep->udc = udc;
2575
2576 switch (type) {
2577 case USB_ENDPOINT_XFER_CONTROL:
2578 ep->ep.caps.type_control = true;
2579 ep->ep.caps.dir_in = true;
2580 ep->ep.caps.dir_out = true;
2581 break;
2582 case USB_ENDPOINT_XFER_ISOC:
2583 ep->ep.caps.type_iso = true;
2584 break;
2585 case USB_ENDPOINT_XFER_BULK:
2586 ep->ep.caps.type_bulk = true;
2587 break;
2588 case USB_ENDPOINT_XFER_INT:
2589 ep->ep.caps.type_int = true;
2590 break;
2591 };
2592
2593 if (addr & USB_DIR_IN)
2594 ep->ep.caps.dir_in = true;
2595 else
2596 ep->ep.caps.dir_out = true;
2597
2598 ep->ep.name = ep->name;
2599 ep->ep.ops = &omap_ep_ops;
2600 ep->maxpacket = maxp;
2601 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2602 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2603
2604 return buf;
2605}
2606
2607static void omap_udc_release(struct device *dev)
2608{
2609 complete(udc->done);
2610 kfree(udc);
2611 udc = NULL;
2612}
2613
2614static int
2615omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2616{
2617 unsigned tmp, buf;
2618
2619 /* abolish any previous hardware state */
2620 omap_writew(0, UDC_SYSCON1);
2621 omap_writew(0, UDC_IRQ_EN);
2622 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2623 omap_writew(0, UDC_DMA_IRQ_EN);
2624 omap_writew(0, UDC_RXDMA_CFG);
2625 omap_writew(0, UDC_TXDMA_CFG);
2626
2627 /* UDC_PULLUP_EN gates the chip clock */
2628 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2629
2630 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2631 if (!udc)
2632 return -ENOMEM;
2633
2634 spin_lock_init(&udc->lock);
2635
2636 udc->gadget.ops = &omap_gadget_ops;
2637 udc->gadget.ep0 = &udc->ep[0].ep;
2638 INIT_LIST_HEAD(&udc->gadget.ep_list);
2639 INIT_LIST_HEAD(&udc->iso);
2640 udc->gadget.speed = USB_SPEED_UNKNOWN;
2641 udc->gadget.max_speed = USB_SPEED_FULL;
2642 udc->gadget.name = driver_name;
2643 udc->transceiver = xceiv;
2644
2645 /* ep0 is special; put it right after the SETUP buffer */
2646 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2647 8 /* after SETUP */, 64 /* maxpacket */, 0);
2648 list_del_init(&udc->ep[0].ep.ep_list);
2649
2650 /* initially disable all non-ep0 endpoints */
2651 for (tmp = 1; tmp < 15; tmp++) {
2652 omap_writew(0, UDC_EP_RX(tmp));
2653 omap_writew(0, UDC_EP_TX(tmp));
2654 }
2655
2656#define OMAP_BULK_EP(name, addr) \
2657 buf = omap_ep_setup(name "-bulk", addr, \
2658 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2659#define OMAP_INT_EP(name, addr, maxp) \
2660 buf = omap_ep_setup(name "-int", addr, \
2661 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2662#define OMAP_ISO_EP(name, addr, maxp) \
2663 buf = omap_ep_setup(name "-iso", addr, \
2664 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2665
2666 switch (fifo_mode) {
2667 case 0:
2668 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2669 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2670 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2671 break;
2672 case 1:
2673 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2674 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2675 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2676
2677 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2678 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2679 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2680
2681 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2682 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2683 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2684
2685 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2686 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2687 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2688
2689 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2690 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2691 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2692 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2693
2694 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2695 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2696 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2697 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2698
2699 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2700 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2701
2702 break;
2703
2704#ifdef USE_ISO
2705 case 2: /* mixed iso/bulk */
2706 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2707 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2708 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2709 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2710
2711 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2712
2713 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2714 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2715 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2716 break;
2717 case 3: /* mixed bulk/iso */
2718 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2719 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2720 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2721
2722 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2723 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2724 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2725
2726 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2727 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2728 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2729 break;
2730#endif
2731
2732 /* add more modes as needed */
2733
2734 default:
2735 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2736 return -ENODEV;
2737 }
2738 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2739 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2740 return 0;
2741}
2742
2743static int omap_udc_probe(struct platform_device *pdev)
2744{
2745 int status = -ENODEV;
2746 int hmc;
2747 struct usb_phy *xceiv = NULL;
2748 const char *type = NULL;
2749 struct omap_usb_config *config = dev_get_platdata(&pdev->dev);
2750 struct clk *dc_clk = NULL;
2751 struct clk *hhc_clk = NULL;
2752
2753 if (cpu_is_omap7xx())
2754 use_dma = 0;
2755
2756 /* NOTE: "knows" the order of the resources! */
2757 if (!request_mem_region(pdev->resource[0].start,
2758 pdev->resource[0].end - pdev->resource[0].start + 1,
2759 driver_name)) {
2760 DBG("request_mem_region failed\n");
2761 return -EBUSY;
2762 }
2763
2764 if (cpu_is_omap16xx()) {
2765 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2766 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2767 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2768 /* can't use omap_udc_enable_clock yet */
2769 clk_enable(dc_clk);
2770 clk_enable(hhc_clk);
2771 udelay(100);
2772 }
2773
2774 if (cpu_is_omap7xx()) {
2775 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2776 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2777 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2778 /* can't use omap_udc_enable_clock yet */
2779 clk_enable(dc_clk);
2780 clk_enable(hhc_clk);
2781 udelay(100);
2782 }
2783
2784 INFO("OMAP UDC rev %d.%d%s\n",
2785 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2786 config->otg ? ", Mini-AB" : "");
2787
2788 /* use the mode given to us by board init code */
2789 if (cpu_is_omap15xx()) {
2790 hmc = HMC_1510;
2791 type = "(unknown)";
2792
2793 if (machine_without_vbus_sense()) {
2794 /* just set up software VBUS detect, and then
2795 * later rig it so we always report VBUS.
2796 * FIXME without really sensing VBUS, we can't
2797 * know when to turn PULLUP_EN on/off; and that
2798 * means we always "need" the 48MHz clock.
2799 */
2800 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2801 tmp &= ~VBUS_CTRL_1510;
2802 omap_writel(tmp, FUNC_MUX_CTRL_0);
2803 tmp |= VBUS_MODE_1510;
2804 tmp &= ~VBUS_CTRL_1510;
2805 omap_writel(tmp, FUNC_MUX_CTRL_0);
2806 }
2807 } else {
2808 /* The transceiver may package some GPIO logic or handle
2809 * loopback and/or transceiverless setup; if we find one,
2810 * use it. Except for OTG, we don't _need_ to talk to one;
2811 * but not having one probably means no VBUS detection.
2812 */
2813 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2814 if (!IS_ERR_OR_NULL(xceiv))
2815 type = xceiv->label;
2816 else if (config->otg) {
2817 DBG("OTG requires external transceiver!\n");
2818 goto cleanup0;
2819 }
2820
2821 hmc = HMC_1610;
2822
2823 switch (hmc) {
2824 case 0: /* POWERUP DEFAULT == 0 */
2825 case 4:
2826 case 12:
2827 case 20:
2828 if (!cpu_is_omap1710()) {
2829 type = "integrated";
2830 break;
2831 }
2832 /* FALL THROUGH */
2833 case 3:
2834 case 11:
2835 case 16:
2836 case 19:
2837 case 25:
2838 if (IS_ERR_OR_NULL(xceiv)) {
2839 DBG("external transceiver not registered!\n");
2840 type = "unknown";
2841 }
2842 break;
2843 case 21: /* internal loopback */
2844 type = "loopback";
2845 break;
2846 case 14: /* transceiverless */
2847 if (cpu_is_omap1710())
2848 goto bad_on_1710;
2849 /* FALL THROUGH */
2850 case 13:
2851 case 15:
2852 type = "no";
2853 break;
2854
2855 default:
2856bad_on_1710:
2857 ERR("unrecognized UDC HMC mode %d\n", hmc);
2858 goto cleanup0;
2859 }
2860 }
2861
2862 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2863
2864 /* a "gadget" abstracts/virtualizes the controller */
2865 status = omap_udc_setup(pdev, xceiv);
2866 if (status)
2867 goto cleanup0;
2868
2869 xceiv = NULL;
2870 /* "udc" is now valid */
2871 pullup_disable(udc);
2872#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
2873 udc->gadget.is_otg = (config->otg != 0);
2874#endif
2875
2876 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2877 if (omap_readw(UDC_REV) >= 0x61)
2878 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2879 else
2880 udc->clr_halt = UDC_RESET_EP;
2881
2882 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2883 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2884 0, driver_name, udc);
2885 if (status != 0) {
2886 ERR("can't get irq %d, err %d\n",
2887 (int) pdev->resource[1].start, status);
2888 goto cleanup1;
2889 }
2890
2891 /* USB "non-iso" IRQ (PIO for all but ep0) */
2892 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2893 0, "omap_udc pio", udc);
2894 if (status != 0) {
2895 ERR("can't get irq %d, err %d\n",
2896 (int) pdev->resource[2].start, status);
2897 goto cleanup2;
2898 }
2899#ifdef USE_ISO
2900 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2901 0, "omap_udc iso", udc);
2902 if (status != 0) {
2903 ERR("can't get irq %d, err %d\n",
2904 (int) pdev->resource[3].start, status);
2905 goto cleanup3;
2906 }
2907#endif
2908 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2909 udc->dc_clk = dc_clk;
2910 udc->hhc_clk = hhc_clk;
2911 clk_disable(hhc_clk);
2912 clk_disable(dc_clk);
2913 }
2914
2915 create_proc_file();
2916 status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2917 omap_udc_release);
2918 if (status)
2919 goto cleanup4;
2920
2921 return 0;
2922
2923cleanup4:
2924 remove_proc_file();
2925
2926#ifdef USE_ISO
2927cleanup3:
2928 free_irq(pdev->resource[2].start, udc);
2929#endif
2930
2931cleanup2:
2932 free_irq(pdev->resource[1].start, udc);
2933
2934cleanup1:
2935 kfree(udc);
2936 udc = NULL;
2937
2938cleanup0:
2939 if (!IS_ERR_OR_NULL(xceiv))
2940 usb_put_phy(xceiv);
2941
2942 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2943 clk_disable(hhc_clk);
2944 clk_disable(dc_clk);
2945 clk_put(hhc_clk);
2946 clk_put(dc_clk);
2947 }
2948
2949 release_mem_region(pdev->resource[0].start,
2950 pdev->resource[0].end - pdev->resource[0].start + 1);
2951
2952 return status;
2953}
2954
2955static int omap_udc_remove(struct platform_device *pdev)
2956{
2957 DECLARE_COMPLETION_ONSTACK(done);
2958
2959 if (!udc)
2960 return -ENODEV;
2961
2962 usb_del_gadget_udc(&udc->gadget);
2963 if (udc->driver)
2964 return -EBUSY;
2965
2966 udc->done = &done;
2967
2968 pullup_disable(udc);
2969 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2970 usb_put_phy(udc->transceiver);
2971 udc->transceiver = NULL;
2972 }
2973 omap_writew(0, UDC_SYSCON1);
2974
2975 remove_proc_file();
2976
2977#ifdef USE_ISO
2978 free_irq(pdev->resource[3].start, udc);
2979#endif
2980 free_irq(pdev->resource[2].start, udc);
2981 free_irq(pdev->resource[1].start, udc);
2982
2983 if (udc->dc_clk) {
2984 if (udc->clk_requested)
2985 omap_udc_enable_clock(0);
2986 clk_put(udc->hhc_clk);
2987 clk_put(udc->dc_clk);
2988 }
2989
2990 release_mem_region(pdev->resource[0].start,
2991 pdev->resource[0].end - pdev->resource[0].start + 1);
2992
2993 wait_for_completion(&done);
2994
2995 return 0;
2996}
2997
2998/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2999 * system is forced into deep sleep
3000 *
3001 * REVISIT we should probably reject suspend requests when there's a host
3002 * session active, rather than disconnecting, at least on boards that can
3003 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3004 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3005 * may involve talking to an external transceiver (e.g. isp1301).
3006 */
3007
3008static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3009{
3010 u32 devstat;
3011
3012 devstat = omap_readw(UDC_DEVSTAT);
3013
3014 /* we're requesting 48 MHz clock if the pullup is enabled
3015 * (== we're attached to the host) and we're not suspended,
3016 * which would prevent entry to deep sleep...
3017 */
3018 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3019 WARNING("session active; suspend requires disconnect\n");
3020 omap_pullup(&udc->gadget, 0);
3021 }
3022
3023 return 0;
3024}
3025
3026static int omap_udc_resume(struct platform_device *dev)
3027{
3028 DBG("resume + wakeup/SRP\n");
3029 omap_pullup(&udc->gadget, 1);
3030
3031 /* maybe the host would enumerate us if we nudged it */
3032 msleep(100);
3033 return omap_wakeup(&udc->gadget);
3034}
3035
3036/*-------------------------------------------------------------------------*/
3037
3038static struct platform_driver udc_driver = {
3039 .probe = omap_udc_probe,
3040 .remove = omap_udc_remove,
3041 .suspend = omap_udc_suspend,
3042 .resume = omap_udc_resume,
3043 .driver = {
3044 .name = (char *) driver_name,
3045 },
3046};
3047
3048module_platform_driver(udc_driver);
3049
3050MODULE_DESCRIPTION(DRIVER_DESC);
3051MODULE_LICENSE("GPL");
3052MODULE_ALIAS("platform:omap_udc");