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1/*
2 * Dallas DS1302 RTC Support
3 *
4 * Copyright (C) 2002 David McCullough
5 * Copyright (C) 2003 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License version 2. See the file "COPYING" in the main directory of
9 * this archive for more details.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/rtc.h>
17#include <linux/io.h>
18#include <linux/bcd.h>
19
20#define DRV_NAME "rtc-ds1302"
21#define DRV_VERSION "0.1.1"
22
23#define RTC_CMD_READ 0x81 /* Read command */
24#define RTC_CMD_WRITE 0x80 /* Write command */
25
26#define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
27#define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
28
29#define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
30#define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
31#define RTC_ADDR_CTRL 0x07 /* Address of control register */
32#define RTC_ADDR_YEAR 0x06 /* Address of year register */
33#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
34#define RTC_ADDR_MON 0x04 /* Address of month register */
35#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
36#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
37#define RTC_ADDR_MIN 0x01 /* Address of minute register */
38#define RTC_ADDR_SEC 0x00 /* Address of second register */
39
40#ifdef CONFIG_SH_SECUREEDGE5410
41#include <asm/rtc.h>
42#include <mach/secureedge5410.h>
43
44#define RTC_RESET 0x1000
45#define RTC_IODATA 0x0800
46#define RTC_SCLK 0x0400
47
48#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
49#define get_dp() SECUREEDGE_READ_IOPORT()
50#define ds1302_set_tx()
51#define ds1302_set_rx()
52
53static inline int ds1302_hw_init(void)
54{
55 return 0;
56}
57
58static inline void ds1302_reset(void)
59{
60 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
61}
62
63static inline void ds1302_clock(void)
64{
65 set_dp(get_dp() | RTC_SCLK); /* clock high */
66 set_dp(get_dp() & ~RTC_SCLK); /* clock low */
67}
68
69static inline void ds1302_start(void)
70{
71 set_dp(get_dp() | RTC_RESET);
72}
73
74static inline void ds1302_stop(void)
75{
76 set_dp(get_dp() & ~RTC_RESET);
77}
78
79static inline void ds1302_txbit(int bit)
80{
81 set_dp((get_dp() & ~RTC_IODATA) | (bit ? RTC_IODATA : 0));
82}
83
84static inline int ds1302_rxbit(void)
85{
86 return !!(get_dp() & RTC_IODATA);
87}
88
89#else
90#error "Add support for your platform"
91#endif
92
93static void ds1302_sendbits(unsigned int val)
94{
95 int i;
96
97 ds1302_set_tx();
98
99 for (i = 8; (i); i--, val >>= 1) {
100 ds1302_txbit(val & 0x1);
101 ds1302_clock();
102 }
103}
104
105static unsigned int ds1302_recvbits(void)
106{
107 unsigned int val;
108 int i;
109
110 ds1302_set_rx();
111
112 for (i = 0, val = 0; (i < 8); i++) {
113 val |= (ds1302_rxbit() << i);
114 ds1302_clock();
115 }
116
117 return val;
118}
119
120static unsigned int ds1302_readbyte(unsigned int addr)
121{
122 unsigned int val;
123
124 ds1302_reset();
125
126 ds1302_start();
127 ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
128 val = ds1302_recvbits();
129 ds1302_stop();
130
131 return val;
132}
133
134static void ds1302_writebyte(unsigned int addr, unsigned int val)
135{
136 ds1302_reset();
137
138 ds1302_start();
139 ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
140 ds1302_sendbits(val);
141 ds1302_stop();
142}
143
144static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
145{
146 tm->tm_sec = bcd2bin(ds1302_readbyte(RTC_ADDR_SEC));
147 tm->tm_min = bcd2bin(ds1302_readbyte(RTC_ADDR_MIN));
148 tm->tm_hour = bcd2bin(ds1302_readbyte(RTC_ADDR_HOUR));
149 tm->tm_wday = bcd2bin(ds1302_readbyte(RTC_ADDR_DAY));
150 tm->tm_mday = bcd2bin(ds1302_readbyte(RTC_ADDR_DATE));
151 tm->tm_mon = bcd2bin(ds1302_readbyte(RTC_ADDR_MON)) - 1;
152 tm->tm_year = bcd2bin(ds1302_readbyte(RTC_ADDR_YEAR));
153
154 if (tm->tm_year < 70)
155 tm->tm_year += 100;
156
157 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
158 "mday=%d, mon=%d, year=%d, wday=%d\n",
159 __func__,
160 tm->tm_sec, tm->tm_min, tm->tm_hour,
161 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
162
163 return rtc_valid_tm(tm);
164}
165
166static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *tm)
167{
168 ds1302_writebyte(RTC_ADDR_CTRL, RTC_CMD_WRITE_ENABLE);
169 /* Stop RTC */
170 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80);
171
172 ds1302_writebyte(RTC_ADDR_SEC, bin2bcd(tm->tm_sec));
173 ds1302_writebyte(RTC_ADDR_MIN, bin2bcd(tm->tm_min));
174 ds1302_writebyte(RTC_ADDR_HOUR, bin2bcd(tm->tm_hour));
175 ds1302_writebyte(RTC_ADDR_DAY, bin2bcd(tm->tm_wday));
176 ds1302_writebyte(RTC_ADDR_DATE, bin2bcd(tm->tm_mday));
177 ds1302_writebyte(RTC_ADDR_MON, bin2bcd(tm->tm_mon + 1));
178 ds1302_writebyte(RTC_ADDR_YEAR, bin2bcd(tm->tm_year % 100));
179
180 /* Start RTC */
181 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80);
182
183 ds1302_writebyte(RTC_ADDR_CTRL, RTC_CMD_WRITE_DISABLE);
184
185 return 0;
186}
187
188static int ds1302_rtc_ioctl(struct device *dev, unsigned int cmd,
189 unsigned long arg)
190{
191 switch (cmd) {
192#ifdef RTC_SET_CHARGE
193 case RTC_SET_CHARGE:
194 {
195 int tcs_val;
196
197 if (copy_from_user(&tcs_val, (int __user *)arg, sizeof(int)))
198 return -EFAULT;
199
200 ds1302_writebyte(RTC_ADDR_TCR, (0xa0 | tcs_val * 0xf));
201 return 0;
202 }
203#endif
204 }
205
206 return -ENOIOCTLCMD;
207}
208
209static struct rtc_class_ops ds1302_rtc_ops = {
210 .read_time = ds1302_rtc_read_time,
211 .set_time = ds1302_rtc_set_time,
212 .ioctl = ds1302_rtc_ioctl,
213};
214
215static int __init ds1302_rtc_probe(struct platform_device *pdev)
216{
217 struct rtc_device *rtc;
218
219 if (ds1302_hw_init()) {
220 dev_err(&pdev->dev, "Failed to init communication channel");
221 return -EINVAL;
222 }
223
224 /* Reset */
225 ds1302_reset();
226
227 /* Write a magic value to the DS1302 RAM, and see if it sticks. */
228 ds1302_writebyte(RTC_ADDR_RAM0, 0x42);
229 if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42) {
230 dev_err(&pdev->dev, "Failed to probe");
231 return -ENODEV;
232 }
233
234 rtc = devm_rtc_device_register(&pdev->dev, "ds1302",
235 &ds1302_rtc_ops, THIS_MODULE);
236 if (IS_ERR(rtc))
237 return PTR_ERR(rtc);
238
239 platform_set_drvdata(pdev, rtc);
240
241 return 0;
242}
243
244static struct platform_driver ds1302_platform_driver = {
245 .driver = {
246 .name = DRV_NAME,
247 },
248};
249
250module_platform_driver_probe(ds1302_platform_driver, ds1302_rtc_probe);
251
252MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
253MODULE_VERSION(DRV_VERSION);
254MODULE_AUTHOR("Paul Mundt, David McCullough");
255MODULE_LICENSE("GPL v2");
1/*
2 * Dallas DS1302 RTC Support
3 *
4 * Copyright (C) 2002 David McCullough
5 * Copyright (C) 2003 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License version 2. See the file "COPYING" in the main directory of
9 * this archive for more details.
10 */
11
12#include <linux/bcd.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/rtc.h>
19#include <linux/spi/spi.h>
20
21#define DRV_NAME "rtc-ds1302"
22
23#define RTC_CMD_READ 0x81 /* Read command */
24#define RTC_CMD_WRITE 0x80 /* Write command */
25
26#define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
27#define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
28
29#define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
30#define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
31#define RTC_CLCK_BURST 0x1F /* Address of clock burst */
32#define RTC_CLCK_LEN 0x08 /* Size of clock burst */
33#define RTC_ADDR_CTRL 0x07 /* Address of control register */
34#define RTC_ADDR_YEAR 0x06 /* Address of year register */
35#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
36#define RTC_ADDR_MON 0x04 /* Address of month register */
37#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
38#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
39#define RTC_ADDR_MIN 0x01 /* Address of minute register */
40#define RTC_ADDR_SEC 0x00 /* Address of second register */
41
42static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
43{
44 struct spi_device *spi = dev_get_drvdata(dev);
45 u8 buf[1 + RTC_CLCK_LEN];
46 u8 *bp;
47 int status;
48
49 /* Enable writing */
50 bp = buf;
51 *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
52 *bp++ = RTC_CMD_WRITE_ENABLE;
53
54 status = spi_write_then_read(spi, buf, 2,
55 NULL, 0);
56 if (status)
57 return status;
58
59 /* Write registers starting at the first time/date address. */
60 bp = buf;
61 *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
62
63 *bp++ = bin2bcd(time->tm_sec);
64 *bp++ = bin2bcd(time->tm_min);
65 *bp++ = bin2bcd(time->tm_hour);
66 *bp++ = bin2bcd(time->tm_mday);
67 *bp++ = bin2bcd(time->tm_mon + 1);
68 *bp++ = time->tm_wday + 1;
69 *bp++ = bin2bcd(time->tm_year % 100);
70 *bp++ = RTC_CMD_WRITE_DISABLE;
71
72 /* use write-then-read since dma from stack is nonportable */
73 return spi_write_then_read(spi, buf, sizeof(buf),
74 NULL, 0);
75}
76
77static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
78{
79 struct spi_device *spi = dev_get_drvdata(dev);
80 u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
81 u8 buf[RTC_CLCK_LEN - 1];
82 int status;
83
84 /* Use write-then-read to get all the date/time registers
85 * since dma from stack is nonportable
86 */
87 status = spi_write_then_read(spi, &addr, sizeof(addr),
88 buf, sizeof(buf));
89 if (status < 0)
90 return status;
91
92 /* Decode the registers */
93 time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
94 time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
95 time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
96 time->tm_wday = buf[RTC_ADDR_DAY] - 1;
97 time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
98 time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
99 time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
100
101 return 0;
102}
103
104static const struct rtc_class_ops ds1302_rtc_ops = {
105 .read_time = ds1302_rtc_get_time,
106 .set_time = ds1302_rtc_set_time,
107};
108
109static int ds1302_probe(struct spi_device *spi)
110{
111 struct rtc_device *rtc;
112 u8 addr;
113 u8 buf[4];
114 u8 *bp;
115 int status;
116
117 /* Sanity check board setup data. This may be hooked up
118 * in 3wire mode, but we don't care. Note that unless
119 * there's an inverter in place, this needs SPI_CS_HIGH!
120 */
121 if (spi->bits_per_word && (spi->bits_per_word != 8)) {
122 dev_err(&spi->dev, "bad word length\n");
123 return -EINVAL;
124 } else if (spi->max_speed_hz > 2000000) {
125 dev_err(&spi->dev, "speed is too high\n");
126 return -EINVAL;
127 } else if (spi->mode & SPI_CPHA) {
128 dev_err(&spi->dev, "bad mode\n");
129 return -EINVAL;
130 }
131
132 addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
133 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
134 if (status < 0) {
135 dev_err(&spi->dev, "control register read error %d\n",
136 status);
137 return status;
138 }
139
140 if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
141 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
142 if (status < 0) {
143 dev_err(&spi->dev, "control register read error %d\n",
144 status);
145 return status;
146 }
147
148 if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
149 dev_err(&spi->dev, "junk in control register\n");
150 return -ENODEV;
151 }
152 }
153 if (buf[0] == 0) {
154 bp = buf;
155 *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
156 *bp++ = RTC_CMD_WRITE_DISABLE;
157
158 status = spi_write_then_read(spi, buf, 2, NULL, 0);
159 if (status < 0) {
160 dev_err(&spi->dev, "control register write error %d\n",
161 status);
162 return status;
163 }
164
165 addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
166 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
167 if (status < 0) {
168 dev_err(&spi->dev,
169 "error %d reading control register\n",
170 status);
171 return status;
172 }
173
174 if (buf[0] != RTC_CMD_WRITE_DISABLE) {
175 dev_err(&spi->dev, "failed to detect chip\n");
176 return -ENODEV;
177 }
178 }
179
180 spi_set_drvdata(spi, spi);
181
182 rtc = devm_rtc_device_register(&spi->dev, "ds1302",
183 &ds1302_rtc_ops, THIS_MODULE);
184 if (IS_ERR(rtc)) {
185 status = PTR_ERR(rtc);
186 dev_err(&spi->dev, "error %d registering rtc\n", status);
187 return status;
188 }
189
190 return 0;
191}
192
193static int ds1302_remove(struct spi_device *spi)
194{
195 spi_set_drvdata(spi, NULL);
196 return 0;
197}
198
199#ifdef CONFIG_OF
200static const struct of_device_id ds1302_dt_ids[] = {
201 { .compatible = "maxim,ds1302", },
202 { /* sentinel */ }
203};
204MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
205#endif
206
207static struct spi_driver ds1302_driver = {
208 .driver.name = "rtc-ds1302",
209 .driver.of_match_table = of_match_ptr(ds1302_dt_ids),
210 .probe = ds1302_probe,
211 .remove = ds1302_remove,
212};
213
214module_spi_driver(ds1302_driver);
215
216MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
217MODULE_AUTHOR("Paul Mundt, David McCullough");
218MODULE_LICENSE("GPL v2");