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1/*
2 * Intel Atom SOC Power Management Controller Driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/debugfs.h>
19#include <linux/device.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/platform_data/x86/clk-pmc-atom.h>
23#include <linux/platform_data/x86/pmc_atom.h>
24#include <linux/platform_device.h>
25#include <linux/pci.h>
26#include <linux/seq_file.h>
27
28struct pmc_bit_map {
29 const char *name;
30 u32 bit_mask;
31};
32
33struct pmc_reg_map {
34 const struct pmc_bit_map *d3_sts_0;
35 const struct pmc_bit_map *d3_sts_1;
36 const struct pmc_bit_map *func_dis;
37 const struct pmc_bit_map *func_dis_2;
38 const struct pmc_bit_map *pss;
39};
40
41struct pmc_data {
42 const struct pmc_reg_map *map;
43 const struct pmc_clk *clks;
44};
45
46struct pmc_dev {
47 u32 base_addr;
48 void __iomem *regmap;
49 const struct pmc_reg_map *map;
50#ifdef CONFIG_DEBUG_FS
51 struct dentry *dbgfs_dir;
52#endif /* CONFIG_DEBUG_FS */
53 bool init;
54};
55
56static struct pmc_dev pmc_device;
57static u32 acpi_base_addr;
58
59static const struct pmc_clk byt_clks[] = {
60 {
61 .name = "xtal",
62 .freq = 25000000,
63 .parent_name = NULL,
64 },
65 {
66 .name = "pll",
67 .freq = 19200000,
68 .parent_name = "xtal",
69 },
70 {},
71};
72
73static const struct pmc_clk cht_clks[] = {
74 {
75 .name = "xtal",
76 .freq = 19200000,
77 .parent_name = NULL,
78 },
79 {},
80};
81
82static const struct pmc_bit_map d3_sts_0_map[] = {
83 {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
84 {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
85 {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
86 {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
87 {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
88 {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
89 {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
90 {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
91 {"SCC_EMMC", BIT_SCC_EMMC},
92 {"SCC_SDIO", BIT_SCC_SDIO},
93 {"SCC_SDCARD", BIT_SCC_SDCARD},
94 {"SCC_MIPI", BIT_SCC_MIPI},
95 {"HDA", BIT_HDA},
96 {"LPE", BIT_LPE},
97 {"OTG", BIT_OTG},
98 {"USH", BIT_USH},
99 {"GBE", BIT_GBE},
100 {"SATA", BIT_SATA},
101 {"USB_EHCI", BIT_USB_EHCI},
102 {"SEC", BIT_SEC},
103 {"PCIE_PORT0", BIT_PCIE_PORT0},
104 {"PCIE_PORT1", BIT_PCIE_PORT1},
105 {"PCIE_PORT2", BIT_PCIE_PORT2},
106 {"PCIE_PORT3", BIT_PCIE_PORT3},
107 {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
108 {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
109 {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
110 {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
111 {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
112 {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
113 {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
114 {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
115 {},
116};
117
118static struct pmc_bit_map byt_d3_sts_1_map[] = {
119 {"SMB", BIT_SMB},
120 {"OTG_SS_PHY", BIT_OTG_SS_PHY},
121 {"USH_SS_PHY", BIT_USH_SS_PHY},
122 {"DFX", BIT_DFX},
123 {},
124};
125
126static struct pmc_bit_map cht_d3_sts_1_map[] = {
127 {"SMB", BIT_SMB},
128 {"GMM", BIT_STS_GMM},
129 {"ISH", BIT_STS_ISH},
130 {},
131};
132
133static struct pmc_bit_map cht_func_dis_2_map[] = {
134 {"SMB", BIT_SMB},
135 {"GMM", BIT_FD_GMM},
136 {"ISH", BIT_FD_ISH},
137 {},
138};
139
140static const struct pmc_bit_map byt_pss_map[] = {
141 {"GBE", PMC_PSS_BIT_GBE},
142 {"SATA", PMC_PSS_BIT_SATA},
143 {"HDA", PMC_PSS_BIT_HDA},
144 {"SEC", PMC_PSS_BIT_SEC},
145 {"PCIE", PMC_PSS_BIT_PCIE},
146 {"LPSS", PMC_PSS_BIT_LPSS},
147 {"LPE", PMC_PSS_BIT_LPE},
148 {"DFX", PMC_PSS_BIT_DFX},
149 {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
150 {"USH_SUS", PMC_PSS_BIT_USH_SUS},
151 {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
152 {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
153 {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
154 {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
155 {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
156 {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
157 {"USB", PMC_PSS_BIT_USB},
158 {"USB_SUS", PMC_PSS_BIT_USB_SUS},
159 {},
160};
161
162static const struct pmc_bit_map cht_pss_map[] = {
163 {"SATA", PMC_PSS_BIT_SATA},
164 {"HDA", PMC_PSS_BIT_HDA},
165 {"SEC", PMC_PSS_BIT_SEC},
166 {"PCIE", PMC_PSS_BIT_PCIE},
167 {"LPSS", PMC_PSS_BIT_LPSS},
168 {"LPE", PMC_PSS_BIT_LPE},
169 {"UFS", PMC_PSS_BIT_CHT_UFS},
170 {"UXD", PMC_PSS_BIT_CHT_UXD},
171 {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
172 {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
173 {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
174 {"GMM", PMC_PSS_BIT_CHT_GMM},
175 {"ISH", PMC_PSS_BIT_CHT_ISH},
176 {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
177 {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
178 {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
179 {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
180 {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
181 {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
182 {},
183};
184
185static const struct pmc_reg_map byt_reg_map = {
186 .d3_sts_0 = d3_sts_0_map,
187 .d3_sts_1 = byt_d3_sts_1_map,
188 .func_dis = d3_sts_0_map,
189 .func_dis_2 = byt_d3_sts_1_map,
190 .pss = byt_pss_map,
191};
192
193static const struct pmc_reg_map cht_reg_map = {
194 .d3_sts_0 = d3_sts_0_map,
195 .d3_sts_1 = cht_d3_sts_1_map,
196 .func_dis = d3_sts_0_map,
197 .func_dis_2 = cht_func_dis_2_map,
198 .pss = cht_pss_map,
199};
200
201static const struct pmc_data byt_data = {
202 .map = &byt_reg_map,
203 .clks = byt_clks,
204};
205
206static const struct pmc_data cht_data = {
207 .map = &cht_reg_map,
208 .clks = cht_clks,
209};
210
211static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
212{
213 return readl(pmc->regmap + reg_offset);
214}
215
216static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
217{
218 writel(val, pmc->regmap + reg_offset);
219}
220
221int pmc_atom_read(int offset, u32 *value)
222{
223 struct pmc_dev *pmc = &pmc_device;
224
225 if (!pmc->init)
226 return -ENODEV;
227
228 *value = pmc_reg_read(pmc, offset);
229 return 0;
230}
231EXPORT_SYMBOL_GPL(pmc_atom_read);
232
233int pmc_atom_write(int offset, u32 value)
234{
235 struct pmc_dev *pmc = &pmc_device;
236
237 if (!pmc->init)
238 return -ENODEV;
239
240 pmc_reg_write(pmc, offset, value);
241 return 0;
242}
243EXPORT_SYMBOL_GPL(pmc_atom_write);
244
245static void pmc_power_off(void)
246{
247 u16 pm1_cnt_port;
248 u32 pm1_cnt_value;
249
250 pr_info("Preparing to enter system sleep state S5\n");
251
252 pm1_cnt_port = acpi_base_addr + PM1_CNT;
253
254 pm1_cnt_value = inl(pm1_cnt_port);
255 pm1_cnt_value &= SLEEP_TYPE_MASK;
256 pm1_cnt_value |= SLEEP_TYPE_S5;
257 pm1_cnt_value |= SLEEP_ENABLE;
258
259 outl(pm1_cnt_value, pm1_cnt_port);
260}
261
262static void pmc_hw_reg_setup(struct pmc_dev *pmc)
263{
264 /*
265 * Disable PMC S0IX_WAKE_EN events coming from:
266 * - LPC clock run
267 * - GPIO_SUS ored dedicated IRQs
268 * - GPIO_SCORE ored dedicated IRQs
269 * - GPIO_SUS shared IRQ
270 * - GPIO_SCORE shared IRQ
271 */
272 pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
273}
274
275#ifdef CONFIG_DEBUG_FS
276static void pmc_dev_state_print(struct seq_file *s, int reg_index,
277 u32 sts, const struct pmc_bit_map *sts_map,
278 u32 fd, const struct pmc_bit_map *fd_map)
279{
280 int offset = PMC_REG_BIT_WIDTH * reg_index;
281 int index;
282
283 for (index = 0; sts_map[index].name; index++) {
284 seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
285 offset + index, sts_map[index].name,
286 fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
287 sts_map[index].bit_mask & sts ? "D3" : "D0");
288 }
289}
290
291static int pmc_dev_state_show(struct seq_file *s, void *unused)
292{
293 struct pmc_dev *pmc = s->private;
294 const struct pmc_reg_map *m = pmc->map;
295 u32 func_dis, func_dis_2;
296 u32 d3_sts_0, d3_sts_1;
297
298 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
299 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
300 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
301 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
302
303 /* Low part */
304 pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
305
306 /* High part */
307 pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
308
309 return 0;
310}
311
312DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
313
314static int pmc_pss_state_show(struct seq_file *s, void *unused)
315{
316 struct pmc_dev *pmc = s->private;
317 const struct pmc_bit_map *map = pmc->map->pss;
318 u32 pss = pmc_reg_read(pmc, PMC_PSS);
319 int index;
320
321 for (index = 0; map[index].name; index++) {
322 seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
323 index, map[index].name,
324 map[index].bit_mask & pss ? "Off" : "On");
325 }
326 return 0;
327}
328
329DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
330
331static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
332{
333 struct pmc_dev *pmc = s->private;
334 u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
335
336 s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
337 s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
338 s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
339 s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
340 s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
341
342 seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
343 seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
344 seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
345 seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
346 seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
347 return 0;
348}
349
350DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
351
352static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
353{
354 debugfs_remove_recursive(pmc->dbgfs_dir);
355}
356
357static int pmc_dbgfs_register(struct pmc_dev *pmc)
358{
359 struct dentry *dir, *f;
360
361 dir = debugfs_create_dir("pmc_atom", NULL);
362 if (!dir)
363 return -ENOMEM;
364
365 pmc->dbgfs_dir = dir;
366
367 f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
368 dir, pmc, &pmc_dev_state_fops);
369 if (!f)
370 goto err;
371
372 f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
373 dir, pmc, &pmc_pss_state_fops);
374 if (!f)
375 goto err;
376
377 f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
378 dir, pmc, &pmc_sleep_tmr_fops);
379 if (!f)
380 goto err;
381
382 return 0;
383err:
384 pmc_dbgfs_unregister(pmc);
385 return -ENODEV;
386}
387#else
388static int pmc_dbgfs_register(struct pmc_dev *pmc)
389{
390 return 0;
391}
392#endif /* CONFIG_DEBUG_FS */
393
394static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
395 const struct pmc_data *pmc_data)
396{
397 struct platform_device *clkdev;
398 struct pmc_clk_data *clk_data;
399
400 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
401 if (!clk_data)
402 return -ENOMEM;
403
404 clk_data->base = pmc_regmap; /* offset is added by client */
405 clk_data->clks = pmc_data->clks;
406
407 clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
408 PLATFORM_DEVID_NONE,
409 clk_data, sizeof(*clk_data));
410 if (IS_ERR(clkdev)) {
411 kfree(clk_data);
412 return PTR_ERR(clkdev);
413 }
414
415 kfree(clk_data);
416
417 return 0;
418}
419
420static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
421{
422 struct pmc_dev *pmc = &pmc_device;
423 const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
424 const struct pmc_reg_map *map = data->map;
425 int ret;
426
427 /* Obtain ACPI base address */
428 pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
429 acpi_base_addr &= ACPI_BASE_ADDR_MASK;
430
431 /* Install power off function */
432 if (acpi_base_addr != 0 && pm_power_off == NULL)
433 pm_power_off = pmc_power_off;
434
435 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
436 pmc->base_addr &= PMC_BASE_ADDR_MASK;
437
438 pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
439 if (!pmc->regmap) {
440 dev_err(&pdev->dev, "error: ioremap failed\n");
441 return -ENOMEM;
442 }
443
444 pmc->map = map;
445
446 /* PMC hardware registers setup */
447 pmc_hw_reg_setup(pmc);
448
449 ret = pmc_dbgfs_register(pmc);
450 if (ret)
451 dev_warn(&pdev->dev, "debugfs register failed\n");
452
453 /* Register platform clocks - PMC_PLT_CLK [0..5] */
454 ret = pmc_setup_clks(pdev, pmc->regmap, data);
455 if (ret)
456 dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
457 ret);
458
459 pmc->init = true;
460 return ret;
461}
462
463/*
464 * Data for PCI driver interface
465 *
466 * used by pci_match_id() call below.
467 */
468static const struct pci_device_id pmc_pci_ids[] = {
469 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
470 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
471 { 0, },
472};
473
474static int __init pmc_atom_init(void)
475{
476 struct pci_dev *pdev = NULL;
477 const struct pci_device_id *ent;
478
479 /* We look for our device - PCU PMC
480 * we assume that there is max. one device.
481 *
482 * We can't use plain pci_driver mechanism,
483 * as the device is really a multiple function device,
484 * main driver that binds to the pci_device is lpc_ich
485 * and have to find & bind to the device this way.
486 */
487 for_each_pci_dev(pdev) {
488 ent = pci_match_id(pmc_pci_ids, pdev);
489 if (ent)
490 return pmc_setup_dev(pdev, ent);
491 }
492 /* Device not found. */
493 return -ENODEV;
494}
495
496device_initcall(pmc_atom_init);
497
498/*
499MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
500MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
501MODULE_LICENSE("GPL v2");
502*/