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1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/module.h>
38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
40#include <linux/firmware.h>
41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
43#include <linux/io.h>
44#include <linux/dma-mapping.h>
45#include <linux/slab.h>
46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
51#include "phy_common.h"
52#include "phy_g.h"
53#include "phy_n.h"
54#include "dma.h"
55#include "pio.h"
56#include "sysfs.h"
57#include "xmit.h"
58#include "lo.h"
59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
66MODULE_AUTHOR("Gábor Stefanik");
67MODULE_AUTHOR("Rafał Miłecki");
68MODULE_LICENSE("GPL");
69
70MODULE_FIRMWARE("b43/ucode11.fw");
71MODULE_FIRMWARE("b43/ucode13.fw");
72MODULE_FIRMWARE("b43/ucode14.fw");
73MODULE_FIRMWARE("b43/ucode15.fw");
74MODULE_FIRMWARE("b43/ucode16_mimo.fw");
75MODULE_FIRMWARE("b43/ucode5.fw");
76MODULE_FIRMWARE("b43/ucode9.fw");
77
78static int modparam_bad_frames_preempt;
79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
82
83static char modparam_fwpostfix[16];
84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
86
87static int modparam_hwpctl;
88module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
90
91static int modparam_nohwcrypt;
92module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94
95static int modparam_hwtkip;
96module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
98
99static int modparam_qos = 1;
100module_param_named(qos, modparam_qos, int, 0444);
101MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
102
103static int modparam_btcoex = 1;
104module_param_named(btcoex, modparam_btcoex, int, 0444);
105MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
106
107int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108module_param_named(verbose, b43_modparam_verbose, int, 0644);
109MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110
111static int b43_modparam_pio = 0;
112module_param_named(pio, b43_modparam_pio, int, 0644);
113MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
114
115static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
116module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
117MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
118
119#ifdef CONFIG_B43_BCMA
120static const struct bcma_device_id b43_bcma_tbl[] = {
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
130 {},
131};
132MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
133#endif
134
135#ifdef CONFIG_B43_SSB
136static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
147 {},
148};
149MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
150#endif
151
152/* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156#define RATETAB_ENT(_rateid, _flags) \
157 { \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
160 .flags = (_flags), \
161 }
162
163/*
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
166 */
167static struct ieee80211_rate __b43_ratetable[] = {
168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
180};
181
182#define b43_a_ratetable (__b43_ratetable + 4)
183#define b43_a_ratetable_size 8
184#define b43_b_ratetable (__b43_ratetable + 0)
185#define b43_b_ratetable_size 4
186#define b43_g_ratetable (__b43_ratetable + 0)
187#define b43_g_ratetable_size 12
188
189#define CHAN2G(_channel, _freq, _flags) { \
190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
193 .flags = (_flags), \
194 .max_antenna_gain = 0, \
195 .max_power = 30, \
196}
197static struct ieee80211_channel b43_2ghz_chantable[] = {
198 CHAN2G(1, 2412, 0),
199 CHAN2G(2, 2417, 0),
200 CHAN2G(3, 2422, 0),
201 CHAN2G(4, 2427, 0),
202 CHAN2G(5, 2432, 0),
203 CHAN2G(6, 2437, 0),
204 CHAN2G(7, 2442, 0),
205 CHAN2G(8, 2447, 0),
206 CHAN2G(9, 2452, 0),
207 CHAN2G(10, 2457, 0),
208 CHAN2G(11, 2462, 0),
209 CHAN2G(12, 2467, 0),
210 CHAN2G(13, 2472, 0),
211 CHAN2G(14, 2484, 0),
212};
213
214/* No support for the last 3 channels (12, 13, 14) */
215#define b43_2ghz_chantable_limited_size 11
216#undef CHAN2G
217
218#define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
222 .flags = (_flags), \
223 .max_antenna_gain = 0, \
224 .max_power = 30, \
225}
226#define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
230 .flags = (_flags), \
231 .max_antenna_gain = 0, \
232 .max_power = 30, \
233}
234static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
246 CHAN4G(228, 0),
247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
290 CHAN5G(182, 0),
291};
292
293static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
294 CHAN5G(36, 0), CHAN5G(40, 0),
295 CHAN5G(44, 0), CHAN5G(48, 0),
296 CHAN5G(149, 0), CHAN5G(153, 0),
297 CHAN5G(157, 0), CHAN5G(161, 0),
298 CHAN5G(165, 0),
299};
300
301static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
302 CHAN5G(34, 0), CHAN5G(36, 0),
303 CHAN5G(38, 0), CHAN5G(40, 0),
304 CHAN5G(42, 0), CHAN5G(44, 0),
305 CHAN5G(46, 0), CHAN5G(48, 0),
306 CHAN5G(52, 0), CHAN5G(56, 0),
307 CHAN5G(60, 0), CHAN5G(64, 0),
308 CHAN5G(100, 0), CHAN5G(104, 0),
309 CHAN5G(108, 0), CHAN5G(112, 0),
310 CHAN5G(116, 0), CHAN5G(120, 0),
311 CHAN5G(124, 0), CHAN5G(128, 0),
312 CHAN5G(132, 0), CHAN5G(136, 0),
313 CHAN5G(140, 0), CHAN5G(149, 0),
314 CHAN5G(153, 0), CHAN5G(157, 0),
315 CHAN5G(161, 0), CHAN5G(165, 0),
316 CHAN5G(184, 0), CHAN5G(188, 0),
317 CHAN5G(192, 0), CHAN5G(196, 0),
318 CHAN5G(200, 0), CHAN5G(204, 0),
319 CHAN5G(208, 0), CHAN5G(212, 0),
320 CHAN5G(216, 0),
321};
322#undef CHAN4G
323#undef CHAN5G
324
325static struct ieee80211_supported_band b43_band_5GHz_nphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_nphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
331};
332
333static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
334 .band = IEEE80211_BAND_5GHZ,
335 .channels = b43_5ghz_nphy_chantable_limited,
336 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
337 .bitrates = b43_a_ratetable,
338 .n_bitrates = b43_a_ratetable_size,
339};
340
341static struct ieee80211_supported_band b43_band_5GHz_aphy = {
342 .band = IEEE80211_BAND_5GHZ,
343 .channels = b43_5ghz_aphy_chantable,
344 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
345 .bitrates = b43_a_ratetable,
346 .n_bitrates = b43_a_ratetable_size,
347};
348
349static struct ieee80211_supported_band b43_band_2GHz = {
350 .band = IEEE80211_BAND_2GHZ,
351 .channels = b43_2ghz_chantable,
352 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
353 .bitrates = b43_g_ratetable,
354 .n_bitrates = b43_g_ratetable_size,
355};
356
357static struct ieee80211_supported_band b43_band_2ghz_limited = {
358 .band = IEEE80211_BAND_2GHZ,
359 .channels = b43_2ghz_chantable,
360 .n_channels = b43_2ghz_chantable_limited_size,
361 .bitrates = b43_g_ratetable,
362 .n_bitrates = b43_g_ratetable_size,
363};
364
365static void b43_wireless_core_exit(struct b43_wldev *dev);
366static int b43_wireless_core_init(struct b43_wldev *dev);
367static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
368static int b43_wireless_core_start(struct b43_wldev *dev);
369static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
370 struct ieee80211_vif *vif,
371 struct ieee80211_bss_conf *conf,
372 u32 changed);
373
374static int b43_ratelimit(struct b43_wl *wl)
375{
376 if (!wl || !wl->current_dev)
377 return 1;
378 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
379 return 1;
380 /* We are up and running.
381 * Ratelimit the messages to avoid DoS over the net. */
382 return net_ratelimit();
383}
384
385void b43info(struct b43_wl *wl, const char *fmt, ...)
386{
387 struct va_format vaf;
388 va_list args;
389
390 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
391 return;
392 if (!b43_ratelimit(wl))
393 return;
394
395 va_start(args, fmt);
396
397 vaf.fmt = fmt;
398 vaf.va = &args;
399
400 printk(KERN_INFO "b43-%s: %pV",
401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
402
403 va_end(args);
404}
405
406void b43err(struct b43_wl *wl, const char *fmt, ...)
407{
408 struct va_format vaf;
409 va_list args;
410
411 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
412 return;
413 if (!b43_ratelimit(wl))
414 return;
415
416 va_start(args, fmt);
417
418 vaf.fmt = fmt;
419 vaf.va = &args;
420
421 printk(KERN_ERR "b43-%s ERROR: %pV",
422 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
423
424 va_end(args);
425}
426
427void b43warn(struct b43_wl *wl, const char *fmt, ...)
428{
429 struct va_format vaf;
430 va_list args;
431
432 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
433 return;
434 if (!b43_ratelimit(wl))
435 return;
436
437 va_start(args, fmt);
438
439 vaf.fmt = fmt;
440 vaf.va = &args;
441
442 printk(KERN_WARNING "b43-%s warning: %pV",
443 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
444
445 va_end(args);
446}
447
448void b43dbg(struct b43_wl *wl, const char *fmt, ...)
449{
450 struct va_format vaf;
451 va_list args;
452
453 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
454 return;
455
456 va_start(args, fmt);
457
458 vaf.fmt = fmt;
459 vaf.va = &args;
460
461 printk(KERN_DEBUG "b43-%s debug: %pV",
462 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
463
464 va_end(args);
465}
466
467static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
468{
469 u32 macctl;
470
471 B43_WARN_ON(offset % 4 != 0);
472
473 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 if (macctl & B43_MACCTL_BE)
475 val = swab32(val);
476
477 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
478 mmiowb();
479 b43_write32(dev, B43_MMIO_RAM_DATA, val);
480}
481
482static inline void b43_shm_control_word(struct b43_wldev *dev,
483 u16 routing, u16 offset)
484{
485 u32 control;
486
487 /* "offset" is the WORD offset. */
488 control = routing;
489 control <<= 16;
490 control |= offset;
491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
492}
493
494u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
495{
496 u32 ret;
497
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
506
507 goto out;
508 }
509 offset >>= 2;
510 }
511 b43_shm_control_word(dev, routing, offset);
512 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
513out:
514 return ret;
515}
516
517u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
518{
519 u16 ret;
520
521 if (routing == B43_SHM_SHARED) {
522 B43_WARN_ON(offset & 0x0001);
523 if (offset & 0x0003) {
524 /* Unaligned access */
525 b43_shm_control_word(dev, routing, offset >> 2);
526 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
527
528 goto out;
529 }
530 offset >>= 2;
531 }
532 b43_shm_control_word(dev, routing, offset);
533 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
534out:
535 return ret;
536}
537
538void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
539{
540 if (routing == B43_SHM_SHARED) {
541 B43_WARN_ON(offset & 0x0001);
542 if (offset & 0x0003) {
543 /* Unaligned access */
544 b43_shm_control_word(dev, routing, offset >> 2);
545 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
546 value & 0xFFFF);
547 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
548 b43_write16(dev, B43_MMIO_SHM_DATA,
549 (value >> 16) & 0xFFFF);
550 return;
551 }
552 offset >>= 2;
553 }
554 b43_shm_control_word(dev, routing, offset);
555 b43_write32(dev, B43_MMIO_SHM_DATA, value);
556}
557
558void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
559{
560 if (routing == B43_SHM_SHARED) {
561 B43_WARN_ON(offset & 0x0001);
562 if (offset & 0x0003) {
563 /* Unaligned access */
564 b43_shm_control_word(dev, routing, offset >> 2);
565 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
566 return;
567 }
568 offset >>= 2;
569 }
570 b43_shm_control_word(dev, routing, offset);
571 b43_write16(dev, B43_MMIO_SHM_DATA, value);
572}
573
574/* Read HostFlags */
575u64 b43_hf_read(struct b43_wldev *dev)
576{
577 u64 ret;
578
579 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
580 ret <<= 16;
581 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
582 ret <<= 16;
583 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
584
585 return ret;
586}
587
588/* Write HostFlags */
589void b43_hf_write(struct b43_wldev *dev, u64 value)
590{
591 u16 lo, mi, hi;
592
593 lo = (value & 0x00000000FFFFULL);
594 mi = (value & 0x0000FFFF0000ULL) >> 16;
595 hi = (value & 0xFFFF00000000ULL) >> 32;
596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
599}
600
601/* Read the firmware capabilities bitmask (Opensource firmware only) */
602static u16 b43_fwcapa_read(struct b43_wldev *dev)
603{
604 B43_WARN_ON(!dev->fw.opensource);
605 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
606}
607
608void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
609{
610 u32 low, high;
611
612 B43_WARN_ON(dev->dev->core_rev < 3);
613
614 /* The hardware guarantees us an atomic read, if we
615 * read the low register first. */
616 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
617 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
618
619 *tsf = high;
620 *tsf <<= 32;
621 *tsf |= low;
622}
623
624static void b43_time_lock(struct b43_wldev *dev)
625{
626 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
627 /* Commit the write */
628 b43_read32(dev, B43_MMIO_MACCTL);
629}
630
631static void b43_time_unlock(struct b43_wldev *dev)
632{
633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
634 /* Commit the write */
635 b43_read32(dev, B43_MMIO_MACCTL);
636}
637
638static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
639{
640 u32 low, high;
641
642 B43_WARN_ON(dev->dev->core_rev < 3);
643
644 low = tsf;
645 high = (tsf >> 32);
646 /* The hardware guarantees us an atomic write, if we
647 * write the low register first. */
648 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
649 mmiowb();
650 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
651 mmiowb();
652}
653
654void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
655{
656 b43_time_lock(dev);
657 b43_tsf_write_locked(dev, tsf);
658 b43_time_unlock(dev);
659}
660
661static
662void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
663{
664 static const u8 zero_addr[ETH_ALEN] = { 0 };
665 u16 data;
666
667 if (!mac)
668 mac = zero_addr;
669
670 offset |= 0x0020;
671 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
672
673 data = mac[0];
674 data |= mac[1] << 8;
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
676 data = mac[2];
677 data |= mac[3] << 8;
678 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
679 data = mac[4];
680 data |= mac[5] << 8;
681 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
682}
683
684static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
685{
686 const u8 *mac;
687 const u8 *bssid;
688 u8 mac_bssid[ETH_ALEN * 2];
689 int i;
690 u32 tmp;
691
692 bssid = dev->wl->bssid;
693 mac = dev->wl->mac_addr;
694
695 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
696
697 memcpy(mac_bssid, mac, ETH_ALEN);
698 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
699
700 /* Write our MAC address and BSSID to template ram */
701 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
702 tmp = (u32) (mac_bssid[i + 0]);
703 tmp |= (u32) (mac_bssid[i + 1]) << 8;
704 tmp |= (u32) (mac_bssid[i + 2]) << 16;
705 tmp |= (u32) (mac_bssid[i + 3]) << 24;
706 b43_ram_write(dev, 0x20 + i, tmp);
707 }
708}
709
710static void b43_upload_card_macaddress(struct b43_wldev *dev)
711{
712 b43_write_mac_bssid_templates(dev);
713 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
714}
715
716static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
717{
718 /* slot_time is in usec. */
719 /* This test used to exit for all but a G PHY. */
720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
721 return;
722 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
723 /* Shared memory location 0x0010 is the slot time and should be
724 * set to slot_time; however, this register is initially 0 and changing
725 * the value adversely affects the transmit rate for BCM4311
726 * devices. Until this behavior is unterstood, delete this step
727 *
728 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
729 */
730}
731
732static void b43_short_slot_timing_enable(struct b43_wldev *dev)
733{
734 b43_set_slot_time(dev, 9);
735}
736
737static void b43_short_slot_timing_disable(struct b43_wldev *dev)
738{
739 b43_set_slot_time(dev, 20);
740}
741
742/* DummyTransmission function, as documented on
743 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
744 */
745void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
746{
747 struct b43_phy *phy = &dev->phy;
748 unsigned int i, max_loop;
749 u16 value;
750 u32 buffer[5] = {
751 0x00000000,
752 0x00D40000,
753 0x00000000,
754 0x01000000,
755 0x00000000,
756 };
757
758 if (ofdm) {
759 max_loop = 0x1E;
760 buffer[0] = 0x000201CC;
761 } else {
762 max_loop = 0xFA;
763 buffer[0] = 0x000B846E;
764 }
765
766 for (i = 0; i < 5; i++)
767 b43_ram_write(dev, i * 4, buffer[i]);
768
769 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
770
771 if (dev->dev->core_rev < 11)
772 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
773 else
774 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
775
776 value = (ofdm ? 0x41 : 0x40);
777 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
778 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
779 phy->type == B43_PHYTYPE_LCN)
780 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
781
782 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
783 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
784
785 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
786 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
787 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
788 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
789
790 if (!pa_on && phy->type == B43_PHYTYPE_N)
791 ; /*b43_nphy_pa_override(dev, false) */
792
793 switch (phy->type) {
794 case B43_PHYTYPE_N:
795 case B43_PHYTYPE_LCN:
796 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
797 break;
798 case B43_PHYTYPE_LP:
799 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
800 break;
801 default:
802 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
803 }
804 b43_read16(dev, B43_MMIO_TXE0_AUX);
805
806 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
807 b43_radio_write16(dev, 0x0051, 0x0017);
808 for (i = 0x00; i < max_loop; i++) {
809 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
810 if (value & 0x0080)
811 break;
812 udelay(10);
813 }
814 for (i = 0x00; i < 0x0A; i++) {
815 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
816 if (value & 0x0400)
817 break;
818 udelay(10);
819 }
820 for (i = 0x00; i < 0x19; i++) {
821 value = b43_read16(dev, B43_MMIO_IFSSTAT);
822 if (!(value & 0x0100))
823 break;
824 udelay(10);
825 }
826 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
827 b43_radio_write16(dev, 0x0051, 0x0037);
828}
829
830static void key_write(struct b43_wldev *dev,
831 u8 index, u8 algorithm, const u8 *key)
832{
833 unsigned int i;
834 u32 offset;
835 u16 value;
836 u16 kidx;
837
838 /* Key index/algo block */
839 kidx = b43_kidx_to_fw(dev, index);
840 value = ((kidx << 4) | algorithm);
841 b43_shm_write16(dev, B43_SHM_SHARED,
842 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
843
844 /* Write the key to the Key Table Pointer offset */
845 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
846 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
847 value = key[i];
848 value |= (u16) (key[i + 1]) << 8;
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
850 }
851}
852
853static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
854{
855 u32 addrtmp[2] = { 0, 0, };
856 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
857
858 if (b43_new_kidx_api(dev))
859 pairwise_keys_start = B43_NR_GROUP_KEYS;
860
861 B43_WARN_ON(index < pairwise_keys_start);
862 /* We have four default TX keys and possibly four default RX keys.
863 * Physical mac 0 is mapped to physical key 4 or 8, depending
864 * on the firmware version.
865 * So we must adjust the index here.
866 */
867 index -= pairwise_keys_start;
868 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
869
870 if (addr) {
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 }
878
879 /* Receive match transmitter address (RCMTA) mechanism */
880 b43_shm_write32(dev, B43_SHM_RCMTA,
881 (index * 2) + 0, addrtmp[0]);
882 b43_shm_write16(dev, B43_SHM_RCMTA,
883 (index * 2) + 1, addrtmp[1]);
884}
885
886/* The ucode will use phase1 key with TEK key to decrypt rx packets.
887 * When a packet is received, the iv32 is checked.
888 * - if it doesn't the packet is returned without modification (and software
889 * decryption can be done). That's what happen when iv16 wrap.
890 * - if it does, the rc4 key is computed, and decryption is tried.
891 * Either it will success and B43_RX_MAC_DEC is returned,
892 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
893 * and the packet is not usable (it got modified by the ucode).
894 * So in order to never have B43_RX_MAC_DECERR, we should provide
895 * a iv32 and phase1key that match. Because we drop packets in case of
896 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
897 * packets will be lost without higher layer knowing (ie no resync possible
898 * until next wrap).
899 *
900 * NOTE : this should support 50 key like RCMTA because
901 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
902 */
903static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
904 u16 *phase1key)
905{
906 unsigned int i;
907 u32 offset;
908 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
909
910 if (!modparam_hwtkip)
911 return;
912
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
915
916 B43_WARN_ON(index < pairwise_keys_start);
917 /* We have four default TX keys and possibly four default RX keys.
918 * Physical mac 0 is mapped to physical key 4 or 8, depending
919 * on the firmware version.
920 * So we must adjust the index here.
921 */
922 index -= pairwise_keys_start;
923 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
924
925 if (b43_debug(dev, B43_DBG_KEYS)) {
926 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
927 index, iv32);
928 }
929 /* Write the key to the RX tkip shared mem */
930 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
931 for (i = 0; i < 10; i += 2) {
932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
933 phase1key ? phase1key[i / 2] : 0);
934 }
935 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
936 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
937}
938
939static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
940 struct ieee80211_vif *vif,
941 struct ieee80211_key_conf *keyconf,
942 struct ieee80211_sta *sta,
943 u32 iv32, u16 *phase1key)
944{
945 struct b43_wl *wl = hw_to_b43_wl(hw);
946 struct b43_wldev *dev;
947 int index = keyconf->hw_key_idx;
948
949 if (B43_WARN_ON(!modparam_hwtkip))
950 return;
951
952 /* This is only called from the RX path through mac80211, where
953 * our mutex is already locked. */
954 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
955 dev = wl->current_dev;
956 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
957
958 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
959
960 rx_tkip_phase1_write(dev, index, iv32, phase1key);
961 /* only pairwise TKIP keys are supported right now */
962 if (WARN_ON(!sta))
963 return;
964 keymac_write(dev, index, sta->addr);
965}
966
967static void do_key_write(struct b43_wldev *dev,
968 u8 index, u8 algorithm,
969 const u8 *key, size_t key_len, const u8 *mac_addr)
970{
971 u8 buf[B43_SEC_KEYSIZE] = { 0, };
972 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
973
974 if (b43_new_kidx_api(dev))
975 pairwise_keys_start = B43_NR_GROUP_KEYS;
976
977 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
978 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
979
980 if (index >= pairwise_keys_start)
981 keymac_write(dev, index, NULL); /* First zero out mac. */
982 if (algorithm == B43_SEC_ALGO_TKIP) {
983 /*
984 * We should provide an initial iv32, phase1key pair.
985 * We could start with iv32=0 and compute the corresponding
986 * phase1key, but this means calling ieee80211_get_tkip_key
987 * with a fake skb (or export other tkip function).
988 * Because we are lazy we hope iv32 won't start with
989 * 0xffffffff and let's b43_op_update_tkip_key provide a
990 * correct pair.
991 */
992 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
993 } else if (index >= pairwise_keys_start) /* clear it */
994 rx_tkip_phase1_write(dev, index, 0, NULL);
995 if (key)
996 memcpy(buf, key, key_len);
997 key_write(dev, index, algorithm, buf);
998 if (index >= pairwise_keys_start)
999 keymac_write(dev, index, mac_addr);
1000
1001 dev->key[index].algorithm = algorithm;
1002}
1003
1004static int b43_key_write(struct b43_wldev *dev,
1005 int index, u8 algorithm,
1006 const u8 *key, size_t key_len,
1007 const u8 *mac_addr,
1008 struct ieee80211_key_conf *keyconf)
1009{
1010 int i;
1011 int pairwise_keys_start;
1012
1013 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1014 * - Temporal Encryption Key (128 bits)
1015 * - Temporal Authenticator Tx MIC Key (64 bits)
1016 * - Temporal Authenticator Rx MIC Key (64 bits)
1017 *
1018 * Hardware only store TEK
1019 */
1020 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1021 key_len = 16;
1022 if (key_len > B43_SEC_KEYSIZE)
1023 return -EINVAL;
1024 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
1025 /* Check that we don't already have this key. */
1026 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1027 }
1028 if (index < 0) {
1029 /* Pairwise key. Get an empty slot for the key. */
1030 if (b43_new_kidx_api(dev))
1031 pairwise_keys_start = B43_NR_GROUP_KEYS;
1032 else
1033 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1034 for (i = pairwise_keys_start;
1035 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1036 i++) {
1037 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
1038 if (!dev->key[i].keyconf) {
1039 /* found empty */
1040 index = i;
1041 break;
1042 }
1043 }
1044 if (index < 0) {
1045 b43warn(dev->wl, "Out of hardware key memory\n");
1046 return -ENOSPC;
1047 }
1048 } else
1049 B43_WARN_ON(index > 3);
1050
1051 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1052 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1053 /* Default RX key */
1054 B43_WARN_ON(mac_addr);
1055 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1056 }
1057 keyconf->hw_key_idx = index;
1058 dev->key[index].keyconf = keyconf;
1059
1060 return 0;
1061}
1062
1063static int b43_key_clear(struct b43_wldev *dev, int index)
1064{
1065 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1066 return -EINVAL;
1067 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1068 NULL, B43_SEC_KEYSIZE, NULL);
1069 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1070 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1071 NULL, B43_SEC_KEYSIZE, NULL);
1072 }
1073 dev->key[index].keyconf = NULL;
1074
1075 return 0;
1076}
1077
1078static void b43_clear_keys(struct b43_wldev *dev)
1079{
1080 int i, count;
1081
1082 if (b43_new_kidx_api(dev))
1083 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1084 else
1085 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1086 for (i = 0; i < count; i++)
1087 b43_key_clear(dev, i);
1088}
1089
1090static void b43_dump_keymemory(struct b43_wldev *dev)
1091{
1092 unsigned int i, index, count, offset, pairwise_keys_start;
1093 u8 mac[ETH_ALEN];
1094 u16 algo;
1095 u32 rcmta0;
1096 u16 rcmta1;
1097 u64 hf;
1098 struct b43_key *key;
1099
1100 if (!b43_debug(dev, B43_DBG_KEYS))
1101 return;
1102
1103 hf = b43_hf_read(dev);
1104 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1105 !!(hf & B43_HF_USEDEFKEYS));
1106 if (b43_new_kidx_api(dev)) {
1107 pairwise_keys_start = B43_NR_GROUP_KEYS;
1108 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1109 } else {
1110 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1111 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1112 }
1113 for (index = 0; index < count; index++) {
1114 key = &(dev->key[index]);
1115 printk(KERN_DEBUG "Key slot %02u: %s",
1116 index, (key->keyconf == NULL) ? " " : "*");
1117 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1118 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1119 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1120 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1121 }
1122
1123 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1124 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1125 printk(" Algo: %04X/%02X", algo, key->algorithm);
1126
1127 if (index >= pairwise_keys_start) {
1128 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1129 printk(" TKIP: ");
1130 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1131 for (i = 0; i < 14; i += 2) {
1132 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1133 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1134 }
1135 }
1136 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1137 ((index - pairwise_keys_start) * 2) + 0);
1138 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1139 ((index - pairwise_keys_start) * 2) + 1);
1140 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1141 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1142 printk(" MAC: %pM", mac);
1143 } else
1144 printk(" DEFAULT KEY");
1145 printk("\n");
1146 }
1147}
1148
1149void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1150{
1151 u32 macctl;
1152 u16 ucstat;
1153 bool hwps;
1154 bool awake;
1155 int i;
1156
1157 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1158 (ps_flags & B43_PS_DISABLED));
1159 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1160
1161 if (ps_flags & B43_PS_ENABLED) {
1162 hwps = true;
1163 } else if (ps_flags & B43_PS_DISABLED) {
1164 hwps = false;
1165 } else {
1166 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1167 // and thus is not an AP and we are associated, set bit 25
1168 }
1169 if (ps_flags & B43_PS_AWAKE) {
1170 awake = true;
1171 } else if (ps_flags & B43_PS_ASLEEP) {
1172 awake = false;
1173 } else {
1174 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1175 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1176 // successful, set bit26
1177 }
1178
1179/* FIXME: For now we force awake-on and hwps-off */
1180 hwps = false;
1181 awake = true;
1182
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1184 if (hwps)
1185 macctl |= B43_MACCTL_HWPS;
1186 else
1187 macctl &= ~B43_MACCTL_HWPS;
1188 if (awake)
1189 macctl |= B43_MACCTL_AWAKE;
1190 else
1191 macctl &= ~B43_MACCTL_AWAKE;
1192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1193 /* Commit write */
1194 b43_read32(dev, B43_MMIO_MACCTL);
1195 if (awake && dev->dev->core_rev >= 5) {
1196 /* Wait for the microcode to wake up. */
1197 for (i = 0; i < 100; i++) {
1198 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1199 B43_SHM_SH_UCODESTAT);
1200 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1201 break;
1202 udelay(10);
1203 }
1204 }
1205}
1206
1207/* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
1208void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1209{
1210 struct bcma_drv_cc *bcma_cc __maybe_unused;
1211 struct ssb_chipcommon *ssb_cc __maybe_unused;
1212
1213 switch (dev->dev->bus_type) {
1214#ifdef CONFIG_B43_BCMA
1215 case B43_BUS_BCMA:
1216 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1217
1218 bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
1219 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1220 bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
1221 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1222 break;
1223#endif
1224#ifdef CONFIG_B43_SSB
1225 case B43_BUS_SSB:
1226 ssb_cc = &dev->dev->sdev->bus->chipco;
1227
1228 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0);
1229 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1230 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4);
1231 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1232 break;
1233#endif
1234 }
1235}
1236
1237#ifdef CONFIG_B43_BCMA
1238static void b43_bcma_phy_reset(struct b43_wldev *dev)
1239{
1240 u32 flags;
1241
1242 /* Put PHY into reset */
1243 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1244 flags |= B43_BCMA_IOCTL_PHY_RESET;
1245 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1246 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1247 udelay(2);
1248
1249 b43_phy_take_out_of_reset(dev);
1250}
1251
1252static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1253{
1254 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1255 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1256 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1257 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1258 u32 flags;
1259
1260 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1261 if (gmode)
1262 flags |= B43_BCMA_IOCTL_GMODE;
1263 b43_device_enable(dev, flags);
1264
1265 if (dev->phy.type == B43_PHYTYPE_AC) {
1266 u16 tmp;
1267
1268 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1269 tmp &= ~B43_BCMA_IOCTL_DAC;
1270 tmp |= 0x100;
1271 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1272
1273 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1274 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
1275 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1276
1277 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1278 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
1279 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1280 }
1281
1282 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1283 b43_bcma_phy_reset(dev);
1284 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1285}
1286#endif
1287
1288#ifdef CONFIG_B43_SSB
1289static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1290{
1291 u32 flags = 0;
1292
1293 if (gmode)
1294 flags |= B43_TMSLOW_GMODE;
1295 flags |= B43_TMSLOW_PHYCLKEN;
1296 flags |= B43_TMSLOW_PHYRESET;
1297 if (dev->phy.type == B43_PHYTYPE_N)
1298 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1299 b43_device_enable(dev, flags);
1300 msleep(2); /* Wait for the PLL to turn on. */
1301
1302 b43_phy_take_out_of_reset(dev);
1303}
1304#endif
1305
1306void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1307{
1308 u32 macctl;
1309
1310 switch (dev->dev->bus_type) {
1311#ifdef CONFIG_B43_BCMA
1312 case B43_BUS_BCMA:
1313 b43_bcma_wireless_core_reset(dev, gmode);
1314 break;
1315#endif
1316#ifdef CONFIG_B43_SSB
1317 case B43_BUS_SSB:
1318 b43_ssb_wireless_core_reset(dev, gmode);
1319 break;
1320#endif
1321 }
1322
1323 /* Turn Analog ON, but only if we already know the PHY-type.
1324 * This protects against very early setup where we don't know the
1325 * PHY-type, yet. wireless_core_reset will be called once again later,
1326 * when we know the PHY-type. */
1327 if (dev->phy.ops)
1328 dev->phy.ops->switch_analog(dev, 1);
1329
1330 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1331 macctl &= ~B43_MACCTL_GMODE;
1332 if (gmode)
1333 macctl |= B43_MACCTL_GMODE;
1334 macctl |= B43_MACCTL_IHR_ENABLED;
1335 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1336}
1337
1338static void handle_irq_transmit_status(struct b43_wldev *dev)
1339{
1340 u32 v0, v1;
1341 u16 tmp;
1342 struct b43_txstatus stat;
1343
1344 while (1) {
1345 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1346 if (!(v0 & 0x00000001))
1347 break;
1348 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1349
1350 stat.cookie = (v0 >> 16);
1351 stat.seq = (v1 & 0x0000FFFF);
1352 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1353 tmp = (v0 & 0x0000FFFF);
1354 stat.frame_count = ((tmp & 0xF000) >> 12);
1355 stat.rts_count = ((tmp & 0x0F00) >> 8);
1356 stat.supp_reason = ((tmp & 0x001C) >> 2);
1357 stat.pm_indicated = !!(tmp & 0x0080);
1358 stat.intermediate = !!(tmp & 0x0040);
1359 stat.for_ampdu = !!(tmp & 0x0020);
1360 stat.acked = !!(tmp & 0x0002);
1361
1362 b43_handle_txstatus(dev, &stat);
1363 }
1364}
1365
1366static void drain_txstatus_queue(struct b43_wldev *dev)
1367{
1368 u32 dummy;
1369
1370 if (dev->dev->core_rev < 5)
1371 return;
1372 /* Read all entries from the microcode TXstatus FIFO
1373 * and throw them away.
1374 */
1375 while (1) {
1376 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1377 if (!(dummy & 0x00000001))
1378 break;
1379 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1380 }
1381}
1382
1383static u32 b43_jssi_read(struct b43_wldev *dev)
1384{
1385 u32 val = 0;
1386
1387 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1388 val <<= 16;
1389 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1390
1391 return val;
1392}
1393
1394static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1395{
1396 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1397 (jssi & 0x0000FFFF));
1398 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1399 (jssi & 0xFFFF0000) >> 16);
1400}
1401
1402static void b43_generate_noise_sample(struct b43_wldev *dev)
1403{
1404 b43_jssi_write(dev, 0x7F7F7F7F);
1405 b43_write32(dev, B43_MMIO_MACCMD,
1406 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1407}
1408
1409static void b43_calculate_link_quality(struct b43_wldev *dev)
1410{
1411 /* Top half of Link Quality calculation. */
1412
1413 if (dev->phy.type != B43_PHYTYPE_G)
1414 return;
1415 if (dev->noisecalc.calculation_running)
1416 return;
1417 dev->noisecalc.calculation_running = true;
1418 dev->noisecalc.nr_samples = 0;
1419
1420 b43_generate_noise_sample(dev);
1421}
1422
1423static void handle_irq_noise(struct b43_wldev *dev)
1424{
1425 struct b43_phy_g *phy = dev->phy.g;
1426 u16 tmp;
1427 u8 noise[4];
1428 u8 i, j;
1429 s32 average;
1430
1431 /* Bottom half of Link Quality calculation. */
1432
1433 if (dev->phy.type != B43_PHYTYPE_G)
1434 return;
1435
1436 /* Possible race condition: It might be possible that the user
1437 * changed to a different channel in the meantime since we
1438 * started the calculation. We ignore that fact, since it's
1439 * not really that much of a problem. The background noise is
1440 * an estimation only anyway. Slightly wrong results will get damped
1441 * by the averaging of the 8 sample rounds. Additionally the
1442 * value is shortlived. So it will be replaced by the next noise
1443 * calculation round soon. */
1444
1445 B43_WARN_ON(!dev->noisecalc.calculation_running);
1446 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1447 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1448 noise[2] == 0x7F || noise[3] == 0x7F)
1449 goto generate_new;
1450
1451 /* Get the noise samples. */
1452 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1453 i = dev->noisecalc.nr_samples;
1454 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1455 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1456 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1457 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1458 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1459 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1460 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1461 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1462 dev->noisecalc.nr_samples++;
1463 if (dev->noisecalc.nr_samples == 8) {
1464 /* Calculate the Link Quality by the noise samples. */
1465 average = 0;
1466 for (i = 0; i < 8; i++) {
1467 for (j = 0; j < 4; j++)
1468 average += dev->noisecalc.samples[i][j];
1469 }
1470 average /= (8 * 4);
1471 average *= 125;
1472 average += 64;
1473 average /= 128;
1474 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1475 tmp = (tmp / 128) & 0x1F;
1476 if (tmp >= 8)
1477 average += 2;
1478 else
1479 average -= 25;
1480 if (tmp == 8)
1481 average -= 72;
1482 else
1483 average -= 48;
1484
1485 dev->stats.link_noise = average;
1486 dev->noisecalc.calculation_running = false;
1487 return;
1488 }
1489generate_new:
1490 b43_generate_noise_sample(dev);
1491}
1492
1493static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1494{
1495 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1496 ///TODO: PS TBTT
1497 } else {
1498 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1499 b43_power_saving_ctl_bits(dev, 0);
1500 }
1501 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1502 dev->dfq_valid = true;
1503}
1504
1505static void handle_irq_atim_end(struct b43_wldev *dev)
1506{
1507 if (dev->dfq_valid) {
1508 b43_write32(dev, B43_MMIO_MACCMD,
1509 b43_read32(dev, B43_MMIO_MACCMD)
1510 | B43_MACCMD_DFQ_VALID);
1511 dev->dfq_valid = false;
1512 }
1513}
1514
1515static void handle_irq_pmq(struct b43_wldev *dev)
1516{
1517 u32 tmp;
1518
1519 //TODO: AP mode.
1520
1521 while (1) {
1522 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1523 if (!(tmp & 0x00000008))
1524 break;
1525 }
1526 /* 16bit write is odd, but correct. */
1527 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1528}
1529
1530static void b43_write_template_common(struct b43_wldev *dev,
1531 const u8 *data, u16 size,
1532 u16 ram_offset,
1533 u16 shm_size_offset, u8 rate)
1534{
1535 u32 i, tmp;
1536 struct b43_plcp_hdr4 plcp;
1537
1538 plcp.data = 0;
1539 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1540 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1541 ram_offset += sizeof(u32);
1542 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1543 * So leave the first two bytes of the next write blank.
1544 */
1545 tmp = (u32) (data[0]) << 16;
1546 tmp |= (u32) (data[1]) << 24;
1547 b43_ram_write(dev, ram_offset, tmp);
1548 ram_offset += sizeof(u32);
1549 for (i = 2; i < size; i += sizeof(u32)) {
1550 tmp = (u32) (data[i + 0]);
1551 if (i + 1 < size)
1552 tmp |= (u32) (data[i + 1]) << 8;
1553 if (i + 2 < size)
1554 tmp |= (u32) (data[i + 2]) << 16;
1555 if (i + 3 < size)
1556 tmp |= (u32) (data[i + 3]) << 24;
1557 b43_ram_write(dev, ram_offset + i - 2, tmp);
1558 }
1559 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1560 size + sizeof(struct b43_plcp_hdr6));
1561}
1562
1563/* Check if the use of the antenna that ieee80211 told us to
1564 * use is possible. This will fall back to DEFAULT.
1565 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1566u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1567 u8 antenna_nr)
1568{
1569 u8 antenna_mask;
1570
1571 if (antenna_nr == 0) {
1572 /* Zero means "use default antenna". That's always OK. */
1573 return 0;
1574 }
1575
1576 /* Get the mask of available antennas. */
1577 if (dev->phy.gmode)
1578 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1579 else
1580 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1581
1582 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1583 /* This antenna is not available. Fall back to default. */
1584 return 0;
1585 }
1586
1587 return antenna_nr;
1588}
1589
1590/* Convert a b43 antenna number value to the PHY TX control value. */
1591static u16 b43_antenna_to_phyctl(int antenna)
1592{
1593 switch (antenna) {
1594 case B43_ANTENNA0:
1595 return B43_TXH_PHY_ANT0;
1596 case B43_ANTENNA1:
1597 return B43_TXH_PHY_ANT1;
1598 case B43_ANTENNA2:
1599 return B43_TXH_PHY_ANT2;
1600 case B43_ANTENNA3:
1601 return B43_TXH_PHY_ANT3;
1602 case B43_ANTENNA_AUTO0:
1603 case B43_ANTENNA_AUTO1:
1604 return B43_TXH_PHY_ANT01AUTO;
1605 }
1606 B43_WARN_ON(1);
1607 return 0;
1608}
1609
1610static void b43_write_beacon_template(struct b43_wldev *dev,
1611 u16 ram_offset,
1612 u16 shm_size_offset)
1613{
1614 unsigned int i, len, variable_len;
1615 const struct ieee80211_mgmt *bcn;
1616 const u8 *ie;
1617 bool tim_found = false;
1618 unsigned int rate;
1619 u16 ctl;
1620 int antenna;
1621 struct ieee80211_tx_info *info;
1622 unsigned long flags;
1623 struct sk_buff *beacon_skb;
1624
1625 spin_lock_irqsave(&dev->wl->beacon_lock, flags);
1626 info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1627 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1628 /* Clone the beacon, so it cannot go away, while we write it to hw. */
1629 beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC);
1630 spin_unlock_irqrestore(&dev->wl->beacon_lock, flags);
1631
1632 if (!beacon_skb) {
1633 b43dbg(dev->wl, "Could not upload beacon. "
1634 "Failed to clone beacon skb.");
1635 return;
1636 }
1637
1638 bcn = (const struct ieee80211_mgmt *)(beacon_skb->data);
1639 len = min_t(size_t, beacon_skb->len,
1640 0x200 - sizeof(struct b43_plcp_hdr6));
1641
1642 b43_write_template_common(dev, (const u8 *)bcn,
1643 len, ram_offset, shm_size_offset, rate);
1644
1645 /* Write the PHY TX control parameters. */
1646 antenna = B43_ANTENNA_DEFAULT;
1647 antenna = b43_antenna_to_phyctl(antenna);
1648 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1649 /* We can't send beacons with short preamble. Would get PHY errors. */
1650 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1651 ctl &= ~B43_TXH_PHY_ANT;
1652 ctl &= ~B43_TXH_PHY_ENC;
1653 ctl |= antenna;
1654 if (b43_is_cck_rate(rate))
1655 ctl |= B43_TXH_PHY_ENC_CCK;
1656 else
1657 ctl |= B43_TXH_PHY_ENC_OFDM;
1658 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1659
1660 /* Find the position of the TIM and the DTIM_period value
1661 * and write them to SHM. */
1662 ie = bcn->u.beacon.variable;
1663 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1664 for (i = 0; i < variable_len - 2; ) {
1665 uint8_t ie_id, ie_len;
1666
1667 ie_id = ie[i];
1668 ie_len = ie[i + 1];
1669 if (ie_id == 5) {
1670 u16 tim_position;
1671 u16 dtim_period;
1672 /* This is the TIM Information Element */
1673
1674 /* Check whether the ie_len is in the beacon data range. */
1675 if (variable_len < ie_len + 2 + i)
1676 break;
1677 /* A valid TIM is at least 4 bytes long. */
1678 if (ie_len < 4)
1679 break;
1680 tim_found = true;
1681
1682 tim_position = sizeof(struct b43_plcp_hdr6);
1683 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1684 tim_position += i;
1685
1686 dtim_period = ie[i + 3];
1687
1688 b43_shm_write16(dev, B43_SHM_SHARED,
1689 B43_SHM_SH_TIMBPOS, tim_position);
1690 b43_shm_write16(dev, B43_SHM_SHARED,
1691 B43_SHM_SH_DTIMPER, dtim_period);
1692 break;
1693 }
1694 i += ie_len + 2;
1695 }
1696 if (!tim_found) {
1697 /*
1698 * If ucode wants to modify TIM do it behind the beacon, this
1699 * will happen, for example, when doing mesh networking.
1700 */
1701 b43_shm_write16(dev, B43_SHM_SHARED,
1702 B43_SHM_SH_TIMBPOS,
1703 len + sizeof(struct b43_plcp_hdr6));
1704 b43_shm_write16(dev, B43_SHM_SHARED,
1705 B43_SHM_SH_DTIMPER, 0);
1706 }
1707 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1708
1709 dev_kfree_skb_any(beacon_skb);
1710}
1711
1712static void b43_upload_beacon0(struct b43_wldev *dev)
1713{
1714 struct b43_wl *wl = dev->wl;
1715
1716 if (wl->beacon0_uploaded)
1717 return;
1718 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1719 wl->beacon0_uploaded = true;
1720}
1721
1722static void b43_upload_beacon1(struct b43_wldev *dev)
1723{
1724 struct b43_wl *wl = dev->wl;
1725
1726 if (wl->beacon1_uploaded)
1727 return;
1728 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1729 wl->beacon1_uploaded = true;
1730}
1731
1732static void handle_irq_beacon(struct b43_wldev *dev)
1733{
1734 struct b43_wl *wl = dev->wl;
1735 u32 cmd, beacon0_valid, beacon1_valid;
1736
1737 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1738 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1739 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1740 return;
1741
1742 /* This is the bottom half of the asynchronous beacon update. */
1743
1744 /* Ignore interrupt in the future. */
1745 dev->irq_mask &= ~B43_IRQ_BEACON;
1746
1747 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1748 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1749 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1750
1751 /* Schedule interrupt manually, if busy. */
1752 if (beacon0_valid && beacon1_valid) {
1753 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1754 dev->irq_mask |= B43_IRQ_BEACON;
1755 return;
1756 }
1757
1758 if (unlikely(wl->beacon_templates_virgin)) {
1759 /* We never uploaded a beacon before.
1760 * Upload both templates now, but only mark one valid. */
1761 wl->beacon_templates_virgin = false;
1762 b43_upload_beacon0(dev);
1763 b43_upload_beacon1(dev);
1764 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1765 cmd |= B43_MACCMD_BEACON0_VALID;
1766 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1767 } else {
1768 if (!beacon0_valid) {
1769 b43_upload_beacon0(dev);
1770 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1771 cmd |= B43_MACCMD_BEACON0_VALID;
1772 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1773 } else if (!beacon1_valid) {
1774 b43_upload_beacon1(dev);
1775 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1776 cmd |= B43_MACCMD_BEACON1_VALID;
1777 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1778 }
1779 }
1780}
1781
1782static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1783{
1784 u32 old_irq_mask = dev->irq_mask;
1785
1786 /* update beacon right away or defer to irq */
1787 handle_irq_beacon(dev);
1788 if (old_irq_mask != dev->irq_mask) {
1789 /* The handler updated the IRQ mask. */
1790 B43_WARN_ON(!dev->irq_mask);
1791 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1792 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1793 } else {
1794 /* Device interrupts are currently disabled. That means
1795 * we just ran the hardirq handler and scheduled the
1796 * IRQ thread. The thread will write the IRQ mask when
1797 * it finished, so there's nothing to do here. Writing
1798 * the mask _here_ would incorrectly re-enable IRQs. */
1799 }
1800 }
1801}
1802
1803static void b43_beacon_update_trigger_work(struct work_struct *work)
1804{
1805 struct b43_wl *wl = container_of(work, struct b43_wl,
1806 beacon_update_trigger);
1807 struct b43_wldev *dev;
1808
1809 mutex_lock(&wl->mutex);
1810 dev = wl->current_dev;
1811 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1812 if (b43_bus_host_is_sdio(dev->dev)) {
1813 /* wl->mutex is enough. */
1814 b43_do_beacon_update_trigger_work(dev);
1815 mmiowb();
1816 } else {
1817 spin_lock_irq(&wl->hardirq_lock);
1818 b43_do_beacon_update_trigger_work(dev);
1819 mmiowb();
1820 spin_unlock_irq(&wl->hardirq_lock);
1821 }
1822 }
1823 mutex_unlock(&wl->mutex);
1824}
1825
1826/* Asynchronously update the packet templates in template RAM. */
1827static void b43_update_templates(struct b43_wl *wl)
1828{
1829 struct sk_buff *beacon, *old_beacon;
1830 unsigned long flags;
1831
1832 /* This is the top half of the asynchronous beacon update.
1833 * The bottom half is the beacon IRQ.
1834 * Beacon update must be asynchronous to avoid sending an
1835 * invalid beacon. This can happen for example, if the firmware
1836 * transmits a beacon while we are updating it. */
1837
1838 /* We could modify the existing beacon and set the aid bit in
1839 * the TIM field, but that would probably require resizing and
1840 * moving of data within the beacon template.
1841 * Simply request a new beacon and let mac80211 do the hard work. */
1842 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1843 if (unlikely(!beacon))
1844 return;
1845
1846 spin_lock_irqsave(&wl->beacon_lock, flags);
1847 old_beacon = wl->current_beacon;
1848 wl->current_beacon = beacon;
1849 wl->beacon0_uploaded = false;
1850 wl->beacon1_uploaded = false;
1851 spin_unlock_irqrestore(&wl->beacon_lock, flags);
1852
1853 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1854
1855 if (old_beacon)
1856 dev_kfree_skb_any(old_beacon);
1857}
1858
1859static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1860{
1861 b43_time_lock(dev);
1862 if (dev->dev->core_rev >= 3) {
1863 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1864 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1865 } else {
1866 b43_write16(dev, 0x606, (beacon_int >> 6));
1867 b43_write16(dev, 0x610, beacon_int);
1868 }
1869 b43_time_unlock(dev);
1870 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1871}
1872
1873static void b43_handle_firmware_panic(struct b43_wldev *dev)
1874{
1875 u16 reason;
1876
1877 /* Read the register that contains the reason code for the panic. */
1878 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1879 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1880
1881 switch (reason) {
1882 default:
1883 b43dbg(dev->wl, "The panic reason is unknown.\n");
1884 /* fallthrough */
1885 case B43_FWPANIC_DIE:
1886 /* Do not restart the controller or firmware.
1887 * The device is nonfunctional from now on.
1888 * Restarting would result in this panic to trigger again,
1889 * so we avoid that recursion. */
1890 break;
1891 case B43_FWPANIC_RESTART:
1892 b43_controller_restart(dev, "Microcode panic");
1893 break;
1894 }
1895}
1896
1897static void handle_irq_ucode_debug(struct b43_wldev *dev)
1898{
1899 unsigned int i, cnt;
1900 u16 reason, marker_id, marker_line;
1901 __le16 *buf;
1902
1903 /* The proprietary firmware doesn't have this IRQ. */
1904 if (!dev->fw.opensource)
1905 return;
1906
1907 /* Read the register that contains the reason code for this IRQ. */
1908 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1909
1910 switch (reason) {
1911 case B43_DEBUGIRQ_PANIC:
1912 b43_handle_firmware_panic(dev);
1913 break;
1914 case B43_DEBUGIRQ_DUMP_SHM:
1915 if (!B43_DEBUG)
1916 break; /* Only with driver debugging enabled. */
1917 buf = kmalloc(4096, GFP_ATOMIC);
1918 if (!buf) {
1919 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1920 goto out;
1921 }
1922 for (i = 0; i < 4096; i += 2) {
1923 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1924 buf[i / 2] = cpu_to_le16(tmp);
1925 }
1926 b43info(dev->wl, "Shared memory dump:\n");
1927 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1928 16, 2, buf, 4096, 1);
1929 kfree(buf);
1930 break;
1931 case B43_DEBUGIRQ_DUMP_REGS:
1932 if (!B43_DEBUG)
1933 break; /* Only with driver debugging enabled. */
1934 b43info(dev->wl, "Microcode register dump:\n");
1935 for (i = 0, cnt = 0; i < 64; i++) {
1936 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1937 if (cnt == 0)
1938 printk(KERN_INFO);
1939 printk("r%02u: 0x%04X ", i, tmp);
1940 cnt++;
1941 if (cnt == 6) {
1942 printk("\n");
1943 cnt = 0;
1944 }
1945 }
1946 printk("\n");
1947 break;
1948 case B43_DEBUGIRQ_MARKER:
1949 if (!B43_DEBUG)
1950 break; /* Only with driver debugging enabled. */
1951 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1952 B43_MARKER_ID_REG);
1953 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1954 B43_MARKER_LINE_REG);
1955 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1956 "at line number %u\n",
1957 marker_id, marker_line);
1958 break;
1959 default:
1960 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1961 reason);
1962 }
1963out:
1964 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1965 b43_shm_write16(dev, B43_SHM_SCRATCH,
1966 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1967}
1968
1969static void b43_do_interrupt_thread(struct b43_wldev *dev)
1970{
1971 u32 reason;
1972 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1973 u32 merged_dma_reason = 0;
1974 int i;
1975
1976 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1977 return;
1978
1979 reason = dev->irq_reason;
1980 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1981 dma_reason[i] = dev->dma_reason[i];
1982 merged_dma_reason |= dma_reason[i];
1983 }
1984
1985 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1986 b43err(dev->wl, "MAC transmission error\n");
1987
1988 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1989 b43err(dev->wl, "PHY transmission error\n");
1990 rmb();
1991 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1992 atomic_set(&dev->phy.txerr_cnt,
1993 B43_PHY_TX_BADNESS_LIMIT);
1994 b43err(dev->wl, "Too many PHY TX errors, "
1995 "restarting the controller\n");
1996 b43_controller_restart(dev, "PHY TX errors");
1997 }
1998 }
1999
2000 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
2001 b43err(dev->wl,
2002 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
2003 dma_reason[0], dma_reason[1],
2004 dma_reason[2], dma_reason[3],
2005 dma_reason[4], dma_reason[5]);
2006 b43err(dev->wl, "This device does not support DMA "
2007 "on your system. It will now be switched to PIO.\n");
2008 /* Fall back to PIO transfers if we get fatal DMA errors! */
2009 dev->use_pio = true;
2010 b43_controller_restart(dev, "DMA error");
2011 return;
2012 }
2013
2014 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
2015 handle_irq_ucode_debug(dev);
2016 if (reason & B43_IRQ_TBTT_INDI)
2017 handle_irq_tbtt_indication(dev);
2018 if (reason & B43_IRQ_ATIM_END)
2019 handle_irq_atim_end(dev);
2020 if (reason & B43_IRQ_BEACON)
2021 handle_irq_beacon(dev);
2022 if (reason & B43_IRQ_PMQ)
2023 handle_irq_pmq(dev);
2024 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
2025 ;/* TODO */
2026 if (reason & B43_IRQ_NOISESAMPLE_OK)
2027 handle_irq_noise(dev);
2028
2029 /* Check the DMA reason registers for received data. */
2030 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
2031 if (B43_DEBUG)
2032 b43warn(dev->wl, "RX descriptor underrun\n");
2033 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
2034 }
2035 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
2036 if (b43_using_pio_transfers(dev))
2037 b43_pio_rx(dev->pio.rx_queue);
2038 else
2039 b43_dma_rx(dev->dma.rx_ring);
2040 }
2041 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
2042 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
2043 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
2044 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
2045 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
2046
2047 if (reason & B43_IRQ_TX_OK)
2048 handle_irq_transmit_status(dev);
2049
2050 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
2051 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2052
2053#if B43_DEBUG
2054 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2055 dev->irq_count++;
2056 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2057 if (reason & (1 << i))
2058 dev->irq_bit_count[i]++;
2059 }
2060 }
2061#endif
2062}
2063
2064/* Interrupt thread handler. Handles device interrupts in thread context. */
2065static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
2066{
2067 struct b43_wldev *dev = dev_id;
2068
2069 mutex_lock(&dev->wl->mutex);
2070 b43_do_interrupt_thread(dev);
2071 mmiowb();
2072 mutex_unlock(&dev->wl->mutex);
2073
2074 return IRQ_HANDLED;
2075}
2076
2077static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
2078{
2079 u32 reason;
2080
2081 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2082 * On SDIO, this runs under wl->mutex. */
2083
2084 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2085 if (reason == 0xffffffff) /* shared IRQ */
2086 return IRQ_NONE;
2087 reason &= dev->irq_mask;
2088 if (!reason)
2089 return IRQ_NONE;
2090
2091 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2092 & 0x0001FC00;
2093 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2094 & 0x0000DC00;
2095 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2096 & 0x0000DC00;
2097 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2098 & 0x0001DC00;
2099 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2100 & 0x0000DC00;
2101/* Unused ring
2102 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2103 & 0x0000DC00;
2104*/
2105
2106 /* ACK the interrupt. */
2107 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2108 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2109 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2110 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2111 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2112 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2113/* Unused ring
2114 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2115*/
2116
2117 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2118 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2119 /* Save the reason bitmasks for the IRQ thread handler. */
2120 dev->irq_reason = reason;
2121
2122 return IRQ_WAKE_THREAD;
2123}
2124
2125/* Interrupt handler top-half. This runs with interrupts disabled. */
2126static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2127{
2128 struct b43_wldev *dev = dev_id;
2129 irqreturn_t ret;
2130
2131 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2132 return IRQ_NONE;
2133
2134 spin_lock(&dev->wl->hardirq_lock);
2135 ret = b43_do_interrupt(dev);
2136 mmiowb();
2137 spin_unlock(&dev->wl->hardirq_lock);
2138
2139 return ret;
2140}
2141
2142/* SDIO interrupt handler. This runs in process context. */
2143static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2144{
2145 struct b43_wl *wl = dev->wl;
2146 irqreturn_t ret;
2147
2148 mutex_lock(&wl->mutex);
2149
2150 ret = b43_do_interrupt(dev);
2151 if (ret == IRQ_WAKE_THREAD)
2152 b43_do_interrupt_thread(dev);
2153
2154 mutex_unlock(&wl->mutex);
2155}
2156
2157void b43_do_release_fw(struct b43_firmware_file *fw)
2158{
2159 release_firmware(fw->data);
2160 fw->data = NULL;
2161 fw->filename = NULL;
2162}
2163
2164static void b43_release_firmware(struct b43_wldev *dev)
2165{
2166 complete(&dev->fw_load_complete);
2167 b43_do_release_fw(&dev->fw.ucode);
2168 b43_do_release_fw(&dev->fw.pcm);
2169 b43_do_release_fw(&dev->fw.initvals);
2170 b43_do_release_fw(&dev->fw.initvals_band);
2171}
2172
2173static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2174{
2175 const char text[] =
2176 "You must go to " \
2177 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2178 "and download the correct firmware for this driver version. " \
2179 "Please carefully read all instructions on this website.\n";
2180
2181 if (error)
2182 b43err(wl, text);
2183 else
2184 b43warn(wl, text);
2185}
2186
2187static void b43_fw_cb(const struct firmware *firmware, void *context)
2188{
2189 struct b43_request_fw_context *ctx = context;
2190
2191 ctx->blob = firmware;
2192 complete(&ctx->dev->fw_load_complete);
2193}
2194
2195int b43_do_request_fw(struct b43_request_fw_context *ctx,
2196 const char *name,
2197 struct b43_firmware_file *fw, bool async)
2198{
2199 struct b43_fw_header *hdr;
2200 u32 size;
2201 int err;
2202
2203 if (!name) {
2204 /* Don't fetch anything. Free possibly cached firmware. */
2205 /* FIXME: We should probably keep it anyway, to save some headache
2206 * on suspend/resume with multiband devices. */
2207 b43_do_release_fw(fw);
2208 return 0;
2209 }
2210 if (fw->filename) {
2211 if ((fw->type == ctx->req_type) &&
2212 (strcmp(fw->filename, name) == 0))
2213 return 0; /* Already have this fw. */
2214 /* Free the cached firmware first. */
2215 /* FIXME: We should probably do this later after we successfully
2216 * got the new fw. This could reduce headache with multiband devices.
2217 * We could also redesign this to cache the firmware for all possible
2218 * bands all the time. */
2219 b43_do_release_fw(fw);
2220 }
2221
2222 switch (ctx->req_type) {
2223 case B43_FWTYPE_PROPRIETARY:
2224 snprintf(ctx->fwname, sizeof(ctx->fwname),
2225 "b43%s/%s.fw",
2226 modparam_fwpostfix, name);
2227 break;
2228 case B43_FWTYPE_OPENSOURCE:
2229 snprintf(ctx->fwname, sizeof(ctx->fwname),
2230 "b43-open%s/%s.fw",
2231 modparam_fwpostfix, name);
2232 break;
2233 default:
2234 B43_WARN_ON(1);
2235 return -ENOSYS;
2236 }
2237 if (async) {
2238 /* do this part asynchronously */
2239 init_completion(&ctx->dev->fw_load_complete);
2240 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2241 ctx->dev->dev->dev, GFP_KERNEL,
2242 ctx, b43_fw_cb);
2243 if (err < 0) {
2244 pr_err("Unable to load firmware\n");
2245 return err;
2246 }
2247 wait_for_completion(&ctx->dev->fw_load_complete);
2248 if (ctx->blob)
2249 goto fw_ready;
2250 /* On some ARM systems, the async request will fail, but the next sync
2251 * request works. For this reason, we fall through here
2252 */
2253 }
2254 err = request_firmware(&ctx->blob, ctx->fwname,
2255 ctx->dev->dev->dev);
2256 if (err == -ENOENT) {
2257 snprintf(ctx->errors[ctx->req_type],
2258 sizeof(ctx->errors[ctx->req_type]),
2259 "Firmware file \"%s\" not found\n",
2260 ctx->fwname);
2261 return err;
2262 } else if (err) {
2263 snprintf(ctx->errors[ctx->req_type],
2264 sizeof(ctx->errors[ctx->req_type]),
2265 "Firmware file \"%s\" request failed (err=%d)\n",
2266 ctx->fwname, err);
2267 return err;
2268 }
2269fw_ready:
2270 if (ctx->blob->size < sizeof(struct b43_fw_header))
2271 goto err_format;
2272 hdr = (struct b43_fw_header *)(ctx->blob->data);
2273 switch (hdr->type) {
2274 case B43_FW_TYPE_UCODE:
2275 case B43_FW_TYPE_PCM:
2276 size = be32_to_cpu(hdr->size);
2277 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2278 goto err_format;
2279 /* fallthrough */
2280 case B43_FW_TYPE_IV:
2281 if (hdr->ver != 1)
2282 goto err_format;
2283 break;
2284 default:
2285 goto err_format;
2286 }
2287
2288 fw->data = ctx->blob;
2289 fw->filename = name;
2290 fw->type = ctx->req_type;
2291
2292 return 0;
2293
2294err_format:
2295 snprintf(ctx->errors[ctx->req_type],
2296 sizeof(ctx->errors[ctx->req_type]),
2297 "Firmware file \"%s\" format error.\n", ctx->fwname);
2298 release_firmware(ctx->blob);
2299
2300 return -EPROTO;
2301}
2302
2303/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
2304static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2305{
2306 struct b43_wldev *dev = ctx->dev;
2307 struct b43_firmware *fw = &ctx->dev->fw;
2308 struct b43_phy *phy = &dev->phy;
2309 const u8 rev = ctx->dev->dev->core_rev;
2310 const char *filename;
2311 int err;
2312
2313 /* Get microcode */
2314 filename = NULL;
2315 switch (rev) {
2316 case 42:
2317 if (phy->type == B43_PHYTYPE_AC)
2318 filename = "ucode42";
2319 break;
2320 case 40:
2321 if (phy->type == B43_PHYTYPE_AC)
2322 filename = "ucode40";
2323 break;
2324 case 33:
2325 if (phy->type == B43_PHYTYPE_LCN40)
2326 filename = "ucode33_lcn40";
2327 break;
2328 case 30:
2329 if (phy->type == B43_PHYTYPE_N)
2330 filename = "ucode30_mimo";
2331 break;
2332 case 29:
2333 if (phy->type == B43_PHYTYPE_HT)
2334 filename = "ucode29_mimo";
2335 break;
2336 case 26:
2337 if (phy->type == B43_PHYTYPE_HT)
2338 filename = "ucode26_mimo";
2339 break;
2340 case 28:
2341 case 25:
2342 if (phy->type == B43_PHYTYPE_N)
2343 filename = "ucode25_mimo";
2344 else if (phy->type == B43_PHYTYPE_LCN)
2345 filename = "ucode25_lcn";
2346 break;
2347 case 24:
2348 if (phy->type == B43_PHYTYPE_LCN)
2349 filename = "ucode24_lcn";
2350 break;
2351 case 23:
2352 if (phy->type == B43_PHYTYPE_N)
2353 filename = "ucode16_mimo";
2354 break;
2355 case 16 ... 19:
2356 if (phy->type == B43_PHYTYPE_N)
2357 filename = "ucode16_mimo";
2358 else if (phy->type == B43_PHYTYPE_LP)
2359 filename = "ucode16_lp";
2360 break;
2361 case 15:
2362 filename = "ucode15";
2363 break;
2364 case 14:
2365 filename = "ucode14";
2366 break;
2367 case 13:
2368 filename = "ucode13";
2369 break;
2370 case 11 ... 12:
2371 filename = "ucode11";
2372 break;
2373 case 5 ... 10:
2374 filename = "ucode5";
2375 break;
2376 }
2377 if (!filename)
2378 goto err_no_ucode;
2379 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2380 if (err)
2381 goto err_load;
2382
2383 /* Get PCM code */
2384 if ((rev >= 5) && (rev <= 10))
2385 filename = "pcm5";
2386 else if (rev >= 11)
2387 filename = NULL;
2388 else
2389 goto err_no_pcm;
2390 fw->pcm_request_failed = false;
2391 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2392 if (err == -ENOENT) {
2393 /* We did not find a PCM file? Not fatal, but
2394 * core rev <= 10 must do without hwcrypto then. */
2395 fw->pcm_request_failed = true;
2396 } else if (err)
2397 goto err_load;
2398
2399 /* Get initvals */
2400 filename = NULL;
2401 switch (dev->phy.type) {
2402 case B43_PHYTYPE_G:
2403 if (rev == 13)
2404 filename = "b0g0initvals13";
2405 else if (rev >= 5 && rev <= 10)
2406 filename = "b0g0initvals5";
2407 break;
2408 case B43_PHYTYPE_N:
2409 if (rev == 30)
2410 filename = "n16initvals30";
2411 else if (rev == 28 || rev == 25)
2412 filename = "n0initvals25";
2413 else if (rev == 24)
2414 filename = "n0initvals24";
2415 else if (rev == 23)
2416 filename = "n0initvals16"; /* What about n0initvals22? */
2417 else if (rev >= 16 && rev <= 18)
2418 filename = "n0initvals16";
2419 else if (rev >= 11 && rev <= 12)
2420 filename = "n0initvals11";
2421 break;
2422 case B43_PHYTYPE_LP:
2423 if (rev >= 16 && rev <= 18)
2424 filename = "lp0initvals16";
2425 else if (rev == 15)
2426 filename = "lp0initvals15";
2427 else if (rev == 14)
2428 filename = "lp0initvals14";
2429 else if (rev == 13)
2430 filename = "lp0initvals13";
2431 break;
2432 case B43_PHYTYPE_HT:
2433 if (rev == 29)
2434 filename = "ht0initvals29";
2435 else if (rev == 26)
2436 filename = "ht0initvals26";
2437 break;
2438 case B43_PHYTYPE_LCN:
2439 if (rev == 24)
2440 filename = "lcn0initvals24";
2441 break;
2442 case B43_PHYTYPE_LCN40:
2443 if (rev == 33)
2444 filename = "lcn400initvals33";
2445 break;
2446 case B43_PHYTYPE_AC:
2447 if (rev == 42)
2448 filename = "ac1initvals42";
2449 else if (rev == 40)
2450 filename = "ac0initvals40";
2451 break;
2452 }
2453 if (!filename)
2454 goto err_no_initvals;
2455 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2456 if (err)
2457 goto err_load;
2458
2459 /* Get bandswitch initvals */
2460 filename = NULL;
2461 switch (dev->phy.type) {
2462 case B43_PHYTYPE_G:
2463 if (rev == 13)
2464 filename = "b0g0bsinitvals13";
2465 else if (rev >= 5 && rev <= 10)
2466 filename = "b0g0bsinitvals5";
2467 break;
2468 case B43_PHYTYPE_N:
2469 if (rev == 30)
2470 filename = "n16bsinitvals30";
2471 else if (rev == 28 || rev == 25)
2472 filename = "n0bsinitvals25";
2473 else if (rev == 24)
2474 filename = "n0bsinitvals24";
2475 else if (rev == 23)
2476 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2477 else if (rev >= 16 && rev <= 18)
2478 filename = "n0bsinitvals16";
2479 else if (rev >= 11 && rev <= 12)
2480 filename = "n0bsinitvals11";
2481 break;
2482 case B43_PHYTYPE_LP:
2483 if (rev >= 16 && rev <= 18)
2484 filename = "lp0bsinitvals16";
2485 else if (rev == 15)
2486 filename = "lp0bsinitvals15";
2487 else if (rev == 14)
2488 filename = "lp0bsinitvals14";
2489 else if (rev == 13)
2490 filename = "lp0bsinitvals13";
2491 break;
2492 case B43_PHYTYPE_HT:
2493 if (rev == 29)
2494 filename = "ht0bsinitvals29";
2495 else if (rev == 26)
2496 filename = "ht0bsinitvals26";
2497 break;
2498 case B43_PHYTYPE_LCN:
2499 if (rev == 24)
2500 filename = "lcn0bsinitvals24";
2501 break;
2502 case B43_PHYTYPE_LCN40:
2503 if (rev == 33)
2504 filename = "lcn400bsinitvals33";
2505 break;
2506 case B43_PHYTYPE_AC:
2507 if (rev == 42)
2508 filename = "ac1bsinitvals42";
2509 else if (rev == 40)
2510 filename = "ac0bsinitvals40";
2511 break;
2512 }
2513 if (!filename)
2514 goto err_no_initvals;
2515 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2516 if (err)
2517 goto err_load;
2518
2519 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2520
2521 return 0;
2522
2523err_no_ucode:
2524 err = ctx->fatal_failure = -EOPNOTSUPP;
2525 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2526 "is required for your device (wl-core rev %u)\n", rev);
2527 goto error;
2528
2529err_no_pcm:
2530 err = ctx->fatal_failure = -EOPNOTSUPP;
2531 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2532 "is required for your device (wl-core rev %u)\n", rev);
2533 goto error;
2534
2535err_no_initvals:
2536 err = ctx->fatal_failure = -EOPNOTSUPP;
2537 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2538 "is required for your device (wl-core rev %u)\n", rev);
2539 goto error;
2540
2541err_load:
2542 /* We failed to load this firmware image. The error message
2543 * already is in ctx->errors. Return and let our caller decide
2544 * what to do. */
2545 goto error;
2546
2547error:
2548 b43_release_firmware(dev);
2549 return err;
2550}
2551
2552static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2553static void b43_one_core_detach(struct b43_bus_dev *dev);
2554static int b43_rng_init(struct b43_wl *wl);
2555
2556static void b43_request_firmware(struct work_struct *work)
2557{
2558 struct b43_wl *wl = container_of(work,
2559 struct b43_wl, firmware_load);
2560 struct b43_wldev *dev = wl->current_dev;
2561 struct b43_request_fw_context *ctx;
2562 unsigned int i;
2563 int err;
2564 const char *errmsg;
2565
2566 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2567 if (!ctx)
2568 return;
2569 ctx->dev = dev;
2570
2571 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2572 err = b43_try_request_fw(ctx);
2573 if (!err)
2574 goto start_ieee80211; /* Successfully loaded it. */
2575 /* Was fw version known? */
2576 if (ctx->fatal_failure)
2577 goto out;
2578
2579 /* proprietary fw not found, try open source */
2580 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2581 err = b43_try_request_fw(ctx);
2582 if (!err)
2583 goto start_ieee80211; /* Successfully loaded it. */
2584 if(ctx->fatal_failure)
2585 goto out;
2586
2587 /* Could not find a usable firmware. Print the errors. */
2588 for (i = 0; i < B43_NR_FWTYPES; i++) {
2589 errmsg = ctx->errors[i];
2590 if (strlen(errmsg))
2591 b43err(dev->wl, "%s", errmsg);
2592 }
2593 b43_print_fw_helptext(dev->wl, 1);
2594 goto out;
2595
2596start_ieee80211:
2597 wl->hw->queues = B43_QOS_QUEUE_NUM;
2598 if (!modparam_qos || dev->fw.opensource)
2599 wl->hw->queues = 1;
2600
2601 err = ieee80211_register_hw(wl->hw);
2602 if (err)
2603 goto err_one_core_detach;
2604 wl->hw_registred = true;
2605 b43_leds_register(wl->current_dev);
2606
2607 /* Register HW RNG driver */
2608 b43_rng_init(wl);
2609
2610 goto out;
2611
2612err_one_core_detach:
2613 b43_one_core_detach(dev->dev);
2614
2615out:
2616 kfree(ctx);
2617}
2618
2619static int b43_upload_microcode(struct b43_wldev *dev)
2620{
2621 struct wiphy *wiphy = dev->wl->hw->wiphy;
2622 const size_t hdr_len = sizeof(struct b43_fw_header);
2623 const __be32 *data;
2624 unsigned int i, len;
2625 u16 fwrev, fwpatch, fwdate, fwtime;
2626 u32 tmp, macctl;
2627 int err = 0;
2628
2629 /* Jump the microcode PSM to offset 0 */
2630 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2631 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2632 macctl |= B43_MACCTL_PSM_JMP0;
2633 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2634 /* Zero out all microcode PSM registers and shared memory. */
2635 for (i = 0; i < 64; i++)
2636 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2637 for (i = 0; i < 4096; i += 2)
2638 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2639
2640 /* Upload Microcode. */
2641 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2642 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2643 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2644 for (i = 0; i < len; i++) {
2645 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2646 udelay(10);
2647 }
2648
2649 if (dev->fw.pcm.data) {
2650 /* Upload PCM data. */
2651 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2652 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2653 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2654 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2655 /* No need for autoinc bit in SHM_HW */
2656 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2657 for (i = 0; i < len; i++) {
2658 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2659 udelay(10);
2660 }
2661 }
2662
2663 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2664
2665 /* Start the microcode PSM */
2666 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2667 B43_MACCTL_PSM_RUN);
2668
2669 /* Wait for the microcode to load and respond */
2670 i = 0;
2671 while (1) {
2672 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2673 if (tmp == B43_IRQ_MAC_SUSPENDED)
2674 break;
2675 i++;
2676 if (i >= 20) {
2677 b43err(dev->wl, "Microcode not responding\n");
2678 b43_print_fw_helptext(dev->wl, 1);
2679 err = -ENODEV;
2680 goto error;
2681 }
2682 msleep(50);
2683 }
2684 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2685
2686 /* Get and check the revisions. */
2687 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2688 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2689 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2690 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2691
2692 if (fwrev <= 0x128) {
2693 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2694 "binary drivers older than version 4.x is unsupported. "
2695 "You must upgrade your firmware files.\n");
2696 b43_print_fw_helptext(dev->wl, 1);
2697 err = -EOPNOTSUPP;
2698 goto error;
2699 }
2700 dev->fw.rev = fwrev;
2701 dev->fw.patch = fwpatch;
2702 if (dev->fw.rev >= 598)
2703 dev->fw.hdr_format = B43_FW_HDR_598;
2704 else if (dev->fw.rev >= 410)
2705 dev->fw.hdr_format = B43_FW_HDR_410;
2706 else
2707 dev->fw.hdr_format = B43_FW_HDR_351;
2708 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2709
2710 dev->qos_enabled = dev->wl->hw->queues > 1;
2711 /* Default to firmware/hardware crypto acceleration. */
2712 dev->hwcrypto_enabled = true;
2713
2714 if (dev->fw.opensource) {
2715 u16 fwcapa;
2716
2717 /* Patchlevel info is encoded in the "time" field. */
2718 dev->fw.patch = fwtime;
2719 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2720 dev->fw.rev, dev->fw.patch);
2721
2722 fwcapa = b43_fwcapa_read(dev);
2723 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2724 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2725 /* Disable hardware crypto and fall back to software crypto. */
2726 dev->hwcrypto_enabled = false;
2727 }
2728 /* adding QoS support should use an offline discovery mechanism */
2729 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2730 } else {
2731 b43info(dev->wl, "Loading firmware version %u.%u "
2732 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2733 fwrev, fwpatch,
2734 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2735 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2736 if (dev->fw.pcm_request_failed) {
2737 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2738 "Hardware accelerated cryptography is disabled.\n");
2739 b43_print_fw_helptext(dev->wl, 0);
2740 }
2741 }
2742
2743 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2744 dev->fw.rev, dev->fw.patch);
2745 wiphy->hw_version = dev->dev->core_id;
2746
2747 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2748 /* We're over the deadline, but we keep support for old fw
2749 * until it turns out to be in major conflict with something new. */
2750 b43warn(dev->wl, "You are using an old firmware image. "
2751 "Support for old firmware will be removed soon "
2752 "(official deadline was July 2008).\n");
2753 b43_print_fw_helptext(dev->wl, 0);
2754 }
2755
2756 return 0;
2757
2758error:
2759 /* Stop the microcode PSM. */
2760 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2761 B43_MACCTL_PSM_JMP0);
2762
2763 return err;
2764}
2765
2766static int b43_write_initvals(struct b43_wldev *dev,
2767 const struct b43_iv *ivals,
2768 size_t count,
2769 size_t array_size)
2770{
2771 const struct b43_iv *iv;
2772 u16 offset;
2773 size_t i;
2774 bool bit32;
2775
2776 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2777 iv = ivals;
2778 for (i = 0; i < count; i++) {
2779 if (array_size < sizeof(iv->offset_size))
2780 goto err_format;
2781 array_size -= sizeof(iv->offset_size);
2782 offset = be16_to_cpu(iv->offset_size);
2783 bit32 = !!(offset & B43_IV_32BIT);
2784 offset &= B43_IV_OFFSET_MASK;
2785 if (offset >= 0x1000)
2786 goto err_format;
2787 if (bit32) {
2788 u32 value;
2789
2790 if (array_size < sizeof(iv->data.d32))
2791 goto err_format;
2792 array_size -= sizeof(iv->data.d32);
2793
2794 value = get_unaligned_be32(&iv->data.d32);
2795 b43_write32(dev, offset, value);
2796
2797 iv = (const struct b43_iv *)((const uint8_t *)iv +
2798 sizeof(__be16) +
2799 sizeof(__be32));
2800 } else {
2801 u16 value;
2802
2803 if (array_size < sizeof(iv->data.d16))
2804 goto err_format;
2805 array_size -= sizeof(iv->data.d16);
2806
2807 value = be16_to_cpu(iv->data.d16);
2808 b43_write16(dev, offset, value);
2809
2810 iv = (const struct b43_iv *)((const uint8_t *)iv +
2811 sizeof(__be16) +
2812 sizeof(__be16));
2813 }
2814 }
2815 if (array_size)
2816 goto err_format;
2817
2818 return 0;
2819
2820err_format:
2821 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2822 b43_print_fw_helptext(dev->wl, 1);
2823
2824 return -EPROTO;
2825}
2826
2827static int b43_upload_initvals(struct b43_wldev *dev)
2828{
2829 const size_t hdr_len = sizeof(struct b43_fw_header);
2830 const struct b43_fw_header *hdr;
2831 struct b43_firmware *fw = &dev->fw;
2832 const struct b43_iv *ivals;
2833 size_t count;
2834
2835 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2836 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2837 count = be32_to_cpu(hdr->size);
2838 return b43_write_initvals(dev, ivals, count,
2839 fw->initvals.data->size - hdr_len);
2840}
2841
2842static int b43_upload_initvals_band(struct b43_wldev *dev)
2843{
2844 const size_t hdr_len = sizeof(struct b43_fw_header);
2845 const struct b43_fw_header *hdr;
2846 struct b43_firmware *fw = &dev->fw;
2847 const struct b43_iv *ivals;
2848 size_t count;
2849
2850 if (!fw->initvals_band.data)
2851 return 0;
2852
2853 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2854 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2855 count = be32_to_cpu(hdr->size);
2856 return b43_write_initvals(dev, ivals, count,
2857 fw->initvals_band.data->size - hdr_len);
2858}
2859
2860/* Initialize the GPIOs
2861 * http://bcm-specs.sipsolutions.net/GPIO
2862 */
2863
2864#ifdef CONFIG_B43_SSB
2865static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2866{
2867 struct ssb_bus *bus = dev->dev->sdev->bus;
2868
2869#ifdef CONFIG_SSB_DRIVER_PCICORE
2870 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2871#else
2872 return bus->chipco.dev;
2873#endif
2874}
2875#endif
2876
2877static int b43_gpio_init(struct b43_wldev *dev)
2878{
2879#ifdef CONFIG_B43_SSB
2880 struct ssb_device *gpiodev;
2881#endif
2882 u32 mask, set;
2883
2884 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2885 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2886
2887 mask = 0x0000001F;
2888 set = 0x0000000F;
2889 if (dev->dev->chip_id == 0x4301) {
2890 mask |= 0x0060;
2891 set |= 0x0060;
2892 } else if (dev->dev->chip_id == 0x5354) {
2893 /* Don't allow overtaking buttons GPIOs */
2894 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2895 }
2896
2897 if (0 /* FIXME: conditional unknown */ ) {
2898 b43_write16(dev, B43_MMIO_GPIO_MASK,
2899 b43_read16(dev, B43_MMIO_GPIO_MASK)
2900 | 0x0100);
2901 /* BT Coexistance Input */
2902 mask |= 0x0080;
2903 set |= 0x0080;
2904 /* BT Coexistance Out */
2905 mask |= 0x0100;
2906 set |= 0x0100;
2907 }
2908 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2909 /* PA is controlled by gpio 9, let ucode handle it */
2910 b43_write16(dev, B43_MMIO_GPIO_MASK,
2911 b43_read16(dev, B43_MMIO_GPIO_MASK)
2912 | 0x0200);
2913 mask |= 0x0200;
2914 set |= 0x0200;
2915 }
2916
2917 switch (dev->dev->bus_type) {
2918#ifdef CONFIG_B43_BCMA
2919 case B43_BUS_BCMA:
2920 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2921 break;
2922#endif
2923#ifdef CONFIG_B43_SSB
2924 case B43_BUS_SSB:
2925 gpiodev = b43_ssb_gpio_dev(dev);
2926 if (gpiodev)
2927 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2928 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2929 & ~mask) | set);
2930 break;
2931#endif
2932 }
2933
2934 return 0;
2935}
2936
2937/* Turn off all GPIO stuff. Call this on module unload, for example. */
2938static void b43_gpio_cleanup(struct b43_wldev *dev)
2939{
2940#ifdef CONFIG_B43_SSB
2941 struct ssb_device *gpiodev;
2942#endif
2943
2944 switch (dev->dev->bus_type) {
2945#ifdef CONFIG_B43_BCMA
2946 case B43_BUS_BCMA:
2947 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2948 break;
2949#endif
2950#ifdef CONFIG_B43_SSB
2951 case B43_BUS_SSB:
2952 gpiodev = b43_ssb_gpio_dev(dev);
2953 if (gpiodev)
2954 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2955 break;
2956#endif
2957 }
2958}
2959
2960/* http://bcm-specs.sipsolutions.net/EnableMac */
2961void b43_mac_enable(struct b43_wldev *dev)
2962{
2963 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2964 u16 fwstate;
2965
2966 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2967 B43_SHM_SH_UCODESTAT);
2968 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2969 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2970 b43err(dev->wl, "b43_mac_enable(): The firmware "
2971 "should be suspended, but current state is %u\n",
2972 fwstate);
2973 }
2974 }
2975
2976 dev->mac_suspended--;
2977 B43_WARN_ON(dev->mac_suspended < 0);
2978 if (dev->mac_suspended == 0) {
2979 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2980 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2981 B43_IRQ_MAC_SUSPENDED);
2982 /* Commit writes */
2983 b43_read32(dev, B43_MMIO_MACCTL);
2984 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2985 b43_power_saving_ctl_bits(dev, 0);
2986 }
2987}
2988
2989/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2990void b43_mac_suspend(struct b43_wldev *dev)
2991{
2992 int i;
2993 u32 tmp;
2994
2995 might_sleep();
2996 B43_WARN_ON(dev->mac_suspended < 0);
2997
2998 if (dev->mac_suspended == 0) {
2999 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
3000 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
3001 /* force pci to flush the write */
3002 b43_read32(dev, B43_MMIO_MACCTL);
3003 for (i = 35; i; i--) {
3004 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3005 if (tmp & B43_IRQ_MAC_SUSPENDED)
3006 goto out;
3007 udelay(10);
3008 }
3009 /* Hm, it seems this will take some time. Use msleep(). */
3010 for (i = 40; i; i--) {
3011 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3012 if (tmp & B43_IRQ_MAC_SUSPENDED)
3013 goto out;
3014 msleep(1);
3015 }
3016 b43err(dev->wl, "MAC suspend failed\n");
3017 }
3018out:
3019 dev->mac_suspended++;
3020}
3021
3022/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3023void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3024{
3025 u32 tmp;
3026
3027 switch (dev->dev->bus_type) {
3028#ifdef CONFIG_B43_BCMA
3029 case B43_BUS_BCMA:
3030 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3031 if (on)
3032 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
3033 else
3034 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
3035 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3036 break;
3037#endif
3038#ifdef CONFIG_B43_SSB
3039 case B43_BUS_SSB:
3040 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3041 if (on)
3042 tmp |= B43_TMSLOW_MACPHYCLKEN;
3043 else
3044 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
3045 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3046 break;
3047#endif
3048 }
3049}
3050
3051/* brcms_b_switch_macfreq */
3052void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3053{
3054 u16 chip_id = dev->dev->chip_id;
3055
3056 if (chip_id == BCMA_CHIP_ID_BCM4331) {
3057 switch (spurmode) {
3058 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
3059 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3060 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3061 break;
3062 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
3063 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3064 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3065 break;
3066 default: /* 160 Mhz: 2^26/160 = 0x66666 */
3067 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3068 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3069 break;
3070 }
3071 } else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
3072 chip_id == BCMA_CHIP_ID_BCM43217 ||
3073 chip_id == BCMA_CHIP_ID_BCM43222 ||
3074 chip_id == BCMA_CHIP_ID_BCM43224 ||
3075 chip_id == BCMA_CHIP_ID_BCM43225 ||
3076 chip_id == BCMA_CHIP_ID_BCM43227 ||
3077 chip_id == BCMA_CHIP_ID_BCM43228) {
3078 switch (spurmode) {
3079 case 2: /* 126 Mhz */
3080 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3081 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3082 break;
3083 case 1: /* 123 Mhz */
3084 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3085 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3086 break;
3087 default: /* 120 Mhz */
3088 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3089 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3090 break;
3091 }
3092 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3093 switch (spurmode) {
3094 case 1: /* 82 Mhz */
3095 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3096 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3097 break;
3098 default: /* 80 Mhz */
3099 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3100 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3101 break;
3102 }
3103 }
3104}
3105
3106static void b43_adjust_opmode(struct b43_wldev *dev)
3107{
3108 struct b43_wl *wl = dev->wl;
3109 u32 ctl;
3110 u16 cfp_pretbtt;
3111
3112 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3113 /* Reset status to STA infrastructure mode. */
3114 ctl &= ~B43_MACCTL_AP;
3115 ctl &= ~B43_MACCTL_KEEP_CTL;
3116 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3117 ctl &= ~B43_MACCTL_KEEP_BAD;
3118 ctl &= ~B43_MACCTL_PROMISC;
3119 ctl &= ~B43_MACCTL_BEACPROMISC;
3120 ctl |= B43_MACCTL_INFRA;
3121
3122 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3123 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3124 ctl |= B43_MACCTL_AP;
3125 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
3126 ctl &= ~B43_MACCTL_INFRA;
3127
3128 if (wl->filter_flags & FIF_CONTROL)
3129 ctl |= B43_MACCTL_KEEP_CTL;
3130 if (wl->filter_flags & FIF_FCSFAIL)
3131 ctl |= B43_MACCTL_KEEP_BAD;
3132 if (wl->filter_flags & FIF_PLCPFAIL)
3133 ctl |= B43_MACCTL_KEEP_BADPLCP;
3134 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3135 ctl |= B43_MACCTL_BEACPROMISC;
3136
3137 /* Workaround: On old hardware the HW-MAC-address-filter
3138 * doesn't work properly, so always run promisc in filter
3139 * it in software. */
3140 if (dev->dev->core_rev <= 4)
3141 ctl |= B43_MACCTL_PROMISC;
3142
3143 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3144
3145 cfp_pretbtt = 2;
3146 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
3147 if (dev->dev->chip_id == 0x4306 &&
3148 dev->dev->chip_rev == 3)
3149 cfp_pretbtt = 100;
3150 else
3151 cfp_pretbtt = 50;
3152 }
3153 b43_write16(dev, 0x612, cfp_pretbtt);
3154
3155 /* FIXME: We don't currently implement the PMQ mechanism,
3156 * so always disable it. If we want to implement PMQ,
3157 * we need to enable it here (clear DISCPMQ) in AP mode.
3158 */
3159 if (0 /* ctl & B43_MACCTL_AP */)
3160 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3161 else
3162 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
3163}
3164
3165static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3166{
3167 u16 offset;
3168
3169 if (is_ofdm) {
3170 offset = 0x480;
3171 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3172 } else {
3173 offset = 0x4C0;
3174 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3175 }
3176 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3177 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3178}
3179
3180static void b43_rate_memory_init(struct b43_wldev *dev)
3181{
3182 switch (dev->phy.type) {
3183 case B43_PHYTYPE_A:
3184 case B43_PHYTYPE_G:
3185 case B43_PHYTYPE_N:
3186 case B43_PHYTYPE_LP:
3187 case B43_PHYTYPE_HT:
3188 case B43_PHYTYPE_LCN:
3189 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3190 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1);
3191 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3192 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3193 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3194 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3195 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3196 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3197 if (dev->phy.type == B43_PHYTYPE_A)
3198 break;
3199 /* fallthrough */
3200 case B43_PHYTYPE_B:
3201 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3202 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3203 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3204 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3205 break;
3206 default:
3207 B43_WARN_ON(1);
3208 }
3209}
3210
3211/* Set the default values for the PHY TX Control Words. */
3212static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3213{
3214 u16 ctl = 0;
3215
3216 ctl |= B43_TXH_PHY_ENC_CCK;
3217 ctl |= B43_TXH_PHY_ANT01AUTO;
3218 ctl |= B43_TXH_PHY_TXPWR;
3219
3220 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3221 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3222 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3223}
3224
3225/* Set the TX-Antenna for management frames sent by firmware. */
3226static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3227{
3228 u16 ant;
3229 u16 tmp;
3230
3231 ant = b43_antenna_to_phyctl(antenna);
3232
3233 /* For ACK/CTS */
3234 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3235 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3236 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3237 /* For Probe Resposes */
3238 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3239 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3240 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3241}
3242
3243/* This is the opposite of b43_chip_init() */
3244static void b43_chip_exit(struct b43_wldev *dev)
3245{
3246 b43_phy_exit(dev);
3247 b43_gpio_cleanup(dev);
3248 /* firmware is released later */
3249}
3250
3251/* Initialize the chip
3252 * http://bcm-specs.sipsolutions.net/ChipInit
3253 */
3254static int b43_chip_init(struct b43_wldev *dev)
3255{
3256 struct b43_phy *phy = &dev->phy;
3257 int err;
3258 u32 macctl;
3259 u16 value16;
3260
3261 /* Initialize the MAC control */
3262 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3263 if (dev->phy.gmode)
3264 macctl |= B43_MACCTL_GMODE;
3265 macctl |= B43_MACCTL_INFRA;
3266 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3267
3268 err = b43_upload_microcode(dev);
3269 if (err)
3270 goto out; /* firmware is released later */
3271
3272 err = b43_gpio_init(dev);
3273 if (err)
3274 goto out; /* firmware is released later */
3275
3276 err = b43_upload_initvals(dev);
3277 if (err)
3278 goto err_gpio_clean;
3279
3280 err = b43_upload_initvals_band(dev);
3281 if (err)
3282 goto err_gpio_clean;
3283
3284 /* Turn the Analog on and initialize the PHY. */
3285 phy->ops->switch_analog(dev, 1);
3286 err = b43_phy_init(dev);
3287 if (err)
3288 goto err_gpio_clean;
3289
3290 /* Disable Interference Mitigation. */
3291 if (phy->ops->interf_mitigation)
3292 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3293
3294 /* Select the antennae */
3295 if (phy->ops->set_rx_antenna)
3296 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3297 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3298
3299 if (phy->type == B43_PHYTYPE_B) {
3300 value16 = b43_read16(dev, 0x005E);
3301 value16 |= 0x0004;
3302 b43_write16(dev, 0x005E, value16);
3303 }
3304 b43_write32(dev, 0x0100, 0x01000000);
3305 if (dev->dev->core_rev < 5)
3306 b43_write32(dev, 0x010C, 0x01000000);
3307
3308 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3309 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3310
3311 /* Probe Response Timeout value */
3312 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3313 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3314
3315 /* Initially set the wireless operation mode. */
3316 b43_adjust_opmode(dev);
3317
3318 if (dev->dev->core_rev < 3) {
3319 b43_write16(dev, 0x060E, 0x0000);
3320 b43_write16(dev, 0x0610, 0x8000);
3321 b43_write16(dev, 0x0604, 0x0000);
3322 b43_write16(dev, 0x0606, 0x0200);
3323 } else {
3324 b43_write32(dev, 0x0188, 0x80000000);
3325 b43_write32(dev, 0x018C, 0x02000000);
3326 }
3327 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3328 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3329 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3330 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3331 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3332 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3333 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3334
3335 b43_mac_phy_clock_set(dev, true);
3336
3337 switch (dev->dev->bus_type) {
3338#ifdef CONFIG_B43_BCMA
3339 case B43_BUS_BCMA:
3340 /* FIXME: 0xE74 is quite common, but should be read from CC */
3341 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3342 break;
3343#endif
3344#ifdef CONFIG_B43_SSB
3345 case B43_BUS_SSB:
3346 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3347 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3348 break;
3349#endif
3350 }
3351
3352 err = 0;
3353 b43dbg(dev->wl, "Chip initialized\n");
3354out:
3355 return err;
3356
3357err_gpio_clean:
3358 b43_gpio_cleanup(dev);
3359 return err;
3360}
3361
3362static void b43_periodic_every60sec(struct b43_wldev *dev)
3363{
3364 const struct b43_phy_operations *ops = dev->phy.ops;
3365
3366 if (ops->pwork_60sec)
3367 ops->pwork_60sec(dev);
3368
3369 /* Force check the TX power emission now. */
3370 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3371}
3372
3373static void b43_periodic_every30sec(struct b43_wldev *dev)
3374{
3375 /* Update device statistics. */
3376 b43_calculate_link_quality(dev);
3377}
3378
3379static void b43_periodic_every15sec(struct b43_wldev *dev)
3380{
3381 struct b43_phy *phy = &dev->phy;
3382 u16 wdr;
3383
3384 if (dev->fw.opensource) {
3385 /* Check if the firmware is still alive.
3386 * It will reset the watchdog counter to 0 in its idle loop. */
3387 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3388 if (unlikely(wdr)) {
3389 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3390 b43_controller_restart(dev, "Firmware watchdog");
3391 return;
3392 } else {
3393 b43_shm_write16(dev, B43_SHM_SCRATCH,
3394 B43_WATCHDOG_REG, 1);
3395 }
3396 }
3397
3398 if (phy->ops->pwork_15sec)
3399 phy->ops->pwork_15sec(dev);
3400
3401 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3402 wmb();
3403
3404#if B43_DEBUG
3405 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3406 unsigned int i;
3407
3408 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3409 dev->irq_count / 15,
3410 dev->tx_count / 15,
3411 dev->rx_count / 15);
3412 dev->irq_count = 0;
3413 dev->tx_count = 0;
3414 dev->rx_count = 0;
3415 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3416 if (dev->irq_bit_count[i]) {
3417 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3418 dev->irq_bit_count[i] / 15, i, (1 << i));
3419 dev->irq_bit_count[i] = 0;
3420 }
3421 }
3422 }
3423#endif
3424}
3425
3426static void do_periodic_work(struct b43_wldev *dev)
3427{
3428 unsigned int state;
3429
3430 state = dev->periodic_state;
3431 if (state % 4 == 0)
3432 b43_periodic_every60sec(dev);
3433 if (state % 2 == 0)
3434 b43_periodic_every30sec(dev);
3435 b43_periodic_every15sec(dev);
3436}
3437
3438/* Periodic work locking policy:
3439 * The whole periodic work handler is protected by
3440 * wl->mutex. If another lock is needed somewhere in the
3441 * pwork callchain, it's acquired in-place, where it's needed.
3442 */
3443static void b43_periodic_work_handler(struct work_struct *work)
3444{
3445 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3446 periodic_work.work);
3447 struct b43_wl *wl = dev->wl;
3448 unsigned long delay;
3449
3450 mutex_lock(&wl->mutex);
3451
3452 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3453 goto out;
3454 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3455 goto out_requeue;
3456
3457 do_periodic_work(dev);
3458
3459 dev->periodic_state++;
3460out_requeue:
3461 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3462 delay = msecs_to_jiffies(50);
3463 else
3464 delay = round_jiffies_relative(HZ * 15);
3465 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3466out:
3467 mutex_unlock(&wl->mutex);
3468}
3469
3470static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3471{
3472 struct delayed_work *work = &dev->periodic_work;
3473
3474 dev->periodic_state = 0;
3475 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3476 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3477}
3478
3479/* Check if communication with the device works correctly. */
3480static int b43_validate_chipaccess(struct b43_wldev *dev)
3481{
3482 u32 v, backup0, backup4;
3483
3484 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3485 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3486
3487 /* Check for read/write and endianness problems. */
3488 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3489 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3490 goto error;
3491 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3492 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3493 goto error;
3494
3495 /* Check if unaligned 32bit SHM_SHARED access works properly.
3496 * However, don't bail out on failure, because it's noncritical. */
3497 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3498 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3499 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3500 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3501 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3502 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3503 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3504 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3505 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3506 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3507 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3508 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3509
3510 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3511 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3512
3513 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3514 /* The 32bit register shadows the two 16bit registers
3515 * with update sideeffects. Validate this. */
3516 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3517 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3518 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3519 goto error;
3520 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3521 goto error;
3522 }
3523 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3524
3525 v = b43_read32(dev, B43_MMIO_MACCTL);
3526 v |= B43_MACCTL_GMODE;
3527 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3528 goto error;
3529
3530 return 0;
3531error:
3532 b43err(dev->wl, "Failed to validate the chipaccess\n");
3533 return -ENODEV;
3534}
3535
3536static void b43_security_init(struct b43_wldev *dev)
3537{
3538 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3539 /* KTP is a word address, but we address SHM bytewise.
3540 * So multiply by two.
3541 */
3542 dev->ktp *= 2;
3543 /* Number of RCMTA address slots */
3544 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3545 /* Clear the key memory. */
3546 b43_clear_keys(dev);
3547}
3548
3549#ifdef CONFIG_B43_HWRNG
3550static int b43_rng_read(struct hwrng *rng, u32 *data)
3551{
3552 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3553 struct b43_wldev *dev;
3554 int count = -ENODEV;
3555
3556 mutex_lock(&wl->mutex);
3557 dev = wl->current_dev;
3558 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3559 *data = b43_read16(dev, B43_MMIO_RNG);
3560 count = sizeof(u16);
3561 }
3562 mutex_unlock(&wl->mutex);
3563
3564 return count;
3565}
3566#endif /* CONFIG_B43_HWRNG */
3567
3568static void b43_rng_exit(struct b43_wl *wl)
3569{
3570#ifdef CONFIG_B43_HWRNG
3571 if (wl->rng_initialized)
3572 hwrng_unregister(&wl->rng);
3573#endif /* CONFIG_B43_HWRNG */
3574}
3575
3576static int b43_rng_init(struct b43_wl *wl)
3577{
3578 int err = 0;
3579
3580#ifdef CONFIG_B43_HWRNG
3581 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3582 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3583 wl->rng.name = wl->rng_name;
3584 wl->rng.data_read = b43_rng_read;
3585 wl->rng.priv = (unsigned long)wl;
3586 wl->rng_initialized = true;
3587 err = hwrng_register(&wl->rng);
3588 if (err) {
3589 wl->rng_initialized = false;
3590 b43err(wl, "Failed to register the random "
3591 "number generator (%d)\n", err);
3592 }
3593#endif /* CONFIG_B43_HWRNG */
3594
3595 return err;
3596}
3597
3598static void b43_tx_work(struct work_struct *work)
3599{
3600 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3601 struct b43_wldev *dev;
3602 struct sk_buff *skb;
3603 int queue_num;
3604 int err = 0;
3605
3606 mutex_lock(&wl->mutex);
3607 dev = wl->current_dev;
3608 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3609 mutex_unlock(&wl->mutex);
3610 return;
3611 }
3612
3613 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3614 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3615 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3616 if (b43_using_pio_transfers(dev))
3617 err = b43_pio_tx(dev, skb);
3618 else
3619 err = b43_dma_tx(dev, skb);
3620 if (err == -ENOSPC) {
3621 wl->tx_queue_stopped[queue_num] = 1;
3622 ieee80211_stop_queue(wl->hw, queue_num);
3623 skb_queue_head(&wl->tx_queue[queue_num], skb);
3624 break;
3625 }
3626 if (unlikely(err))
3627 ieee80211_free_txskb(wl->hw, skb);
3628 err = 0;
3629 }
3630
3631 if (!err)
3632 wl->tx_queue_stopped[queue_num] = 0;
3633 }
3634
3635#if B43_DEBUG
3636 dev->tx_count++;
3637#endif
3638 mutex_unlock(&wl->mutex);
3639}
3640
3641static void b43_op_tx(struct ieee80211_hw *hw,
3642 struct ieee80211_tx_control *control,
3643 struct sk_buff *skb)
3644{
3645 struct b43_wl *wl = hw_to_b43_wl(hw);
3646
3647 if (unlikely(skb->len < 2 + 2 + 6)) {
3648 /* Too short, this can't be a valid frame. */
3649 ieee80211_free_txskb(hw, skb);
3650 return;
3651 }
3652 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3653
3654 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3655 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3656 ieee80211_queue_work(wl->hw, &wl->tx_work);
3657 } else {
3658 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3659 }
3660}
3661
3662static void b43_qos_params_upload(struct b43_wldev *dev,
3663 const struct ieee80211_tx_queue_params *p,
3664 u16 shm_offset)
3665{
3666 u16 params[B43_NR_QOSPARAMS];
3667 int bslots, tmp;
3668 unsigned int i;
3669
3670 if (!dev->qos_enabled)
3671 return;
3672
3673 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3674
3675 memset(¶ms, 0, sizeof(params));
3676
3677 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3678 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3679 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3680 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3681 params[B43_QOSPARAM_AIFS] = p->aifs;
3682 params[B43_QOSPARAM_BSLOTS] = bslots;
3683 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3684
3685 for (i = 0; i < ARRAY_SIZE(params); i++) {
3686 if (i == B43_QOSPARAM_STATUS) {
3687 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3688 shm_offset + (i * 2));
3689 /* Mark the parameters as updated. */
3690 tmp |= 0x100;
3691 b43_shm_write16(dev, B43_SHM_SHARED,
3692 shm_offset + (i * 2),
3693 tmp);
3694 } else {
3695 b43_shm_write16(dev, B43_SHM_SHARED,
3696 shm_offset + (i * 2),
3697 params[i]);
3698 }
3699 }
3700}
3701
3702/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3703static const u16 b43_qos_shm_offsets[] = {
3704 /* [mac80211-queue-nr] = SHM_OFFSET, */
3705 [0] = B43_QOS_VOICE,
3706 [1] = B43_QOS_VIDEO,
3707 [2] = B43_QOS_BESTEFFORT,
3708 [3] = B43_QOS_BACKGROUND,
3709};
3710
3711/* Update all QOS parameters in hardware. */
3712static void b43_qos_upload_all(struct b43_wldev *dev)
3713{
3714 struct b43_wl *wl = dev->wl;
3715 struct b43_qos_params *params;
3716 unsigned int i;
3717
3718 if (!dev->qos_enabled)
3719 return;
3720
3721 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3722 ARRAY_SIZE(wl->qos_params));
3723
3724 b43_mac_suspend(dev);
3725 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3726 params = &(wl->qos_params[i]);
3727 b43_qos_params_upload(dev, &(params->p),
3728 b43_qos_shm_offsets[i]);
3729 }
3730 b43_mac_enable(dev);
3731}
3732
3733static void b43_qos_clear(struct b43_wl *wl)
3734{
3735 struct b43_qos_params *params;
3736 unsigned int i;
3737
3738 /* Initialize QoS parameters to sane defaults. */
3739
3740 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3741 ARRAY_SIZE(wl->qos_params));
3742
3743 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3744 params = &(wl->qos_params[i]);
3745
3746 switch (b43_qos_shm_offsets[i]) {
3747 case B43_QOS_VOICE:
3748 params->p.txop = 0;
3749 params->p.aifs = 2;
3750 params->p.cw_min = 0x0001;
3751 params->p.cw_max = 0x0001;
3752 break;
3753 case B43_QOS_VIDEO:
3754 params->p.txop = 0;
3755 params->p.aifs = 2;
3756 params->p.cw_min = 0x0001;
3757 params->p.cw_max = 0x0001;
3758 break;
3759 case B43_QOS_BESTEFFORT:
3760 params->p.txop = 0;
3761 params->p.aifs = 3;
3762 params->p.cw_min = 0x0001;
3763 params->p.cw_max = 0x03FF;
3764 break;
3765 case B43_QOS_BACKGROUND:
3766 params->p.txop = 0;
3767 params->p.aifs = 7;
3768 params->p.cw_min = 0x0001;
3769 params->p.cw_max = 0x03FF;
3770 break;
3771 default:
3772 B43_WARN_ON(1);
3773 }
3774 }
3775}
3776
3777/* Initialize the core's QOS capabilities */
3778static void b43_qos_init(struct b43_wldev *dev)
3779{
3780 if (!dev->qos_enabled) {
3781 /* Disable QOS support. */
3782 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3783 b43_write16(dev, B43_MMIO_IFSCTL,
3784 b43_read16(dev, B43_MMIO_IFSCTL)
3785 & ~B43_MMIO_IFSCTL_USE_EDCF);
3786 b43dbg(dev->wl, "QoS disabled\n");
3787 return;
3788 }
3789
3790 /* Upload the current QOS parameters. */
3791 b43_qos_upload_all(dev);
3792
3793 /* Enable QOS support. */
3794 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3795 b43_write16(dev, B43_MMIO_IFSCTL,
3796 b43_read16(dev, B43_MMIO_IFSCTL)
3797 | B43_MMIO_IFSCTL_USE_EDCF);
3798 b43dbg(dev->wl, "QoS enabled\n");
3799}
3800
3801static int b43_op_conf_tx(struct ieee80211_hw *hw,
3802 struct ieee80211_vif *vif, u16 _queue,
3803 const struct ieee80211_tx_queue_params *params)
3804{
3805 struct b43_wl *wl = hw_to_b43_wl(hw);
3806 struct b43_wldev *dev;
3807 unsigned int queue = (unsigned int)_queue;
3808 int err = -ENODEV;
3809
3810 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3811 /* Queue not available or don't support setting
3812 * params on this queue. Return success to not
3813 * confuse mac80211. */
3814 return 0;
3815 }
3816 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3817 ARRAY_SIZE(wl->qos_params));
3818
3819 mutex_lock(&wl->mutex);
3820 dev = wl->current_dev;
3821 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3822 goto out_unlock;
3823
3824 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3825 b43_mac_suspend(dev);
3826 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3827 b43_qos_shm_offsets[queue]);
3828 b43_mac_enable(dev);
3829 err = 0;
3830
3831out_unlock:
3832 mutex_unlock(&wl->mutex);
3833
3834 return err;
3835}
3836
3837static int b43_op_get_stats(struct ieee80211_hw *hw,
3838 struct ieee80211_low_level_stats *stats)
3839{
3840 struct b43_wl *wl = hw_to_b43_wl(hw);
3841
3842 mutex_lock(&wl->mutex);
3843 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3844 mutex_unlock(&wl->mutex);
3845
3846 return 0;
3847}
3848
3849static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3850{
3851 struct b43_wl *wl = hw_to_b43_wl(hw);
3852 struct b43_wldev *dev;
3853 u64 tsf;
3854
3855 mutex_lock(&wl->mutex);
3856 dev = wl->current_dev;
3857
3858 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3859 b43_tsf_read(dev, &tsf);
3860 else
3861 tsf = 0;
3862
3863 mutex_unlock(&wl->mutex);
3864
3865 return tsf;
3866}
3867
3868static void b43_op_set_tsf(struct ieee80211_hw *hw,
3869 struct ieee80211_vif *vif, u64 tsf)
3870{
3871 struct b43_wl *wl = hw_to_b43_wl(hw);
3872 struct b43_wldev *dev;
3873
3874 mutex_lock(&wl->mutex);
3875 dev = wl->current_dev;
3876
3877 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3878 b43_tsf_write(dev, tsf);
3879
3880 mutex_unlock(&wl->mutex);
3881}
3882
3883static const char *band_to_string(enum ieee80211_band band)
3884{
3885 switch (band) {
3886 case IEEE80211_BAND_5GHZ:
3887 return "5";
3888 case IEEE80211_BAND_2GHZ:
3889 return "2.4";
3890 default:
3891 break;
3892 }
3893 B43_WARN_ON(1);
3894 return "";
3895}
3896
3897/* Expects wl->mutex locked */
3898static int b43_switch_band(struct b43_wldev *dev,
3899 struct ieee80211_channel *chan)
3900{
3901 struct b43_phy *phy = &dev->phy;
3902 bool gmode;
3903 u32 tmp;
3904
3905 switch (chan->band) {
3906 case IEEE80211_BAND_5GHZ:
3907 gmode = false;
3908 break;
3909 case IEEE80211_BAND_2GHZ:
3910 gmode = true;
3911 break;
3912 default:
3913 B43_WARN_ON(1);
3914 return -EINVAL;
3915 }
3916
3917 if (!((gmode && phy->supports_2ghz) ||
3918 (!gmode && phy->supports_5ghz))) {
3919 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3920 band_to_string(chan->band));
3921 return -ENODEV;
3922 }
3923
3924 if (!!phy->gmode == !!gmode) {
3925 /* This device is already running. */
3926 return 0;
3927 }
3928
3929 b43dbg(dev->wl, "Switching to %s GHz band\n",
3930 band_to_string(chan->band));
3931
3932 /* Some new devices don't need disabling radio for band switching */
3933 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3934 b43_software_rfkill(dev, true);
3935
3936 phy->gmode = gmode;
3937 b43_phy_put_into_reset(dev);
3938 switch (dev->dev->bus_type) {
3939#ifdef CONFIG_B43_BCMA
3940 case B43_BUS_BCMA:
3941 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3942 if (gmode)
3943 tmp |= B43_BCMA_IOCTL_GMODE;
3944 else
3945 tmp &= ~B43_BCMA_IOCTL_GMODE;
3946 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3947 break;
3948#endif
3949#ifdef CONFIG_B43_SSB
3950 case B43_BUS_SSB:
3951 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3952 if (gmode)
3953 tmp |= B43_TMSLOW_GMODE;
3954 else
3955 tmp &= ~B43_TMSLOW_GMODE;
3956 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3957 break;
3958#endif
3959 }
3960 b43_phy_take_out_of_reset(dev);
3961
3962 b43_upload_initvals_band(dev);
3963
3964 b43_phy_init(dev);
3965
3966 return 0;
3967}
3968
3969static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval)
3970{
3971 interval = min_t(u16, interval, (u16)0xFF);
3972 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval);
3973}
3974
3975/* Write the short and long frame retry limit values. */
3976static void b43_set_retry_limits(struct b43_wldev *dev,
3977 unsigned int short_retry,
3978 unsigned int long_retry)
3979{
3980 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3981 * the chip-internal counter. */
3982 short_retry = min(short_retry, (unsigned int)0xF);
3983 long_retry = min(long_retry, (unsigned int)0xF);
3984
3985 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3986 short_retry);
3987 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3988 long_retry);
3989}
3990
3991static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3992{
3993 struct b43_wl *wl = hw_to_b43_wl(hw);
3994 struct b43_wldev *dev = wl->current_dev;
3995 struct b43_phy *phy = &dev->phy;
3996 struct ieee80211_conf *conf = &hw->conf;
3997 int antenna;
3998 int err = 0;
3999
4000 mutex_lock(&wl->mutex);
4001 b43_mac_suspend(dev);
4002
4003 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL)
4004 b43_set_beacon_listen_interval(dev, conf->listen_interval);
4005
4006 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4007 phy->chandef = &conf->chandef;
4008 phy->channel = conf->chandef.chan->hw_value;
4009
4010 /* Switch the band (if necessary). */
4011 err = b43_switch_band(dev, conf->chandef.chan);
4012 if (err)
4013 goto out_mac_enable;
4014
4015 /* Switch to the requested channel.
4016 * The firmware takes care of races with the TX handler.
4017 */
4018 b43_switch_channel(dev, phy->channel);
4019 }
4020
4021 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4022 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
4023 conf->long_frame_max_tx_count);
4024 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
4025 if (!changed)
4026 goto out_mac_enable;
4027
4028 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
4029
4030 /* Adjust the desired TX power level. */
4031 if (conf->power_level != 0) {
4032 if (conf->power_level != phy->desired_txpower) {
4033 phy->desired_txpower = conf->power_level;
4034 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
4035 B43_TXPWR_IGNORE_TSSI);
4036 }
4037 }
4038
4039 /* Antennas for RX and management frame TX. */
4040 antenna = B43_ANTENNA_DEFAULT;
4041 b43_mgmtframe_txantenna(dev, antenna);
4042 antenna = B43_ANTENNA_DEFAULT;
4043 if (phy->ops->set_rx_antenna)
4044 phy->ops->set_rx_antenna(dev, antenna);
4045
4046 if (wl->radio_enabled != phy->radio_on) {
4047 if (wl->radio_enabled) {
4048 b43_software_rfkill(dev, false);
4049 b43info(dev->wl, "Radio turned on by software\n");
4050 if (!dev->radio_hw_enable) {
4051 b43info(dev->wl, "The hardware RF-kill button "
4052 "still turns the radio physically off. "
4053 "Press the button to turn it on.\n");
4054 }
4055 } else {
4056 b43_software_rfkill(dev, true);
4057 b43info(dev->wl, "Radio turned off by software\n");
4058 }
4059 }
4060
4061out_mac_enable:
4062 b43_mac_enable(dev);
4063 mutex_unlock(&wl->mutex);
4064
4065 return err;
4066}
4067
4068static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
4069{
4070 struct ieee80211_supported_band *sband =
4071 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4072 struct ieee80211_rate *rate;
4073 int i;
4074 u16 basic, direct, offset, basic_offset, rateptr;
4075
4076 for (i = 0; i < sband->n_bitrates; i++) {
4077 rate = &sband->bitrates[i];
4078
4079 if (b43_is_cck_rate(rate->hw_value)) {
4080 direct = B43_SHM_SH_CCKDIRECT;
4081 basic = B43_SHM_SH_CCKBASIC;
4082 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4083 offset &= 0xF;
4084 } else {
4085 direct = B43_SHM_SH_OFDMDIRECT;
4086 basic = B43_SHM_SH_OFDMBASIC;
4087 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4088 offset &= 0xF;
4089 }
4090
4091 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4092
4093 if (b43_is_cck_rate(rate->hw_value)) {
4094 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4095 basic_offset &= 0xF;
4096 } else {
4097 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4098 basic_offset &= 0xF;
4099 }
4100
4101 /*
4102 * Get the pointer that we need to point to
4103 * from the direct map
4104 */
4105 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4106 direct + 2 * basic_offset);
4107 /* and write it to the basic map */
4108 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4109 rateptr);
4110 }
4111}
4112
4113static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4114 struct ieee80211_vif *vif,
4115 struct ieee80211_bss_conf *conf,
4116 u32 changed)
4117{
4118 struct b43_wl *wl = hw_to_b43_wl(hw);
4119 struct b43_wldev *dev;
4120
4121 mutex_lock(&wl->mutex);
4122
4123 dev = wl->current_dev;
4124 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4125 goto out_unlock_mutex;
4126
4127 B43_WARN_ON(wl->vif != vif);
4128
4129 if (changed & BSS_CHANGED_BSSID) {
4130 if (conf->bssid)
4131 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4132 else
4133 eth_zero_addr(wl->bssid);
4134 }
4135
4136 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4137 if (changed & BSS_CHANGED_BEACON &&
4138 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4139 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4140 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4141 b43_update_templates(wl);
4142
4143 if (changed & BSS_CHANGED_BSSID)
4144 b43_write_mac_bssid_templates(dev);
4145 }
4146
4147 b43_mac_suspend(dev);
4148
4149 /* Update templates for AP/mesh mode. */
4150 if (changed & BSS_CHANGED_BEACON_INT &&
4151 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4152 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4153 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4154 conf->beacon_int)
4155 b43_set_beacon_int(dev, conf->beacon_int);
4156
4157 if (changed & BSS_CHANGED_BASIC_RATES)
4158 b43_update_basic_rates(dev, conf->basic_rates);
4159
4160 if (changed & BSS_CHANGED_ERP_SLOT) {
4161 if (conf->use_short_slot)
4162 b43_short_slot_timing_enable(dev);
4163 else
4164 b43_short_slot_timing_disable(dev);
4165 }
4166
4167 b43_mac_enable(dev);
4168out_unlock_mutex:
4169 mutex_unlock(&wl->mutex);
4170}
4171
4172static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4173 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4174 struct ieee80211_key_conf *key)
4175{
4176 struct b43_wl *wl = hw_to_b43_wl(hw);
4177 struct b43_wldev *dev;
4178 u8 algorithm;
4179 u8 index;
4180 int err;
4181 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4182
4183 if (modparam_nohwcrypt)
4184 return -ENOSPC; /* User disabled HW-crypto */
4185
4186 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4187 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4188 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4189 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4190 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4191 /*
4192 * For now, disable hw crypto for the RSN IBSS group keys. This
4193 * could be optimized in the future, but until that gets
4194 * implemented, use of software crypto for group addressed
4195 * frames is a acceptable to allow RSN IBSS to be used.
4196 */
4197 return -EOPNOTSUPP;
4198 }
4199
4200 mutex_lock(&wl->mutex);
4201
4202 dev = wl->current_dev;
4203 err = -ENODEV;
4204 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4205 goto out_unlock;
4206
4207 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4208 /* We don't have firmware for the crypto engine.
4209 * Must use software-crypto. */
4210 err = -EOPNOTSUPP;
4211 goto out_unlock;
4212 }
4213
4214 err = -EINVAL;
4215 switch (key->cipher) {
4216 case WLAN_CIPHER_SUITE_WEP40:
4217 algorithm = B43_SEC_ALGO_WEP40;
4218 break;
4219 case WLAN_CIPHER_SUITE_WEP104:
4220 algorithm = B43_SEC_ALGO_WEP104;
4221 break;
4222 case WLAN_CIPHER_SUITE_TKIP:
4223 algorithm = B43_SEC_ALGO_TKIP;
4224 break;
4225 case WLAN_CIPHER_SUITE_CCMP:
4226 algorithm = B43_SEC_ALGO_AES;
4227 break;
4228 default:
4229 B43_WARN_ON(1);
4230 goto out_unlock;
4231 }
4232 index = (u8) (key->keyidx);
4233 if (index > 3)
4234 goto out_unlock;
4235
4236 switch (cmd) {
4237 case SET_KEY:
4238 if (algorithm == B43_SEC_ALGO_TKIP &&
4239 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4240 !modparam_hwtkip)) {
4241 /* We support only pairwise key */
4242 err = -EOPNOTSUPP;
4243 goto out_unlock;
4244 }
4245
4246 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4247 if (WARN_ON(!sta)) {
4248 err = -EOPNOTSUPP;
4249 goto out_unlock;
4250 }
4251 /* Pairwise key with an assigned MAC address. */
4252 err = b43_key_write(dev, -1, algorithm,
4253 key->key, key->keylen,
4254 sta->addr, key);
4255 } else {
4256 /* Group key */
4257 err = b43_key_write(dev, index, algorithm,
4258 key->key, key->keylen, NULL, key);
4259 }
4260 if (err)
4261 goto out_unlock;
4262
4263 if (algorithm == B43_SEC_ALGO_WEP40 ||
4264 algorithm == B43_SEC_ALGO_WEP104) {
4265 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4266 } else {
4267 b43_hf_write(dev,
4268 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4269 }
4270 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4271 if (algorithm == B43_SEC_ALGO_TKIP)
4272 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4273 break;
4274 case DISABLE_KEY: {
4275 err = b43_key_clear(dev, key->hw_key_idx);
4276 if (err)
4277 goto out_unlock;
4278 break;
4279 }
4280 default:
4281 B43_WARN_ON(1);
4282 }
4283
4284out_unlock:
4285 if (!err) {
4286 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4287 "mac: %pM\n",
4288 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4289 sta ? sta->addr : bcast_addr);
4290 b43_dump_keymemory(dev);
4291 }
4292 mutex_unlock(&wl->mutex);
4293
4294 return err;
4295}
4296
4297static void b43_op_configure_filter(struct ieee80211_hw *hw,
4298 unsigned int changed, unsigned int *fflags,
4299 u64 multicast)
4300{
4301 struct b43_wl *wl = hw_to_b43_wl(hw);
4302 struct b43_wldev *dev;
4303
4304 mutex_lock(&wl->mutex);
4305 dev = wl->current_dev;
4306 if (!dev) {
4307 *fflags = 0;
4308 goto out_unlock;
4309 }
4310
4311 *fflags &= FIF_ALLMULTI |
4312 FIF_FCSFAIL |
4313 FIF_PLCPFAIL |
4314 FIF_CONTROL |
4315 FIF_OTHER_BSS |
4316 FIF_BCN_PRBRESP_PROMISC;
4317
4318 changed &= FIF_ALLMULTI |
4319 FIF_FCSFAIL |
4320 FIF_PLCPFAIL |
4321 FIF_CONTROL |
4322 FIF_OTHER_BSS |
4323 FIF_BCN_PRBRESP_PROMISC;
4324
4325 wl->filter_flags = *fflags;
4326
4327 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4328 b43_adjust_opmode(dev);
4329
4330out_unlock:
4331 mutex_unlock(&wl->mutex);
4332}
4333
4334/* Locking: wl->mutex
4335 * Returns the current dev. This might be different from the passed in dev,
4336 * because the core might be gone away while we unlocked the mutex. */
4337static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4338{
4339 struct b43_wl *wl;
4340 struct b43_wldev *orig_dev;
4341 u32 mask;
4342 int queue_num;
4343
4344 if (!dev)
4345 return NULL;
4346 wl = dev->wl;
4347redo:
4348 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4349 return dev;
4350
4351 /* Cancel work. Unlock to avoid deadlocks. */
4352 mutex_unlock(&wl->mutex);
4353 cancel_delayed_work_sync(&dev->periodic_work);
4354 cancel_work_sync(&wl->tx_work);
4355 b43_leds_stop(dev);
4356 mutex_lock(&wl->mutex);
4357 dev = wl->current_dev;
4358 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4359 /* Whoops, aliens ate up the device while we were unlocked. */
4360 return dev;
4361 }
4362
4363 /* Disable interrupts on the device. */
4364 b43_set_status(dev, B43_STAT_INITIALIZED);
4365 if (b43_bus_host_is_sdio(dev->dev)) {
4366 /* wl->mutex is locked. That is enough. */
4367 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4368 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4369 } else {
4370 spin_lock_irq(&wl->hardirq_lock);
4371 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4372 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4373 spin_unlock_irq(&wl->hardirq_lock);
4374 }
4375 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4376 orig_dev = dev;
4377 mutex_unlock(&wl->mutex);
4378 if (b43_bus_host_is_sdio(dev->dev))
4379 b43_sdio_free_irq(dev);
4380 else
4381 free_irq(dev->dev->irq, dev);
4382 mutex_lock(&wl->mutex);
4383 dev = wl->current_dev;
4384 if (!dev)
4385 return dev;
4386 if (dev != orig_dev) {
4387 if (b43_status(dev) >= B43_STAT_STARTED)
4388 goto redo;
4389 return dev;
4390 }
4391 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4392 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4393
4394 /* Drain all TX queues. */
4395 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4396 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4397 struct sk_buff *skb;
4398
4399 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4400 ieee80211_free_txskb(wl->hw, skb);
4401 }
4402 }
4403
4404 b43_mac_suspend(dev);
4405 b43_leds_exit(dev);
4406 b43dbg(wl, "Wireless interface stopped\n");
4407
4408 return dev;
4409}
4410
4411/* Locking: wl->mutex */
4412static int b43_wireless_core_start(struct b43_wldev *dev)
4413{
4414 int err;
4415
4416 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4417
4418 drain_txstatus_queue(dev);
4419 if (b43_bus_host_is_sdio(dev->dev)) {
4420 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4421 if (err) {
4422 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4423 goto out;
4424 }
4425 } else {
4426 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4427 b43_interrupt_thread_handler,
4428 IRQF_SHARED, KBUILD_MODNAME, dev);
4429 if (err) {
4430 b43err(dev->wl, "Cannot request IRQ-%d\n",
4431 dev->dev->irq);
4432 goto out;
4433 }
4434 }
4435
4436 /* We are ready to run. */
4437 ieee80211_wake_queues(dev->wl->hw);
4438 b43_set_status(dev, B43_STAT_STARTED);
4439
4440 /* Start data flow (TX/RX). */
4441 b43_mac_enable(dev);
4442 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4443
4444 /* Start maintenance work */
4445 b43_periodic_tasks_setup(dev);
4446
4447 b43_leds_init(dev);
4448
4449 b43dbg(dev->wl, "Wireless interface started\n");
4450out:
4451 return err;
4452}
4453
4454static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4455{
4456 switch (phy_type) {
4457 case B43_PHYTYPE_A:
4458 return "A";
4459 case B43_PHYTYPE_B:
4460 return "B";
4461 case B43_PHYTYPE_G:
4462 return "G";
4463 case B43_PHYTYPE_N:
4464 return "N";
4465 case B43_PHYTYPE_LP:
4466 return "LP";
4467 case B43_PHYTYPE_SSLPN:
4468 return "SSLPN";
4469 case B43_PHYTYPE_HT:
4470 return "HT";
4471 case B43_PHYTYPE_LCN:
4472 return "LCN";
4473 case B43_PHYTYPE_LCNXN:
4474 return "LCNXN";
4475 case B43_PHYTYPE_LCN40:
4476 return "LCN40";
4477 case B43_PHYTYPE_AC:
4478 return "AC";
4479 }
4480 return "UNKNOWN";
4481}
4482
4483/* Get PHY and RADIO versioning numbers */
4484static int b43_phy_versioning(struct b43_wldev *dev)
4485{
4486 struct b43_phy *phy = &dev->phy;
4487 const u8 core_rev = dev->dev->core_rev;
4488 u32 tmp;
4489 u8 analog_type;
4490 u8 phy_type;
4491 u8 phy_rev;
4492 u16 radio_manuf;
4493 u16 radio_id;
4494 u16 radio_rev;
4495 u8 radio_ver;
4496 int unsupported = 0;
4497
4498 /* Get PHY versioning */
4499 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4500 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4501 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4502 phy_rev = (tmp & B43_PHYVER_VERSION);
4503
4504 /* LCNXN is continuation of N which run out of revisions */
4505 if (phy_type == B43_PHYTYPE_LCNXN) {
4506 phy_type = B43_PHYTYPE_N;
4507 phy_rev += 16;
4508 }
4509
4510 switch (phy_type) {
4511#ifdef CONFIG_B43_PHY_G
4512 case B43_PHYTYPE_G:
4513 if (phy_rev > 9)
4514 unsupported = 1;
4515 break;
4516#endif
4517#ifdef CONFIG_B43_PHY_N
4518 case B43_PHYTYPE_N:
4519 if (phy_rev >= 19)
4520 unsupported = 1;
4521 break;
4522#endif
4523#ifdef CONFIG_B43_PHY_LP
4524 case B43_PHYTYPE_LP:
4525 if (phy_rev > 2)
4526 unsupported = 1;
4527 break;
4528#endif
4529#ifdef CONFIG_B43_PHY_HT
4530 case B43_PHYTYPE_HT:
4531 if (phy_rev > 1)
4532 unsupported = 1;
4533 break;
4534#endif
4535#ifdef CONFIG_B43_PHY_LCN
4536 case B43_PHYTYPE_LCN:
4537 if (phy_rev > 1)
4538 unsupported = 1;
4539 break;
4540#endif
4541#ifdef CONFIG_B43_PHY_AC
4542 case B43_PHYTYPE_AC:
4543 if (phy_rev > 1)
4544 unsupported = 1;
4545 break;
4546#endif
4547 default:
4548 unsupported = 1;
4549 }
4550 if (unsupported) {
4551 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4552 analog_type, phy_type, b43_phy_name(dev, phy_type),
4553 phy_rev);
4554 return -EOPNOTSUPP;
4555 }
4556 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4557 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4558
4559 /* Get RADIO versioning */
4560 if (core_rev == 40 || core_rev == 42) {
4561 radio_manuf = 0x17F;
4562
4563 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
4564 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4565
4566 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
4567 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4568
4569 radio_ver = 0; /* Is there version somewhere? */
4570 } else if (core_rev >= 24) {
4571 u16 radio24[3];
4572
4573 for (tmp = 0; tmp < 3; tmp++) {
4574 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4575 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4576 }
4577
4578 radio_manuf = 0x17F;
4579 radio_id = (radio24[2] << 8) | radio24[1];
4580 radio_rev = (radio24[0] & 0xF);
4581 radio_ver = (radio24[0] & 0xF0) >> 4;
4582 } else {
4583 if (dev->dev->chip_id == 0x4317) {
4584 if (dev->dev->chip_rev == 0)
4585 tmp = 0x3205017F;
4586 else if (dev->dev->chip_rev == 1)
4587 tmp = 0x4205017F;
4588 else
4589 tmp = 0x5205017F;
4590 } else {
4591 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4592 B43_RADIOCTL_ID);
4593 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4594 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4595 B43_RADIOCTL_ID);
4596 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4597 }
4598 radio_manuf = (tmp & 0x00000FFF);
4599 radio_id = (tmp & 0x0FFFF000) >> 12;
4600 radio_rev = (tmp & 0xF0000000) >> 28;
4601 radio_ver = 0; /* Probably not available on old hw */
4602 }
4603
4604 if (radio_manuf != 0x17F /* Broadcom */)
4605 unsupported = 1;
4606 switch (phy_type) {
4607 case B43_PHYTYPE_A:
4608 if (radio_id != 0x2060)
4609 unsupported = 1;
4610 if (radio_rev != 1)
4611 unsupported = 1;
4612 if (radio_manuf != 0x17F)
4613 unsupported = 1;
4614 break;
4615 case B43_PHYTYPE_B:
4616 if ((radio_id & 0xFFF0) != 0x2050)
4617 unsupported = 1;
4618 break;
4619 case B43_PHYTYPE_G:
4620 if (radio_id != 0x2050)
4621 unsupported = 1;
4622 break;
4623 case B43_PHYTYPE_N:
4624 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4625 radio_id != 0x2057)
4626 unsupported = 1;
4627 if (radio_id == 0x2057 &&
4628 !(radio_rev == 9 || radio_rev == 14))
4629 unsupported = 1;
4630 break;
4631 case B43_PHYTYPE_LP:
4632 if (radio_id != 0x2062 && radio_id != 0x2063)
4633 unsupported = 1;
4634 break;
4635 case B43_PHYTYPE_HT:
4636 if (radio_id != 0x2059)
4637 unsupported = 1;
4638 break;
4639 case B43_PHYTYPE_LCN:
4640 if (radio_id != 0x2064)
4641 unsupported = 1;
4642 break;
4643 case B43_PHYTYPE_AC:
4644 if (radio_id != 0x2069)
4645 unsupported = 1;
4646 break;
4647 default:
4648 B43_WARN_ON(1);
4649 }
4650 if (unsupported) {
4651 b43err(dev->wl,
4652 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4653 radio_manuf, radio_id, radio_rev, radio_ver);
4654 return -EOPNOTSUPP;
4655 }
4656 b43info(dev->wl,
4657 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4658 radio_manuf, radio_id, radio_rev, radio_ver);
4659
4660 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
4661 phy->radio_manuf = radio_manuf;
4662 phy->radio_ver = radio_id;
4663 phy->radio_rev = radio_rev;
4664
4665 phy->analog = analog_type;
4666 phy->type = phy_type;
4667 phy->rev = phy_rev;
4668
4669 return 0;
4670}
4671
4672static void setup_struct_phy_for_init(struct b43_wldev *dev,
4673 struct b43_phy *phy)
4674{
4675 phy->hardware_power_control = !!modparam_hwpctl;
4676 phy->next_txpwr_check_time = jiffies;
4677 /* PHY TX errors counter. */
4678 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4679
4680#if B43_DEBUG
4681 phy->phy_locked = false;
4682 phy->radio_locked = false;
4683#endif
4684}
4685
4686static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4687{
4688 dev->dfq_valid = false;
4689
4690 /* Assume the radio is enabled. If it's not enabled, the state will
4691 * immediately get fixed on the first periodic work run. */
4692 dev->radio_hw_enable = true;
4693
4694 /* Stats */
4695 memset(&dev->stats, 0, sizeof(dev->stats));
4696
4697 setup_struct_phy_for_init(dev, &dev->phy);
4698
4699 /* IRQ related flags */
4700 dev->irq_reason = 0;
4701 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4702 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4703 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4704 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4705
4706 dev->mac_suspended = 1;
4707
4708 /* Noise calculation context */
4709 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4710}
4711
4712static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4713{
4714 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4715 u64 hf;
4716
4717 if (!modparam_btcoex)
4718 return;
4719 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4720 return;
4721 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4722 return;
4723
4724 hf = b43_hf_read(dev);
4725 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4726 hf |= B43_HF_BTCOEXALT;
4727 else
4728 hf |= B43_HF_BTCOEX;
4729 b43_hf_write(dev, hf);
4730}
4731
4732static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4733{
4734 if (!modparam_btcoex)
4735 return;
4736 //TODO
4737}
4738
4739static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4740{
4741 struct ssb_bus *bus;
4742 u32 tmp;
4743
4744#ifdef CONFIG_B43_SSB
4745 if (dev->dev->bus_type != B43_BUS_SSB)
4746 return;
4747#else
4748 return;
4749#endif
4750
4751 bus = dev->dev->sdev->bus;
4752
4753 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4754 (bus->chip_id == 0x4312)) {
4755 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4756 tmp &= ~SSB_IMCFGLO_REQTO;
4757 tmp &= ~SSB_IMCFGLO_SERTO;
4758 tmp |= 0x3;
4759 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4760 ssb_commit_settings(bus);
4761 }
4762}
4763
4764static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4765{
4766 u16 pu_delay;
4767
4768 /* The time value is in microseconds. */
4769 if (dev->phy.type == B43_PHYTYPE_A)
4770 pu_delay = 3700;
4771 else
4772 pu_delay = 1050;
4773 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4774 pu_delay = 500;
4775 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4776 pu_delay = max(pu_delay, (u16)2400);
4777
4778 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4779}
4780
4781/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4782static void b43_set_pretbtt(struct b43_wldev *dev)
4783{
4784 u16 pretbtt;
4785
4786 /* The time value is in microseconds. */
4787 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4788 pretbtt = 2;
4789 } else {
4790 if (dev->phy.type == B43_PHYTYPE_A)
4791 pretbtt = 120;
4792 else
4793 pretbtt = 250;
4794 }
4795 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4796 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4797}
4798
4799/* Shutdown a wireless core */
4800/* Locking: wl->mutex */
4801static void b43_wireless_core_exit(struct b43_wldev *dev)
4802{
4803 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4804 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4805 return;
4806
4807 b43_set_status(dev, B43_STAT_UNINIT);
4808
4809 /* Stop the microcode PSM. */
4810 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4811 B43_MACCTL_PSM_JMP0);
4812
4813 switch (dev->dev->bus_type) {
4814#ifdef CONFIG_B43_BCMA
4815 case B43_BUS_BCMA:
4816 bcma_host_pci_down(dev->dev->bdev->bus);
4817 break;
4818#endif
4819#ifdef CONFIG_B43_SSB
4820 case B43_BUS_SSB:
4821 /* TODO */
4822 break;
4823#endif
4824 }
4825
4826 b43_dma_free(dev);
4827 b43_pio_free(dev);
4828 b43_chip_exit(dev);
4829 dev->phy.ops->switch_analog(dev, 0);
4830 if (dev->wl->current_beacon) {
4831 dev_kfree_skb_any(dev->wl->current_beacon);
4832 dev->wl->current_beacon = NULL;
4833 }
4834
4835 b43_device_disable(dev, 0);
4836 b43_bus_may_powerdown(dev);
4837}
4838
4839/* Initialize a wireless core */
4840static int b43_wireless_core_init(struct b43_wldev *dev)
4841{
4842 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4843 struct b43_phy *phy = &dev->phy;
4844 int err;
4845 u64 hf;
4846
4847 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4848
4849 err = b43_bus_powerup(dev, 0);
4850 if (err)
4851 goto out;
4852 if (!b43_device_is_enabled(dev))
4853 b43_wireless_core_reset(dev, phy->gmode);
4854
4855 /* Reset all data structures. */
4856 setup_struct_wldev_for_init(dev);
4857 phy->ops->prepare_structs(dev);
4858
4859 /* Enable IRQ routing to this device. */
4860 switch (dev->dev->bus_type) {
4861#ifdef CONFIG_B43_BCMA
4862 case B43_BUS_BCMA:
4863 bcma_host_pci_irq_ctl(dev->dev->bdev->bus,
4864 dev->dev->bdev, true);
4865 bcma_host_pci_up(dev->dev->bdev->bus);
4866 break;
4867#endif
4868#ifdef CONFIG_B43_SSB
4869 case B43_BUS_SSB:
4870 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4871 dev->dev->sdev);
4872 break;
4873#endif
4874 }
4875
4876 b43_imcfglo_timeouts_workaround(dev);
4877 b43_bluetooth_coext_disable(dev);
4878 if (phy->ops->prepare_hardware) {
4879 err = phy->ops->prepare_hardware(dev);
4880 if (err)
4881 goto err_busdown;
4882 }
4883 err = b43_chip_init(dev);
4884 if (err)
4885 goto err_busdown;
4886 b43_shm_write16(dev, B43_SHM_SHARED,
4887 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4888 hf = b43_hf_read(dev);
4889 if (phy->type == B43_PHYTYPE_G) {
4890 hf |= B43_HF_SYMW;
4891 if (phy->rev == 1)
4892 hf |= B43_HF_GDCW;
4893 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4894 hf |= B43_HF_OFDMPABOOST;
4895 }
4896 if (phy->radio_ver == 0x2050) {
4897 if (phy->radio_rev == 6)
4898 hf |= B43_HF_4318TSSI;
4899 if (phy->radio_rev < 6)
4900 hf |= B43_HF_VCORECALC;
4901 }
4902 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4903 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4904#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4905 if (dev->dev->bus_type == B43_BUS_SSB &&
4906 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4907 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4908 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4909#endif
4910 hf &= ~B43_HF_SKCFPUP;
4911 b43_hf_write(dev, hf);
4912
4913 /* tell the ucode MAC capabilities */
4914 if (dev->dev->core_rev >= 13) {
4915 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4916
4917 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4918 mac_hw_cap & 0xffff);
4919 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4920 (mac_hw_cap >> 16) & 0xffff);
4921 }
4922
4923 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4924 B43_DEFAULT_LONG_RETRY_LIMIT);
4925 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4926 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4927
4928 /* Disable sending probe responses from firmware.
4929 * Setting the MaxTime to one usec will always trigger
4930 * a timeout, so we never send any probe resp.
4931 * A timeout of zero is infinite. */
4932 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4933
4934 b43_rate_memory_init(dev);
4935 b43_set_phytxctl_defaults(dev);
4936
4937 /* Minimum Contention Window */
4938 if (phy->type == B43_PHYTYPE_B)
4939 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4940 else
4941 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4942 /* Maximum Contention Window */
4943 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4944
4945 /* write phytype and phyvers */
4946 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4947 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4948
4949 if (b43_bus_host_is_pcmcia(dev->dev) ||
4950 b43_bus_host_is_sdio(dev->dev)) {
4951 dev->__using_pio_transfers = true;
4952 err = b43_pio_init(dev);
4953 } else if (dev->use_pio) {
4954 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4955 "This should not be needed and will result in lower "
4956 "performance.\n");
4957 dev->__using_pio_transfers = true;
4958 err = b43_pio_init(dev);
4959 } else {
4960 dev->__using_pio_transfers = false;
4961 err = b43_dma_init(dev);
4962 }
4963 if (err)
4964 goto err_chip_exit;
4965 b43_qos_init(dev);
4966 b43_set_synth_pu_delay(dev, 1);
4967 b43_bluetooth_coext_enable(dev);
4968
4969 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4970 b43_upload_card_macaddress(dev);
4971 b43_security_init(dev);
4972
4973 ieee80211_wake_queues(dev->wl->hw);
4974
4975 b43_set_status(dev, B43_STAT_INITIALIZED);
4976
4977out:
4978 return err;
4979
4980err_chip_exit:
4981 b43_chip_exit(dev);
4982err_busdown:
4983 b43_bus_may_powerdown(dev);
4984 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4985 return err;
4986}
4987
4988static int b43_op_add_interface(struct ieee80211_hw *hw,
4989 struct ieee80211_vif *vif)
4990{
4991 struct b43_wl *wl = hw_to_b43_wl(hw);
4992 struct b43_wldev *dev;
4993 int err = -EOPNOTSUPP;
4994
4995 /* TODO: allow WDS/AP devices to coexist */
4996
4997 if (vif->type != NL80211_IFTYPE_AP &&
4998 vif->type != NL80211_IFTYPE_MESH_POINT &&
4999 vif->type != NL80211_IFTYPE_STATION &&
5000 vif->type != NL80211_IFTYPE_WDS &&
5001 vif->type != NL80211_IFTYPE_ADHOC)
5002 return -EOPNOTSUPP;
5003
5004 mutex_lock(&wl->mutex);
5005 if (wl->operating)
5006 goto out_mutex_unlock;
5007
5008 b43dbg(wl, "Adding Interface type %d\n", vif->type);
5009
5010 dev = wl->current_dev;
5011 wl->operating = true;
5012 wl->vif = vif;
5013 wl->if_type = vif->type;
5014 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
5015
5016 b43_adjust_opmode(dev);
5017 b43_set_pretbtt(dev);
5018 b43_set_synth_pu_delay(dev, 0);
5019 b43_upload_card_macaddress(dev);
5020
5021 err = 0;
5022 out_mutex_unlock:
5023 mutex_unlock(&wl->mutex);
5024
5025 if (err == 0)
5026 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
5027
5028 return err;
5029}
5030
5031static void b43_op_remove_interface(struct ieee80211_hw *hw,
5032 struct ieee80211_vif *vif)
5033{
5034 struct b43_wl *wl = hw_to_b43_wl(hw);
5035 struct b43_wldev *dev = wl->current_dev;
5036
5037 b43dbg(wl, "Removing Interface type %d\n", vif->type);
5038
5039 mutex_lock(&wl->mutex);
5040
5041 B43_WARN_ON(!wl->operating);
5042 B43_WARN_ON(wl->vif != vif);
5043 wl->vif = NULL;
5044
5045 wl->operating = false;
5046
5047 b43_adjust_opmode(dev);
5048 eth_zero_addr(wl->mac_addr);
5049 b43_upload_card_macaddress(dev);
5050
5051 mutex_unlock(&wl->mutex);
5052}
5053
5054static int b43_op_start(struct ieee80211_hw *hw)
5055{
5056 struct b43_wl *wl = hw_to_b43_wl(hw);
5057 struct b43_wldev *dev = wl->current_dev;
5058 int did_init = 0;
5059 int err = 0;
5060
5061 /* Kill all old instance specific information to make sure
5062 * the card won't use it in the short timeframe between start
5063 * and mac80211 reconfiguring it. */
5064 eth_zero_addr(wl->bssid);
5065 eth_zero_addr(wl->mac_addr);
5066 wl->filter_flags = 0;
5067 wl->radiotap_enabled = false;
5068 b43_qos_clear(wl);
5069 wl->beacon0_uploaded = false;
5070 wl->beacon1_uploaded = false;
5071 wl->beacon_templates_virgin = true;
5072 wl->radio_enabled = true;
5073
5074 mutex_lock(&wl->mutex);
5075
5076 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5077 err = b43_wireless_core_init(dev);
5078 if (err)
5079 goto out_mutex_unlock;
5080 did_init = 1;
5081 }
5082
5083 if (b43_status(dev) < B43_STAT_STARTED) {
5084 err = b43_wireless_core_start(dev);
5085 if (err) {
5086 if (did_init)
5087 b43_wireless_core_exit(dev);
5088 goto out_mutex_unlock;
5089 }
5090 }
5091
5092 /* XXX: only do if device doesn't support rfkill irq */
5093 wiphy_rfkill_start_polling(hw->wiphy);
5094
5095 out_mutex_unlock:
5096 mutex_unlock(&wl->mutex);
5097
5098 /*
5099 * Configuration may have been overwritten during initialization.
5100 * Reload the configuration, but only if initialization was
5101 * successful. Reloading the configuration after a failed init
5102 * may hang the system.
5103 */
5104 if (!err)
5105 b43_op_config(hw, ~0);
5106
5107 return err;
5108}
5109
5110static void b43_op_stop(struct ieee80211_hw *hw)
5111{
5112 struct b43_wl *wl = hw_to_b43_wl(hw);
5113 struct b43_wldev *dev = wl->current_dev;
5114
5115 cancel_work_sync(&(wl->beacon_update_trigger));
5116
5117 if (!dev)
5118 goto out;
5119
5120 mutex_lock(&wl->mutex);
5121 if (b43_status(dev) >= B43_STAT_STARTED) {
5122 dev = b43_wireless_core_stop(dev);
5123 if (!dev)
5124 goto out_unlock;
5125 }
5126 b43_wireless_core_exit(dev);
5127 wl->radio_enabled = false;
5128
5129out_unlock:
5130 mutex_unlock(&wl->mutex);
5131out:
5132 cancel_work_sync(&(wl->txpower_adjust_work));
5133}
5134
5135static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5136 struct ieee80211_sta *sta, bool set)
5137{
5138 struct b43_wl *wl = hw_to_b43_wl(hw);
5139
5140 b43_update_templates(wl);
5141
5142 return 0;
5143}
5144
5145static void b43_op_sta_notify(struct ieee80211_hw *hw,
5146 struct ieee80211_vif *vif,
5147 enum sta_notify_cmd notify_cmd,
5148 struct ieee80211_sta *sta)
5149{
5150 struct b43_wl *wl = hw_to_b43_wl(hw);
5151
5152 B43_WARN_ON(!vif || wl->vif != vif);
5153}
5154
5155static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw,
5156 struct ieee80211_vif *vif,
5157 const u8 *mac_addr)
5158{
5159 struct b43_wl *wl = hw_to_b43_wl(hw);
5160 struct b43_wldev *dev;
5161
5162 mutex_lock(&wl->mutex);
5163 dev = wl->current_dev;
5164 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5165 /* Disable CFP update during scan on other channels. */
5166 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5167 }
5168 mutex_unlock(&wl->mutex);
5169}
5170
5171static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw,
5172 struct ieee80211_vif *vif)
5173{
5174 struct b43_wl *wl = hw_to_b43_wl(hw);
5175 struct b43_wldev *dev;
5176
5177 mutex_lock(&wl->mutex);
5178 dev = wl->current_dev;
5179 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5180 /* Re-enable CFP update. */
5181 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5182 }
5183 mutex_unlock(&wl->mutex);
5184}
5185
5186static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5187 struct survey_info *survey)
5188{
5189 struct b43_wl *wl = hw_to_b43_wl(hw);
5190 struct b43_wldev *dev = wl->current_dev;
5191 struct ieee80211_conf *conf = &hw->conf;
5192
5193 if (idx != 0)
5194 return -ENOENT;
5195
5196 survey->channel = conf->chandef.chan;
5197 survey->filled = SURVEY_INFO_NOISE_DBM;
5198 survey->noise = dev->stats.link_noise;
5199
5200 return 0;
5201}
5202
5203static const struct ieee80211_ops b43_hw_ops = {
5204 .tx = b43_op_tx,
5205 .conf_tx = b43_op_conf_tx,
5206 .add_interface = b43_op_add_interface,
5207 .remove_interface = b43_op_remove_interface,
5208 .config = b43_op_config,
5209 .bss_info_changed = b43_op_bss_info_changed,
5210 .configure_filter = b43_op_configure_filter,
5211 .set_key = b43_op_set_key,
5212 .update_tkip_key = b43_op_update_tkip_key,
5213 .get_stats = b43_op_get_stats,
5214 .get_tsf = b43_op_get_tsf,
5215 .set_tsf = b43_op_set_tsf,
5216 .start = b43_op_start,
5217 .stop = b43_op_stop,
5218 .set_tim = b43_op_beacon_set_tim,
5219 .sta_notify = b43_op_sta_notify,
5220 .sw_scan_start = b43_op_sw_scan_start_notifier,
5221 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
5222 .get_survey = b43_op_get_survey,
5223 .rfkill_poll = b43_rfkill_poll,
5224};
5225
5226/* Hard-reset the chip. Do not call this directly.
5227 * Use b43_controller_restart()
5228 */
5229static void b43_chip_reset(struct work_struct *work)
5230{
5231 struct b43_wldev *dev =
5232 container_of(work, struct b43_wldev, restart_work);
5233 struct b43_wl *wl = dev->wl;
5234 int err = 0;
5235 int prev_status;
5236
5237 mutex_lock(&wl->mutex);
5238
5239 prev_status = b43_status(dev);
5240 /* Bring the device down... */
5241 if (prev_status >= B43_STAT_STARTED) {
5242 dev = b43_wireless_core_stop(dev);
5243 if (!dev) {
5244 err = -ENODEV;
5245 goto out;
5246 }
5247 }
5248 if (prev_status >= B43_STAT_INITIALIZED)
5249 b43_wireless_core_exit(dev);
5250
5251 /* ...and up again. */
5252 if (prev_status >= B43_STAT_INITIALIZED) {
5253 err = b43_wireless_core_init(dev);
5254 if (err)
5255 goto out;
5256 }
5257 if (prev_status >= B43_STAT_STARTED) {
5258 err = b43_wireless_core_start(dev);
5259 if (err) {
5260 b43_wireless_core_exit(dev);
5261 goto out;
5262 }
5263 }
5264out:
5265 if (err)
5266 wl->current_dev = NULL; /* Failed to init the dev. */
5267 mutex_unlock(&wl->mutex);
5268
5269 if (err) {
5270 b43err(wl, "Controller restart FAILED\n");
5271 return;
5272 }
5273
5274 /* reload configuration */
5275 b43_op_config(wl->hw, ~0);
5276 if (wl->vif)
5277 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5278
5279 b43info(wl, "Controller restarted\n");
5280}
5281
5282static int b43_setup_bands(struct b43_wldev *dev,
5283 bool have_2ghz_phy, bool have_5ghz_phy)
5284{
5285 struct ieee80211_hw *hw = dev->wl->hw;
5286 struct b43_phy *phy = &dev->phy;
5287 bool limited_2g;
5288 bool limited_5g;
5289
5290 /* We don't support all 2 GHz channels on some devices */
5291 limited_2g = phy->radio_ver == 0x2057 &&
5292 (phy->radio_rev == 9 || phy->radio_rev == 14);
5293 limited_5g = phy->radio_ver == 0x2057 &&
5294 phy->radio_rev == 9;
5295
5296 if (have_2ghz_phy)
5297 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5298 &b43_band_2ghz_limited : &b43_band_2GHz;
5299 if (dev->phy.type == B43_PHYTYPE_N) {
5300 if (have_5ghz_phy)
5301 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ?
5302 &b43_band_5GHz_nphy_limited :
5303 &b43_band_5GHz_nphy;
5304 } else {
5305 if (have_5ghz_phy)
5306 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5307 }
5308
5309 dev->phy.supports_2ghz = have_2ghz_phy;
5310 dev->phy.supports_5ghz = have_5ghz_phy;
5311
5312 return 0;
5313}
5314
5315static void b43_wireless_core_detach(struct b43_wldev *dev)
5316{
5317 /* We release firmware that late to not be required to re-request
5318 * is all the time when we reinit the core. */
5319 b43_release_firmware(dev);
5320 b43_phy_free(dev);
5321}
5322
5323static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5324 bool *have_5ghz_phy)
5325{
5326 u16 dev_id = 0;
5327
5328#ifdef CONFIG_B43_BCMA
5329 if (dev->dev->bus_type == B43_BUS_BCMA &&
5330 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5331 dev_id = dev->dev->bdev->bus->host_pci->device;
5332#endif
5333#ifdef CONFIG_B43_SSB
5334 if (dev->dev->bus_type == B43_BUS_SSB &&
5335 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5336 dev_id = dev->dev->sdev->bus->host_pci->device;
5337#endif
5338 /* Override with SPROM value if available */
5339 if (dev->dev->bus_sprom->dev_id)
5340 dev_id = dev->dev->bus_sprom->dev_id;
5341
5342 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5343 switch (dev_id) {
5344 case 0x4324: /* BCM4306 */
5345 case 0x4312: /* BCM4311 */
5346 case 0x4319: /* BCM4318 */
5347 case 0x4328: /* BCM4321 */
5348 case 0x432b: /* BCM4322 */
5349 case 0x4350: /* BCM43222 */
5350 case 0x4353: /* BCM43224 */
5351 case 0x0576: /* BCM43224 */
5352 case 0x435f: /* BCM6362 */
5353 case 0x4331: /* BCM4331 */
5354 case 0x4359: /* BCM43228 */
5355 case 0x43a0: /* BCM4360 */
5356 case 0x43b1: /* BCM4352 */
5357 /* Dual band devices */
5358 *have_2ghz_phy = true;
5359 *have_5ghz_phy = true;
5360 return;
5361 case 0x4321: /* BCM4306 */
5362 /* There are 14e4:4321 PCI devs with 2.4 GHz BCM4321 (N-PHY) */
5363 if (dev->phy.type != B43_PHYTYPE_G)
5364 break;
5365 /* fall through */
5366 case 0x4313: /* BCM4311 */
5367 case 0x431a: /* BCM4318 */
5368 case 0x432a: /* BCM4321 */
5369 case 0x432d: /* BCM4322 */
5370 case 0x4352: /* BCM43222 */
5371 case 0x435a: /* BCM43228 */
5372 case 0x4333: /* BCM4331 */
5373 case 0x43a2: /* BCM4360 */
5374 case 0x43b3: /* BCM4352 */
5375 /* 5 GHz only devices */
5376 *have_2ghz_phy = false;
5377 *have_5ghz_phy = true;
5378 return;
5379 }
5380
5381 /* As a fallback, try to guess using PHY type */
5382 switch (dev->phy.type) {
5383 case B43_PHYTYPE_A:
5384 *have_2ghz_phy = false;
5385 *have_5ghz_phy = true;
5386 return;
5387 case B43_PHYTYPE_G:
5388 case B43_PHYTYPE_N:
5389 case B43_PHYTYPE_LP:
5390 case B43_PHYTYPE_HT:
5391 case B43_PHYTYPE_LCN:
5392 *have_2ghz_phy = true;
5393 *have_5ghz_phy = false;
5394 return;
5395 }
5396
5397 B43_WARN_ON(1);
5398}
5399
5400static int b43_wireless_core_attach(struct b43_wldev *dev)
5401{
5402 struct b43_wl *wl = dev->wl;
5403 struct b43_phy *phy = &dev->phy;
5404 int err;
5405 u32 tmp;
5406 bool have_2ghz_phy = false, have_5ghz_phy = false;
5407
5408 /* Do NOT do any device initialization here.
5409 * Do it in wireless_core_init() instead.
5410 * This function is for gathering basic information about the HW, only.
5411 * Also some structs may be set up here. But most likely you want to have
5412 * that in core_init(), too.
5413 */
5414
5415 err = b43_bus_powerup(dev, 0);
5416 if (err) {
5417 b43err(wl, "Bus powerup failed\n");
5418 goto out;
5419 }
5420
5421 phy->do_full_init = true;
5422
5423 /* Try to guess supported bands for the first init needs */
5424 switch (dev->dev->bus_type) {
5425#ifdef CONFIG_B43_BCMA
5426 case B43_BUS_BCMA:
5427 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5428 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5429 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5430 break;
5431#endif
5432#ifdef CONFIG_B43_SSB
5433 case B43_BUS_SSB:
5434 if (dev->dev->core_rev >= 5) {
5435 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5436 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5437 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5438 } else
5439 B43_WARN_ON(1);
5440 break;
5441#endif
5442 }
5443
5444 dev->phy.gmode = have_2ghz_phy;
5445 b43_wireless_core_reset(dev, dev->phy.gmode);
5446
5447 /* Get the PHY type. */
5448 err = b43_phy_versioning(dev);
5449 if (err)
5450 goto err_powerdown;
5451
5452 /* Get real info about supported bands */
5453 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5454
5455 /* We don't support 5 GHz on some PHYs yet */
5456 if (have_5ghz_phy) {
5457 switch (dev->phy.type) {
5458 case B43_PHYTYPE_A:
5459 case B43_PHYTYPE_G:
5460 case B43_PHYTYPE_LP:
5461 case B43_PHYTYPE_HT:
5462 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5463 have_5ghz_phy = false;
5464 }
5465 }
5466
5467 if (!have_2ghz_phy && !have_5ghz_phy) {
5468 b43err(wl, "b43 can't support any band on this device\n");
5469 err = -EOPNOTSUPP;
5470 goto err_powerdown;
5471 }
5472
5473 err = b43_phy_allocate(dev);
5474 if (err)
5475 goto err_powerdown;
5476
5477 dev->phy.gmode = have_2ghz_phy;
5478 b43_wireless_core_reset(dev, dev->phy.gmode);
5479
5480 err = b43_validate_chipaccess(dev);
5481 if (err)
5482 goto err_phy_free;
5483 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5484 if (err)
5485 goto err_phy_free;
5486
5487 /* Now set some default "current_dev" */
5488 if (!wl->current_dev)
5489 wl->current_dev = dev;
5490 INIT_WORK(&dev->restart_work, b43_chip_reset);
5491
5492 dev->phy.ops->switch_analog(dev, 0);
5493 b43_device_disable(dev, 0);
5494 b43_bus_may_powerdown(dev);
5495
5496out:
5497 return err;
5498
5499err_phy_free:
5500 b43_phy_free(dev);
5501err_powerdown:
5502 b43_bus_may_powerdown(dev);
5503 return err;
5504}
5505
5506static void b43_one_core_detach(struct b43_bus_dev *dev)
5507{
5508 struct b43_wldev *wldev;
5509 struct b43_wl *wl;
5510
5511 /* Do not cancel ieee80211-workqueue based work here.
5512 * See comment in b43_remove(). */
5513
5514 wldev = b43_bus_get_wldev(dev);
5515 wl = wldev->wl;
5516 b43_debugfs_remove_device(wldev);
5517 b43_wireless_core_detach(wldev);
5518 list_del(&wldev->list);
5519 b43_bus_set_wldev(dev, NULL);
5520 kfree(wldev);
5521}
5522
5523static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5524{
5525 struct b43_wldev *wldev;
5526 int err = -ENOMEM;
5527
5528 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5529 if (!wldev)
5530 goto out;
5531
5532 wldev->use_pio = b43_modparam_pio;
5533 wldev->dev = dev;
5534 wldev->wl = wl;
5535 b43_set_status(wldev, B43_STAT_UNINIT);
5536 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5537 INIT_LIST_HEAD(&wldev->list);
5538
5539 err = b43_wireless_core_attach(wldev);
5540 if (err)
5541 goto err_kfree_wldev;
5542
5543 b43_bus_set_wldev(dev, wldev);
5544 b43_debugfs_add_device(wldev);
5545
5546 out:
5547 return err;
5548
5549 err_kfree_wldev:
5550 kfree(wldev);
5551 return err;
5552}
5553
5554#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5555 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5556 (pdev->device == _device) && \
5557 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5558 (pdev->subsystem_device == _subdevice) )
5559
5560#ifdef CONFIG_B43_SSB
5561static void b43_sprom_fixup(struct ssb_bus *bus)
5562{
5563 struct pci_dev *pdev;
5564
5565 /* boardflags workarounds */
5566 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5567 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5568 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5569 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5570 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5571 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5572 if (bus->bustype == SSB_BUSTYPE_PCI) {
5573 pdev = bus->host_pci;
5574 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5575 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5576 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5577 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5578 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5579 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5580 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5581 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5582 }
5583}
5584
5585static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5586{
5587 struct ieee80211_hw *hw = wl->hw;
5588
5589 ssb_set_devtypedata(dev->sdev, NULL);
5590 ieee80211_free_hw(hw);
5591}
5592#endif
5593
5594static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5595{
5596 struct ssb_sprom *sprom = dev->bus_sprom;
5597 struct ieee80211_hw *hw;
5598 struct b43_wl *wl;
5599 char chip_name[6];
5600 int queue_num;
5601
5602 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5603 if (!hw) {
5604 b43err(NULL, "Could not allocate ieee80211 device\n");
5605 return ERR_PTR(-ENOMEM);
5606 }
5607 wl = hw_to_b43_wl(hw);
5608
5609 /* fill hw info */
5610 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5611 ieee80211_hw_set(hw, SIGNAL_DBM);
5612
5613 hw->wiphy->interface_modes =
5614 BIT(NL80211_IFTYPE_AP) |
5615 BIT(NL80211_IFTYPE_MESH_POINT) |
5616 BIT(NL80211_IFTYPE_STATION) |
5617 BIT(NL80211_IFTYPE_WDS) |
5618 BIT(NL80211_IFTYPE_ADHOC);
5619
5620 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5621
5622 wl->hw_registred = false;
5623 hw->max_rates = 2;
5624 SET_IEEE80211_DEV(hw, dev->dev);
5625 if (is_valid_ether_addr(sprom->et1mac))
5626 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5627 else
5628 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5629
5630 /* Initialize struct b43_wl */
5631 wl->hw = hw;
5632 mutex_init(&wl->mutex);
5633 spin_lock_init(&wl->hardirq_lock);
5634 spin_lock_init(&wl->beacon_lock);
5635 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5636 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5637 INIT_WORK(&wl->tx_work, b43_tx_work);
5638
5639 /* Initialize queues and flags. */
5640 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5641 skb_queue_head_init(&wl->tx_queue[queue_num]);
5642 wl->tx_queue_stopped[queue_num] = 0;
5643 }
5644
5645 snprintf(chip_name, ARRAY_SIZE(chip_name),
5646 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5647 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5648 dev->core_rev);
5649 return wl;
5650}
5651
5652#ifdef CONFIG_B43_BCMA
5653static int b43_bcma_probe(struct bcma_device *core)
5654{
5655 struct b43_bus_dev *dev;
5656 struct b43_wl *wl;
5657 int err;
5658
5659 if (!modparam_allhwsupport &&
5660 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5661 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5662 return -ENOTSUPP;
5663 }
5664
5665 dev = b43_bus_dev_bcma_init(core);
5666 if (!dev)
5667 return -ENODEV;
5668
5669 wl = b43_wireless_init(dev);
5670 if (IS_ERR(wl)) {
5671 err = PTR_ERR(wl);
5672 goto bcma_out;
5673 }
5674
5675 err = b43_one_core_attach(dev, wl);
5676 if (err)
5677 goto bcma_err_wireless_exit;
5678
5679 /* setup and start work to load firmware */
5680 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5681 schedule_work(&wl->firmware_load);
5682
5683 return err;
5684
5685bcma_err_wireless_exit:
5686 ieee80211_free_hw(wl->hw);
5687bcma_out:
5688 kfree(dev);
5689 return err;
5690}
5691
5692static void b43_bcma_remove(struct bcma_device *core)
5693{
5694 struct b43_wldev *wldev = bcma_get_drvdata(core);
5695 struct b43_wl *wl = wldev->wl;
5696
5697 /* We must cancel any work here before unregistering from ieee80211,
5698 * as the ieee80211 unreg will destroy the workqueue. */
5699 cancel_work_sync(&wldev->restart_work);
5700 cancel_work_sync(&wl->firmware_load);
5701
5702 B43_WARN_ON(!wl);
5703 if (!wldev->fw.ucode.data)
5704 return; /* NULL if firmware never loaded */
5705 if (wl->current_dev == wldev && wl->hw_registred) {
5706 b43_leds_stop(wldev);
5707 ieee80211_unregister_hw(wl->hw);
5708 }
5709
5710 b43_one_core_detach(wldev->dev);
5711
5712 /* Unregister HW RNG driver */
5713 b43_rng_exit(wl);
5714
5715 b43_leds_unregister(wl);
5716 ieee80211_free_hw(wl->hw);
5717 kfree(wldev->dev);
5718}
5719
5720static struct bcma_driver b43_bcma_driver = {
5721 .name = KBUILD_MODNAME,
5722 .id_table = b43_bcma_tbl,
5723 .probe = b43_bcma_probe,
5724 .remove = b43_bcma_remove,
5725};
5726#endif
5727
5728#ifdef CONFIG_B43_SSB
5729static
5730int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5731{
5732 struct b43_bus_dev *dev;
5733 struct b43_wl *wl;
5734 int err;
5735
5736 dev = b43_bus_dev_ssb_init(sdev);
5737 if (!dev)
5738 return -ENOMEM;
5739
5740 wl = ssb_get_devtypedata(sdev);
5741 if (wl) {
5742 b43err(NULL, "Dual-core devices are not supported\n");
5743 err = -ENOTSUPP;
5744 goto err_ssb_kfree_dev;
5745 }
5746
5747 b43_sprom_fixup(sdev->bus);
5748
5749 wl = b43_wireless_init(dev);
5750 if (IS_ERR(wl)) {
5751 err = PTR_ERR(wl);
5752 goto err_ssb_kfree_dev;
5753 }
5754 ssb_set_devtypedata(sdev, wl);
5755 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5756
5757 err = b43_one_core_attach(dev, wl);
5758 if (err)
5759 goto err_ssb_wireless_exit;
5760
5761 /* setup and start work to load firmware */
5762 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5763 schedule_work(&wl->firmware_load);
5764
5765 return err;
5766
5767err_ssb_wireless_exit:
5768 b43_wireless_exit(dev, wl);
5769err_ssb_kfree_dev:
5770 kfree(dev);
5771 return err;
5772}
5773
5774static void b43_ssb_remove(struct ssb_device *sdev)
5775{
5776 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5777 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5778 struct b43_bus_dev *dev = wldev->dev;
5779
5780 /* We must cancel any work here before unregistering from ieee80211,
5781 * as the ieee80211 unreg will destroy the workqueue. */
5782 cancel_work_sync(&wldev->restart_work);
5783 cancel_work_sync(&wl->firmware_load);
5784
5785 B43_WARN_ON(!wl);
5786 if (!wldev->fw.ucode.data)
5787 return; /* NULL if firmware never loaded */
5788 if (wl->current_dev == wldev && wl->hw_registred) {
5789 b43_leds_stop(wldev);
5790 ieee80211_unregister_hw(wl->hw);
5791 }
5792
5793 b43_one_core_detach(dev);
5794
5795 /* Unregister HW RNG driver */
5796 b43_rng_exit(wl);
5797
5798 b43_leds_unregister(wl);
5799 b43_wireless_exit(dev, wl);
5800 kfree(dev);
5801}
5802
5803static struct ssb_driver b43_ssb_driver = {
5804 .name = KBUILD_MODNAME,
5805 .id_table = b43_ssb_tbl,
5806 .probe = b43_ssb_probe,
5807 .remove = b43_ssb_remove,
5808};
5809#endif /* CONFIG_B43_SSB */
5810
5811/* Perform a hardware reset. This can be called from any context. */
5812void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5813{
5814 /* Must avoid requeueing, if we are in shutdown. */
5815 if (b43_status(dev) < B43_STAT_INITIALIZED)
5816 return;
5817 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5818 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5819}
5820
5821static void b43_print_driverinfo(void)
5822{
5823 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5824 *feat_leds = "", *feat_sdio = "";
5825
5826#ifdef CONFIG_B43_PCI_AUTOSELECT
5827 feat_pci = "P";
5828#endif
5829#ifdef CONFIG_B43_PCMCIA
5830 feat_pcmcia = "M";
5831#endif
5832#ifdef CONFIG_B43_PHY_N
5833 feat_nphy = "N";
5834#endif
5835#ifdef CONFIG_B43_LEDS
5836 feat_leds = "L";
5837#endif
5838#ifdef CONFIG_B43_SDIO
5839 feat_sdio = "S";
5840#endif
5841 printk(KERN_INFO "Broadcom 43xx driver loaded "
5842 "[ Features: %s%s%s%s%s ]\n",
5843 feat_pci, feat_pcmcia, feat_nphy,
5844 feat_leds, feat_sdio);
5845}
5846
5847static int __init b43_init(void)
5848{
5849 int err;
5850
5851 b43_debugfs_init();
5852 err = b43_sdio_init();
5853 if (err)
5854 goto err_dfs_exit;
5855#ifdef CONFIG_B43_BCMA
5856 err = bcma_driver_register(&b43_bcma_driver);
5857 if (err)
5858 goto err_sdio_exit;
5859#endif
5860#ifdef CONFIG_B43_SSB
5861 err = ssb_driver_register(&b43_ssb_driver);
5862 if (err)
5863 goto err_bcma_driver_exit;
5864#endif
5865 b43_print_driverinfo();
5866
5867 return err;
5868
5869#ifdef CONFIG_B43_SSB
5870err_bcma_driver_exit:
5871#endif
5872#ifdef CONFIG_B43_BCMA
5873 bcma_driver_unregister(&b43_bcma_driver);
5874err_sdio_exit:
5875#endif
5876 b43_sdio_exit();
5877err_dfs_exit:
5878 b43_debugfs_exit();
5879 return err;
5880}
5881
5882static void __exit b43_exit(void)
5883{
5884#ifdef CONFIG_B43_SSB
5885 ssb_driver_unregister(&b43_ssb_driver);
5886#endif
5887#ifdef CONFIG_B43_BCMA
5888 bcma_driver_unregister(&b43_bcma_driver);
5889#endif
5890 b43_sdio_exit();
5891 b43_debugfs_exit();
5892}
5893
5894module_init(b43_init)
5895module_exit(b43_exit)
1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/module.h>
38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
40#include <linux/firmware.h>
41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
43#include <linux/io.h>
44#include <linux/dma-mapping.h>
45#include <linux/slab.h>
46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
51#include "phy_common.h"
52#include "phy_g.h"
53#include "phy_n.h"
54#include "dma.h"
55#include "pio.h"
56#include "sysfs.h"
57#include "xmit.h"
58#include "lo.h"
59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
66MODULE_AUTHOR("Gábor Stefanik");
67MODULE_AUTHOR("Rafał Miłecki");
68MODULE_LICENSE("GPL");
69
70MODULE_FIRMWARE("b43/ucode11.fw");
71MODULE_FIRMWARE("b43/ucode13.fw");
72MODULE_FIRMWARE("b43/ucode14.fw");
73MODULE_FIRMWARE("b43/ucode15.fw");
74MODULE_FIRMWARE("b43/ucode16_lp.fw");
75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76MODULE_FIRMWARE("b43/ucode24_lcn.fw");
77MODULE_FIRMWARE("b43/ucode25_lcn.fw");
78MODULE_FIRMWARE("b43/ucode25_mimo.fw");
79MODULE_FIRMWARE("b43/ucode26_mimo.fw");
80MODULE_FIRMWARE("b43/ucode29_mimo.fw");
81MODULE_FIRMWARE("b43/ucode33_lcn40.fw");
82MODULE_FIRMWARE("b43/ucode30_mimo.fw");
83MODULE_FIRMWARE("b43/ucode5.fw");
84MODULE_FIRMWARE("b43/ucode40.fw");
85MODULE_FIRMWARE("b43/ucode42.fw");
86MODULE_FIRMWARE("b43/ucode9.fw");
87
88static int modparam_bad_frames_preempt;
89module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
90MODULE_PARM_DESC(bad_frames_preempt,
91 "enable(1) / disable(0) Bad Frames Preemption");
92
93static char modparam_fwpostfix[16];
94module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
95MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
96
97static int modparam_hwpctl;
98module_param_named(hwpctl, modparam_hwpctl, int, 0444);
99MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
100
101static int modparam_nohwcrypt;
102module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
103MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
104
105static int modparam_hwtkip;
106module_param_named(hwtkip, modparam_hwtkip, int, 0444);
107MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
108
109static int modparam_qos = 1;
110module_param_named(qos, modparam_qos, int, 0444);
111MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
112
113static int modparam_btcoex = 1;
114module_param_named(btcoex, modparam_btcoex, int, 0444);
115MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
116
117int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
118module_param_named(verbose, b43_modparam_verbose, int, 0644);
119MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
120
121static int b43_modparam_pio = 0;
122module_param_named(pio, b43_modparam_pio, int, 0644);
123MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
124
125static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
126module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
127MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
128
129#ifdef CONFIG_B43_BCMA
130static const struct bcma_device_id b43_bcma_tbl[] = {
131 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
132 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS),
133 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
134 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
135 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
136 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
137 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
138 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
139 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
140 {},
141};
142MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
143#endif
144
145#ifdef CONFIG_B43_SSB
146static const struct ssb_device_id b43_ssb_tbl[] = {
147 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
148 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
149 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
150 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
151 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
152 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
153 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
154 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
155 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
156 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
157 {},
158};
159MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
160#endif
161
162/* Channel and ratetables are shared for all devices.
163 * They can't be const, because ieee80211 puts some precalculated
164 * data in there. This data is the same for all devices, so we don't
165 * get concurrency issues */
166#define RATETAB_ENT(_rateid, _flags) \
167 { \
168 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
169 .hw_value = (_rateid), \
170 .flags = (_flags), \
171 }
172
173/*
174 * NOTE: When changing this, sync with xmit.c's
175 * b43_plcp_get_bitrate_idx_* functions!
176 */
177static struct ieee80211_rate __b43_ratetable[] = {
178 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
179 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
180 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
181 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
182 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
183 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
184 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
185 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
186 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
187 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
188 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
189 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
190};
191
192#define b43_a_ratetable (__b43_ratetable + 4)
193#define b43_a_ratetable_size 8
194#define b43_b_ratetable (__b43_ratetable + 0)
195#define b43_b_ratetable_size 4
196#define b43_g_ratetable (__b43_ratetable + 0)
197#define b43_g_ratetable_size 12
198
199#define CHAN2G(_channel, _freq, _flags) { \
200 .band = NL80211_BAND_2GHZ, \
201 .center_freq = (_freq), \
202 .hw_value = (_channel), \
203 .flags = (_flags), \
204 .max_antenna_gain = 0, \
205 .max_power = 30, \
206}
207static struct ieee80211_channel b43_2ghz_chantable[] = {
208 CHAN2G(1, 2412, 0),
209 CHAN2G(2, 2417, 0),
210 CHAN2G(3, 2422, 0),
211 CHAN2G(4, 2427, 0),
212 CHAN2G(5, 2432, 0),
213 CHAN2G(6, 2437, 0),
214 CHAN2G(7, 2442, 0),
215 CHAN2G(8, 2447, 0),
216 CHAN2G(9, 2452, 0),
217 CHAN2G(10, 2457, 0),
218 CHAN2G(11, 2462, 0),
219 CHAN2G(12, 2467, 0),
220 CHAN2G(13, 2472, 0),
221 CHAN2G(14, 2484, 0),
222};
223
224/* No support for the last 3 channels (12, 13, 14) */
225#define b43_2ghz_chantable_limited_size 11
226#undef CHAN2G
227
228#define CHAN4G(_channel, _flags) { \
229 .band = NL80211_BAND_5GHZ, \
230 .center_freq = 4000 + (5 * (_channel)), \
231 .hw_value = (_channel), \
232 .flags = (_flags), \
233 .max_antenna_gain = 0, \
234 .max_power = 30, \
235}
236#define CHAN5G(_channel, _flags) { \
237 .band = NL80211_BAND_5GHZ, \
238 .center_freq = 5000 + (5 * (_channel)), \
239 .hw_value = (_channel), \
240 .flags = (_flags), \
241 .max_antenna_gain = 0, \
242 .max_power = 30, \
243}
244static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
245 CHAN4G(184, 0), CHAN4G(186, 0),
246 CHAN4G(188, 0), CHAN4G(190, 0),
247 CHAN4G(192, 0), CHAN4G(194, 0),
248 CHAN4G(196, 0), CHAN4G(198, 0),
249 CHAN4G(200, 0), CHAN4G(202, 0),
250 CHAN4G(204, 0), CHAN4G(206, 0),
251 CHAN4G(208, 0), CHAN4G(210, 0),
252 CHAN4G(212, 0), CHAN4G(214, 0),
253 CHAN4G(216, 0), CHAN4G(218, 0),
254 CHAN4G(220, 0), CHAN4G(222, 0),
255 CHAN4G(224, 0), CHAN4G(226, 0),
256 CHAN4G(228, 0),
257 CHAN5G(32, 0), CHAN5G(34, 0),
258 CHAN5G(36, 0), CHAN5G(38, 0),
259 CHAN5G(40, 0), CHAN5G(42, 0),
260 CHAN5G(44, 0), CHAN5G(46, 0),
261 CHAN5G(48, 0), CHAN5G(50, 0),
262 CHAN5G(52, 0), CHAN5G(54, 0),
263 CHAN5G(56, 0), CHAN5G(58, 0),
264 CHAN5G(60, 0), CHAN5G(62, 0),
265 CHAN5G(64, 0), CHAN5G(66, 0),
266 CHAN5G(68, 0), CHAN5G(70, 0),
267 CHAN5G(72, 0), CHAN5G(74, 0),
268 CHAN5G(76, 0), CHAN5G(78, 0),
269 CHAN5G(80, 0), CHAN5G(82, 0),
270 CHAN5G(84, 0), CHAN5G(86, 0),
271 CHAN5G(88, 0), CHAN5G(90, 0),
272 CHAN5G(92, 0), CHAN5G(94, 0),
273 CHAN5G(96, 0), CHAN5G(98, 0),
274 CHAN5G(100, 0), CHAN5G(102, 0),
275 CHAN5G(104, 0), CHAN5G(106, 0),
276 CHAN5G(108, 0), CHAN5G(110, 0),
277 CHAN5G(112, 0), CHAN5G(114, 0),
278 CHAN5G(116, 0), CHAN5G(118, 0),
279 CHAN5G(120, 0), CHAN5G(122, 0),
280 CHAN5G(124, 0), CHAN5G(126, 0),
281 CHAN5G(128, 0), CHAN5G(130, 0),
282 CHAN5G(132, 0), CHAN5G(134, 0),
283 CHAN5G(136, 0), CHAN5G(138, 0),
284 CHAN5G(140, 0), CHAN5G(142, 0),
285 CHAN5G(144, 0), CHAN5G(145, 0),
286 CHAN5G(146, 0), CHAN5G(147, 0),
287 CHAN5G(148, 0), CHAN5G(149, 0),
288 CHAN5G(150, 0), CHAN5G(151, 0),
289 CHAN5G(152, 0), CHAN5G(153, 0),
290 CHAN5G(154, 0), CHAN5G(155, 0),
291 CHAN5G(156, 0), CHAN5G(157, 0),
292 CHAN5G(158, 0), CHAN5G(159, 0),
293 CHAN5G(160, 0), CHAN5G(161, 0),
294 CHAN5G(162, 0), CHAN5G(163, 0),
295 CHAN5G(164, 0), CHAN5G(165, 0),
296 CHAN5G(166, 0), CHAN5G(168, 0),
297 CHAN5G(170, 0), CHAN5G(172, 0),
298 CHAN5G(174, 0), CHAN5G(176, 0),
299 CHAN5G(178, 0), CHAN5G(180, 0),
300 CHAN5G(182, 0),
301};
302
303static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
304 CHAN5G(36, 0), CHAN5G(40, 0),
305 CHAN5G(44, 0), CHAN5G(48, 0),
306 CHAN5G(149, 0), CHAN5G(153, 0),
307 CHAN5G(157, 0), CHAN5G(161, 0),
308 CHAN5G(165, 0),
309};
310
311static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
312 CHAN5G(34, 0), CHAN5G(36, 0),
313 CHAN5G(38, 0), CHAN5G(40, 0),
314 CHAN5G(42, 0), CHAN5G(44, 0),
315 CHAN5G(46, 0), CHAN5G(48, 0),
316 CHAN5G(52, 0), CHAN5G(56, 0),
317 CHAN5G(60, 0), CHAN5G(64, 0),
318 CHAN5G(100, 0), CHAN5G(104, 0),
319 CHAN5G(108, 0), CHAN5G(112, 0),
320 CHAN5G(116, 0), CHAN5G(120, 0),
321 CHAN5G(124, 0), CHAN5G(128, 0),
322 CHAN5G(132, 0), CHAN5G(136, 0),
323 CHAN5G(140, 0), CHAN5G(149, 0),
324 CHAN5G(153, 0), CHAN5G(157, 0),
325 CHAN5G(161, 0), CHAN5G(165, 0),
326 CHAN5G(184, 0), CHAN5G(188, 0),
327 CHAN5G(192, 0), CHAN5G(196, 0),
328 CHAN5G(200, 0), CHAN5G(204, 0),
329 CHAN5G(208, 0), CHAN5G(212, 0),
330 CHAN5G(216, 0),
331};
332#undef CHAN4G
333#undef CHAN5G
334
335static struct ieee80211_supported_band b43_band_5GHz_nphy = {
336 .band = NL80211_BAND_5GHZ,
337 .channels = b43_5ghz_nphy_chantable,
338 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
339 .bitrates = b43_a_ratetable,
340 .n_bitrates = b43_a_ratetable_size,
341};
342
343static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
344 .band = NL80211_BAND_5GHZ,
345 .channels = b43_5ghz_nphy_chantable_limited,
346 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
347 .bitrates = b43_a_ratetable,
348 .n_bitrates = b43_a_ratetable_size,
349};
350
351static struct ieee80211_supported_band b43_band_5GHz_aphy = {
352 .band = NL80211_BAND_5GHZ,
353 .channels = b43_5ghz_aphy_chantable,
354 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
355 .bitrates = b43_a_ratetable,
356 .n_bitrates = b43_a_ratetable_size,
357};
358
359static struct ieee80211_supported_band b43_band_2GHz = {
360 .band = NL80211_BAND_2GHZ,
361 .channels = b43_2ghz_chantable,
362 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
363 .bitrates = b43_g_ratetable,
364 .n_bitrates = b43_g_ratetable_size,
365};
366
367static struct ieee80211_supported_band b43_band_2ghz_limited = {
368 .band = NL80211_BAND_2GHZ,
369 .channels = b43_2ghz_chantable,
370 .n_channels = b43_2ghz_chantable_limited_size,
371 .bitrates = b43_g_ratetable,
372 .n_bitrates = b43_g_ratetable_size,
373};
374
375static void b43_wireless_core_exit(struct b43_wldev *dev);
376static int b43_wireless_core_init(struct b43_wldev *dev);
377static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
378static int b43_wireless_core_start(struct b43_wldev *dev);
379static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
380 struct ieee80211_vif *vif,
381 struct ieee80211_bss_conf *conf,
382 u32 changed);
383
384static int b43_ratelimit(struct b43_wl *wl)
385{
386 if (!wl || !wl->current_dev)
387 return 1;
388 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
389 return 1;
390 /* We are up and running.
391 * Ratelimit the messages to avoid DoS over the net. */
392 return net_ratelimit();
393}
394
395void b43info(struct b43_wl *wl, const char *fmt, ...)
396{
397 struct va_format vaf;
398 va_list args;
399
400 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
401 return;
402 if (!b43_ratelimit(wl))
403 return;
404
405 va_start(args, fmt);
406
407 vaf.fmt = fmt;
408 vaf.va = &args;
409
410 printk(KERN_INFO "b43-%s: %pV",
411 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
412
413 va_end(args);
414}
415
416void b43err(struct b43_wl *wl, const char *fmt, ...)
417{
418 struct va_format vaf;
419 va_list args;
420
421 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
422 return;
423 if (!b43_ratelimit(wl))
424 return;
425
426 va_start(args, fmt);
427
428 vaf.fmt = fmt;
429 vaf.va = &args;
430
431 printk(KERN_ERR "b43-%s ERROR: %pV",
432 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
433
434 va_end(args);
435}
436
437void b43warn(struct b43_wl *wl, const char *fmt, ...)
438{
439 struct va_format vaf;
440 va_list args;
441
442 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
443 return;
444 if (!b43_ratelimit(wl))
445 return;
446
447 va_start(args, fmt);
448
449 vaf.fmt = fmt;
450 vaf.va = &args;
451
452 printk(KERN_WARNING "b43-%s warning: %pV",
453 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
454
455 va_end(args);
456}
457
458void b43dbg(struct b43_wl *wl, const char *fmt, ...)
459{
460 struct va_format vaf;
461 va_list args;
462
463 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
464 return;
465
466 va_start(args, fmt);
467
468 vaf.fmt = fmt;
469 vaf.va = &args;
470
471 printk(KERN_DEBUG "b43-%s debug: %pV",
472 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
473
474 va_end(args);
475}
476
477static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
478{
479 u32 macctl;
480
481 B43_WARN_ON(offset % 4 != 0);
482
483 macctl = b43_read32(dev, B43_MMIO_MACCTL);
484 if (macctl & B43_MACCTL_BE)
485 val = swab32(val);
486
487 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
488 mmiowb();
489 b43_write32(dev, B43_MMIO_RAM_DATA, val);
490}
491
492static inline void b43_shm_control_word(struct b43_wldev *dev,
493 u16 routing, u16 offset)
494{
495 u32 control;
496
497 /* "offset" is the WORD offset. */
498 control = routing;
499 control <<= 16;
500 control |= offset;
501 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
502}
503
504u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
505{
506 u32 ret;
507
508 if (routing == B43_SHM_SHARED) {
509 B43_WARN_ON(offset & 0x0001);
510 if (offset & 0x0003) {
511 /* Unaligned access */
512 b43_shm_control_word(dev, routing, offset >> 2);
513 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
514 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
515 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
516
517 goto out;
518 }
519 offset >>= 2;
520 }
521 b43_shm_control_word(dev, routing, offset);
522 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
523out:
524 return ret;
525}
526
527u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
528{
529 u16 ret;
530
531 if (routing == B43_SHM_SHARED) {
532 B43_WARN_ON(offset & 0x0001);
533 if (offset & 0x0003) {
534 /* Unaligned access */
535 b43_shm_control_word(dev, routing, offset >> 2);
536 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
537
538 goto out;
539 }
540 offset >>= 2;
541 }
542 b43_shm_control_word(dev, routing, offset);
543 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
544out:
545 return ret;
546}
547
548void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
549{
550 if (routing == B43_SHM_SHARED) {
551 B43_WARN_ON(offset & 0x0001);
552 if (offset & 0x0003) {
553 /* Unaligned access */
554 b43_shm_control_word(dev, routing, offset >> 2);
555 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
556 value & 0xFFFF);
557 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
558 b43_write16(dev, B43_MMIO_SHM_DATA,
559 (value >> 16) & 0xFFFF);
560 return;
561 }
562 offset >>= 2;
563 }
564 b43_shm_control_word(dev, routing, offset);
565 b43_write32(dev, B43_MMIO_SHM_DATA, value);
566}
567
568void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
569{
570 if (routing == B43_SHM_SHARED) {
571 B43_WARN_ON(offset & 0x0001);
572 if (offset & 0x0003) {
573 /* Unaligned access */
574 b43_shm_control_word(dev, routing, offset >> 2);
575 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
576 return;
577 }
578 offset >>= 2;
579 }
580 b43_shm_control_word(dev, routing, offset);
581 b43_write16(dev, B43_MMIO_SHM_DATA, value);
582}
583
584/* Read HostFlags */
585u64 b43_hf_read(struct b43_wldev *dev)
586{
587 u64 ret;
588
589 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
590 ret <<= 16;
591 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
592 ret <<= 16;
593 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
594
595 return ret;
596}
597
598/* Write HostFlags */
599void b43_hf_write(struct b43_wldev *dev, u64 value)
600{
601 u16 lo, mi, hi;
602
603 lo = (value & 0x00000000FFFFULL);
604 mi = (value & 0x0000FFFF0000ULL) >> 16;
605 hi = (value & 0xFFFF00000000ULL) >> 32;
606 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
607 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
608 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
609}
610
611/* Read the firmware capabilities bitmask (Opensource firmware only) */
612static u16 b43_fwcapa_read(struct b43_wldev *dev)
613{
614 B43_WARN_ON(!dev->fw.opensource);
615 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
616}
617
618void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
619{
620 u32 low, high;
621
622 B43_WARN_ON(dev->dev->core_rev < 3);
623
624 /* The hardware guarantees us an atomic read, if we
625 * read the low register first. */
626 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
627 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
628
629 *tsf = high;
630 *tsf <<= 32;
631 *tsf |= low;
632}
633
634static void b43_time_lock(struct b43_wldev *dev)
635{
636 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
637 /* Commit the write */
638 b43_read32(dev, B43_MMIO_MACCTL);
639}
640
641static void b43_time_unlock(struct b43_wldev *dev)
642{
643 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
644 /* Commit the write */
645 b43_read32(dev, B43_MMIO_MACCTL);
646}
647
648static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
649{
650 u32 low, high;
651
652 B43_WARN_ON(dev->dev->core_rev < 3);
653
654 low = tsf;
655 high = (tsf >> 32);
656 /* The hardware guarantees us an atomic write, if we
657 * write the low register first. */
658 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
659 mmiowb();
660 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
661 mmiowb();
662}
663
664void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
665{
666 b43_time_lock(dev);
667 b43_tsf_write_locked(dev, tsf);
668 b43_time_unlock(dev);
669}
670
671static
672void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
673{
674 static const u8 zero_addr[ETH_ALEN] = { 0 };
675 u16 data;
676
677 if (!mac)
678 mac = zero_addr;
679
680 offset |= 0x0020;
681 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
682
683 data = mac[0];
684 data |= mac[1] << 8;
685 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
686 data = mac[2];
687 data |= mac[3] << 8;
688 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
689 data = mac[4];
690 data |= mac[5] << 8;
691 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
692}
693
694static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
695{
696 const u8 *mac;
697 const u8 *bssid;
698 u8 mac_bssid[ETH_ALEN * 2];
699 int i;
700 u32 tmp;
701
702 bssid = dev->wl->bssid;
703 mac = dev->wl->mac_addr;
704
705 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
706
707 memcpy(mac_bssid, mac, ETH_ALEN);
708 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
709
710 /* Write our MAC address and BSSID to template ram */
711 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
712 tmp = (u32) (mac_bssid[i + 0]);
713 tmp |= (u32) (mac_bssid[i + 1]) << 8;
714 tmp |= (u32) (mac_bssid[i + 2]) << 16;
715 tmp |= (u32) (mac_bssid[i + 3]) << 24;
716 b43_ram_write(dev, 0x20 + i, tmp);
717 }
718}
719
720static void b43_upload_card_macaddress(struct b43_wldev *dev)
721{
722 b43_write_mac_bssid_templates(dev);
723 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
724}
725
726static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
727{
728 /* slot_time is in usec. */
729 /* This test used to exit for all but a G PHY. */
730 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
731 return;
732 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
733 /* Shared memory location 0x0010 is the slot time and should be
734 * set to slot_time; however, this register is initially 0 and changing
735 * the value adversely affects the transmit rate for BCM4311
736 * devices. Until this behavior is unterstood, delete this step
737 *
738 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
739 */
740}
741
742static void b43_short_slot_timing_enable(struct b43_wldev *dev)
743{
744 b43_set_slot_time(dev, 9);
745}
746
747static void b43_short_slot_timing_disable(struct b43_wldev *dev)
748{
749 b43_set_slot_time(dev, 20);
750}
751
752/* DummyTransmission function, as documented on
753 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
754 */
755void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
756{
757 struct b43_phy *phy = &dev->phy;
758 unsigned int i, max_loop;
759 u16 value;
760 u32 buffer[5] = {
761 0x00000000,
762 0x00D40000,
763 0x00000000,
764 0x01000000,
765 0x00000000,
766 };
767
768 if (ofdm) {
769 max_loop = 0x1E;
770 buffer[0] = 0x000201CC;
771 } else {
772 max_loop = 0xFA;
773 buffer[0] = 0x000B846E;
774 }
775
776 for (i = 0; i < 5; i++)
777 b43_ram_write(dev, i * 4, buffer[i]);
778
779 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
780
781 if (dev->dev->core_rev < 11)
782 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
783 else
784 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
785
786 value = (ofdm ? 0x41 : 0x40);
787 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
788 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
789 phy->type == B43_PHYTYPE_LCN)
790 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
791
792 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
793 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
794
795 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
796 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
797 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
798 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
799
800 if (!pa_on && phy->type == B43_PHYTYPE_N)
801 ; /*b43_nphy_pa_override(dev, false) */
802
803 switch (phy->type) {
804 case B43_PHYTYPE_N:
805 case B43_PHYTYPE_LCN:
806 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
807 break;
808 case B43_PHYTYPE_LP:
809 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
810 break;
811 default:
812 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
813 }
814 b43_read16(dev, B43_MMIO_TXE0_AUX);
815
816 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
817 b43_radio_write16(dev, 0x0051, 0x0017);
818 for (i = 0x00; i < max_loop; i++) {
819 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
820 if (value & 0x0080)
821 break;
822 udelay(10);
823 }
824 for (i = 0x00; i < 0x0A; i++) {
825 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
826 if (value & 0x0400)
827 break;
828 udelay(10);
829 }
830 for (i = 0x00; i < 0x19; i++) {
831 value = b43_read16(dev, B43_MMIO_IFSSTAT);
832 if (!(value & 0x0100))
833 break;
834 udelay(10);
835 }
836 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
837 b43_radio_write16(dev, 0x0051, 0x0037);
838}
839
840static void key_write(struct b43_wldev *dev,
841 u8 index, u8 algorithm, const u8 *key)
842{
843 unsigned int i;
844 u32 offset;
845 u16 value;
846 u16 kidx;
847
848 /* Key index/algo block */
849 kidx = b43_kidx_to_fw(dev, index);
850 value = ((kidx << 4) | algorithm);
851 b43_shm_write16(dev, B43_SHM_SHARED,
852 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
853
854 /* Write the key to the Key Table Pointer offset */
855 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
856 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
857 value = key[i];
858 value |= (u16) (key[i + 1]) << 8;
859 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
860 }
861}
862
863static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
864{
865 u32 addrtmp[2] = { 0, 0, };
866 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
867
868 if (b43_new_kidx_api(dev))
869 pairwise_keys_start = B43_NR_GROUP_KEYS;
870
871 B43_WARN_ON(index < pairwise_keys_start);
872 /* We have four default TX keys and possibly four default RX keys.
873 * Physical mac 0 is mapped to physical key 4 or 8, depending
874 * on the firmware version.
875 * So we must adjust the index here.
876 */
877 index -= pairwise_keys_start;
878 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
879
880 if (addr) {
881 addrtmp[0] = addr[0];
882 addrtmp[0] |= ((u32) (addr[1]) << 8);
883 addrtmp[0] |= ((u32) (addr[2]) << 16);
884 addrtmp[0] |= ((u32) (addr[3]) << 24);
885 addrtmp[1] = addr[4];
886 addrtmp[1] |= ((u32) (addr[5]) << 8);
887 }
888
889 /* Receive match transmitter address (RCMTA) mechanism */
890 b43_shm_write32(dev, B43_SHM_RCMTA,
891 (index * 2) + 0, addrtmp[0]);
892 b43_shm_write16(dev, B43_SHM_RCMTA,
893 (index * 2) + 1, addrtmp[1]);
894}
895
896/* The ucode will use phase1 key with TEK key to decrypt rx packets.
897 * When a packet is received, the iv32 is checked.
898 * - if it doesn't the packet is returned without modification (and software
899 * decryption can be done). That's what happen when iv16 wrap.
900 * - if it does, the rc4 key is computed, and decryption is tried.
901 * Either it will success and B43_RX_MAC_DEC is returned,
902 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
903 * and the packet is not usable (it got modified by the ucode).
904 * So in order to never have B43_RX_MAC_DECERR, we should provide
905 * a iv32 and phase1key that match. Because we drop packets in case of
906 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
907 * packets will be lost without higher layer knowing (ie no resync possible
908 * until next wrap).
909 *
910 * NOTE : this should support 50 key like RCMTA because
911 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
912 */
913static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
914 u16 *phase1key)
915{
916 unsigned int i;
917 u32 offset;
918 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
919
920 if (!modparam_hwtkip)
921 return;
922
923 if (b43_new_kidx_api(dev))
924 pairwise_keys_start = B43_NR_GROUP_KEYS;
925
926 B43_WARN_ON(index < pairwise_keys_start);
927 /* We have four default TX keys and possibly four default RX keys.
928 * Physical mac 0 is mapped to physical key 4 or 8, depending
929 * on the firmware version.
930 * So we must adjust the index here.
931 */
932 index -= pairwise_keys_start;
933 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
934
935 if (b43_debug(dev, B43_DBG_KEYS)) {
936 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
937 index, iv32);
938 }
939 /* Write the key to the RX tkip shared mem */
940 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
941 for (i = 0; i < 10; i += 2) {
942 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
943 phase1key ? phase1key[i / 2] : 0);
944 }
945 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
946 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
947}
948
949static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
950 struct ieee80211_vif *vif,
951 struct ieee80211_key_conf *keyconf,
952 struct ieee80211_sta *sta,
953 u32 iv32, u16 *phase1key)
954{
955 struct b43_wl *wl = hw_to_b43_wl(hw);
956 struct b43_wldev *dev;
957 int index = keyconf->hw_key_idx;
958
959 if (B43_WARN_ON(!modparam_hwtkip))
960 return;
961
962 /* This is only called from the RX path through mac80211, where
963 * our mutex is already locked. */
964 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
965 dev = wl->current_dev;
966 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
967
968 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
969
970 rx_tkip_phase1_write(dev, index, iv32, phase1key);
971 /* only pairwise TKIP keys are supported right now */
972 if (WARN_ON(!sta))
973 return;
974 keymac_write(dev, index, sta->addr);
975}
976
977static void do_key_write(struct b43_wldev *dev,
978 u8 index, u8 algorithm,
979 const u8 *key, size_t key_len, const u8 *mac_addr)
980{
981 u8 buf[B43_SEC_KEYSIZE] = { 0, };
982 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
983
984 if (b43_new_kidx_api(dev))
985 pairwise_keys_start = B43_NR_GROUP_KEYS;
986
987 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
988 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
989
990 if (index >= pairwise_keys_start)
991 keymac_write(dev, index, NULL); /* First zero out mac. */
992 if (algorithm == B43_SEC_ALGO_TKIP) {
993 /*
994 * We should provide an initial iv32, phase1key pair.
995 * We could start with iv32=0 and compute the corresponding
996 * phase1key, but this means calling ieee80211_get_tkip_key
997 * with a fake skb (or export other tkip function).
998 * Because we are lazy we hope iv32 won't start with
999 * 0xffffffff and let's b43_op_update_tkip_key provide a
1000 * correct pair.
1001 */
1002 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
1003 } else if (index >= pairwise_keys_start) /* clear it */
1004 rx_tkip_phase1_write(dev, index, 0, NULL);
1005 if (key)
1006 memcpy(buf, key, key_len);
1007 key_write(dev, index, algorithm, buf);
1008 if (index >= pairwise_keys_start)
1009 keymac_write(dev, index, mac_addr);
1010
1011 dev->key[index].algorithm = algorithm;
1012}
1013
1014static int b43_key_write(struct b43_wldev *dev,
1015 int index, u8 algorithm,
1016 const u8 *key, size_t key_len,
1017 const u8 *mac_addr,
1018 struct ieee80211_key_conf *keyconf)
1019{
1020 int i;
1021 int pairwise_keys_start;
1022
1023 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1024 * - Temporal Encryption Key (128 bits)
1025 * - Temporal Authenticator Tx MIC Key (64 bits)
1026 * - Temporal Authenticator Rx MIC Key (64 bits)
1027 *
1028 * Hardware only store TEK
1029 */
1030 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1031 key_len = 16;
1032 if (key_len > B43_SEC_KEYSIZE)
1033 return -EINVAL;
1034 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
1035 /* Check that we don't already have this key. */
1036 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1037 }
1038 if (index < 0) {
1039 /* Pairwise key. Get an empty slot for the key. */
1040 if (b43_new_kidx_api(dev))
1041 pairwise_keys_start = B43_NR_GROUP_KEYS;
1042 else
1043 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1044 for (i = pairwise_keys_start;
1045 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1046 i++) {
1047 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
1048 if (!dev->key[i].keyconf) {
1049 /* found empty */
1050 index = i;
1051 break;
1052 }
1053 }
1054 if (index < 0) {
1055 b43warn(dev->wl, "Out of hardware key memory\n");
1056 return -ENOSPC;
1057 }
1058 } else
1059 B43_WARN_ON(index > 3);
1060
1061 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1062 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1063 /* Default RX key */
1064 B43_WARN_ON(mac_addr);
1065 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1066 }
1067 keyconf->hw_key_idx = index;
1068 dev->key[index].keyconf = keyconf;
1069
1070 return 0;
1071}
1072
1073static int b43_key_clear(struct b43_wldev *dev, int index)
1074{
1075 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1076 return -EINVAL;
1077 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1078 NULL, B43_SEC_KEYSIZE, NULL);
1079 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1080 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1081 NULL, B43_SEC_KEYSIZE, NULL);
1082 }
1083 dev->key[index].keyconf = NULL;
1084
1085 return 0;
1086}
1087
1088static void b43_clear_keys(struct b43_wldev *dev)
1089{
1090 int i, count;
1091
1092 if (b43_new_kidx_api(dev))
1093 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1094 else
1095 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1096 for (i = 0; i < count; i++)
1097 b43_key_clear(dev, i);
1098}
1099
1100static void b43_dump_keymemory(struct b43_wldev *dev)
1101{
1102 unsigned int i, index, count, offset, pairwise_keys_start;
1103 u8 mac[ETH_ALEN];
1104 u16 algo;
1105 u32 rcmta0;
1106 u16 rcmta1;
1107 u64 hf;
1108 struct b43_key *key;
1109
1110 if (!b43_debug(dev, B43_DBG_KEYS))
1111 return;
1112
1113 hf = b43_hf_read(dev);
1114 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1115 !!(hf & B43_HF_USEDEFKEYS));
1116 if (b43_new_kidx_api(dev)) {
1117 pairwise_keys_start = B43_NR_GROUP_KEYS;
1118 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1119 } else {
1120 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1121 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1122 }
1123 for (index = 0; index < count; index++) {
1124 key = &(dev->key[index]);
1125 printk(KERN_DEBUG "Key slot %02u: %s",
1126 index, (key->keyconf == NULL) ? " " : "*");
1127 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1128 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1129 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1130 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1131 }
1132
1133 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1134 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1135 printk(" Algo: %04X/%02X", algo, key->algorithm);
1136
1137 if (index >= pairwise_keys_start) {
1138 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1139 printk(" TKIP: ");
1140 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1141 for (i = 0; i < 14; i += 2) {
1142 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1143 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1144 }
1145 }
1146 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1147 ((index - pairwise_keys_start) * 2) + 0);
1148 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1149 ((index - pairwise_keys_start) * 2) + 1);
1150 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1151 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1152 printk(" MAC: %pM", mac);
1153 } else
1154 printk(" DEFAULT KEY");
1155 printk("\n");
1156 }
1157}
1158
1159void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1160{
1161 u32 macctl;
1162 u16 ucstat;
1163 bool hwps;
1164 bool awake;
1165 int i;
1166
1167 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1168 (ps_flags & B43_PS_DISABLED));
1169 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1170
1171 if (ps_flags & B43_PS_ENABLED) {
1172 hwps = true;
1173 } else if (ps_flags & B43_PS_DISABLED) {
1174 hwps = false;
1175 } else {
1176 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1177 // and thus is not an AP and we are associated, set bit 25
1178 }
1179 if (ps_flags & B43_PS_AWAKE) {
1180 awake = true;
1181 } else if (ps_flags & B43_PS_ASLEEP) {
1182 awake = false;
1183 } else {
1184 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1185 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1186 // successful, set bit26
1187 }
1188
1189/* FIXME: For now we force awake-on and hwps-off */
1190 hwps = false;
1191 awake = true;
1192
1193 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1194 if (hwps)
1195 macctl |= B43_MACCTL_HWPS;
1196 else
1197 macctl &= ~B43_MACCTL_HWPS;
1198 if (awake)
1199 macctl |= B43_MACCTL_AWAKE;
1200 else
1201 macctl &= ~B43_MACCTL_AWAKE;
1202 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1203 /* Commit write */
1204 b43_read32(dev, B43_MMIO_MACCTL);
1205 if (awake && dev->dev->core_rev >= 5) {
1206 /* Wait for the microcode to wake up. */
1207 for (i = 0; i < 100; i++) {
1208 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1209 B43_SHM_SH_UCODESTAT);
1210 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1211 break;
1212 udelay(10);
1213 }
1214 }
1215}
1216
1217/* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
1218void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1219{
1220 struct bcma_drv_cc *bcma_cc __maybe_unused;
1221 struct ssb_chipcommon *ssb_cc __maybe_unused;
1222
1223 switch (dev->dev->bus_type) {
1224#ifdef CONFIG_B43_BCMA
1225 case B43_BUS_BCMA:
1226 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1227
1228 bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
1229 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1230 bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
1231 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1232 break;
1233#endif
1234#ifdef CONFIG_B43_SSB
1235 case B43_BUS_SSB:
1236 ssb_cc = &dev->dev->sdev->bus->chipco;
1237
1238 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0);
1239 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1240 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4);
1241 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1242 break;
1243#endif
1244 }
1245}
1246
1247#ifdef CONFIG_B43_BCMA
1248static void b43_bcma_phy_reset(struct b43_wldev *dev)
1249{
1250 u32 flags;
1251
1252 /* Put PHY into reset */
1253 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1254 flags |= B43_BCMA_IOCTL_PHY_RESET;
1255 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1256 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1257 udelay(2);
1258
1259 b43_phy_take_out_of_reset(dev);
1260}
1261
1262static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1263{
1264 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1265 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1266 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1267 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1268 u32 flags;
1269
1270 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1271 if (gmode)
1272 flags |= B43_BCMA_IOCTL_GMODE;
1273 b43_device_enable(dev, flags);
1274
1275 if (dev->phy.type == B43_PHYTYPE_AC) {
1276 u16 tmp;
1277
1278 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1279 tmp &= ~B43_BCMA_IOCTL_DAC;
1280 tmp |= 0x100;
1281 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1282
1283 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1284 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
1285 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1286
1287 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1288 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
1289 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1290 }
1291
1292 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1293 b43_bcma_phy_reset(dev);
1294 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1295}
1296#endif
1297
1298#ifdef CONFIG_B43_SSB
1299static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1300{
1301 u32 flags = 0;
1302
1303 if (gmode)
1304 flags |= B43_TMSLOW_GMODE;
1305 flags |= B43_TMSLOW_PHYCLKEN;
1306 flags |= B43_TMSLOW_PHYRESET;
1307 if (dev->phy.type == B43_PHYTYPE_N)
1308 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1309 b43_device_enable(dev, flags);
1310 msleep(2); /* Wait for the PLL to turn on. */
1311
1312 b43_phy_take_out_of_reset(dev);
1313}
1314#endif
1315
1316void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1317{
1318 u32 macctl;
1319
1320 switch (dev->dev->bus_type) {
1321#ifdef CONFIG_B43_BCMA
1322 case B43_BUS_BCMA:
1323 b43_bcma_wireless_core_reset(dev, gmode);
1324 break;
1325#endif
1326#ifdef CONFIG_B43_SSB
1327 case B43_BUS_SSB:
1328 b43_ssb_wireless_core_reset(dev, gmode);
1329 break;
1330#endif
1331 }
1332
1333 /* Turn Analog ON, but only if we already know the PHY-type.
1334 * This protects against very early setup where we don't know the
1335 * PHY-type, yet. wireless_core_reset will be called once again later,
1336 * when we know the PHY-type. */
1337 if (dev->phy.ops)
1338 dev->phy.ops->switch_analog(dev, 1);
1339
1340 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1341 macctl &= ~B43_MACCTL_GMODE;
1342 if (gmode)
1343 macctl |= B43_MACCTL_GMODE;
1344 macctl |= B43_MACCTL_IHR_ENABLED;
1345 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1346}
1347
1348static void handle_irq_transmit_status(struct b43_wldev *dev)
1349{
1350 u32 v0, v1;
1351 u16 tmp;
1352 struct b43_txstatus stat;
1353
1354 while (1) {
1355 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1356 if (!(v0 & 0x00000001))
1357 break;
1358 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1359
1360 stat.cookie = (v0 >> 16);
1361 stat.seq = (v1 & 0x0000FFFF);
1362 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1363 tmp = (v0 & 0x0000FFFF);
1364 stat.frame_count = ((tmp & 0xF000) >> 12);
1365 stat.rts_count = ((tmp & 0x0F00) >> 8);
1366 stat.supp_reason = ((tmp & 0x001C) >> 2);
1367 stat.pm_indicated = !!(tmp & 0x0080);
1368 stat.intermediate = !!(tmp & 0x0040);
1369 stat.for_ampdu = !!(tmp & 0x0020);
1370 stat.acked = !!(tmp & 0x0002);
1371
1372 b43_handle_txstatus(dev, &stat);
1373 }
1374}
1375
1376static void drain_txstatus_queue(struct b43_wldev *dev)
1377{
1378 u32 dummy;
1379
1380 if (dev->dev->core_rev < 5)
1381 return;
1382 /* Read all entries from the microcode TXstatus FIFO
1383 * and throw them away.
1384 */
1385 while (1) {
1386 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1387 if (!(dummy & 0x00000001))
1388 break;
1389 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1390 }
1391}
1392
1393static u32 b43_jssi_read(struct b43_wldev *dev)
1394{
1395 u32 val = 0;
1396
1397 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1398 val <<= 16;
1399 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1400
1401 return val;
1402}
1403
1404static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1405{
1406 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1407 (jssi & 0x0000FFFF));
1408 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1409 (jssi & 0xFFFF0000) >> 16);
1410}
1411
1412static void b43_generate_noise_sample(struct b43_wldev *dev)
1413{
1414 b43_jssi_write(dev, 0x7F7F7F7F);
1415 b43_write32(dev, B43_MMIO_MACCMD,
1416 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1417}
1418
1419static void b43_calculate_link_quality(struct b43_wldev *dev)
1420{
1421 /* Top half of Link Quality calculation. */
1422
1423 if (dev->phy.type != B43_PHYTYPE_G)
1424 return;
1425 if (dev->noisecalc.calculation_running)
1426 return;
1427 dev->noisecalc.calculation_running = true;
1428 dev->noisecalc.nr_samples = 0;
1429
1430 b43_generate_noise_sample(dev);
1431}
1432
1433static void handle_irq_noise(struct b43_wldev *dev)
1434{
1435 struct b43_phy_g *phy = dev->phy.g;
1436 u16 tmp;
1437 u8 noise[4];
1438 u8 i, j;
1439 s32 average;
1440
1441 /* Bottom half of Link Quality calculation. */
1442
1443 if (dev->phy.type != B43_PHYTYPE_G)
1444 return;
1445
1446 /* Possible race condition: It might be possible that the user
1447 * changed to a different channel in the meantime since we
1448 * started the calculation. We ignore that fact, since it's
1449 * not really that much of a problem. The background noise is
1450 * an estimation only anyway. Slightly wrong results will get damped
1451 * by the averaging of the 8 sample rounds. Additionally the
1452 * value is shortlived. So it will be replaced by the next noise
1453 * calculation round soon. */
1454
1455 B43_WARN_ON(!dev->noisecalc.calculation_running);
1456 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1457 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1458 noise[2] == 0x7F || noise[3] == 0x7F)
1459 goto generate_new;
1460
1461 /* Get the noise samples. */
1462 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1463 i = dev->noisecalc.nr_samples;
1464 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1465 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1466 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1467 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1468 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1469 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1470 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1471 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1472 dev->noisecalc.nr_samples++;
1473 if (dev->noisecalc.nr_samples == 8) {
1474 /* Calculate the Link Quality by the noise samples. */
1475 average = 0;
1476 for (i = 0; i < 8; i++) {
1477 for (j = 0; j < 4; j++)
1478 average += dev->noisecalc.samples[i][j];
1479 }
1480 average /= (8 * 4);
1481 average *= 125;
1482 average += 64;
1483 average /= 128;
1484 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1485 tmp = (tmp / 128) & 0x1F;
1486 if (tmp >= 8)
1487 average += 2;
1488 else
1489 average -= 25;
1490 if (tmp == 8)
1491 average -= 72;
1492 else
1493 average -= 48;
1494
1495 dev->stats.link_noise = average;
1496 dev->noisecalc.calculation_running = false;
1497 return;
1498 }
1499generate_new:
1500 b43_generate_noise_sample(dev);
1501}
1502
1503static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1504{
1505 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1506 ///TODO: PS TBTT
1507 } else {
1508 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1509 b43_power_saving_ctl_bits(dev, 0);
1510 }
1511 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1512 dev->dfq_valid = true;
1513}
1514
1515static void handle_irq_atim_end(struct b43_wldev *dev)
1516{
1517 if (dev->dfq_valid) {
1518 b43_write32(dev, B43_MMIO_MACCMD,
1519 b43_read32(dev, B43_MMIO_MACCMD)
1520 | B43_MACCMD_DFQ_VALID);
1521 dev->dfq_valid = false;
1522 }
1523}
1524
1525static void handle_irq_pmq(struct b43_wldev *dev)
1526{
1527 u32 tmp;
1528
1529 //TODO: AP mode.
1530
1531 while (1) {
1532 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1533 if (!(tmp & 0x00000008))
1534 break;
1535 }
1536 /* 16bit write is odd, but correct. */
1537 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1538}
1539
1540static void b43_write_template_common(struct b43_wldev *dev,
1541 const u8 *data, u16 size,
1542 u16 ram_offset,
1543 u16 shm_size_offset, u8 rate)
1544{
1545 u32 i, tmp;
1546 struct b43_plcp_hdr4 plcp;
1547
1548 plcp.data = 0;
1549 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1550 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1551 ram_offset += sizeof(u32);
1552 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1553 * So leave the first two bytes of the next write blank.
1554 */
1555 tmp = (u32) (data[0]) << 16;
1556 tmp |= (u32) (data[1]) << 24;
1557 b43_ram_write(dev, ram_offset, tmp);
1558 ram_offset += sizeof(u32);
1559 for (i = 2; i < size; i += sizeof(u32)) {
1560 tmp = (u32) (data[i + 0]);
1561 if (i + 1 < size)
1562 tmp |= (u32) (data[i + 1]) << 8;
1563 if (i + 2 < size)
1564 tmp |= (u32) (data[i + 2]) << 16;
1565 if (i + 3 < size)
1566 tmp |= (u32) (data[i + 3]) << 24;
1567 b43_ram_write(dev, ram_offset + i - 2, tmp);
1568 }
1569 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1570 size + sizeof(struct b43_plcp_hdr6));
1571}
1572
1573/* Check if the use of the antenna that ieee80211 told us to
1574 * use is possible. This will fall back to DEFAULT.
1575 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1576u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1577 u8 antenna_nr)
1578{
1579 u8 antenna_mask;
1580
1581 if (antenna_nr == 0) {
1582 /* Zero means "use default antenna". That's always OK. */
1583 return 0;
1584 }
1585
1586 /* Get the mask of available antennas. */
1587 if (dev->phy.gmode)
1588 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1589 else
1590 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1591
1592 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1593 /* This antenna is not available. Fall back to default. */
1594 return 0;
1595 }
1596
1597 return antenna_nr;
1598}
1599
1600/* Convert a b43 antenna number value to the PHY TX control value. */
1601static u16 b43_antenna_to_phyctl(int antenna)
1602{
1603 switch (antenna) {
1604 case B43_ANTENNA0:
1605 return B43_TXH_PHY_ANT0;
1606 case B43_ANTENNA1:
1607 return B43_TXH_PHY_ANT1;
1608 case B43_ANTENNA2:
1609 return B43_TXH_PHY_ANT2;
1610 case B43_ANTENNA3:
1611 return B43_TXH_PHY_ANT3;
1612 case B43_ANTENNA_AUTO0:
1613 case B43_ANTENNA_AUTO1:
1614 return B43_TXH_PHY_ANT01AUTO;
1615 }
1616 B43_WARN_ON(1);
1617 return 0;
1618}
1619
1620static void b43_write_beacon_template(struct b43_wldev *dev,
1621 u16 ram_offset,
1622 u16 shm_size_offset)
1623{
1624 unsigned int i, len, variable_len;
1625 const struct ieee80211_mgmt *bcn;
1626 const u8 *ie;
1627 bool tim_found = false;
1628 unsigned int rate;
1629 u16 ctl;
1630 int antenna;
1631 struct ieee80211_tx_info *info;
1632 unsigned long flags;
1633 struct sk_buff *beacon_skb;
1634
1635 spin_lock_irqsave(&dev->wl->beacon_lock, flags);
1636 info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1637 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1638 /* Clone the beacon, so it cannot go away, while we write it to hw. */
1639 beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC);
1640 spin_unlock_irqrestore(&dev->wl->beacon_lock, flags);
1641
1642 if (!beacon_skb) {
1643 b43dbg(dev->wl, "Could not upload beacon. "
1644 "Failed to clone beacon skb.");
1645 return;
1646 }
1647
1648 bcn = (const struct ieee80211_mgmt *)(beacon_skb->data);
1649 len = min_t(size_t, beacon_skb->len,
1650 0x200 - sizeof(struct b43_plcp_hdr6));
1651
1652 b43_write_template_common(dev, (const u8 *)bcn,
1653 len, ram_offset, shm_size_offset, rate);
1654
1655 /* Write the PHY TX control parameters. */
1656 antenna = B43_ANTENNA_DEFAULT;
1657 antenna = b43_antenna_to_phyctl(antenna);
1658 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1659 /* We can't send beacons with short preamble. Would get PHY errors. */
1660 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1661 ctl &= ~B43_TXH_PHY_ANT;
1662 ctl &= ~B43_TXH_PHY_ENC;
1663 ctl |= antenna;
1664 if (b43_is_cck_rate(rate))
1665 ctl |= B43_TXH_PHY_ENC_CCK;
1666 else
1667 ctl |= B43_TXH_PHY_ENC_OFDM;
1668 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1669
1670 /* Find the position of the TIM and the DTIM_period value
1671 * and write them to SHM. */
1672 ie = bcn->u.beacon.variable;
1673 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1674 for (i = 0; i < variable_len - 2; ) {
1675 uint8_t ie_id, ie_len;
1676
1677 ie_id = ie[i];
1678 ie_len = ie[i + 1];
1679 if (ie_id == 5) {
1680 u16 tim_position;
1681 u16 dtim_period;
1682 /* This is the TIM Information Element */
1683
1684 /* Check whether the ie_len is in the beacon data range. */
1685 if (variable_len < ie_len + 2 + i)
1686 break;
1687 /* A valid TIM is at least 4 bytes long. */
1688 if (ie_len < 4)
1689 break;
1690 tim_found = true;
1691
1692 tim_position = sizeof(struct b43_plcp_hdr6);
1693 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1694 tim_position += i;
1695
1696 dtim_period = ie[i + 3];
1697
1698 b43_shm_write16(dev, B43_SHM_SHARED,
1699 B43_SHM_SH_TIMBPOS, tim_position);
1700 b43_shm_write16(dev, B43_SHM_SHARED,
1701 B43_SHM_SH_DTIMPER, dtim_period);
1702 break;
1703 }
1704 i += ie_len + 2;
1705 }
1706 if (!tim_found) {
1707 /*
1708 * If ucode wants to modify TIM do it behind the beacon, this
1709 * will happen, for example, when doing mesh networking.
1710 */
1711 b43_shm_write16(dev, B43_SHM_SHARED,
1712 B43_SHM_SH_TIMBPOS,
1713 len + sizeof(struct b43_plcp_hdr6));
1714 b43_shm_write16(dev, B43_SHM_SHARED,
1715 B43_SHM_SH_DTIMPER, 0);
1716 }
1717 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1718
1719 dev_kfree_skb_any(beacon_skb);
1720}
1721
1722static void b43_upload_beacon0(struct b43_wldev *dev)
1723{
1724 struct b43_wl *wl = dev->wl;
1725
1726 if (wl->beacon0_uploaded)
1727 return;
1728 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1729 wl->beacon0_uploaded = true;
1730}
1731
1732static void b43_upload_beacon1(struct b43_wldev *dev)
1733{
1734 struct b43_wl *wl = dev->wl;
1735
1736 if (wl->beacon1_uploaded)
1737 return;
1738 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1739 wl->beacon1_uploaded = true;
1740}
1741
1742static void handle_irq_beacon(struct b43_wldev *dev)
1743{
1744 struct b43_wl *wl = dev->wl;
1745 u32 cmd, beacon0_valid, beacon1_valid;
1746
1747 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1748 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1749 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1750 return;
1751
1752 /* This is the bottom half of the asynchronous beacon update. */
1753
1754 /* Ignore interrupt in the future. */
1755 dev->irq_mask &= ~B43_IRQ_BEACON;
1756
1757 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1758 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1759 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1760
1761 /* Schedule interrupt manually, if busy. */
1762 if (beacon0_valid && beacon1_valid) {
1763 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1764 dev->irq_mask |= B43_IRQ_BEACON;
1765 return;
1766 }
1767
1768 if (unlikely(wl->beacon_templates_virgin)) {
1769 /* We never uploaded a beacon before.
1770 * Upload both templates now, but only mark one valid. */
1771 wl->beacon_templates_virgin = false;
1772 b43_upload_beacon0(dev);
1773 b43_upload_beacon1(dev);
1774 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1775 cmd |= B43_MACCMD_BEACON0_VALID;
1776 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1777 } else {
1778 if (!beacon0_valid) {
1779 b43_upload_beacon0(dev);
1780 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1781 cmd |= B43_MACCMD_BEACON0_VALID;
1782 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1783 } else if (!beacon1_valid) {
1784 b43_upload_beacon1(dev);
1785 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1786 cmd |= B43_MACCMD_BEACON1_VALID;
1787 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1788 }
1789 }
1790}
1791
1792static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1793{
1794 u32 old_irq_mask = dev->irq_mask;
1795
1796 /* update beacon right away or defer to irq */
1797 handle_irq_beacon(dev);
1798 if (old_irq_mask != dev->irq_mask) {
1799 /* The handler updated the IRQ mask. */
1800 B43_WARN_ON(!dev->irq_mask);
1801 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1802 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1803 } else {
1804 /* Device interrupts are currently disabled. That means
1805 * we just ran the hardirq handler and scheduled the
1806 * IRQ thread. The thread will write the IRQ mask when
1807 * it finished, so there's nothing to do here. Writing
1808 * the mask _here_ would incorrectly re-enable IRQs. */
1809 }
1810 }
1811}
1812
1813static void b43_beacon_update_trigger_work(struct work_struct *work)
1814{
1815 struct b43_wl *wl = container_of(work, struct b43_wl,
1816 beacon_update_trigger);
1817 struct b43_wldev *dev;
1818
1819 mutex_lock(&wl->mutex);
1820 dev = wl->current_dev;
1821 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1822 if (b43_bus_host_is_sdio(dev->dev)) {
1823 /* wl->mutex is enough. */
1824 b43_do_beacon_update_trigger_work(dev);
1825 mmiowb();
1826 } else {
1827 spin_lock_irq(&wl->hardirq_lock);
1828 b43_do_beacon_update_trigger_work(dev);
1829 mmiowb();
1830 spin_unlock_irq(&wl->hardirq_lock);
1831 }
1832 }
1833 mutex_unlock(&wl->mutex);
1834}
1835
1836/* Asynchronously update the packet templates in template RAM. */
1837static void b43_update_templates(struct b43_wl *wl)
1838{
1839 struct sk_buff *beacon, *old_beacon;
1840 unsigned long flags;
1841
1842 /* This is the top half of the asynchronous beacon update.
1843 * The bottom half is the beacon IRQ.
1844 * Beacon update must be asynchronous to avoid sending an
1845 * invalid beacon. This can happen for example, if the firmware
1846 * transmits a beacon while we are updating it. */
1847
1848 /* We could modify the existing beacon and set the aid bit in
1849 * the TIM field, but that would probably require resizing and
1850 * moving of data within the beacon template.
1851 * Simply request a new beacon and let mac80211 do the hard work. */
1852 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1853 if (unlikely(!beacon))
1854 return;
1855
1856 spin_lock_irqsave(&wl->beacon_lock, flags);
1857 old_beacon = wl->current_beacon;
1858 wl->current_beacon = beacon;
1859 wl->beacon0_uploaded = false;
1860 wl->beacon1_uploaded = false;
1861 spin_unlock_irqrestore(&wl->beacon_lock, flags);
1862
1863 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1864
1865 if (old_beacon)
1866 dev_kfree_skb_any(old_beacon);
1867}
1868
1869static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1870{
1871 b43_time_lock(dev);
1872 if (dev->dev->core_rev >= 3) {
1873 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1874 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1875 } else {
1876 b43_write16(dev, 0x606, (beacon_int >> 6));
1877 b43_write16(dev, 0x610, beacon_int);
1878 }
1879 b43_time_unlock(dev);
1880 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1881}
1882
1883static void b43_handle_firmware_panic(struct b43_wldev *dev)
1884{
1885 u16 reason;
1886
1887 /* Read the register that contains the reason code for the panic. */
1888 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1889 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1890
1891 switch (reason) {
1892 default:
1893 b43dbg(dev->wl, "The panic reason is unknown.\n");
1894 /* fallthrough */
1895 case B43_FWPANIC_DIE:
1896 /* Do not restart the controller or firmware.
1897 * The device is nonfunctional from now on.
1898 * Restarting would result in this panic to trigger again,
1899 * so we avoid that recursion. */
1900 break;
1901 case B43_FWPANIC_RESTART:
1902 b43_controller_restart(dev, "Microcode panic");
1903 break;
1904 }
1905}
1906
1907static void handle_irq_ucode_debug(struct b43_wldev *dev)
1908{
1909 unsigned int i, cnt;
1910 u16 reason, marker_id, marker_line;
1911 __le16 *buf;
1912
1913 /* The proprietary firmware doesn't have this IRQ. */
1914 if (!dev->fw.opensource)
1915 return;
1916
1917 /* Read the register that contains the reason code for this IRQ. */
1918 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1919
1920 switch (reason) {
1921 case B43_DEBUGIRQ_PANIC:
1922 b43_handle_firmware_panic(dev);
1923 break;
1924 case B43_DEBUGIRQ_DUMP_SHM:
1925 if (!B43_DEBUG)
1926 break; /* Only with driver debugging enabled. */
1927 buf = kmalloc(4096, GFP_ATOMIC);
1928 if (!buf) {
1929 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1930 goto out;
1931 }
1932 for (i = 0; i < 4096; i += 2) {
1933 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1934 buf[i / 2] = cpu_to_le16(tmp);
1935 }
1936 b43info(dev->wl, "Shared memory dump:\n");
1937 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1938 16, 2, buf, 4096, 1);
1939 kfree(buf);
1940 break;
1941 case B43_DEBUGIRQ_DUMP_REGS:
1942 if (!B43_DEBUG)
1943 break; /* Only with driver debugging enabled. */
1944 b43info(dev->wl, "Microcode register dump:\n");
1945 for (i = 0, cnt = 0; i < 64; i++) {
1946 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1947 if (cnt == 0)
1948 printk(KERN_INFO);
1949 printk("r%02u: 0x%04X ", i, tmp);
1950 cnt++;
1951 if (cnt == 6) {
1952 printk("\n");
1953 cnt = 0;
1954 }
1955 }
1956 printk("\n");
1957 break;
1958 case B43_DEBUGIRQ_MARKER:
1959 if (!B43_DEBUG)
1960 break; /* Only with driver debugging enabled. */
1961 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1962 B43_MARKER_ID_REG);
1963 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1964 B43_MARKER_LINE_REG);
1965 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1966 "at line number %u\n",
1967 marker_id, marker_line);
1968 break;
1969 default:
1970 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1971 reason);
1972 }
1973out:
1974 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1975 b43_shm_write16(dev, B43_SHM_SCRATCH,
1976 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1977}
1978
1979static void b43_do_interrupt_thread(struct b43_wldev *dev)
1980{
1981 u32 reason;
1982 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1983 u32 merged_dma_reason = 0;
1984 int i;
1985
1986 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1987 return;
1988
1989 reason = dev->irq_reason;
1990 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1991 dma_reason[i] = dev->dma_reason[i];
1992 merged_dma_reason |= dma_reason[i];
1993 }
1994
1995 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1996 b43err(dev->wl, "MAC transmission error\n");
1997
1998 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1999 b43err(dev->wl, "PHY transmission error\n");
2000 rmb();
2001 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
2002 atomic_set(&dev->phy.txerr_cnt,
2003 B43_PHY_TX_BADNESS_LIMIT);
2004 b43err(dev->wl, "Too many PHY TX errors, "
2005 "restarting the controller\n");
2006 b43_controller_restart(dev, "PHY TX errors");
2007 }
2008 }
2009
2010 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
2011 b43err(dev->wl,
2012 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
2013 dma_reason[0], dma_reason[1],
2014 dma_reason[2], dma_reason[3],
2015 dma_reason[4], dma_reason[5]);
2016 b43err(dev->wl, "This device does not support DMA "
2017 "on your system. It will now be switched to PIO.\n");
2018 /* Fall back to PIO transfers if we get fatal DMA errors! */
2019 dev->use_pio = true;
2020 b43_controller_restart(dev, "DMA error");
2021 return;
2022 }
2023
2024 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
2025 handle_irq_ucode_debug(dev);
2026 if (reason & B43_IRQ_TBTT_INDI)
2027 handle_irq_tbtt_indication(dev);
2028 if (reason & B43_IRQ_ATIM_END)
2029 handle_irq_atim_end(dev);
2030 if (reason & B43_IRQ_BEACON)
2031 handle_irq_beacon(dev);
2032 if (reason & B43_IRQ_PMQ)
2033 handle_irq_pmq(dev);
2034 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
2035 ;/* TODO */
2036 if (reason & B43_IRQ_NOISESAMPLE_OK)
2037 handle_irq_noise(dev);
2038
2039 /* Check the DMA reason registers for received data. */
2040 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
2041 if (B43_DEBUG)
2042 b43warn(dev->wl, "RX descriptor underrun\n");
2043 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
2044 }
2045 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
2046 if (b43_using_pio_transfers(dev))
2047 b43_pio_rx(dev->pio.rx_queue);
2048 else
2049 b43_dma_rx(dev->dma.rx_ring);
2050 }
2051 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
2052 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
2053 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
2054 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
2055 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
2056
2057 if (reason & B43_IRQ_TX_OK)
2058 handle_irq_transmit_status(dev);
2059
2060 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
2061 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2062
2063#if B43_DEBUG
2064 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2065 dev->irq_count++;
2066 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2067 if (reason & (1 << i))
2068 dev->irq_bit_count[i]++;
2069 }
2070 }
2071#endif
2072}
2073
2074/* Interrupt thread handler. Handles device interrupts in thread context. */
2075static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
2076{
2077 struct b43_wldev *dev = dev_id;
2078
2079 mutex_lock(&dev->wl->mutex);
2080 b43_do_interrupt_thread(dev);
2081 mmiowb();
2082 mutex_unlock(&dev->wl->mutex);
2083
2084 return IRQ_HANDLED;
2085}
2086
2087static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
2088{
2089 u32 reason;
2090
2091 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2092 * On SDIO, this runs under wl->mutex. */
2093
2094 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2095 if (reason == 0xffffffff) /* shared IRQ */
2096 return IRQ_NONE;
2097 reason &= dev->irq_mask;
2098 if (!reason)
2099 return IRQ_NONE;
2100
2101 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2102 & 0x0001FC00;
2103 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2104 & 0x0000DC00;
2105 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2106 & 0x0000DC00;
2107 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2108 & 0x0001DC00;
2109 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2110 & 0x0000DC00;
2111/* Unused ring
2112 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2113 & 0x0000DC00;
2114*/
2115
2116 /* ACK the interrupt. */
2117 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2118 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2119 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2120 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2121 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2122 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2123/* Unused ring
2124 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2125*/
2126
2127 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2128 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2129 /* Save the reason bitmasks for the IRQ thread handler. */
2130 dev->irq_reason = reason;
2131
2132 return IRQ_WAKE_THREAD;
2133}
2134
2135/* Interrupt handler top-half. This runs with interrupts disabled. */
2136static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2137{
2138 struct b43_wldev *dev = dev_id;
2139 irqreturn_t ret;
2140
2141 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2142 return IRQ_NONE;
2143
2144 spin_lock(&dev->wl->hardirq_lock);
2145 ret = b43_do_interrupt(dev);
2146 mmiowb();
2147 spin_unlock(&dev->wl->hardirq_lock);
2148
2149 return ret;
2150}
2151
2152/* SDIO interrupt handler. This runs in process context. */
2153static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2154{
2155 struct b43_wl *wl = dev->wl;
2156 irqreturn_t ret;
2157
2158 mutex_lock(&wl->mutex);
2159
2160 ret = b43_do_interrupt(dev);
2161 if (ret == IRQ_WAKE_THREAD)
2162 b43_do_interrupt_thread(dev);
2163
2164 mutex_unlock(&wl->mutex);
2165}
2166
2167void b43_do_release_fw(struct b43_firmware_file *fw)
2168{
2169 release_firmware(fw->data);
2170 fw->data = NULL;
2171 fw->filename = NULL;
2172}
2173
2174static void b43_release_firmware(struct b43_wldev *dev)
2175{
2176 complete(&dev->fw_load_complete);
2177 b43_do_release_fw(&dev->fw.ucode);
2178 b43_do_release_fw(&dev->fw.pcm);
2179 b43_do_release_fw(&dev->fw.initvals);
2180 b43_do_release_fw(&dev->fw.initvals_band);
2181}
2182
2183static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2184{
2185 const char text[] =
2186 "You must go to " \
2187 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2188 "and download the correct firmware for this driver version. " \
2189 "Please carefully read all instructions on this website.\n";
2190
2191 if (error)
2192 b43err(wl, text);
2193 else
2194 b43warn(wl, text);
2195}
2196
2197static void b43_fw_cb(const struct firmware *firmware, void *context)
2198{
2199 struct b43_request_fw_context *ctx = context;
2200
2201 ctx->blob = firmware;
2202 complete(&ctx->dev->fw_load_complete);
2203}
2204
2205int b43_do_request_fw(struct b43_request_fw_context *ctx,
2206 const char *name,
2207 struct b43_firmware_file *fw, bool async)
2208{
2209 struct b43_fw_header *hdr;
2210 u32 size;
2211 int err;
2212
2213 if (!name) {
2214 /* Don't fetch anything. Free possibly cached firmware. */
2215 /* FIXME: We should probably keep it anyway, to save some headache
2216 * on suspend/resume with multiband devices. */
2217 b43_do_release_fw(fw);
2218 return 0;
2219 }
2220 if (fw->filename) {
2221 if ((fw->type == ctx->req_type) &&
2222 (strcmp(fw->filename, name) == 0))
2223 return 0; /* Already have this fw. */
2224 /* Free the cached firmware first. */
2225 /* FIXME: We should probably do this later after we successfully
2226 * got the new fw. This could reduce headache with multiband devices.
2227 * We could also redesign this to cache the firmware for all possible
2228 * bands all the time. */
2229 b43_do_release_fw(fw);
2230 }
2231
2232 switch (ctx->req_type) {
2233 case B43_FWTYPE_PROPRIETARY:
2234 snprintf(ctx->fwname, sizeof(ctx->fwname),
2235 "b43%s/%s.fw",
2236 modparam_fwpostfix, name);
2237 break;
2238 case B43_FWTYPE_OPENSOURCE:
2239 snprintf(ctx->fwname, sizeof(ctx->fwname),
2240 "b43-open%s/%s.fw",
2241 modparam_fwpostfix, name);
2242 break;
2243 default:
2244 B43_WARN_ON(1);
2245 return -ENOSYS;
2246 }
2247 if (async) {
2248 /* do this part asynchronously */
2249 init_completion(&ctx->dev->fw_load_complete);
2250 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2251 ctx->dev->dev->dev, GFP_KERNEL,
2252 ctx, b43_fw_cb);
2253 if (err < 0) {
2254 pr_err("Unable to load firmware\n");
2255 return err;
2256 }
2257 wait_for_completion(&ctx->dev->fw_load_complete);
2258 if (ctx->blob)
2259 goto fw_ready;
2260 /* On some ARM systems, the async request will fail, but the next sync
2261 * request works. For this reason, we fall through here
2262 */
2263 }
2264 err = request_firmware(&ctx->blob, ctx->fwname,
2265 ctx->dev->dev->dev);
2266 if (err == -ENOENT) {
2267 snprintf(ctx->errors[ctx->req_type],
2268 sizeof(ctx->errors[ctx->req_type]),
2269 "Firmware file \"%s\" not found\n",
2270 ctx->fwname);
2271 return err;
2272 } else if (err) {
2273 snprintf(ctx->errors[ctx->req_type],
2274 sizeof(ctx->errors[ctx->req_type]),
2275 "Firmware file \"%s\" request failed (err=%d)\n",
2276 ctx->fwname, err);
2277 return err;
2278 }
2279fw_ready:
2280 if (ctx->blob->size < sizeof(struct b43_fw_header))
2281 goto err_format;
2282 hdr = (struct b43_fw_header *)(ctx->blob->data);
2283 switch (hdr->type) {
2284 case B43_FW_TYPE_UCODE:
2285 case B43_FW_TYPE_PCM:
2286 size = be32_to_cpu(hdr->size);
2287 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2288 goto err_format;
2289 /* fallthrough */
2290 case B43_FW_TYPE_IV:
2291 if (hdr->ver != 1)
2292 goto err_format;
2293 break;
2294 default:
2295 goto err_format;
2296 }
2297
2298 fw->data = ctx->blob;
2299 fw->filename = name;
2300 fw->type = ctx->req_type;
2301
2302 return 0;
2303
2304err_format:
2305 snprintf(ctx->errors[ctx->req_type],
2306 sizeof(ctx->errors[ctx->req_type]),
2307 "Firmware file \"%s\" format error.\n", ctx->fwname);
2308 release_firmware(ctx->blob);
2309
2310 return -EPROTO;
2311}
2312
2313/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
2314static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2315{
2316 struct b43_wldev *dev = ctx->dev;
2317 struct b43_firmware *fw = &ctx->dev->fw;
2318 struct b43_phy *phy = &dev->phy;
2319 const u8 rev = ctx->dev->dev->core_rev;
2320 const char *filename;
2321 int err;
2322
2323 /* Get microcode */
2324 filename = NULL;
2325 switch (rev) {
2326 case 42:
2327 if (phy->type == B43_PHYTYPE_AC)
2328 filename = "ucode42";
2329 break;
2330 case 40:
2331 if (phy->type == B43_PHYTYPE_AC)
2332 filename = "ucode40";
2333 break;
2334 case 33:
2335 if (phy->type == B43_PHYTYPE_LCN40)
2336 filename = "ucode33_lcn40";
2337 break;
2338 case 30:
2339 if (phy->type == B43_PHYTYPE_N)
2340 filename = "ucode30_mimo";
2341 break;
2342 case 29:
2343 if (phy->type == B43_PHYTYPE_HT)
2344 filename = "ucode29_mimo";
2345 break;
2346 case 26:
2347 if (phy->type == B43_PHYTYPE_HT)
2348 filename = "ucode26_mimo";
2349 break;
2350 case 28:
2351 case 25:
2352 if (phy->type == B43_PHYTYPE_N)
2353 filename = "ucode25_mimo";
2354 else if (phy->type == B43_PHYTYPE_LCN)
2355 filename = "ucode25_lcn";
2356 break;
2357 case 24:
2358 if (phy->type == B43_PHYTYPE_LCN)
2359 filename = "ucode24_lcn";
2360 break;
2361 case 23:
2362 if (phy->type == B43_PHYTYPE_N)
2363 filename = "ucode16_mimo";
2364 break;
2365 case 16 ... 19:
2366 if (phy->type == B43_PHYTYPE_N)
2367 filename = "ucode16_mimo";
2368 else if (phy->type == B43_PHYTYPE_LP)
2369 filename = "ucode16_lp";
2370 break;
2371 case 15:
2372 filename = "ucode15";
2373 break;
2374 case 14:
2375 filename = "ucode14";
2376 break;
2377 case 13:
2378 filename = "ucode13";
2379 break;
2380 case 11 ... 12:
2381 filename = "ucode11";
2382 break;
2383 case 5 ... 10:
2384 filename = "ucode5";
2385 break;
2386 }
2387 if (!filename)
2388 goto err_no_ucode;
2389 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2390 if (err)
2391 goto err_load;
2392
2393 /* Get PCM code */
2394 if ((rev >= 5) && (rev <= 10))
2395 filename = "pcm5";
2396 else if (rev >= 11)
2397 filename = NULL;
2398 else
2399 goto err_no_pcm;
2400 fw->pcm_request_failed = false;
2401 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2402 if (err == -ENOENT) {
2403 /* We did not find a PCM file? Not fatal, but
2404 * core rev <= 10 must do without hwcrypto then. */
2405 fw->pcm_request_failed = true;
2406 } else if (err)
2407 goto err_load;
2408
2409 /* Get initvals */
2410 filename = NULL;
2411 switch (dev->phy.type) {
2412 case B43_PHYTYPE_G:
2413 if (rev == 13)
2414 filename = "b0g0initvals13";
2415 else if (rev >= 5 && rev <= 10)
2416 filename = "b0g0initvals5";
2417 break;
2418 case B43_PHYTYPE_N:
2419 if (rev == 30)
2420 filename = "n16initvals30";
2421 else if (rev == 28 || rev == 25)
2422 filename = "n0initvals25";
2423 else if (rev == 24)
2424 filename = "n0initvals24";
2425 else if (rev == 23)
2426 filename = "n0initvals16"; /* What about n0initvals22? */
2427 else if (rev >= 16 && rev <= 18)
2428 filename = "n0initvals16";
2429 else if (rev >= 11 && rev <= 12)
2430 filename = "n0initvals11";
2431 break;
2432 case B43_PHYTYPE_LP:
2433 if (rev >= 16 && rev <= 18)
2434 filename = "lp0initvals16";
2435 else if (rev == 15)
2436 filename = "lp0initvals15";
2437 else if (rev == 14)
2438 filename = "lp0initvals14";
2439 else if (rev == 13)
2440 filename = "lp0initvals13";
2441 break;
2442 case B43_PHYTYPE_HT:
2443 if (rev == 29)
2444 filename = "ht0initvals29";
2445 else if (rev == 26)
2446 filename = "ht0initvals26";
2447 break;
2448 case B43_PHYTYPE_LCN:
2449 if (rev == 24)
2450 filename = "lcn0initvals24";
2451 break;
2452 case B43_PHYTYPE_LCN40:
2453 if (rev == 33)
2454 filename = "lcn400initvals33";
2455 break;
2456 case B43_PHYTYPE_AC:
2457 if (rev == 42)
2458 filename = "ac1initvals42";
2459 else if (rev == 40)
2460 filename = "ac0initvals40";
2461 break;
2462 }
2463 if (!filename)
2464 goto err_no_initvals;
2465 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2466 if (err)
2467 goto err_load;
2468
2469 /* Get bandswitch initvals */
2470 filename = NULL;
2471 switch (dev->phy.type) {
2472 case B43_PHYTYPE_G:
2473 if (rev == 13)
2474 filename = "b0g0bsinitvals13";
2475 else if (rev >= 5 && rev <= 10)
2476 filename = "b0g0bsinitvals5";
2477 break;
2478 case B43_PHYTYPE_N:
2479 if (rev == 30)
2480 filename = "n16bsinitvals30";
2481 else if (rev == 28 || rev == 25)
2482 filename = "n0bsinitvals25";
2483 else if (rev == 24)
2484 filename = "n0bsinitvals24";
2485 else if (rev == 23)
2486 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2487 else if (rev >= 16 && rev <= 18)
2488 filename = "n0bsinitvals16";
2489 else if (rev >= 11 && rev <= 12)
2490 filename = "n0bsinitvals11";
2491 break;
2492 case B43_PHYTYPE_LP:
2493 if (rev >= 16 && rev <= 18)
2494 filename = "lp0bsinitvals16";
2495 else if (rev == 15)
2496 filename = "lp0bsinitvals15";
2497 else if (rev == 14)
2498 filename = "lp0bsinitvals14";
2499 else if (rev == 13)
2500 filename = "lp0bsinitvals13";
2501 break;
2502 case B43_PHYTYPE_HT:
2503 if (rev == 29)
2504 filename = "ht0bsinitvals29";
2505 else if (rev == 26)
2506 filename = "ht0bsinitvals26";
2507 break;
2508 case B43_PHYTYPE_LCN:
2509 if (rev == 24)
2510 filename = "lcn0bsinitvals24";
2511 break;
2512 case B43_PHYTYPE_LCN40:
2513 if (rev == 33)
2514 filename = "lcn400bsinitvals33";
2515 break;
2516 case B43_PHYTYPE_AC:
2517 if (rev == 42)
2518 filename = "ac1bsinitvals42";
2519 else if (rev == 40)
2520 filename = "ac0bsinitvals40";
2521 break;
2522 }
2523 if (!filename)
2524 goto err_no_initvals;
2525 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2526 if (err)
2527 goto err_load;
2528
2529 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2530
2531 return 0;
2532
2533err_no_ucode:
2534 err = ctx->fatal_failure = -EOPNOTSUPP;
2535 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2536 "is required for your device (wl-core rev %u)\n", rev);
2537 goto error;
2538
2539err_no_pcm:
2540 err = ctx->fatal_failure = -EOPNOTSUPP;
2541 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2542 "is required for your device (wl-core rev %u)\n", rev);
2543 goto error;
2544
2545err_no_initvals:
2546 err = ctx->fatal_failure = -EOPNOTSUPP;
2547 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2548 "is required for your device (wl-core rev %u)\n", rev);
2549 goto error;
2550
2551err_load:
2552 /* We failed to load this firmware image. The error message
2553 * already is in ctx->errors. Return and let our caller decide
2554 * what to do. */
2555 goto error;
2556
2557error:
2558 b43_release_firmware(dev);
2559 return err;
2560}
2561
2562static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2563static void b43_one_core_detach(struct b43_bus_dev *dev);
2564static int b43_rng_init(struct b43_wl *wl);
2565
2566static void b43_request_firmware(struct work_struct *work)
2567{
2568 struct b43_wl *wl = container_of(work,
2569 struct b43_wl, firmware_load);
2570 struct b43_wldev *dev = wl->current_dev;
2571 struct b43_request_fw_context *ctx;
2572 unsigned int i;
2573 int err;
2574 const char *errmsg;
2575
2576 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2577 if (!ctx)
2578 return;
2579 ctx->dev = dev;
2580
2581 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2582 err = b43_try_request_fw(ctx);
2583 if (!err)
2584 goto start_ieee80211; /* Successfully loaded it. */
2585 /* Was fw version known? */
2586 if (ctx->fatal_failure)
2587 goto out;
2588
2589 /* proprietary fw not found, try open source */
2590 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2591 err = b43_try_request_fw(ctx);
2592 if (!err)
2593 goto start_ieee80211; /* Successfully loaded it. */
2594 if(ctx->fatal_failure)
2595 goto out;
2596
2597 /* Could not find a usable firmware. Print the errors. */
2598 for (i = 0; i < B43_NR_FWTYPES; i++) {
2599 errmsg = ctx->errors[i];
2600 if (strlen(errmsg))
2601 b43err(dev->wl, "%s", errmsg);
2602 }
2603 b43_print_fw_helptext(dev->wl, 1);
2604 goto out;
2605
2606start_ieee80211:
2607 wl->hw->queues = B43_QOS_QUEUE_NUM;
2608 if (!modparam_qos || dev->fw.opensource)
2609 wl->hw->queues = 1;
2610
2611 err = ieee80211_register_hw(wl->hw);
2612 if (err)
2613 goto err_one_core_detach;
2614 wl->hw_registred = true;
2615 b43_leds_register(wl->current_dev);
2616
2617 /* Register HW RNG driver */
2618 b43_rng_init(wl);
2619
2620 goto out;
2621
2622err_one_core_detach:
2623 b43_one_core_detach(dev->dev);
2624
2625out:
2626 kfree(ctx);
2627}
2628
2629static int b43_upload_microcode(struct b43_wldev *dev)
2630{
2631 struct wiphy *wiphy = dev->wl->hw->wiphy;
2632 const size_t hdr_len = sizeof(struct b43_fw_header);
2633 const __be32 *data;
2634 unsigned int i, len;
2635 u16 fwrev, fwpatch, fwdate, fwtime;
2636 u32 tmp, macctl;
2637 int err = 0;
2638
2639 /* Jump the microcode PSM to offset 0 */
2640 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2641 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2642 macctl |= B43_MACCTL_PSM_JMP0;
2643 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2644 /* Zero out all microcode PSM registers and shared memory. */
2645 for (i = 0; i < 64; i++)
2646 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2647 for (i = 0; i < 4096; i += 2)
2648 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2649
2650 /* Upload Microcode. */
2651 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2652 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2653 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2654 for (i = 0; i < len; i++) {
2655 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2656 udelay(10);
2657 }
2658
2659 if (dev->fw.pcm.data) {
2660 /* Upload PCM data. */
2661 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2662 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2663 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2664 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2665 /* No need for autoinc bit in SHM_HW */
2666 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2667 for (i = 0; i < len; i++) {
2668 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2669 udelay(10);
2670 }
2671 }
2672
2673 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2674
2675 /* Start the microcode PSM */
2676 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2677 B43_MACCTL_PSM_RUN);
2678
2679 /* Wait for the microcode to load and respond */
2680 i = 0;
2681 while (1) {
2682 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2683 if (tmp == B43_IRQ_MAC_SUSPENDED)
2684 break;
2685 i++;
2686 if (i >= 20) {
2687 b43err(dev->wl, "Microcode not responding\n");
2688 b43_print_fw_helptext(dev->wl, 1);
2689 err = -ENODEV;
2690 goto error;
2691 }
2692 msleep(50);
2693 }
2694 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2695
2696 /* Get and check the revisions. */
2697 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2698 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2699 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2700 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2701
2702 if (fwrev <= 0x128) {
2703 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2704 "binary drivers older than version 4.x is unsupported. "
2705 "You must upgrade your firmware files.\n");
2706 b43_print_fw_helptext(dev->wl, 1);
2707 err = -EOPNOTSUPP;
2708 goto error;
2709 }
2710 dev->fw.rev = fwrev;
2711 dev->fw.patch = fwpatch;
2712 if (dev->fw.rev >= 598)
2713 dev->fw.hdr_format = B43_FW_HDR_598;
2714 else if (dev->fw.rev >= 410)
2715 dev->fw.hdr_format = B43_FW_HDR_410;
2716 else
2717 dev->fw.hdr_format = B43_FW_HDR_351;
2718 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2719
2720 dev->qos_enabled = dev->wl->hw->queues > 1;
2721 /* Default to firmware/hardware crypto acceleration. */
2722 dev->hwcrypto_enabled = true;
2723
2724 if (dev->fw.opensource) {
2725 u16 fwcapa;
2726
2727 /* Patchlevel info is encoded in the "time" field. */
2728 dev->fw.patch = fwtime;
2729 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2730 dev->fw.rev, dev->fw.patch);
2731
2732 fwcapa = b43_fwcapa_read(dev);
2733 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2734 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2735 /* Disable hardware crypto and fall back to software crypto. */
2736 dev->hwcrypto_enabled = false;
2737 }
2738 /* adding QoS support should use an offline discovery mechanism */
2739 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2740 } else {
2741 b43info(dev->wl, "Loading firmware version %u.%u "
2742 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2743 fwrev, fwpatch,
2744 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2745 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2746 if (dev->fw.pcm_request_failed) {
2747 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2748 "Hardware accelerated cryptography is disabled.\n");
2749 b43_print_fw_helptext(dev->wl, 0);
2750 }
2751 }
2752
2753 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2754 dev->fw.rev, dev->fw.patch);
2755 wiphy->hw_version = dev->dev->core_id;
2756
2757 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2758 /* We're over the deadline, but we keep support for old fw
2759 * until it turns out to be in major conflict with something new. */
2760 b43warn(dev->wl, "You are using an old firmware image. "
2761 "Support for old firmware will be removed soon "
2762 "(official deadline was July 2008).\n");
2763 b43_print_fw_helptext(dev->wl, 0);
2764 }
2765
2766 return 0;
2767
2768error:
2769 /* Stop the microcode PSM. */
2770 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2771 B43_MACCTL_PSM_JMP0);
2772
2773 return err;
2774}
2775
2776static int b43_write_initvals(struct b43_wldev *dev,
2777 const struct b43_iv *ivals,
2778 size_t count,
2779 size_t array_size)
2780{
2781 const struct b43_iv *iv;
2782 u16 offset;
2783 size_t i;
2784 bool bit32;
2785
2786 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2787 iv = ivals;
2788 for (i = 0; i < count; i++) {
2789 if (array_size < sizeof(iv->offset_size))
2790 goto err_format;
2791 array_size -= sizeof(iv->offset_size);
2792 offset = be16_to_cpu(iv->offset_size);
2793 bit32 = !!(offset & B43_IV_32BIT);
2794 offset &= B43_IV_OFFSET_MASK;
2795 if (offset >= 0x1000)
2796 goto err_format;
2797 if (bit32) {
2798 u32 value;
2799
2800 if (array_size < sizeof(iv->data.d32))
2801 goto err_format;
2802 array_size -= sizeof(iv->data.d32);
2803
2804 value = get_unaligned_be32(&iv->data.d32);
2805 b43_write32(dev, offset, value);
2806
2807 iv = (const struct b43_iv *)((const uint8_t *)iv +
2808 sizeof(__be16) +
2809 sizeof(__be32));
2810 } else {
2811 u16 value;
2812
2813 if (array_size < sizeof(iv->data.d16))
2814 goto err_format;
2815 array_size -= sizeof(iv->data.d16);
2816
2817 value = be16_to_cpu(iv->data.d16);
2818 b43_write16(dev, offset, value);
2819
2820 iv = (const struct b43_iv *)((const uint8_t *)iv +
2821 sizeof(__be16) +
2822 sizeof(__be16));
2823 }
2824 }
2825 if (array_size)
2826 goto err_format;
2827
2828 return 0;
2829
2830err_format:
2831 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2832 b43_print_fw_helptext(dev->wl, 1);
2833
2834 return -EPROTO;
2835}
2836
2837static int b43_upload_initvals(struct b43_wldev *dev)
2838{
2839 const size_t hdr_len = sizeof(struct b43_fw_header);
2840 const struct b43_fw_header *hdr;
2841 struct b43_firmware *fw = &dev->fw;
2842 const struct b43_iv *ivals;
2843 size_t count;
2844
2845 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2846 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2847 count = be32_to_cpu(hdr->size);
2848 return b43_write_initvals(dev, ivals, count,
2849 fw->initvals.data->size - hdr_len);
2850}
2851
2852static int b43_upload_initvals_band(struct b43_wldev *dev)
2853{
2854 const size_t hdr_len = sizeof(struct b43_fw_header);
2855 const struct b43_fw_header *hdr;
2856 struct b43_firmware *fw = &dev->fw;
2857 const struct b43_iv *ivals;
2858 size_t count;
2859
2860 if (!fw->initvals_band.data)
2861 return 0;
2862
2863 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2864 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2865 count = be32_to_cpu(hdr->size);
2866 return b43_write_initvals(dev, ivals, count,
2867 fw->initvals_band.data->size - hdr_len);
2868}
2869
2870/* Initialize the GPIOs
2871 * http://bcm-specs.sipsolutions.net/GPIO
2872 */
2873
2874#ifdef CONFIG_B43_SSB
2875static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2876{
2877 struct ssb_bus *bus = dev->dev->sdev->bus;
2878
2879#ifdef CONFIG_SSB_DRIVER_PCICORE
2880 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2881#else
2882 return bus->chipco.dev;
2883#endif
2884}
2885#endif
2886
2887static int b43_gpio_init(struct b43_wldev *dev)
2888{
2889#ifdef CONFIG_B43_SSB
2890 struct ssb_device *gpiodev;
2891#endif
2892 u32 mask, set;
2893
2894 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2895 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2896
2897 mask = 0x0000001F;
2898 set = 0x0000000F;
2899 if (dev->dev->chip_id == 0x4301) {
2900 mask |= 0x0060;
2901 set |= 0x0060;
2902 } else if (dev->dev->chip_id == 0x5354) {
2903 /* Don't allow overtaking buttons GPIOs */
2904 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2905 }
2906
2907 if (0 /* FIXME: conditional unknown */ ) {
2908 b43_write16(dev, B43_MMIO_GPIO_MASK,
2909 b43_read16(dev, B43_MMIO_GPIO_MASK)
2910 | 0x0100);
2911 /* BT Coexistance Input */
2912 mask |= 0x0080;
2913 set |= 0x0080;
2914 /* BT Coexistance Out */
2915 mask |= 0x0100;
2916 set |= 0x0100;
2917 }
2918 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2919 /* PA is controlled by gpio 9, let ucode handle it */
2920 b43_write16(dev, B43_MMIO_GPIO_MASK,
2921 b43_read16(dev, B43_MMIO_GPIO_MASK)
2922 | 0x0200);
2923 mask |= 0x0200;
2924 set |= 0x0200;
2925 }
2926
2927 switch (dev->dev->bus_type) {
2928#ifdef CONFIG_B43_BCMA
2929 case B43_BUS_BCMA:
2930 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2931 break;
2932#endif
2933#ifdef CONFIG_B43_SSB
2934 case B43_BUS_SSB:
2935 gpiodev = b43_ssb_gpio_dev(dev);
2936 if (gpiodev)
2937 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2938 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2939 & ~mask) | set);
2940 break;
2941#endif
2942 }
2943
2944 return 0;
2945}
2946
2947/* Turn off all GPIO stuff. Call this on module unload, for example. */
2948static void b43_gpio_cleanup(struct b43_wldev *dev)
2949{
2950#ifdef CONFIG_B43_SSB
2951 struct ssb_device *gpiodev;
2952#endif
2953
2954 switch (dev->dev->bus_type) {
2955#ifdef CONFIG_B43_BCMA
2956 case B43_BUS_BCMA:
2957 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2958 break;
2959#endif
2960#ifdef CONFIG_B43_SSB
2961 case B43_BUS_SSB:
2962 gpiodev = b43_ssb_gpio_dev(dev);
2963 if (gpiodev)
2964 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2965 break;
2966#endif
2967 }
2968}
2969
2970/* http://bcm-specs.sipsolutions.net/EnableMac */
2971void b43_mac_enable(struct b43_wldev *dev)
2972{
2973 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2974 u16 fwstate;
2975
2976 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2977 B43_SHM_SH_UCODESTAT);
2978 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2979 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2980 b43err(dev->wl, "b43_mac_enable(): The firmware "
2981 "should be suspended, but current state is %u\n",
2982 fwstate);
2983 }
2984 }
2985
2986 dev->mac_suspended--;
2987 B43_WARN_ON(dev->mac_suspended < 0);
2988 if (dev->mac_suspended == 0) {
2989 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2990 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2991 B43_IRQ_MAC_SUSPENDED);
2992 /* Commit writes */
2993 b43_read32(dev, B43_MMIO_MACCTL);
2994 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2995 b43_power_saving_ctl_bits(dev, 0);
2996 }
2997}
2998
2999/* http://bcm-specs.sipsolutions.net/SuspendMAC */
3000void b43_mac_suspend(struct b43_wldev *dev)
3001{
3002 int i;
3003 u32 tmp;
3004
3005 might_sleep();
3006 B43_WARN_ON(dev->mac_suspended < 0);
3007
3008 if (dev->mac_suspended == 0) {
3009 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
3010 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
3011 /* force pci to flush the write */
3012 b43_read32(dev, B43_MMIO_MACCTL);
3013 for (i = 35; i; i--) {
3014 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3015 if (tmp & B43_IRQ_MAC_SUSPENDED)
3016 goto out;
3017 udelay(10);
3018 }
3019 /* Hm, it seems this will take some time. Use msleep(). */
3020 for (i = 40; i; i--) {
3021 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3022 if (tmp & B43_IRQ_MAC_SUSPENDED)
3023 goto out;
3024 msleep(1);
3025 }
3026 b43err(dev->wl, "MAC suspend failed\n");
3027 }
3028out:
3029 dev->mac_suspended++;
3030}
3031
3032/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3033void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3034{
3035 u32 tmp;
3036
3037 switch (dev->dev->bus_type) {
3038#ifdef CONFIG_B43_BCMA
3039 case B43_BUS_BCMA:
3040 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3041 if (on)
3042 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
3043 else
3044 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
3045 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3046 break;
3047#endif
3048#ifdef CONFIG_B43_SSB
3049 case B43_BUS_SSB:
3050 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3051 if (on)
3052 tmp |= B43_TMSLOW_MACPHYCLKEN;
3053 else
3054 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
3055 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3056 break;
3057#endif
3058 }
3059}
3060
3061/* brcms_b_switch_macfreq */
3062void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3063{
3064 u16 chip_id = dev->dev->chip_id;
3065
3066 if (chip_id == BCMA_CHIP_ID_BCM4331) {
3067 switch (spurmode) {
3068 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
3069 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3070 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3071 break;
3072 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
3073 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3074 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3075 break;
3076 default: /* 160 Mhz: 2^26/160 = 0x66666 */
3077 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3078 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3079 break;
3080 }
3081 } else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
3082 chip_id == BCMA_CHIP_ID_BCM43217 ||
3083 chip_id == BCMA_CHIP_ID_BCM43222 ||
3084 chip_id == BCMA_CHIP_ID_BCM43224 ||
3085 chip_id == BCMA_CHIP_ID_BCM43225 ||
3086 chip_id == BCMA_CHIP_ID_BCM43227 ||
3087 chip_id == BCMA_CHIP_ID_BCM43228) {
3088 switch (spurmode) {
3089 case 2: /* 126 Mhz */
3090 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3091 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3092 break;
3093 case 1: /* 123 Mhz */
3094 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3095 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3096 break;
3097 default: /* 120 Mhz */
3098 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3099 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3100 break;
3101 }
3102 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3103 switch (spurmode) {
3104 case 1: /* 82 Mhz */
3105 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3106 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3107 break;
3108 default: /* 80 Mhz */
3109 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3110 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3111 break;
3112 }
3113 }
3114}
3115
3116static void b43_adjust_opmode(struct b43_wldev *dev)
3117{
3118 struct b43_wl *wl = dev->wl;
3119 u32 ctl;
3120 u16 cfp_pretbtt;
3121
3122 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3123 /* Reset status to STA infrastructure mode. */
3124 ctl &= ~B43_MACCTL_AP;
3125 ctl &= ~B43_MACCTL_KEEP_CTL;
3126 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3127 ctl &= ~B43_MACCTL_KEEP_BAD;
3128 ctl &= ~B43_MACCTL_PROMISC;
3129 ctl &= ~B43_MACCTL_BEACPROMISC;
3130 ctl |= B43_MACCTL_INFRA;
3131
3132 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3133 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3134 ctl |= B43_MACCTL_AP;
3135 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
3136 ctl &= ~B43_MACCTL_INFRA;
3137
3138 if (wl->filter_flags & FIF_CONTROL)
3139 ctl |= B43_MACCTL_KEEP_CTL;
3140 if (wl->filter_flags & FIF_FCSFAIL)
3141 ctl |= B43_MACCTL_KEEP_BAD;
3142 if (wl->filter_flags & FIF_PLCPFAIL)
3143 ctl |= B43_MACCTL_KEEP_BADPLCP;
3144 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3145 ctl |= B43_MACCTL_BEACPROMISC;
3146
3147 /* Workaround: On old hardware the HW-MAC-address-filter
3148 * doesn't work properly, so always run promisc in filter
3149 * it in software. */
3150 if (dev->dev->core_rev <= 4)
3151 ctl |= B43_MACCTL_PROMISC;
3152
3153 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3154
3155 cfp_pretbtt = 2;
3156 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
3157 if (dev->dev->chip_id == 0x4306 &&
3158 dev->dev->chip_rev == 3)
3159 cfp_pretbtt = 100;
3160 else
3161 cfp_pretbtt = 50;
3162 }
3163 b43_write16(dev, 0x612, cfp_pretbtt);
3164
3165 /* FIXME: We don't currently implement the PMQ mechanism,
3166 * so always disable it. If we want to implement PMQ,
3167 * we need to enable it here (clear DISCPMQ) in AP mode.
3168 */
3169 if (0 /* ctl & B43_MACCTL_AP */)
3170 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3171 else
3172 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
3173}
3174
3175static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3176{
3177 u16 offset;
3178
3179 if (is_ofdm) {
3180 offset = 0x480;
3181 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3182 } else {
3183 offset = 0x4C0;
3184 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3185 }
3186 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3187 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3188}
3189
3190static void b43_rate_memory_init(struct b43_wldev *dev)
3191{
3192 switch (dev->phy.type) {
3193 case B43_PHYTYPE_G:
3194 case B43_PHYTYPE_N:
3195 case B43_PHYTYPE_LP:
3196 case B43_PHYTYPE_HT:
3197 case B43_PHYTYPE_LCN:
3198 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3199 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1);
3200 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3201 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3202 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3203 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3204 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3205 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3206 /* fallthrough */
3207 case B43_PHYTYPE_B:
3208 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3209 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3210 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3211 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3212 break;
3213 default:
3214 B43_WARN_ON(1);
3215 }
3216}
3217
3218/* Set the default values for the PHY TX Control Words. */
3219static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3220{
3221 u16 ctl = 0;
3222
3223 ctl |= B43_TXH_PHY_ENC_CCK;
3224 ctl |= B43_TXH_PHY_ANT01AUTO;
3225 ctl |= B43_TXH_PHY_TXPWR;
3226
3227 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3228 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3229 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3230}
3231
3232/* Set the TX-Antenna for management frames sent by firmware. */
3233static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3234{
3235 u16 ant;
3236 u16 tmp;
3237
3238 ant = b43_antenna_to_phyctl(antenna);
3239
3240 /* For ACK/CTS */
3241 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3242 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3243 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3244 /* For Probe Resposes */
3245 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3246 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3247 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3248}
3249
3250/* This is the opposite of b43_chip_init() */
3251static void b43_chip_exit(struct b43_wldev *dev)
3252{
3253 b43_phy_exit(dev);
3254 b43_gpio_cleanup(dev);
3255 /* firmware is released later */
3256}
3257
3258/* Initialize the chip
3259 * http://bcm-specs.sipsolutions.net/ChipInit
3260 */
3261static int b43_chip_init(struct b43_wldev *dev)
3262{
3263 struct b43_phy *phy = &dev->phy;
3264 int err;
3265 u32 macctl;
3266 u16 value16;
3267
3268 /* Initialize the MAC control */
3269 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3270 if (dev->phy.gmode)
3271 macctl |= B43_MACCTL_GMODE;
3272 macctl |= B43_MACCTL_INFRA;
3273 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3274
3275 err = b43_upload_microcode(dev);
3276 if (err)
3277 goto out; /* firmware is released later */
3278
3279 err = b43_gpio_init(dev);
3280 if (err)
3281 goto out; /* firmware is released later */
3282
3283 err = b43_upload_initvals(dev);
3284 if (err)
3285 goto err_gpio_clean;
3286
3287 err = b43_upload_initvals_band(dev);
3288 if (err)
3289 goto err_gpio_clean;
3290
3291 /* Turn the Analog on and initialize the PHY. */
3292 phy->ops->switch_analog(dev, 1);
3293 err = b43_phy_init(dev);
3294 if (err)
3295 goto err_gpio_clean;
3296
3297 /* Disable Interference Mitigation. */
3298 if (phy->ops->interf_mitigation)
3299 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3300
3301 /* Select the antennae */
3302 if (phy->ops->set_rx_antenna)
3303 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3304 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3305
3306 if (phy->type == B43_PHYTYPE_B) {
3307 value16 = b43_read16(dev, 0x005E);
3308 value16 |= 0x0004;
3309 b43_write16(dev, 0x005E, value16);
3310 }
3311 b43_write32(dev, 0x0100, 0x01000000);
3312 if (dev->dev->core_rev < 5)
3313 b43_write32(dev, 0x010C, 0x01000000);
3314
3315 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3316 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3317
3318 /* Probe Response Timeout value */
3319 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3320 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3321
3322 /* Initially set the wireless operation mode. */
3323 b43_adjust_opmode(dev);
3324
3325 if (dev->dev->core_rev < 3) {
3326 b43_write16(dev, 0x060E, 0x0000);
3327 b43_write16(dev, 0x0610, 0x8000);
3328 b43_write16(dev, 0x0604, 0x0000);
3329 b43_write16(dev, 0x0606, 0x0200);
3330 } else {
3331 b43_write32(dev, 0x0188, 0x80000000);
3332 b43_write32(dev, 0x018C, 0x02000000);
3333 }
3334 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3335 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3336 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3337 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3338 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3339 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3340 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3341
3342 b43_mac_phy_clock_set(dev, true);
3343
3344 switch (dev->dev->bus_type) {
3345#ifdef CONFIG_B43_BCMA
3346 case B43_BUS_BCMA:
3347 /* FIXME: 0xE74 is quite common, but should be read from CC */
3348 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3349 break;
3350#endif
3351#ifdef CONFIG_B43_SSB
3352 case B43_BUS_SSB:
3353 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3354 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3355 break;
3356#endif
3357 }
3358
3359 err = 0;
3360 b43dbg(dev->wl, "Chip initialized\n");
3361out:
3362 return err;
3363
3364err_gpio_clean:
3365 b43_gpio_cleanup(dev);
3366 return err;
3367}
3368
3369static void b43_periodic_every60sec(struct b43_wldev *dev)
3370{
3371 const struct b43_phy_operations *ops = dev->phy.ops;
3372
3373 if (ops->pwork_60sec)
3374 ops->pwork_60sec(dev);
3375
3376 /* Force check the TX power emission now. */
3377 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3378}
3379
3380static void b43_periodic_every30sec(struct b43_wldev *dev)
3381{
3382 /* Update device statistics. */
3383 b43_calculate_link_quality(dev);
3384}
3385
3386static void b43_periodic_every15sec(struct b43_wldev *dev)
3387{
3388 struct b43_phy *phy = &dev->phy;
3389 u16 wdr;
3390
3391 if (dev->fw.opensource) {
3392 /* Check if the firmware is still alive.
3393 * It will reset the watchdog counter to 0 in its idle loop. */
3394 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3395 if (unlikely(wdr)) {
3396 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3397 b43_controller_restart(dev, "Firmware watchdog");
3398 return;
3399 } else {
3400 b43_shm_write16(dev, B43_SHM_SCRATCH,
3401 B43_WATCHDOG_REG, 1);
3402 }
3403 }
3404
3405 if (phy->ops->pwork_15sec)
3406 phy->ops->pwork_15sec(dev);
3407
3408 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3409 wmb();
3410
3411#if B43_DEBUG
3412 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3413 unsigned int i;
3414
3415 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3416 dev->irq_count / 15,
3417 dev->tx_count / 15,
3418 dev->rx_count / 15);
3419 dev->irq_count = 0;
3420 dev->tx_count = 0;
3421 dev->rx_count = 0;
3422 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3423 if (dev->irq_bit_count[i]) {
3424 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3425 dev->irq_bit_count[i] / 15, i, (1 << i));
3426 dev->irq_bit_count[i] = 0;
3427 }
3428 }
3429 }
3430#endif
3431}
3432
3433static void do_periodic_work(struct b43_wldev *dev)
3434{
3435 unsigned int state;
3436
3437 state = dev->periodic_state;
3438 if (state % 4 == 0)
3439 b43_periodic_every60sec(dev);
3440 if (state % 2 == 0)
3441 b43_periodic_every30sec(dev);
3442 b43_periodic_every15sec(dev);
3443}
3444
3445/* Periodic work locking policy:
3446 * The whole periodic work handler is protected by
3447 * wl->mutex. If another lock is needed somewhere in the
3448 * pwork callchain, it's acquired in-place, where it's needed.
3449 */
3450static void b43_periodic_work_handler(struct work_struct *work)
3451{
3452 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3453 periodic_work.work);
3454 struct b43_wl *wl = dev->wl;
3455 unsigned long delay;
3456
3457 mutex_lock(&wl->mutex);
3458
3459 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3460 goto out;
3461 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3462 goto out_requeue;
3463
3464 do_periodic_work(dev);
3465
3466 dev->periodic_state++;
3467out_requeue:
3468 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3469 delay = msecs_to_jiffies(50);
3470 else
3471 delay = round_jiffies_relative(HZ * 15);
3472 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3473out:
3474 mutex_unlock(&wl->mutex);
3475}
3476
3477static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3478{
3479 struct delayed_work *work = &dev->periodic_work;
3480
3481 dev->periodic_state = 0;
3482 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3483 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3484}
3485
3486/* Check if communication with the device works correctly. */
3487static int b43_validate_chipaccess(struct b43_wldev *dev)
3488{
3489 u32 v, backup0, backup4;
3490
3491 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3492 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3493
3494 /* Check for read/write and endianness problems. */
3495 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3496 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3497 goto error;
3498 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3499 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3500 goto error;
3501
3502 /* Check if unaligned 32bit SHM_SHARED access works properly.
3503 * However, don't bail out on failure, because it's noncritical. */
3504 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3505 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3506 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3507 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3508 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3509 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3510 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3511 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3512 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3513 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3514 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3515 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3516
3517 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3518 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3519
3520 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3521 /* The 32bit register shadows the two 16bit registers
3522 * with update sideeffects. Validate this. */
3523 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3524 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3525 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3526 goto error;
3527 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3528 goto error;
3529 }
3530 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3531
3532 v = b43_read32(dev, B43_MMIO_MACCTL);
3533 v |= B43_MACCTL_GMODE;
3534 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3535 goto error;
3536
3537 return 0;
3538error:
3539 b43err(dev->wl, "Failed to validate the chipaccess\n");
3540 return -ENODEV;
3541}
3542
3543static void b43_security_init(struct b43_wldev *dev)
3544{
3545 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3546 /* KTP is a word address, but we address SHM bytewise.
3547 * So multiply by two.
3548 */
3549 dev->ktp *= 2;
3550 /* Number of RCMTA address slots */
3551 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3552 /* Clear the key memory. */
3553 b43_clear_keys(dev);
3554}
3555
3556#ifdef CONFIG_B43_HWRNG
3557static int b43_rng_read(struct hwrng *rng, u32 *data)
3558{
3559 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3560 struct b43_wldev *dev;
3561 int count = -ENODEV;
3562
3563 mutex_lock(&wl->mutex);
3564 dev = wl->current_dev;
3565 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3566 *data = b43_read16(dev, B43_MMIO_RNG);
3567 count = sizeof(u16);
3568 }
3569 mutex_unlock(&wl->mutex);
3570
3571 return count;
3572}
3573#endif /* CONFIG_B43_HWRNG */
3574
3575static void b43_rng_exit(struct b43_wl *wl)
3576{
3577#ifdef CONFIG_B43_HWRNG
3578 if (wl->rng_initialized)
3579 hwrng_unregister(&wl->rng);
3580#endif /* CONFIG_B43_HWRNG */
3581}
3582
3583static int b43_rng_init(struct b43_wl *wl)
3584{
3585 int err = 0;
3586
3587#ifdef CONFIG_B43_HWRNG
3588 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3589 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3590 wl->rng.name = wl->rng_name;
3591 wl->rng.data_read = b43_rng_read;
3592 wl->rng.priv = (unsigned long)wl;
3593 wl->rng_initialized = true;
3594 err = hwrng_register(&wl->rng);
3595 if (err) {
3596 wl->rng_initialized = false;
3597 b43err(wl, "Failed to register the random "
3598 "number generator (%d)\n", err);
3599 }
3600#endif /* CONFIG_B43_HWRNG */
3601
3602 return err;
3603}
3604
3605static void b43_tx_work(struct work_struct *work)
3606{
3607 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3608 struct b43_wldev *dev;
3609 struct sk_buff *skb;
3610 int queue_num;
3611 int err = 0;
3612
3613 mutex_lock(&wl->mutex);
3614 dev = wl->current_dev;
3615 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3616 mutex_unlock(&wl->mutex);
3617 return;
3618 }
3619
3620 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3621 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3622 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3623 if (b43_using_pio_transfers(dev))
3624 err = b43_pio_tx(dev, skb);
3625 else
3626 err = b43_dma_tx(dev, skb);
3627 if (err == -ENOSPC) {
3628 wl->tx_queue_stopped[queue_num] = 1;
3629 ieee80211_stop_queue(wl->hw, queue_num);
3630 skb_queue_head(&wl->tx_queue[queue_num], skb);
3631 break;
3632 }
3633 if (unlikely(err))
3634 ieee80211_free_txskb(wl->hw, skb);
3635 err = 0;
3636 }
3637
3638 if (!err)
3639 wl->tx_queue_stopped[queue_num] = 0;
3640 }
3641
3642#if B43_DEBUG
3643 dev->tx_count++;
3644#endif
3645 mutex_unlock(&wl->mutex);
3646}
3647
3648static void b43_op_tx(struct ieee80211_hw *hw,
3649 struct ieee80211_tx_control *control,
3650 struct sk_buff *skb)
3651{
3652 struct b43_wl *wl = hw_to_b43_wl(hw);
3653
3654 if (unlikely(skb->len < 2 + 2 + 6)) {
3655 /* Too short, this can't be a valid frame. */
3656 ieee80211_free_txskb(hw, skb);
3657 return;
3658 }
3659 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3660
3661 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3662 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3663 ieee80211_queue_work(wl->hw, &wl->tx_work);
3664 } else {
3665 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3666 }
3667}
3668
3669static void b43_qos_params_upload(struct b43_wldev *dev,
3670 const struct ieee80211_tx_queue_params *p,
3671 u16 shm_offset)
3672{
3673 u16 params[B43_NR_QOSPARAMS];
3674 int bslots, tmp;
3675 unsigned int i;
3676
3677 if (!dev->qos_enabled)
3678 return;
3679
3680 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3681
3682 memset(¶ms, 0, sizeof(params));
3683
3684 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3685 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3686 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3687 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3688 params[B43_QOSPARAM_AIFS] = p->aifs;
3689 params[B43_QOSPARAM_BSLOTS] = bslots;
3690 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3691
3692 for (i = 0; i < ARRAY_SIZE(params); i++) {
3693 if (i == B43_QOSPARAM_STATUS) {
3694 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3695 shm_offset + (i * 2));
3696 /* Mark the parameters as updated. */
3697 tmp |= 0x100;
3698 b43_shm_write16(dev, B43_SHM_SHARED,
3699 shm_offset + (i * 2),
3700 tmp);
3701 } else {
3702 b43_shm_write16(dev, B43_SHM_SHARED,
3703 shm_offset + (i * 2),
3704 params[i]);
3705 }
3706 }
3707}
3708
3709/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3710static const u16 b43_qos_shm_offsets[] = {
3711 /* [mac80211-queue-nr] = SHM_OFFSET, */
3712 [0] = B43_QOS_VOICE,
3713 [1] = B43_QOS_VIDEO,
3714 [2] = B43_QOS_BESTEFFORT,
3715 [3] = B43_QOS_BACKGROUND,
3716};
3717
3718/* Update all QOS parameters in hardware. */
3719static void b43_qos_upload_all(struct b43_wldev *dev)
3720{
3721 struct b43_wl *wl = dev->wl;
3722 struct b43_qos_params *params;
3723 unsigned int i;
3724
3725 if (!dev->qos_enabled)
3726 return;
3727
3728 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3729 ARRAY_SIZE(wl->qos_params));
3730
3731 b43_mac_suspend(dev);
3732 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3733 params = &(wl->qos_params[i]);
3734 b43_qos_params_upload(dev, &(params->p),
3735 b43_qos_shm_offsets[i]);
3736 }
3737 b43_mac_enable(dev);
3738}
3739
3740static void b43_qos_clear(struct b43_wl *wl)
3741{
3742 struct b43_qos_params *params;
3743 unsigned int i;
3744
3745 /* Initialize QoS parameters to sane defaults. */
3746
3747 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3748 ARRAY_SIZE(wl->qos_params));
3749
3750 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3751 params = &(wl->qos_params[i]);
3752
3753 switch (b43_qos_shm_offsets[i]) {
3754 case B43_QOS_VOICE:
3755 params->p.txop = 0;
3756 params->p.aifs = 2;
3757 params->p.cw_min = 0x0001;
3758 params->p.cw_max = 0x0001;
3759 break;
3760 case B43_QOS_VIDEO:
3761 params->p.txop = 0;
3762 params->p.aifs = 2;
3763 params->p.cw_min = 0x0001;
3764 params->p.cw_max = 0x0001;
3765 break;
3766 case B43_QOS_BESTEFFORT:
3767 params->p.txop = 0;
3768 params->p.aifs = 3;
3769 params->p.cw_min = 0x0001;
3770 params->p.cw_max = 0x03FF;
3771 break;
3772 case B43_QOS_BACKGROUND:
3773 params->p.txop = 0;
3774 params->p.aifs = 7;
3775 params->p.cw_min = 0x0001;
3776 params->p.cw_max = 0x03FF;
3777 break;
3778 default:
3779 B43_WARN_ON(1);
3780 }
3781 }
3782}
3783
3784/* Initialize the core's QOS capabilities */
3785static void b43_qos_init(struct b43_wldev *dev)
3786{
3787 if (!dev->qos_enabled) {
3788 /* Disable QOS support. */
3789 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3790 b43_write16(dev, B43_MMIO_IFSCTL,
3791 b43_read16(dev, B43_MMIO_IFSCTL)
3792 & ~B43_MMIO_IFSCTL_USE_EDCF);
3793 b43dbg(dev->wl, "QoS disabled\n");
3794 return;
3795 }
3796
3797 /* Upload the current QOS parameters. */
3798 b43_qos_upload_all(dev);
3799
3800 /* Enable QOS support. */
3801 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3802 b43_write16(dev, B43_MMIO_IFSCTL,
3803 b43_read16(dev, B43_MMIO_IFSCTL)
3804 | B43_MMIO_IFSCTL_USE_EDCF);
3805 b43dbg(dev->wl, "QoS enabled\n");
3806}
3807
3808static int b43_op_conf_tx(struct ieee80211_hw *hw,
3809 struct ieee80211_vif *vif, u16 _queue,
3810 const struct ieee80211_tx_queue_params *params)
3811{
3812 struct b43_wl *wl = hw_to_b43_wl(hw);
3813 struct b43_wldev *dev;
3814 unsigned int queue = (unsigned int)_queue;
3815 int err = -ENODEV;
3816
3817 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3818 /* Queue not available or don't support setting
3819 * params on this queue. Return success to not
3820 * confuse mac80211. */
3821 return 0;
3822 }
3823 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3824 ARRAY_SIZE(wl->qos_params));
3825
3826 mutex_lock(&wl->mutex);
3827 dev = wl->current_dev;
3828 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3829 goto out_unlock;
3830
3831 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3832 b43_mac_suspend(dev);
3833 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3834 b43_qos_shm_offsets[queue]);
3835 b43_mac_enable(dev);
3836 err = 0;
3837
3838out_unlock:
3839 mutex_unlock(&wl->mutex);
3840
3841 return err;
3842}
3843
3844static int b43_op_get_stats(struct ieee80211_hw *hw,
3845 struct ieee80211_low_level_stats *stats)
3846{
3847 struct b43_wl *wl = hw_to_b43_wl(hw);
3848
3849 mutex_lock(&wl->mutex);
3850 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3851 mutex_unlock(&wl->mutex);
3852
3853 return 0;
3854}
3855
3856static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3857{
3858 struct b43_wl *wl = hw_to_b43_wl(hw);
3859 struct b43_wldev *dev;
3860 u64 tsf;
3861
3862 mutex_lock(&wl->mutex);
3863 dev = wl->current_dev;
3864
3865 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3866 b43_tsf_read(dev, &tsf);
3867 else
3868 tsf = 0;
3869
3870 mutex_unlock(&wl->mutex);
3871
3872 return tsf;
3873}
3874
3875static void b43_op_set_tsf(struct ieee80211_hw *hw,
3876 struct ieee80211_vif *vif, u64 tsf)
3877{
3878 struct b43_wl *wl = hw_to_b43_wl(hw);
3879 struct b43_wldev *dev;
3880
3881 mutex_lock(&wl->mutex);
3882 dev = wl->current_dev;
3883
3884 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3885 b43_tsf_write(dev, tsf);
3886
3887 mutex_unlock(&wl->mutex);
3888}
3889
3890static const char *band_to_string(enum nl80211_band band)
3891{
3892 switch (band) {
3893 case NL80211_BAND_5GHZ:
3894 return "5";
3895 case NL80211_BAND_2GHZ:
3896 return "2.4";
3897 default:
3898 break;
3899 }
3900 B43_WARN_ON(1);
3901 return "";
3902}
3903
3904/* Expects wl->mutex locked */
3905static int b43_switch_band(struct b43_wldev *dev,
3906 struct ieee80211_channel *chan)
3907{
3908 struct b43_phy *phy = &dev->phy;
3909 bool gmode;
3910 u32 tmp;
3911
3912 switch (chan->band) {
3913 case NL80211_BAND_5GHZ:
3914 gmode = false;
3915 break;
3916 case NL80211_BAND_2GHZ:
3917 gmode = true;
3918 break;
3919 default:
3920 B43_WARN_ON(1);
3921 return -EINVAL;
3922 }
3923
3924 if (!((gmode && phy->supports_2ghz) ||
3925 (!gmode && phy->supports_5ghz))) {
3926 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3927 band_to_string(chan->band));
3928 return -ENODEV;
3929 }
3930
3931 if (!!phy->gmode == !!gmode) {
3932 /* This device is already running. */
3933 return 0;
3934 }
3935
3936 b43dbg(dev->wl, "Switching to %s GHz band\n",
3937 band_to_string(chan->band));
3938
3939 /* Some new devices don't need disabling radio for band switching */
3940 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3941 b43_software_rfkill(dev, true);
3942
3943 phy->gmode = gmode;
3944 b43_phy_put_into_reset(dev);
3945 switch (dev->dev->bus_type) {
3946#ifdef CONFIG_B43_BCMA
3947 case B43_BUS_BCMA:
3948 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3949 if (gmode)
3950 tmp |= B43_BCMA_IOCTL_GMODE;
3951 else
3952 tmp &= ~B43_BCMA_IOCTL_GMODE;
3953 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3954 break;
3955#endif
3956#ifdef CONFIG_B43_SSB
3957 case B43_BUS_SSB:
3958 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3959 if (gmode)
3960 tmp |= B43_TMSLOW_GMODE;
3961 else
3962 tmp &= ~B43_TMSLOW_GMODE;
3963 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3964 break;
3965#endif
3966 }
3967 b43_phy_take_out_of_reset(dev);
3968
3969 b43_upload_initvals_band(dev);
3970
3971 b43_phy_init(dev);
3972
3973 return 0;
3974}
3975
3976static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval)
3977{
3978 interval = min_t(u16, interval, (u16)0xFF);
3979 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval);
3980}
3981
3982/* Write the short and long frame retry limit values. */
3983static void b43_set_retry_limits(struct b43_wldev *dev,
3984 unsigned int short_retry,
3985 unsigned int long_retry)
3986{
3987 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3988 * the chip-internal counter. */
3989 short_retry = min(short_retry, (unsigned int)0xF);
3990 long_retry = min(long_retry, (unsigned int)0xF);
3991
3992 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3993 short_retry);
3994 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3995 long_retry);
3996}
3997
3998static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3999{
4000 struct b43_wl *wl = hw_to_b43_wl(hw);
4001 struct b43_wldev *dev = wl->current_dev;
4002 struct b43_phy *phy = &dev->phy;
4003 struct ieee80211_conf *conf = &hw->conf;
4004 int antenna;
4005 int err = 0;
4006
4007 mutex_lock(&wl->mutex);
4008 b43_mac_suspend(dev);
4009
4010 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL)
4011 b43_set_beacon_listen_interval(dev, conf->listen_interval);
4012
4013 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4014 phy->chandef = &conf->chandef;
4015 phy->channel = conf->chandef.chan->hw_value;
4016
4017 /* Switch the band (if necessary). */
4018 err = b43_switch_band(dev, conf->chandef.chan);
4019 if (err)
4020 goto out_mac_enable;
4021
4022 /* Switch to the requested channel.
4023 * The firmware takes care of races with the TX handler.
4024 */
4025 b43_switch_channel(dev, phy->channel);
4026 }
4027
4028 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4029 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
4030 conf->long_frame_max_tx_count);
4031 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
4032 if (!changed)
4033 goto out_mac_enable;
4034
4035 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
4036
4037 /* Adjust the desired TX power level. */
4038 if (conf->power_level != 0) {
4039 if (conf->power_level != phy->desired_txpower) {
4040 phy->desired_txpower = conf->power_level;
4041 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
4042 B43_TXPWR_IGNORE_TSSI);
4043 }
4044 }
4045
4046 /* Antennas for RX and management frame TX. */
4047 antenna = B43_ANTENNA_DEFAULT;
4048 b43_mgmtframe_txantenna(dev, antenna);
4049 antenna = B43_ANTENNA_DEFAULT;
4050 if (phy->ops->set_rx_antenna)
4051 phy->ops->set_rx_antenna(dev, antenna);
4052
4053 if (wl->radio_enabled != phy->radio_on) {
4054 if (wl->radio_enabled) {
4055 b43_software_rfkill(dev, false);
4056 b43info(dev->wl, "Radio turned on by software\n");
4057 if (!dev->radio_hw_enable) {
4058 b43info(dev->wl, "The hardware RF-kill button "
4059 "still turns the radio physically off. "
4060 "Press the button to turn it on.\n");
4061 }
4062 } else {
4063 b43_software_rfkill(dev, true);
4064 b43info(dev->wl, "Radio turned off by software\n");
4065 }
4066 }
4067
4068out_mac_enable:
4069 b43_mac_enable(dev);
4070 mutex_unlock(&wl->mutex);
4071
4072 return err;
4073}
4074
4075static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
4076{
4077 struct ieee80211_supported_band *sband =
4078 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4079 struct ieee80211_rate *rate;
4080 int i;
4081 u16 basic, direct, offset, basic_offset, rateptr;
4082
4083 for (i = 0; i < sband->n_bitrates; i++) {
4084 rate = &sband->bitrates[i];
4085
4086 if (b43_is_cck_rate(rate->hw_value)) {
4087 direct = B43_SHM_SH_CCKDIRECT;
4088 basic = B43_SHM_SH_CCKBASIC;
4089 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4090 offset &= 0xF;
4091 } else {
4092 direct = B43_SHM_SH_OFDMDIRECT;
4093 basic = B43_SHM_SH_OFDMBASIC;
4094 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4095 offset &= 0xF;
4096 }
4097
4098 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4099
4100 if (b43_is_cck_rate(rate->hw_value)) {
4101 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4102 basic_offset &= 0xF;
4103 } else {
4104 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4105 basic_offset &= 0xF;
4106 }
4107
4108 /*
4109 * Get the pointer that we need to point to
4110 * from the direct map
4111 */
4112 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4113 direct + 2 * basic_offset);
4114 /* and write it to the basic map */
4115 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4116 rateptr);
4117 }
4118}
4119
4120static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4121 struct ieee80211_vif *vif,
4122 struct ieee80211_bss_conf *conf,
4123 u32 changed)
4124{
4125 struct b43_wl *wl = hw_to_b43_wl(hw);
4126 struct b43_wldev *dev;
4127
4128 mutex_lock(&wl->mutex);
4129
4130 dev = wl->current_dev;
4131 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4132 goto out_unlock_mutex;
4133
4134 B43_WARN_ON(wl->vif != vif);
4135
4136 if (changed & BSS_CHANGED_BSSID) {
4137 if (conf->bssid)
4138 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4139 else
4140 eth_zero_addr(wl->bssid);
4141 }
4142
4143 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4144 if (changed & BSS_CHANGED_BEACON &&
4145 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4146 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4147 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4148 b43_update_templates(wl);
4149
4150 if (changed & BSS_CHANGED_BSSID)
4151 b43_write_mac_bssid_templates(dev);
4152 }
4153
4154 b43_mac_suspend(dev);
4155
4156 /* Update templates for AP/mesh mode. */
4157 if (changed & BSS_CHANGED_BEACON_INT &&
4158 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4159 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4160 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4161 conf->beacon_int)
4162 b43_set_beacon_int(dev, conf->beacon_int);
4163
4164 if (changed & BSS_CHANGED_BASIC_RATES)
4165 b43_update_basic_rates(dev, conf->basic_rates);
4166
4167 if (changed & BSS_CHANGED_ERP_SLOT) {
4168 if (conf->use_short_slot)
4169 b43_short_slot_timing_enable(dev);
4170 else
4171 b43_short_slot_timing_disable(dev);
4172 }
4173
4174 b43_mac_enable(dev);
4175out_unlock_mutex:
4176 mutex_unlock(&wl->mutex);
4177}
4178
4179static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4180 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4181 struct ieee80211_key_conf *key)
4182{
4183 struct b43_wl *wl = hw_to_b43_wl(hw);
4184 struct b43_wldev *dev;
4185 u8 algorithm;
4186 u8 index;
4187 int err;
4188 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4189
4190 if (modparam_nohwcrypt)
4191 return -ENOSPC; /* User disabled HW-crypto */
4192
4193 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4194 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4195 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4196 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4197 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4198 /*
4199 * For now, disable hw crypto for the RSN IBSS group keys. This
4200 * could be optimized in the future, but until that gets
4201 * implemented, use of software crypto for group addressed
4202 * frames is a acceptable to allow RSN IBSS to be used.
4203 */
4204 return -EOPNOTSUPP;
4205 }
4206
4207 mutex_lock(&wl->mutex);
4208
4209 dev = wl->current_dev;
4210 err = -ENODEV;
4211 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4212 goto out_unlock;
4213
4214 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4215 /* We don't have firmware for the crypto engine.
4216 * Must use software-crypto. */
4217 err = -EOPNOTSUPP;
4218 goto out_unlock;
4219 }
4220
4221 err = -EINVAL;
4222 switch (key->cipher) {
4223 case WLAN_CIPHER_SUITE_WEP40:
4224 algorithm = B43_SEC_ALGO_WEP40;
4225 break;
4226 case WLAN_CIPHER_SUITE_WEP104:
4227 algorithm = B43_SEC_ALGO_WEP104;
4228 break;
4229 case WLAN_CIPHER_SUITE_TKIP:
4230 algorithm = B43_SEC_ALGO_TKIP;
4231 break;
4232 case WLAN_CIPHER_SUITE_CCMP:
4233 algorithm = B43_SEC_ALGO_AES;
4234 break;
4235 default:
4236 B43_WARN_ON(1);
4237 goto out_unlock;
4238 }
4239 index = (u8) (key->keyidx);
4240 if (index > 3)
4241 goto out_unlock;
4242
4243 switch (cmd) {
4244 case SET_KEY:
4245 if (algorithm == B43_SEC_ALGO_TKIP &&
4246 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4247 !modparam_hwtkip)) {
4248 /* We support only pairwise key */
4249 err = -EOPNOTSUPP;
4250 goto out_unlock;
4251 }
4252
4253 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4254 if (WARN_ON(!sta)) {
4255 err = -EOPNOTSUPP;
4256 goto out_unlock;
4257 }
4258 /* Pairwise key with an assigned MAC address. */
4259 err = b43_key_write(dev, -1, algorithm,
4260 key->key, key->keylen,
4261 sta->addr, key);
4262 } else {
4263 /* Group key */
4264 err = b43_key_write(dev, index, algorithm,
4265 key->key, key->keylen, NULL, key);
4266 }
4267 if (err)
4268 goto out_unlock;
4269
4270 if (algorithm == B43_SEC_ALGO_WEP40 ||
4271 algorithm == B43_SEC_ALGO_WEP104) {
4272 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4273 } else {
4274 b43_hf_write(dev,
4275 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4276 }
4277 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4278 if (algorithm == B43_SEC_ALGO_TKIP)
4279 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4280 break;
4281 case DISABLE_KEY: {
4282 err = b43_key_clear(dev, key->hw_key_idx);
4283 if (err)
4284 goto out_unlock;
4285 break;
4286 }
4287 default:
4288 B43_WARN_ON(1);
4289 }
4290
4291out_unlock:
4292 if (!err) {
4293 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4294 "mac: %pM\n",
4295 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4296 sta ? sta->addr : bcast_addr);
4297 b43_dump_keymemory(dev);
4298 }
4299 mutex_unlock(&wl->mutex);
4300
4301 return err;
4302}
4303
4304static void b43_op_configure_filter(struct ieee80211_hw *hw,
4305 unsigned int changed, unsigned int *fflags,
4306 u64 multicast)
4307{
4308 struct b43_wl *wl = hw_to_b43_wl(hw);
4309 struct b43_wldev *dev;
4310
4311 mutex_lock(&wl->mutex);
4312 dev = wl->current_dev;
4313 if (!dev) {
4314 *fflags = 0;
4315 goto out_unlock;
4316 }
4317
4318 *fflags &= FIF_ALLMULTI |
4319 FIF_FCSFAIL |
4320 FIF_PLCPFAIL |
4321 FIF_CONTROL |
4322 FIF_OTHER_BSS |
4323 FIF_BCN_PRBRESP_PROMISC;
4324
4325 changed &= FIF_ALLMULTI |
4326 FIF_FCSFAIL |
4327 FIF_PLCPFAIL |
4328 FIF_CONTROL |
4329 FIF_OTHER_BSS |
4330 FIF_BCN_PRBRESP_PROMISC;
4331
4332 wl->filter_flags = *fflags;
4333
4334 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4335 b43_adjust_opmode(dev);
4336
4337out_unlock:
4338 mutex_unlock(&wl->mutex);
4339}
4340
4341/* Locking: wl->mutex
4342 * Returns the current dev. This might be different from the passed in dev,
4343 * because the core might be gone away while we unlocked the mutex. */
4344static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4345{
4346 struct b43_wl *wl;
4347 struct b43_wldev *orig_dev;
4348 u32 mask;
4349 int queue_num;
4350
4351 if (!dev)
4352 return NULL;
4353 wl = dev->wl;
4354redo:
4355 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4356 return dev;
4357
4358 /* Cancel work. Unlock to avoid deadlocks. */
4359 mutex_unlock(&wl->mutex);
4360 cancel_delayed_work_sync(&dev->periodic_work);
4361 cancel_work_sync(&wl->tx_work);
4362 b43_leds_stop(dev);
4363 mutex_lock(&wl->mutex);
4364 dev = wl->current_dev;
4365 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4366 /* Whoops, aliens ate up the device while we were unlocked. */
4367 return dev;
4368 }
4369
4370 /* Disable interrupts on the device. */
4371 b43_set_status(dev, B43_STAT_INITIALIZED);
4372 if (b43_bus_host_is_sdio(dev->dev)) {
4373 /* wl->mutex is locked. That is enough. */
4374 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4375 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4376 } else {
4377 spin_lock_irq(&wl->hardirq_lock);
4378 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4379 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4380 spin_unlock_irq(&wl->hardirq_lock);
4381 }
4382 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4383 orig_dev = dev;
4384 mutex_unlock(&wl->mutex);
4385 if (b43_bus_host_is_sdio(dev->dev))
4386 b43_sdio_free_irq(dev);
4387 else
4388 free_irq(dev->dev->irq, dev);
4389 mutex_lock(&wl->mutex);
4390 dev = wl->current_dev;
4391 if (!dev)
4392 return dev;
4393 if (dev != orig_dev) {
4394 if (b43_status(dev) >= B43_STAT_STARTED)
4395 goto redo;
4396 return dev;
4397 }
4398 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4399 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4400
4401 /* Drain all TX queues. */
4402 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4403 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4404 struct sk_buff *skb;
4405
4406 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4407 ieee80211_free_txskb(wl->hw, skb);
4408 }
4409 }
4410
4411 b43_mac_suspend(dev);
4412 b43_leds_exit(dev);
4413 b43dbg(wl, "Wireless interface stopped\n");
4414
4415 return dev;
4416}
4417
4418/* Locking: wl->mutex */
4419static int b43_wireless_core_start(struct b43_wldev *dev)
4420{
4421 int err;
4422
4423 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4424
4425 drain_txstatus_queue(dev);
4426 if (b43_bus_host_is_sdio(dev->dev)) {
4427 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4428 if (err) {
4429 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4430 goto out;
4431 }
4432 } else {
4433 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4434 b43_interrupt_thread_handler,
4435 IRQF_SHARED, KBUILD_MODNAME, dev);
4436 if (err) {
4437 b43err(dev->wl, "Cannot request IRQ-%d\n",
4438 dev->dev->irq);
4439 goto out;
4440 }
4441 }
4442
4443 /* We are ready to run. */
4444 ieee80211_wake_queues(dev->wl->hw);
4445 b43_set_status(dev, B43_STAT_STARTED);
4446
4447 /* Start data flow (TX/RX). */
4448 b43_mac_enable(dev);
4449 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4450
4451 /* Start maintenance work */
4452 b43_periodic_tasks_setup(dev);
4453
4454 b43_leds_init(dev);
4455
4456 b43dbg(dev->wl, "Wireless interface started\n");
4457out:
4458 return err;
4459}
4460
4461static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4462{
4463 switch (phy_type) {
4464 case B43_PHYTYPE_A:
4465 return "A";
4466 case B43_PHYTYPE_B:
4467 return "B";
4468 case B43_PHYTYPE_G:
4469 return "G";
4470 case B43_PHYTYPE_N:
4471 return "N";
4472 case B43_PHYTYPE_LP:
4473 return "LP";
4474 case B43_PHYTYPE_SSLPN:
4475 return "SSLPN";
4476 case B43_PHYTYPE_HT:
4477 return "HT";
4478 case B43_PHYTYPE_LCN:
4479 return "LCN";
4480 case B43_PHYTYPE_LCNXN:
4481 return "LCNXN";
4482 case B43_PHYTYPE_LCN40:
4483 return "LCN40";
4484 case B43_PHYTYPE_AC:
4485 return "AC";
4486 }
4487 return "UNKNOWN";
4488}
4489
4490/* Get PHY and RADIO versioning numbers */
4491static int b43_phy_versioning(struct b43_wldev *dev)
4492{
4493 struct b43_phy *phy = &dev->phy;
4494 const u8 core_rev = dev->dev->core_rev;
4495 u32 tmp;
4496 u8 analog_type;
4497 u8 phy_type;
4498 u8 phy_rev;
4499 u16 radio_manuf;
4500 u16 radio_id;
4501 u16 radio_rev;
4502 u8 radio_ver;
4503 int unsupported = 0;
4504
4505 /* Get PHY versioning */
4506 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4507 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4508 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4509 phy_rev = (tmp & B43_PHYVER_VERSION);
4510
4511 /* LCNXN is continuation of N which run out of revisions */
4512 if (phy_type == B43_PHYTYPE_LCNXN) {
4513 phy_type = B43_PHYTYPE_N;
4514 phy_rev += 16;
4515 }
4516
4517 switch (phy_type) {
4518#ifdef CONFIG_B43_PHY_G
4519 case B43_PHYTYPE_G:
4520 if (phy_rev > 9)
4521 unsupported = 1;
4522 break;
4523#endif
4524#ifdef CONFIG_B43_PHY_N
4525 case B43_PHYTYPE_N:
4526 if (phy_rev >= 19)
4527 unsupported = 1;
4528 break;
4529#endif
4530#ifdef CONFIG_B43_PHY_LP
4531 case B43_PHYTYPE_LP:
4532 if (phy_rev > 2)
4533 unsupported = 1;
4534 break;
4535#endif
4536#ifdef CONFIG_B43_PHY_HT
4537 case B43_PHYTYPE_HT:
4538 if (phy_rev > 1)
4539 unsupported = 1;
4540 break;
4541#endif
4542#ifdef CONFIG_B43_PHY_LCN
4543 case B43_PHYTYPE_LCN:
4544 if (phy_rev > 1)
4545 unsupported = 1;
4546 break;
4547#endif
4548#ifdef CONFIG_B43_PHY_AC
4549 case B43_PHYTYPE_AC:
4550 if (phy_rev > 1)
4551 unsupported = 1;
4552 break;
4553#endif
4554 default:
4555 unsupported = 1;
4556 }
4557 if (unsupported) {
4558 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4559 analog_type, phy_type, b43_phy_name(dev, phy_type),
4560 phy_rev);
4561 return -EOPNOTSUPP;
4562 }
4563 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4564 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4565
4566 /* Get RADIO versioning */
4567 if (core_rev == 40 || core_rev == 42) {
4568 radio_manuf = 0x17F;
4569
4570 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
4571 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4572
4573 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
4574 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4575
4576 radio_ver = 0; /* Is there version somewhere? */
4577 } else if (core_rev >= 24) {
4578 u16 radio24[3];
4579
4580 for (tmp = 0; tmp < 3; tmp++) {
4581 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4582 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4583 }
4584
4585 radio_manuf = 0x17F;
4586 radio_id = (radio24[2] << 8) | radio24[1];
4587 radio_rev = (radio24[0] & 0xF);
4588 radio_ver = (radio24[0] & 0xF0) >> 4;
4589 } else {
4590 if (dev->dev->chip_id == 0x4317) {
4591 if (dev->dev->chip_rev == 0)
4592 tmp = 0x3205017F;
4593 else if (dev->dev->chip_rev == 1)
4594 tmp = 0x4205017F;
4595 else
4596 tmp = 0x5205017F;
4597 } else {
4598 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4599 B43_RADIOCTL_ID);
4600 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4601 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4602 B43_RADIOCTL_ID);
4603 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4604 }
4605 radio_manuf = (tmp & 0x00000FFF);
4606 radio_id = (tmp & 0x0FFFF000) >> 12;
4607 radio_rev = (tmp & 0xF0000000) >> 28;
4608 radio_ver = 0; /* Probably not available on old hw */
4609 }
4610
4611 if (radio_manuf != 0x17F /* Broadcom */)
4612 unsupported = 1;
4613 switch (phy_type) {
4614 case B43_PHYTYPE_B:
4615 if ((radio_id & 0xFFF0) != 0x2050)
4616 unsupported = 1;
4617 break;
4618 case B43_PHYTYPE_G:
4619 if (radio_id != 0x2050)
4620 unsupported = 1;
4621 break;
4622 case B43_PHYTYPE_N:
4623 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4624 radio_id != 0x2057)
4625 unsupported = 1;
4626 if (radio_id == 0x2057 &&
4627 !(radio_rev == 9 || radio_rev == 14))
4628 unsupported = 1;
4629 break;
4630 case B43_PHYTYPE_LP:
4631 if (radio_id != 0x2062 && radio_id != 0x2063)
4632 unsupported = 1;
4633 break;
4634 case B43_PHYTYPE_HT:
4635 if (radio_id != 0x2059)
4636 unsupported = 1;
4637 break;
4638 case B43_PHYTYPE_LCN:
4639 if (radio_id != 0x2064)
4640 unsupported = 1;
4641 break;
4642 case B43_PHYTYPE_AC:
4643 if (radio_id != 0x2069)
4644 unsupported = 1;
4645 break;
4646 default:
4647 B43_WARN_ON(1);
4648 }
4649 if (unsupported) {
4650 b43err(dev->wl,
4651 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4652 radio_manuf, radio_id, radio_rev, radio_ver);
4653 return -EOPNOTSUPP;
4654 }
4655 b43info(dev->wl,
4656 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4657 radio_manuf, radio_id, radio_rev, radio_ver);
4658
4659 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
4660 phy->radio_manuf = radio_manuf;
4661 phy->radio_ver = radio_id;
4662 phy->radio_rev = radio_rev;
4663
4664 phy->analog = analog_type;
4665 phy->type = phy_type;
4666 phy->rev = phy_rev;
4667
4668 return 0;
4669}
4670
4671static void setup_struct_phy_for_init(struct b43_wldev *dev,
4672 struct b43_phy *phy)
4673{
4674 phy->hardware_power_control = !!modparam_hwpctl;
4675 phy->next_txpwr_check_time = jiffies;
4676 /* PHY TX errors counter. */
4677 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4678
4679#if B43_DEBUG
4680 phy->phy_locked = false;
4681 phy->radio_locked = false;
4682#endif
4683}
4684
4685static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4686{
4687 dev->dfq_valid = false;
4688
4689 /* Assume the radio is enabled. If it's not enabled, the state will
4690 * immediately get fixed on the first periodic work run. */
4691 dev->radio_hw_enable = true;
4692
4693 /* Stats */
4694 memset(&dev->stats, 0, sizeof(dev->stats));
4695
4696 setup_struct_phy_for_init(dev, &dev->phy);
4697
4698 /* IRQ related flags */
4699 dev->irq_reason = 0;
4700 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4701 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4702 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4703 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4704
4705 dev->mac_suspended = 1;
4706
4707 /* Noise calculation context */
4708 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4709}
4710
4711static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4712{
4713 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4714 u64 hf;
4715
4716 if (!modparam_btcoex)
4717 return;
4718 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4719 return;
4720 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4721 return;
4722
4723 hf = b43_hf_read(dev);
4724 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4725 hf |= B43_HF_BTCOEXALT;
4726 else
4727 hf |= B43_HF_BTCOEX;
4728 b43_hf_write(dev, hf);
4729}
4730
4731static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4732{
4733 if (!modparam_btcoex)
4734 return;
4735 //TODO
4736}
4737
4738static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4739{
4740 struct ssb_bus *bus;
4741 u32 tmp;
4742
4743#ifdef CONFIG_B43_SSB
4744 if (dev->dev->bus_type != B43_BUS_SSB)
4745 return;
4746#else
4747 return;
4748#endif
4749
4750 bus = dev->dev->sdev->bus;
4751
4752 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4753 (bus->chip_id == 0x4312)) {
4754 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4755 tmp &= ~SSB_IMCFGLO_REQTO;
4756 tmp &= ~SSB_IMCFGLO_SERTO;
4757 tmp |= 0x3;
4758 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4759 ssb_commit_settings(bus);
4760 }
4761}
4762
4763static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4764{
4765 u16 pu_delay;
4766
4767 /* The time value is in microseconds. */
4768 pu_delay = 1050;
4769 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4770 pu_delay = 500;
4771 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4772 pu_delay = max(pu_delay, (u16)2400);
4773
4774 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4775}
4776
4777/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4778static void b43_set_pretbtt(struct b43_wldev *dev)
4779{
4780 u16 pretbtt;
4781
4782 /* The time value is in microseconds. */
4783 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
4784 pretbtt = 2;
4785 else
4786 pretbtt = 250;
4787 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4788 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4789}
4790
4791/* Shutdown a wireless core */
4792/* Locking: wl->mutex */
4793static void b43_wireless_core_exit(struct b43_wldev *dev)
4794{
4795 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4796 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4797 return;
4798
4799 b43_set_status(dev, B43_STAT_UNINIT);
4800
4801 /* Stop the microcode PSM. */
4802 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4803 B43_MACCTL_PSM_JMP0);
4804
4805 switch (dev->dev->bus_type) {
4806#ifdef CONFIG_B43_BCMA
4807 case B43_BUS_BCMA:
4808 bcma_host_pci_down(dev->dev->bdev->bus);
4809 break;
4810#endif
4811#ifdef CONFIG_B43_SSB
4812 case B43_BUS_SSB:
4813 /* TODO */
4814 break;
4815#endif
4816 }
4817
4818 b43_dma_free(dev);
4819 b43_pio_free(dev);
4820 b43_chip_exit(dev);
4821 dev->phy.ops->switch_analog(dev, 0);
4822 if (dev->wl->current_beacon) {
4823 dev_kfree_skb_any(dev->wl->current_beacon);
4824 dev->wl->current_beacon = NULL;
4825 }
4826
4827 b43_device_disable(dev, 0);
4828 b43_bus_may_powerdown(dev);
4829}
4830
4831/* Initialize a wireless core */
4832static int b43_wireless_core_init(struct b43_wldev *dev)
4833{
4834 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4835 struct b43_phy *phy = &dev->phy;
4836 int err;
4837 u64 hf;
4838
4839 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4840
4841 err = b43_bus_powerup(dev, 0);
4842 if (err)
4843 goto out;
4844 if (!b43_device_is_enabled(dev))
4845 b43_wireless_core_reset(dev, phy->gmode);
4846
4847 /* Reset all data structures. */
4848 setup_struct_wldev_for_init(dev);
4849 phy->ops->prepare_structs(dev);
4850
4851 /* Enable IRQ routing to this device. */
4852 switch (dev->dev->bus_type) {
4853#ifdef CONFIG_B43_BCMA
4854 case B43_BUS_BCMA:
4855 bcma_host_pci_irq_ctl(dev->dev->bdev->bus,
4856 dev->dev->bdev, true);
4857 bcma_host_pci_up(dev->dev->bdev->bus);
4858 break;
4859#endif
4860#ifdef CONFIG_B43_SSB
4861 case B43_BUS_SSB:
4862 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4863 dev->dev->sdev);
4864 break;
4865#endif
4866 }
4867
4868 b43_imcfglo_timeouts_workaround(dev);
4869 b43_bluetooth_coext_disable(dev);
4870 if (phy->ops->prepare_hardware) {
4871 err = phy->ops->prepare_hardware(dev);
4872 if (err)
4873 goto err_busdown;
4874 }
4875 err = b43_chip_init(dev);
4876 if (err)
4877 goto err_busdown;
4878 b43_shm_write16(dev, B43_SHM_SHARED,
4879 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4880 hf = b43_hf_read(dev);
4881 if (phy->type == B43_PHYTYPE_G) {
4882 hf |= B43_HF_SYMW;
4883 if (phy->rev == 1)
4884 hf |= B43_HF_GDCW;
4885 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4886 hf |= B43_HF_OFDMPABOOST;
4887 }
4888 if (phy->radio_ver == 0x2050) {
4889 if (phy->radio_rev == 6)
4890 hf |= B43_HF_4318TSSI;
4891 if (phy->radio_rev < 6)
4892 hf |= B43_HF_VCORECALC;
4893 }
4894 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4895 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4896#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4897 if (dev->dev->bus_type == B43_BUS_SSB &&
4898 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4899 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4900 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4901#endif
4902 hf &= ~B43_HF_SKCFPUP;
4903 b43_hf_write(dev, hf);
4904
4905 /* tell the ucode MAC capabilities */
4906 if (dev->dev->core_rev >= 13) {
4907 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4908
4909 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4910 mac_hw_cap & 0xffff);
4911 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4912 (mac_hw_cap >> 16) & 0xffff);
4913 }
4914
4915 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4916 B43_DEFAULT_LONG_RETRY_LIMIT);
4917 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4918 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4919
4920 /* Disable sending probe responses from firmware.
4921 * Setting the MaxTime to one usec will always trigger
4922 * a timeout, so we never send any probe resp.
4923 * A timeout of zero is infinite. */
4924 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4925
4926 b43_rate_memory_init(dev);
4927 b43_set_phytxctl_defaults(dev);
4928
4929 /* Minimum Contention Window */
4930 if (phy->type == B43_PHYTYPE_B)
4931 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4932 else
4933 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4934 /* Maximum Contention Window */
4935 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4936
4937 /* write phytype and phyvers */
4938 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4939 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4940
4941 if (b43_bus_host_is_pcmcia(dev->dev) ||
4942 b43_bus_host_is_sdio(dev->dev)) {
4943 dev->__using_pio_transfers = true;
4944 err = b43_pio_init(dev);
4945 } else if (dev->use_pio) {
4946 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4947 "This should not be needed and will result in lower "
4948 "performance.\n");
4949 dev->__using_pio_transfers = true;
4950 err = b43_pio_init(dev);
4951 } else {
4952 dev->__using_pio_transfers = false;
4953 err = b43_dma_init(dev);
4954 }
4955 if (err)
4956 goto err_chip_exit;
4957 b43_qos_init(dev);
4958 b43_set_synth_pu_delay(dev, 1);
4959 b43_bluetooth_coext_enable(dev);
4960
4961 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4962 b43_upload_card_macaddress(dev);
4963 b43_security_init(dev);
4964
4965 ieee80211_wake_queues(dev->wl->hw);
4966
4967 b43_set_status(dev, B43_STAT_INITIALIZED);
4968
4969out:
4970 return err;
4971
4972err_chip_exit:
4973 b43_chip_exit(dev);
4974err_busdown:
4975 b43_bus_may_powerdown(dev);
4976 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4977 return err;
4978}
4979
4980static int b43_op_add_interface(struct ieee80211_hw *hw,
4981 struct ieee80211_vif *vif)
4982{
4983 struct b43_wl *wl = hw_to_b43_wl(hw);
4984 struct b43_wldev *dev;
4985 int err = -EOPNOTSUPP;
4986
4987 /* TODO: allow WDS/AP devices to coexist */
4988
4989 if (vif->type != NL80211_IFTYPE_AP &&
4990 vif->type != NL80211_IFTYPE_MESH_POINT &&
4991 vif->type != NL80211_IFTYPE_STATION &&
4992 vif->type != NL80211_IFTYPE_WDS &&
4993 vif->type != NL80211_IFTYPE_ADHOC)
4994 return -EOPNOTSUPP;
4995
4996 mutex_lock(&wl->mutex);
4997 if (wl->operating)
4998 goto out_mutex_unlock;
4999
5000 b43dbg(wl, "Adding Interface type %d\n", vif->type);
5001
5002 dev = wl->current_dev;
5003 wl->operating = true;
5004 wl->vif = vif;
5005 wl->if_type = vif->type;
5006 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
5007
5008 b43_adjust_opmode(dev);
5009 b43_set_pretbtt(dev);
5010 b43_set_synth_pu_delay(dev, 0);
5011 b43_upload_card_macaddress(dev);
5012
5013 err = 0;
5014 out_mutex_unlock:
5015 mutex_unlock(&wl->mutex);
5016
5017 if (err == 0)
5018 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
5019
5020 return err;
5021}
5022
5023static void b43_op_remove_interface(struct ieee80211_hw *hw,
5024 struct ieee80211_vif *vif)
5025{
5026 struct b43_wl *wl = hw_to_b43_wl(hw);
5027 struct b43_wldev *dev = wl->current_dev;
5028
5029 b43dbg(wl, "Removing Interface type %d\n", vif->type);
5030
5031 mutex_lock(&wl->mutex);
5032
5033 B43_WARN_ON(!wl->operating);
5034 B43_WARN_ON(wl->vif != vif);
5035 wl->vif = NULL;
5036
5037 wl->operating = false;
5038
5039 b43_adjust_opmode(dev);
5040 eth_zero_addr(wl->mac_addr);
5041 b43_upload_card_macaddress(dev);
5042
5043 mutex_unlock(&wl->mutex);
5044}
5045
5046static int b43_op_start(struct ieee80211_hw *hw)
5047{
5048 struct b43_wl *wl = hw_to_b43_wl(hw);
5049 struct b43_wldev *dev = wl->current_dev;
5050 int did_init = 0;
5051 int err = 0;
5052
5053 /* Kill all old instance specific information to make sure
5054 * the card won't use it in the short timeframe between start
5055 * and mac80211 reconfiguring it. */
5056 eth_zero_addr(wl->bssid);
5057 eth_zero_addr(wl->mac_addr);
5058 wl->filter_flags = 0;
5059 wl->radiotap_enabled = false;
5060 b43_qos_clear(wl);
5061 wl->beacon0_uploaded = false;
5062 wl->beacon1_uploaded = false;
5063 wl->beacon_templates_virgin = true;
5064 wl->radio_enabled = true;
5065
5066 mutex_lock(&wl->mutex);
5067
5068 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5069 err = b43_wireless_core_init(dev);
5070 if (err)
5071 goto out_mutex_unlock;
5072 did_init = 1;
5073 }
5074
5075 if (b43_status(dev) < B43_STAT_STARTED) {
5076 err = b43_wireless_core_start(dev);
5077 if (err) {
5078 if (did_init)
5079 b43_wireless_core_exit(dev);
5080 goto out_mutex_unlock;
5081 }
5082 }
5083
5084 /* XXX: only do if device doesn't support rfkill irq */
5085 wiphy_rfkill_start_polling(hw->wiphy);
5086
5087 out_mutex_unlock:
5088 mutex_unlock(&wl->mutex);
5089
5090 /*
5091 * Configuration may have been overwritten during initialization.
5092 * Reload the configuration, but only if initialization was
5093 * successful. Reloading the configuration after a failed init
5094 * may hang the system.
5095 */
5096 if (!err)
5097 b43_op_config(hw, ~0);
5098
5099 return err;
5100}
5101
5102static void b43_op_stop(struct ieee80211_hw *hw)
5103{
5104 struct b43_wl *wl = hw_to_b43_wl(hw);
5105 struct b43_wldev *dev = wl->current_dev;
5106
5107 cancel_work_sync(&(wl->beacon_update_trigger));
5108
5109 if (!dev)
5110 goto out;
5111
5112 mutex_lock(&wl->mutex);
5113 if (b43_status(dev) >= B43_STAT_STARTED) {
5114 dev = b43_wireless_core_stop(dev);
5115 if (!dev)
5116 goto out_unlock;
5117 }
5118 b43_wireless_core_exit(dev);
5119 wl->radio_enabled = false;
5120
5121out_unlock:
5122 mutex_unlock(&wl->mutex);
5123out:
5124 cancel_work_sync(&(wl->txpower_adjust_work));
5125}
5126
5127static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5128 struct ieee80211_sta *sta, bool set)
5129{
5130 struct b43_wl *wl = hw_to_b43_wl(hw);
5131
5132 b43_update_templates(wl);
5133
5134 return 0;
5135}
5136
5137static void b43_op_sta_notify(struct ieee80211_hw *hw,
5138 struct ieee80211_vif *vif,
5139 enum sta_notify_cmd notify_cmd,
5140 struct ieee80211_sta *sta)
5141{
5142 struct b43_wl *wl = hw_to_b43_wl(hw);
5143
5144 B43_WARN_ON(!vif || wl->vif != vif);
5145}
5146
5147static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw,
5148 struct ieee80211_vif *vif,
5149 const u8 *mac_addr)
5150{
5151 struct b43_wl *wl = hw_to_b43_wl(hw);
5152 struct b43_wldev *dev;
5153
5154 mutex_lock(&wl->mutex);
5155 dev = wl->current_dev;
5156 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5157 /* Disable CFP update during scan on other channels. */
5158 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5159 }
5160 mutex_unlock(&wl->mutex);
5161}
5162
5163static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw,
5164 struct ieee80211_vif *vif)
5165{
5166 struct b43_wl *wl = hw_to_b43_wl(hw);
5167 struct b43_wldev *dev;
5168
5169 mutex_lock(&wl->mutex);
5170 dev = wl->current_dev;
5171 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5172 /* Re-enable CFP update. */
5173 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5174 }
5175 mutex_unlock(&wl->mutex);
5176}
5177
5178static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5179 struct survey_info *survey)
5180{
5181 struct b43_wl *wl = hw_to_b43_wl(hw);
5182 struct b43_wldev *dev = wl->current_dev;
5183 struct ieee80211_conf *conf = &hw->conf;
5184
5185 if (idx != 0)
5186 return -ENOENT;
5187
5188 survey->channel = conf->chandef.chan;
5189 survey->filled = SURVEY_INFO_NOISE_DBM;
5190 survey->noise = dev->stats.link_noise;
5191
5192 return 0;
5193}
5194
5195static const struct ieee80211_ops b43_hw_ops = {
5196 .tx = b43_op_tx,
5197 .conf_tx = b43_op_conf_tx,
5198 .add_interface = b43_op_add_interface,
5199 .remove_interface = b43_op_remove_interface,
5200 .config = b43_op_config,
5201 .bss_info_changed = b43_op_bss_info_changed,
5202 .configure_filter = b43_op_configure_filter,
5203 .set_key = b43_op_set_key,
5204 .update_tkip_key = b43_op_update_tkip_key,
5205 .get_stats = b43_op_get_stats,
5206 .get_tsf = b43_op_get_tsf,
5207 .set_tsf = b43_op_set_tsf,
5208 .start = b43_op_start,
5209 .stop = b43_op_stop,
5210 .set_tim = b43_op_beacon_set_tim,
5211 .sta_notify = b43_op_sta_notify,
5212 .sw_scan_start = b43_op_sw_scan_start_notifier,
5213 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
5214 .get_survey = b43_op_get_survey,
5215 .rfkill_poll = b43_rfkill_poll,
5216};
5217
5218/* Hard-reset the chip. Do not call this directly.
5219 * Use b43_controller_restart()
5220 */
5221static void b43_chip_reset(struct work_struct *work)
5222{
5223 struct b43_wldev *dev =
5224 container_of(work, struct b43_wldev, restart_work);
5225 struct b43_wl *wl = dev->wl;
5226 int err = 0;
5227 int prev_status;
5228
5229 mutex_lock(&wl->mutex);
5230
5231 prev_status = b43_status(dev);
5232 /* Bring the device down... */
5233 if (prev_status >= B43_STAT_STARTED) {
5234 dev = b43_wireless_core_stop(dev);
5235 if (!dev) {
5236 err = -ENODEV;
5237 goto out;
5238 }
5239 }
5240 if (prev_status >= B43_STAT_INITIALIZED)
5241 b43_wireless_core_exit(dev);
5242
5243 /* ...and up again. */
5244 if (prev_status >= B43_STAT_INITIALIZED) {
5245 err = b43_wireless_core_init(dev);
5246 if (err)
5247 goto out;
5248 }
5249 if (prev_status >= B43_STAT_STARTED) {
5250 err = b43_wireless_core_start(dev);
5251 if (err) {
5252 b43_wireless_core_exit(dev);
5253 goto out;
5254 }
5255 }
5256out:
5257 if (err)
5258 wl->current_dev = NULL; /* Failed to init the dev. */
5259 mutex_unlock(&wl->mutex);
5260
5261 if (err) {
5262 b43err(wl, "Controller restart FAILED\n");
5263 return;
5264 }
5265
5266 /* reload configuration */
5267 b43_op_config(wl->hw, ~0);
5268 if (wl->vif)
5269 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5270
5271 b43info(wl, "Controller restarted\n");
5272}
5273
5274static int b43_setup_bands(struct b43_wldev *dev,
5275 bool have_2ghz_phy, bool have_5ghz_phy)
5276{
5277 struct ieee80211_hw *hw = dev->wl->hw;
5278 struct b43_phy *phy = &dev->phy;
5279 bool limited_2g;
5280 bool limited_5g;
5281
5282 /* We don't support all 2 GHz channels on some devices */
5283 limited_2g = phy->radio_ver == 0x2057 &&
5284 (phy->radio_rev == 9 || phy->radio_rev == 14);
5285 limited_5g = phy->radio_ver == 0x2057 &&
5286 phy->radio_rev == 9;
5287
5288 if (have_2ghz_phy)
5289 hw->wiphy->bands[NL80211_BAND_2GHZ] = limited_2g ?
5290 &b43_band_2ghz_limited : &b43_band_2GHz;
5291 if (dev->phy.type == B43_PHYTYPE_N) {
5292 if (have_5ghz_phy)
5293 hw->wiphy->bands[NL80211_BAND_5GHZ] = limited_5g ?
5294 &b43_band_5GHz_nphy_limited :
5295 &b43_band_5GHz_nphy;
5296 } else {
5297 if (have_5ghz_phy)
5298 hw->wiphy->bands[NL80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5299 }
5300
5301 dev->phy.supports_2ghz = have_2ghz_phy;
5302 dev->phy.supports_5ghz = have_5ghz_phy;
5303
5304 return 0;
5305}
5306
5307static void b43_wireless_core_detach(struct b43_wldev *dev)
5308{
5309 /* We release firmware that late to not be required to re-request
5310 * is all the time when we reinit the core. */
5311 b43_release_firmware(dev);
5312 b43_phy_free(dev);
5313}
5314
5315static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5316 bool *have_5ghz_phy)
5317{
5318 u16 dev_id = 0;
5319
5320#ifdef CONFIG_B43_BCMA
5321 if (dev->dev->bus_type == B43_BUS_BCMA &&
5322 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5323 dev_id = dev->dev->bdev->bus->host_pci->device;
5324#endif
5325#ifdef CONFIG_B43_SSB
5326 if (dev->dev->bus_type == B43_BUS_SSB &&
5327 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5328 dev_id = dev->dev->sdev->bus->host_pci->device;
5329#endif
5330 /* Override with SPROM value if available */
5331 if (dev->dev->bus_sprom->dev_id)
5332 dev_id = dev->dev->bus_sprom->dev_id;
5333
5334 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5335 switch (dev_id) {
5336 case 0x4324: /* BCM4306 */
5337 case 0x4312: /* BCM4311 */
5338 case 0x4319: /* BCM4318 */
5339 case 0x4328: /* BCM4321 */
5340 case 0x432b: /* BCM4322 */
5341 case 0x4350: /* BCM43222 */
5342 case 0x4353: /* BCM43224 */
5343 case 0x0576: /* BCM43224 */
5344 case 0x435f: /* BCM6362 */
5345 case 0x4331: /* BCM4331 */
5346 case 0x4359: /* BCM43228 */
5347 case 0x43a0: /* BCM4360 */
5348 case 0x43b1: /* BCM4352 */
5349 /* Dual band devices */
5350 *have_2ghz_phy = true;
5351 *have_5ghz_phy = true;
5352 return;
5353 case 0x4321: /* BCM4306 */
5354 /* There are 14e4:4321 PCI devs with 2.4 GHz BCM4321 (N-PHY) */
5355 if (dev->phy.type != B43_PHYTYPE_G)
5356 break;
5357 /* fall through */
5358 case 0x4313: /* BCM4311 */
5359 case 0x431a: /* BCM4318 */
5360 case 0x432a: /* BCM4321 */
5361 case 0x432d: /* BCM4322 */
5362 case 0x4352: /* BCM43222 */
5363 case 0x435a: /* BCM43228 */
5364 case 0x4333: /* BCM4331 */
5365 case 0x43a2: /* BCM4360 */
5366 case 0x43b3: /* BCM4352 */
5367 /* 5 GHz only devices */
5368 *have_2ghz_phy = false;
5369 *have_5ghz_phy = true;
5370 return;
5371 }
5372
5373 /* As a fallback, try to guess using PHY type */
5374 switch (dev->phy.type) {
5375 case B43_PHYTYPE_G:
5376 case B43_PHYTYPE_N:
5377 case B43_PHYTYPE_LP:
5378 case B43_PHYTYPE_HT:
5379 case B43_PHYTYPE_LCN:
5380 *have_2ghz_phy = true;
5381 *have_5ghz_phy = false;
5382 return;
5383 }
5384
5385 B43_WARN_ON(1);
5386}
5387
5388static int b43_wireless_core_attach(struct b43_wldev *dev)
5389{
5390 struct b43_wl *wl = dev->wl;
5391 struct b43_phy *phy = &dev->phy;
5392 int err;
5393 u32 tmp;
5394 bool have_2ghz_phy = false, have_5ghz_phy = false;
5395
5396 /* Do NOT do any device initialization here.
5397 * Do it in wireless_core_init() instead.
5398 * This function is for gathering basic information about the HW, only.
5399 * Also some structs may be set up here. But most likely you want to have
5400 * that in core_init(), too.
5401 */
5402
5403 err = b43_bus_powerup(dev, 0);
5404 if (err) {
5405 b43err(wl, "Bus powerup failed\n");
5406 goto out;
5407 }
5408
5409 phy->do_full_init = true;
5410
5411 /* Try to guess supported bands for the first init needs */
5412 switch (dev->dev->bus_type) {
5413#ifdef CONFIG_B43_BCMA
5414 case B43_BUS_BCMA:
5415 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5416 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5417 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5418 break;
5419#endif
5420#ifdef CONFIG_B43_SSB
5421 case B43_BUS_SSB:
5422 if (dev->dev->core_rev >= 5) {
5423 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5424 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5425 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5426 } else
5427 B43_WARN_ON(1);
5428 break;
5429#endif
5430 }
5431
5432 dev->phy.gmode = have_2ghz_phy;
5433 b43_wireless_core_reset(dev, dev->phy.gmode);
5434
5435 /* Get the PHY type. */
5436 err = b43_phy_versioning(dev);
5437 if (err)
5438 goto err_powerdown;
5439
5440 /* Get real info about supported bands */
5441 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5442
5443 /* We don't support 5 GHz on some PHYs yet */
5444 if (have_5ghz_phy) {
5445 switch (dev->phy.type) {
5446 case B43_PHYTYPE_G:
5447 case B43_PHYTYPE_LP:
5448 case B43_PHYTYPE_HT:
5449 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5450 have_5ghz_phy = false;
5451 }
5452 }
5453
5454 if (!have_2ghz_phy && !have_5ghz_phy) {
5455 b43err(wl, "b43 can't support any band on this device\n");
5456 err = -EOPNOTSUPP;
5457 goto err_powerdown;
5458 }
5459
5460 err = b43_phy_allocate(dev);
5461 if (err)
5462 goto err_powerdown;
5463
5464 dev->phy.gmode = have_2ghz_phy;
5465 b43_wireless_core_reset(dev, dev->phy.gmode);
5466
5467 err = b43_validate_chipaccess(dev);
5468 if (err)
5469 goto err_phy_free;
5470 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5471 if (err)
5472 goto err_phy_free;
5473
5474 /* Now set some default "current_dev" */
5475 if (!wl->current_dev)
5476 wl->current_dev = dev;
5477 INIT_WORK(&dev->restart_work, b43_chip_reset);
5478
5479 dev->phy.ops->switch_analog(dev, 0);
5480 b43_device_disable(dev, 0);
5481 b43_bus_may_powerdown(dev);
5482
5483out:
5484 return err;
5485
5486err_phy_free:
5487 b43_phy_free(dev);
5488err_powerdown:
5489 b43_bus_may_powerdown(dev);
5490 return err;
5491}
5492
5493static void b43_one_core_detach(struct b43_bus_dev *dev)
5494{
5495 struct b43_wldev *wldev;
5496 struct b43_wl *wl;
5497
5498 /* Do not cancel ieee80211-workqueue based work here.
5499 * See comment in b43_remove(). */
5500
5501 wldev = b43_bus_get_wldev(dev);
5502 wl = wldev->wl;
5503 b43_debugfs_remove_device(wldev);
5504 b43_wireless_core_detach(wldev);
5505 list_del(&wldev->list);
5506 b43_bus_set_wldev(dev, NULL);
5507 kfree(wldev);
5508}
5509
5510static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5511{
5512 struct b43_wldev *wldev;
5513 int err = -ENOMEM;
5514
5515 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5516 if (!wldev)
5517 goto out;
5518
5519 wldev->use_pio = b43_modparam_pio;
5520 wldev->dev = dev;
5521 wldev->wl = wl;
5522 b43_set_status(wldev, B43_STAT_UNINIT);
5523 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5524 INIT_LIST_HEAD(&wldev->list);
5525
5526 err = b43_wireless_core_attach(wldev);
5527 if (err)
5528 goto err_kfree_wldev;
5529
5530 b43_bus_set_wldev(dev, wldev);
5531 b43_debugfs_add_device(wldev);
5532
5533 out:
5534 return err;
5535
5536 err_kfree_wldev:
5537 kfree(wldev);
5538 return err;
5539}
5540
5541#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5542 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5543 (pdev->device == _device) && \
5544 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5545 (pdev->subsystem_device == _subdevice) )
5546
5547#ifdef CONFIG_B43_SSB
5548static void b43_sprom_fixup(struct ssb_bus *bus)
5549{
5550 struct pci_dev *pdev;
5551
5552 /* boardflags workarounds */
5553 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5554 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5555 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5556 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5557 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5558 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5559 if (bus->bustype == SSB_BUSTYPE_PCI) {
5560 pdev = bus->host_pci;
5561 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5562 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5563 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5564 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5565 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5566 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5567 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5568 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5569 }
5570}
5571
5572static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5573{
5574 struct ieee80211_hw *hw = wl->hw;
5575
5576 ssb_set_devtypedata(dev->sdev, NULL);
5577 ieee80211_free_hw(hw);
5578}
5579#endif
5580
5581static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5582{
5583 struct ssb_sprom *sprom = dev->bus_sprom;
5584 struct ieee80211_hw *hw;
5585 struct b43_wl *wl;
5586 char chip_name[6];
5587 int queue_num;
5588
5589 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5590 if (!hw) {
5591 b43err(NULL, "Could not allocate ieee80211 device\n");
5592 return ERR_PTR(-ENOMEM);
5593 }
5594 wl = hw_to_b43_wl(hw);
5595
5596 /* fill hw info */
5597 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5598 ieee80211_hw_set(hw, SIGNAL_DBM);
5599
5600 hw->wiphy->interface_modes =
5601 BIT(NL80211_IFTYPE_AP) |
5602 BIT(NL80211_IFTYPE_MESH_POINT) |
5603 BIT(NL80211_IFTYPE_STATION) |
5604#ifdef CONFIG_WIRELESS_WDS
5605 BIT(NL80211_IFTYPE_WDS) |
5606#endif
5607 BIT(NL80211_IFTYPE_ADHOC);
5608
5609 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5610
5611 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
5612
5613 wl->hw_registred = false;
5614 hw->max_rates = 2;
5615 SET_IEEE80211_DEV(hw, dev->dev);
5616 if (is_valid_ether_addr(sprom->et1mac))
5617 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5618 else
5619 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5620
5621 /* Initialize struct b43_wl */
5622 wl->hw = hw;
5623 mutex_init(&wl->mutex);
5624 spin_lock_init(&wl->hardirq_lock);
5625 spin_lock_init(&wl->beacon_lock);
5626 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5627 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5628 INIT_WORK(&wl->tx_work, b43_tx_work);
5629
5630 /* Initialize queues and flags. */
5631 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5632 skb_queue_head_init(&wl->tx_queue[queue_num]);
5633 wl->tx_queue_stopped[queue_num] = 0;
5634 }
5635
5636 snprintf(chip_name, ARRAY_SIZE(chip_name),
5637 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5638 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5639 dev->core_rev);
5640 return wl;
5641}
5642
5643#ifdef CONFIG_B43_BCMA
5644static int b43_bcma_probe(struct bcma_device *core)
5645{
5646 struct b43_bus_dev *dev;
5647 struct b43_wl *wl;
5648 int err;
5649
5650 if (!modparam_allhwsupport &&
5651 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5652 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5653 return -ENOTSUPP;
5654 }
5655
5656 dev = b43_bus_dev_bcma_init(core);
5657 if (!dev)
5658 return -ENODEV;
5659
5660 wl = b43_wireless_init(dev);
5661 if (IS_ERR(wl)) {
5662 err = PTR_ERR(wl);
5663 goto bcma_out;
5664 }
5665
5666 err = b43_one_core_attach(dev, wl);
5667 if (err)
5668 goto bcma_err_wireless_exit;
5669
5670 /* setup and start work to load firmware */
5671 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5672 schedule_work(&wl->firmware_load);
5673
5674 return err;
5675
5676bcma_err_wireless_exit:
5677 ieee80211_free_hw(wl->hw);
5678bcma_out:
5679 kfree(dev);
5680 return err;
5681}
5682
5683static void b43_bcma_remove(struct bcma_device *core)
5684{
5685 struct b43_wldev *wldev = bcma_get_drvdata(core);
5686 struct b43_wl *wl = wldev->wl;
5687
5688 /* We must cancel any work here before unregistering from ieee80211,
5689 * as the ieee80211 unreg will destroy the workqueue. */
5690 cancel_work_sync(&wldev->restart_work);
5691 cancel_work_sync(&wl->firmware_load);
5692
5693 B43_WARN_ON(!wl);
5694 if (!wldev->fw.ucode.data)
5695 return; /* NULL if firmware never loaded */
5696 if (wl->current_dev == wldev && wl->hw_registred) {
5697 b43_leds_stop(wldev);
5698 ieee80211_unregister_hw(wl->hw);
5699 }
5700
5701 b43_one_core_detach(wldev->dev);
5702
5703 /* Unregister HW RNG driver */
5704 b43_rng_exit(wl);
5705
5706 b43_leds_unregister(wl);
5707 ieee80211_free_hw(wl->hw);
5708 kfree(wldev->dev);
5709}
5710
5711static struct bcma_driver b43_bcma_driver = {
5712 .name = KBUILD_MODNAME,
5713 .id_table = b43_bcma_tbl,
5714 .probe = b43_bcma_probe,
5715 .remove = b43_bcma_remove,
5716};
5717#endif
5718
5719#ifdef CONFIG_B43_SSB
5720static
5721int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5722{
5723 struct b43_bus_dev *dev;
5724 struct b43_wl *wl;
5725 int err;
5726
5727 dev = b43_bus_dev_ssb_init(sdev);
5728 if (!dev)
5729 return -ENOMEM;
5730
5731 wl = ssb_get_devtypedata(sdev);
5732 if (wl) {
5733 b43err(NULL, "Dual-core devices are not supported\n");
5734 err = -ENOTSUPP;
5735 goto err_ssb_kfree_dev;
5736 }
5737
5738 b43_sprom_fixup(sdev->bus);
5739
5740 wl = b43_wireless_init(dev);
5741 if (IS_ERR(wl)) {
5742 err = PTR_ERR(wl);
5743 goto err_ssb_kfree_dev;
5744 }
5745 ssb_set_devtypedata(sdev, wl);
5746 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5747
5748 err = b43_one_core_attach(dev, wl);
5749 if (err)
5750 goto err_ssb_wireless_exit;
5751
5752 /* setup and start work to load firmware */
5753 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5754 schedule_work(&wl->firmware_load);
5755
5756 return err;
5757
5758err_ssb_wireless_exit:
5759 b43_wireless_exit(dev, wl);
5760err_ssb_kfree_dev:
5761 kfree(dev);
5762 return err;
5763}
5764
5765static void b43_ssb_remove(struct ssb_device *sdev)
5766{
5767 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5768 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5769 struct b43_bus_dev *dev = wldev->dev;
5770
5771 /* We must cancel any work here before unregistering from ieee80211,
5772 * as the ieee80211 unreg will destroy the workqueue. */
5773 cancel_work_sync(&wldev->restart_work);
5774 cancel_work_sync(&wl->firmware_load);
5775
5776 B43_WARN_ON(!wl);
5777 if (!wldev->fw.ucode.data)
5778 return; /* NULL if firmware never loaded */
5779 if (wl->current_dev == wldev && wl->hw_registred) {
5780 b43_leds_stop(wldev);
5781 ieee80211_unregister_hw(wl->hw);
5782 }
5783
5784 b43_one_core_detach(dev);
5785
5786 /* Unregister HW RNG driver */
5787 b43_rng_exit(wl);
5788
5789 b43_leds_unregister(wl);
5790 b43_wireless_exit(dev, wl);
5791 kfree(dev);
5792}
5793
5794static struct ssb_driver b43_ssb_driver = {
5795 .name = KBUILD_MODNAME,
5796 .id_table = b43_ssb_tbl,
5797 .probe = b43_ssb_probe,
5798 .remove = b43_ssb_remove,
5799};
5800#endif /* CONFIG_B43_SSB */
5801
5802/* Perform a hardware reset. This can be called from any context. */
5803void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5804{
5805 /* Must avoid requeueing, if we are in shutdown. */
5806 if (b43_status(dev) < B43_STAT_INITIALIZED)
5807 return;
5808 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5809 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5810}
5811
5812static void b43_print_driverinfo(void)
5813{
5814 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5815 *feat_leds = "", *feat_sdio = "";
5816
5817#ifdef CONFIG_B43_PCI_AUTOSELECT
5818 feat_pci = "P";
5819#endif
5820#ifdef CONFIG_B43_PCMCIA
5821 feat_pcmcia = "M";
5822#endif
5823#ifdef CONFIG_B43_PHY_N
5824 feat_nphy = "N";
5825#endif
5826#ifdef CONFIG_B43_LEDS
5827 feat_leds = "L";
5828#endif
5829#ifdef CONFIG_B43_SDIO
5830 feat_sdio = "S";
5831#endif
5832 printk(KERN_INFO "Broadcom 43xx driver loaded "
5833 "[ Features: %s%s%s%s%s ]\n",
5834 feat_pci, feat_pcmcia, feat_nphy,
5835 feat_leds, feat_sdio);
5836}
5837
5838static int __init b43_init(void)
5839{
5840 int err;
5841
5842 b43_debugfs_init();
5843 err = b43_sdio_init();
5844 if (err)
5845 goto err_dfs_exit;
5846#ifdef CONFIG_B43_BCMA
5847 err = bcma_driver_register(&b43_bcma_driver);
5848 if (err)
5849 goto err_sdio_exit;
5850#endif
5851#ifdef CONFIG_B43_SSB
5852 err = ssb_driver_register(&b43_ssb_driver);
5853 if (err)
5854 goto err_bcma_driver_exit;
5855#endif
5856 b43_print_driverinfo();
5857
5858 return err;
5859
5860#ifdef CONFIG_B43_SSB
5861err_bcma_driver_exit:
5862#endif
5863#ifdef CONFIG_B43_BCMA
5864 bcma_driver_unregister(&b43_bcma_driver);
5865err_sdio_exit:
5866#endif
5867 b43_sdio_exit();
5868err_dfs_exit:
5869 b43_debugfs_exit();
5870 return err;
5871}
5872
5873static void __exit b43_exit(void)
5874{
5875#ifdef CONFIG_B43_SSB
5876 ssb_driver_unregister(&b43_ssb_driver);
5877#endif
5878#ifdef CONFIG_B43_BCMA
5879 bcma_driver_unregister(&b43_bcma_driver);
5880#endif
5881 b43_sdio_exit();
5882 b43_debugfs_exit();
5883}
5884
5885module_init(b43_init)
5886module_exit(b43_exit)