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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e.h"
28#include <linux/ptp_classify.h>
29
30/* The XL710 timesync is very much like Intel's 82599 design when it comes to
31 * the fundamental clock design. However, the clock operations are much simpler
32 * in the XL710 because the device supports a full 64 bits of nanoseconds.
33 * Because the field is so wide, we can forgo the cycle counter and just
34 * operate with the nanosecond field directly without fear of overflow.
35 *
36 * Much like the 82599, the update period is dependent upon the link speed:
37 * At 40Gb link or no link, the period is 1.6ns.
38 * At 10Gb link, the period is multiplied by 2. (3.2ns)
39 * At 1Gb link, the period is multiplied by 20. (32ns)
40 * 1588 functionality is not supported at 100Mbps.
41 */
42#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
43#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
44#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
45
46#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
47#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
48 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
49
50/**
51 * i40e_ptp_read - Read the PHC time from the device
52 * @pf: Board private structure
53 * @ts: timespec structure to hold the current time value
54 *
55 * This function reads the PRTTSYN_TIME registers and stores them in a
56 * timespec. However, since the registers are 64 bits of nanoseconds, we must
57 * convert the result to a timespec before we can return.
58 **/
59static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts)
60{
61 struct i40e_hw *hw = &pf->hw;
62 u32 hi, lo;
63 u64 ns;
64
65 /* The timer latches on the lowest register read. */
66 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
67 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
68
69 ns = (((u64)hi) << 32) | lo;
70
71 *ts = ns_to_timespec64(ns);
72}
73
74/**
75 * i40e_ptp_write - Write the PHC time to the device
76 * @pf: Board private structure
77 * @ts: timespec structure that holds the new time value
78 *
79 * This function writes the PRTTSYN_TIME registers with the user value. Since
80 * we receive a timespec from the stack, we must convert that timespec into
81 * nanoseconds before programming the registers.
82 **/
83static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
84{
85 struct i40e_hw *hw = &pf->hw;
86 u64 ns = timespec64_to_ns(ts);
87
88 /* The timer will not update until the high register is written, so
89 * write the low register first.
90 */
91 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
92 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
93}
94
95/**
96 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
97 * @hwtstamps: Timestamp structure to update
98 * @timestamp: Timestamp from the hardware
99 *
100 * We need to convert the NIC clock value into a hwtstamp which can be used by
101 * the upper level timestamping functions. Since the timestamp is simply a 64-
102 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
103 **/
104static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
105 u64 timestamp)
106{
107 memset(hwtstamps, 0, sizeof(*hwtstamps));
108
109 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
110}
111
112/**
113 * i40e_ptp_adjfreq - Adjust the PHC frequency
114 * @ptp: The PTP clock structure
115 * @ppb: Parts per billion adjustment from the base
116 *
117 * Adjust the frequency of the PHC by the indicated parts per billion from the
118 * base frequency.
119 **/
120static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
121{
122 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
123 struct i40e_hw *hw = &pf->hw;
124 u64 adj, freq, diff;
125 int neg_adj = 0;
126
127 if (ppb < 0) {
128 neg_adj = 1;
129 ppb = -ppb;
130 }
131
132 smp_mb(); /* Force any pending update before accessing. */
133 adj = ACCESS_ONCE(pf->ptp_base_adj);
134
135 freq = adj;
136 freq *= ppb;
137 diff = div_u64(freq, 1000000000ULL);
138
139 if (neg_adj)
140 adj -= diff;
141 else
142 adj += diff;
143
144 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
145 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
146
147 return 0;
148}
149
150/**
151 * i40e_ptp_adjtime - Adjust the PHC time
152 * @ptp: The PTP clock structure
153 * @delta: Offset in nanoseconds to adjust the PHC time by
154 *
155 * Adjust the frequency of the PHC by the indicated parts per billion from the
156 * base frequency.
157 **/
158static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
159{
160 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
161 struct timespec64 now, then = ns_to_timespec64(delta);
162 unsigned long flags;
163
164 spin_lock_irqsave(&pf->tmreg_lock, flags);
165
166 i40e_ptp_read(pf, &now);
167 now = timespec64_add(now, then);
168 i40e_ptp_write(pf, (const struct timespec64 *)&now);
169
170 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
171
172 return 0;
173}
174
175/**
176 * i40e_ptp_gettime - Get the time of the PHC
177 * @ptp: The PTP clock structure
178 * @ts: timespec structure to hold the current time value
179 *
180 * Read the device clock and return the correct value on ns, after converting it
181 * into a timespec struct.
182 **/
183static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
184{
185 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
186 unsigned long flags;
187
188 spin_lock_irqsave(&pf->tmreg_lock, flags);
189 i40e_ptp_read(pf, ts);
190 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
191
192 return 0;
193}
194
195/**
196 * i40e_ptp_settime - Set the time of the PHC
197 * @ptp: The PTP clock structure
198 * @ts: timespec structure that holds the new time value
199 *
200 * Set the device clock to the user input value. The conversion from timespec
201 * to ns happens in the write function.
202 **/
203static int i40e_ptp_settime(struct ptp_clock_info *ptp,
204 const struct timespec64 *ts)
205{
206 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
207 unsigned long flags;
208
209 spin_lock_irqsave(&pf->tmreg_lock, flags);
210 i40e_ptp_write(pf, ts);
211 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
212
213 return 0;
214}
215
216/**
217 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
218 * @ptp: The PTP clock structure
219 * @rq: The requested feature to change
220 * @on: Enable/disable flag
221 *
222 * The XL710 does not support any of the ancillary features of the PHC
223 * subsystem, so this function may just return.
224 **/
225static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
226 struct ptp_clock_request *rq, int on)
227{
228 return -EOPNOTSUPP;
229}
230
231/**
232 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
233 * @vsi: The VSI with the rings relevant to 1588
234 *
235 * This watchdog task is scheduled to detect error case where hardware has
236 * dropped an Rx packet that was timestamped when the ring is full. The
237 * particular error is rare but leaves the device in a state unable to timestamp
238 * any future packets.
239 **/
240void i40e_ptp_rx_hang(struct i40e_vsi *vsi)
241{
242 struct i40e_pf *pf = vsi->back;
243 struct i40e_hw *hw = &pf->hw;
244 struct i40e_ring *rx_ring;
245 unsigned long rx_event;
246 u32 prttsyn_stat;
247 int n;
248
249 /* Since we cannot turn off the Rx timestamp logic if the device is
250 * configured for Tx timestamping, we check if Rx timestamping is
251 * configured. We don't want to spuriously warn about Rx timestamp
252 * hangs if we don't care about the timestamps.
253 */
254 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
255 return;
256
257 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
258
259 /* Unless all four receive timestamp registers are latched, we are not
260 * concerned about a possible PTP Rx hang, so just update the timeout
261 * counter and exit.
262 */
263 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK <<
264 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
265 (I40E_PRTTSYN_STAT_1_RXT1_MASK <<
266 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
267 (I40E_PRTTSYN_STAT_1_RXT2_MASK <<
268 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
269 (I40E_PRTTSYN_STAT_1_RXT3_MASK <<
270 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) {
271 pf->last_rx_ptp_check = jiffies;
272 return;
273 }
274
275 /* Determine the most recent watchdog or rx_timestamp event. */
276 rx_event = pf->last_rx_ptp_check;
277 for (n = 0; n < vsi->num_queue_pairs; n++) {
278 rx_ring = vsi->rx_rings[n];
279 if (time_after(rx_ring->last_rx_timestamp, rx_event))
280 rx_event = rx_ring->last_rx_timestamp;
281 }
282
283 /* Only need to read the high RXSTMP register to clear the lock */
284 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
285 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
286 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
287 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
288 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
289 pf->last_rx_ptp_check = jiffies;
290 pf->rx_hwtstamp_cleared++;
291 dev_warn(&vsi->back->pdev->dev,
292 "%s: clearing Rx timestamp hang\n",
293 __func__);
294 }
295}
296
297/**
298 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
299 * @pf: Board private structure
300 *
301 * Read the value of the Tx timestamp from the registers, convert it into a
302 * value consumable by the stack, and store that result into the shhwtstamps
303 * struct before returning it up the stack.
304 **/
305void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
306{
307 struct skb_shared_hwtstamps shhwtstamps;
308 struct i40e_hw *hw = &pf->hw;
309 u32 hi, lo;
310 u64 ns;
311
312 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
313 return;
314
315 /* don't attempt to timestamp if we don't have an skb */
316 if (!pf->ptp_tx_skb)
317 return;
318
319 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
320 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
321
322 ns = (((u64)hi) << 32) | lo;
323
324 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
325 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps);
326 dev_kfree_skb_any(pf->ptp_tx_skb);
327 pf->ptp_tx_skb = NULL;
328 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state);
329}
330
331/**
332 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
333 * @pf: Board private structure
334 * @skb: Particular skb to send timestamp with
335 * @index: Index into the receive timestamp registers for the timestamp
336 *
337 * The XL710 receives a notification in the receive descriptor with an offset
338 * into the set of RXTIME registers where the timestamp is for that skb. This
339 * function goes and fetches the receive timestamp from that offset, if a valid
340 * one exists. The RXTIME registers are in ns, so we must convert the result
341 * first.
342 **/
343void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
344{
345 u32 prttsyn_stat, hi, lo;
346 struct i40e_hw *hw;
347 u64 ns;
348
349 /* Since we cannot turn off the Rx timestamp logic if the device is
350 * doing Tx timestamping, check if Rx timestamping is configured.
351 */
352 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
353 return;
354
355 hw = &pf->hw;
356
357 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
358
359 if (!(prttsyn_stat & BIT(index)))
360 return;
361
362 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
363 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
364
365 ns = (((u64)hi) << 32) | lo;
366
367 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
368}
369
370/**
371 * i40e_ptp_set_increment - Utility function to update clock increment rate
372 * @pf: Board private structure
373 *
374 * During a link change, the DMA frequency that drives the 1588 logic will
375 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
376 * we must update the increment value per clock tick.
377 **/
378void i40e_ptp_set_increment(struct i40e_pf *pf)
379{
380 struct i40e_link_status *hw_link_info;
381 struct i40e_hw *hw = &pf->hw;
382 u64 incval;
383
384 hw_link_info = &hw->phy.link_info;
385
386 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
387
388 switch (hw_link_info->link_speed) {
389 case I40E_LINK_SPEED_10GB:
390 incval = I40E_PTP_10GB_INCVAL;
391 break;
392 case I40E_LINK_SPEED_1GB:
393 incval = I40E_PTP_1GB_INCVAL;
394 break;
395 case I40E_LINK_SPEED_100MB:
396 {
397 static int warn_once;
398
399 if (!warn_once) {
400 dev_warn(&pf->pdev->dev,
401 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
402 warn_once++;
403 }
404 incval = 0;
405 break;
406 }
407 case I40E_LINK_SPEED_40GB:
408 default:
409 incval = I40E_PTP_40GB_INCVAL;
410 break;
411 }
412
413 /* Write the new increment value into the increment register. The
414 * hardware will not update the clock until both registers have been
415 * written.
416 */
417 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
418 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
419
420 /* Update the base adjustement value. */
421 ACCESS_ONCE(pf->ptp_base_adj) = incval;
422 smp_mb(); /* Force the above update. */
423}
424
425/**
426 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
427 * @pf: Board private structure
428 * @ifreq: ioctl data
429 *
430 * Obtain the current hardware timestamping settigs as requested. To do this,
431 * keep a shadow copy of the timestamp settings rather than attempting to
432 * deconstruct it from the registers.
433 **/
434int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
435{
436 struct hwtstamp_config *config = &pf->tstamp_config;
437
438 if (!(pf->flags & I40E_FLAG_PTP))
439 return -EOPNOTSUPP;
440
441 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
442 -EFAULT : 0;
443}
444
445/**
446 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
447 * @pf: Board private structure
448 * @config: hwtstamp settings requested or saved
449 *
450 * Control hardware registers to enter the specific mode requested by the
451 * user. Also used during reset path to ensure that timestamp settings are
452 * maintained.
453 *
454 * Note: modifies config in place, and may update the requested mode to be
455 * more broad if the specific filter is not directly supported.
456 **/
457static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
458 struct hwtstamp_config *config)
459{
460 struct i40e_hw *hw = &pf->hw;
461 u32 tsyntype, regval;
462
463 /* Reserved for future extensions. */
464 if (config->flags)
465 return -EINVAL;
466
467 switch (config->tx_type) {
468 case HWTSTAMP_TX_OFF:
469 pf->ptp_tx = false;
470 break;
471 case HWTSTAMP_TX_ON:
472 pf->ptp_tx = true;
473 break;
474 default:
475 return -ERANGE;
476 }
477
478 switch (config->rx_filter) {
479 case HWTSTAMP_FILTER_NONE:
480 pf->ptp_rx = false;
481 /* We set the type to V1, but do not enable UDP packet
482 * recognition. In this way, we should be as close to
483 * disabling PTP Rx timestamps as possible since V1 packets
484 * are always UDP, since L2 packets are a V2 feature.
485 */
486 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
487 break;
488 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
489 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
490 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
491 pf->ptp_rx = true;
492 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
493 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
494 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
495 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
496 break;
497 case HWTSTAMP_FILTER_PTP_V2_EVENT:
498 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
500 case HWTSTAMP_FILTER_PTP_V2_SYNC:
501 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
502 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
503 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
504 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
505 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
506 pf->ptp_rx = true;
507 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
508 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 |
509 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
510 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
511 break;
512 case HWTSTAMP_FILTER_ALL:
513 default:
514 return -ERANGE;
515 }
516
517 /* Clear out all 1588-related registers to clear and unlatch them. */
518 rd32(hw, I40E_PRTTSYN_STAT_0);
519 rd32(hw, I40E_PRTTSYN_TXTIME_H);
520 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
521 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
522 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
523 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
524
525 /* Enable/disable the Tx timestamp interrupt based on user input. */
526 regval = rd32(hw, I40E_PRTTSYN_CTL0);
527 if (pf->ptp_tx)
528 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
529 else
530 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
531 wr32(hw, I40E_PRTTSYN_CTL0, regval);
532
533 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
534 if (pf->ptp_tx)
535 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
536 else
537 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
538 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
539
540 /* Although there is no simple on/off switch for Rx, we "disable" Rx
541 * timestamps by setting to V1 only mode and clear the UDP
542 * recognition. This ought to disable all PTP Rx timestamps as V1
543 * packets are always over UDP. Note that software is configured to
544 * ignore Rx timestamps via the pf->ptp_rx flag.
545 */
546 regval = rd32(hw, I40E_PRTTSYN_CTL1);
547 /* clear everything but the enable bit */
548 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
549 /* now enable bits for desired Rx timestamps */
550 regval |= tsyntype;
551 wr32(hw, I40E_PRTTSYN_CTL1, regval);
552
553 return 0;
554}
555
556/**
557 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
558 * @pf: Board private structure
559 * @ifreq: ioctl data
560 *
561 * Respond to the user filter requests and make the appropriate hardware
562 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
563 * logic, so keep track in software of whether to indicate these timestamps
564 * or not.
565 *
566 * It is permissible to "upgrade" the user request to a broader filter, as long
567 * as the user receives the timestamps they care about and the user is notified
568 * the filter has been broadened.
569 **/
570int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
571{
572 struct hwtstamp_config config;
573 int err;
574
575 if (!(pf->flags & I40E_FLAG_PTP))
576 return -EOPNOTSUPP;
577
578 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
579 return -EFAULT;
580
581 err = i40e_ptp_set_timestamp_mode(pf, &config);
582 if (err)
583 return err;
584
585 /* save these settings for future reference */
586 pf->tstamp_config = config;
587
588 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
589 -EFAULT : 0;
590}
591
592/**
593 * i40e_ptp_create_clock - Create PTP clock device for userspace
594 * @pf: Board private structure
595 *
596 * This function creates a new PTP clock device. It only creates one if we
597 * don't already have one, so it is safe to call. Will return error if it
598 * can't create one, but success if we already have a device. Should be used
599 * by i40e_ptp_init to create clock initially, and prevent global resets from
600 * creating new clock devices.
601 **/
602static long i40e_ptp_create_clock(struct i40e_pf *pf)
603{
604 /* no need to create a clock device if we already have one */
605 if (!IS_ERR_OR_NULL(pf->ptp_clock))
606 return 0;
607
608 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name));
609 pf->ptp_caps.owner = THIS_MODULE;
610 pf->ptp_caps.max_adj = 999999999;
611 pf->ptp_caps.n_ext_ts = 0;
612 pf->ptp_caps.pps = 0;
613 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
614 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
615 pf->ptp_caps.gettime64 = i40e_ptp_gettime;
616 pf->ptp_caps.settime64 = i40e_ptp_settime;
617 pf->ptp_caps.enable = i40e_ptp_feature_enable;
618
619 /* Attempt to register the clock before enabling the hardware. */
620 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
621 if (IS_ERR(pf->ptp_clock))
622 return PTR_ERR(pf->ptp_clock);
623
624 /* clear the hwtstamp settings here during clock create, instead of
625 * during regular init, so that we can maintain settings across a
626 * reset or suspend.
627 */
628 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
629 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
630
631 return 0;
632}
633
634/**
635 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
636 * @pf: Board private structure
637 *
638 * This function sets device up for 1588 support. The first time it is run, it
639 * will create a PHC clock device. It does not create a clock device if one
640 * already exists. It also reconfigures the device after a reset.
641 **/
642void i40e_ptp_init(struct i40e_pf *pf)
643{
644 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
645 struct i40e_hw *hw = &pf->hw;
646 u32 pf_id;
647 long err;
648
649 /* Only one PF is assigned to control 1588 logic per port. Do not
650 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
651 */
652 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
653 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
654 if (hw->pf_id != pf_id) {
655 pf->flags &= ~I40E_FLAG_PTP;
656 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
657 __func__,
658 netdev->name);
659 return;
660 }
661
662 /* we have to initialize the lock first, since we can't control
663 * when the user will enter the PHC device entry points
664 */
665 spin_lock_init(&pf->tmreg_lock);
666
667 /* ensure we have a clock device */
668 err = i40e_ptp_create_clock(pf);
669 if (err) {
670 pf->ptp_clock = NULL;
671 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
672 __func__);
673 } else {
674 struct timespec64 ts;
675 u32 regval;
676
677 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
678 dev_info(&pf->pdev->dev, "PHC enabled\n");
679 pf->flags |= I40E_FLAG_PTP;
680
681 /* Ensure the clocks are running. */
682 regval = rd32(hw, I40E_PRTTSYN_CTL0);
683 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
684 wr32(hw, I40E_PRTTSYN_CTL0, regval);
685 regval = rd32(hw, I40E_PRTTSYN_CTL1);
686 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
687 wr32(hw, I40E_PRTTSYN_CTL1, regval);
688
689 /* Set the increment value per clock tick. */
690 i40e_ptp_set_increment(pf);
691
692 /* reset timestamping mode */
693 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
694
695 /* Set the clock value. */
696 ts = ktime_to_timespec64(ktime_get_real());
697 i40e_ptp_settime(&pf->ptp_caps, &ts);
698 }
699}
700
701/**
702 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
703 * @pf: Board private structure
704 *
705 * This function handles the cleanup work required from the initialization by
706 * clearing out the important information and unregistering the PHC.
707 **/
708void i40e_ptp_stop(struct i40e_pf *pf)
709{
710 pf->flags &= ~I40E_FLAG_PTP;
711 pf->ptp_tx = false;
712 pf->ptp_rx = false;
713
714 if (pf->ptp_tx_skb) {
715 dev_kfree_skb_any(pf->ptp_tx_skb);
716 pf->ptp_tx_skb = NULL;
717 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state);
718 }
719
720 if (pf->ptp_clock) {
721 ptp_clock_unregister(pf->ptp_clock);
722 pf->ptp_clock = NULL;
723 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
724 pf->vsi[pf->lan_vsi]->netdev->name);
725 }
726}
1// SPDX-License-Identifier: GPL-2.0
2/*******************************************************************************
3 *
4 * Intel Ethernet Controller XL710 Family Linux Driver
5 * Copyright(c) 2013 - 2014 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e.h"
29#include <linux/ptp_classify.h>
30
31/* The XL710 timesync is very much like Intel's 82599 design when it comes to
32 * the fundamental clock design. However, the clock operations are much simpler
33 * in the XL710 because the device supports a full 64 bits of nanoseconds.
34 * Because the field is so wide, we can forgo the cycle counter and just
35 * operate with the nanosecond field directly without fear of overflow.
36 *
37 * Much like the 82599, the update period is dependent upon the link speed:
38 * At 40Gb link or no link, the period is 1.6ns.
39 * At 10Gb link, the period is multiplied by 2. (3.2ns)
40 * At 1Gb link, the period is multiplied by 20. (32ns)
41 * 1588 functionality is not supported at 100Mbps.
42 */
43#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
44#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
45#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
46
47#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
48#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
49 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
50
51/**
52 * i40e_ptp_read - Read the PHC time from the device
53 * @pf: Board private structure
54 * @ts: timespec structure to hold the current time value
55 *
56 * This function reads the PRTTSYN_TIME registers and stores them in a
57 * timespec. However, since the registers are 64 bits of nanoseconds, we must
58 * convert the result to a timespec before we can return.
59 **/
60static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts)
61{
62 struct i40e_hw *hw = &pf->hw;
63 u32 hi, lo;
64 u64 ns;
65
66 /* The timer latches on the lowest register read. */
67 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
68 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
69
70 ns = (((u64)hi) << 32) | lo;
71
72 *ts = ns_to_timespec64(ns);
73}
74
75/**
76 * i40e_ptp_write - Write the PHC time to the device
77 * @pf: Board private structure
78 * @ts: timespec structure that holds the new time value
79 *
80 * This function writes the PRTTSYN_TIME registers with the user value. Since
81 * we receive a timespec from the stack, we must convert that timespec into
82 * nanoseconds before programming the registers.
83 **/
84static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
85{
86 struct i40e_hw *hw = &pf->hw;
87 u64 ns = timespec64_to_ns(ts);
88
89 /* The timer will not update until the high register is written, so
90 * write the low register first.
91 */
92 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
93 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
94}
95
96/**
97 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
98 * @hwtstamps: Timestamp structure to update
99 * @timestamp: Timestamp from the hardware
100 *
101 * We need to convert the NIC clock value into a hwtstamp which can be used by
102 * the upper level timestamping functions. Since the timestamp is simply a 64-
103 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
104 **/
105static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
106 u64 timestamp)
107{
108 memset(hwtstamps, 0, sizeof(*hwtstamps));
109
110 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
111}
112
113/**
114 * i40e_ptp_adjfreq - Adjust the PHC frequency
115 * @ptp: The PTP clock structure
116 * @ppb: Parts per billion adjustment from the base
117 *
118 * Adjust the frequency of the PHC by the indicated parts per billion from the
119 * base frequency.
120 **/
121static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
122{
123 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
124 struct i40e_hw *hw = &pf->hw;
125 u64 adj, freq, diff;
126 int neg_adj = 0;
127
128 if (ppb < 0) {
129 neg_adj = 1;
130 ppb = -ppb;
131 }
132
133 smp_mb(); /* Force any pending update before accessing. */
134 adj = READ_ONCE(pf->ptp_base_adj);
135
136 freq = adj;
137 freq *= ppb;
138 diff = div_u64(freq, 1000000000ULL);
139
140 if (neg_adj)
141 adj -= diff;
142 else
143 adj += diff;
144
145 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
146 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
147
148 return 0;
149}
150
151/**
152 * i40e_ptp_adjtime - Adjust the PHC time
153 * @ptp: The PTP clock structure
154 * @delta: Offset in nanoseconds to adjust the PHC time by
155 *
156 * Adjust the frequency of the PHC by the indicated parts per billion from the
157 * base frequency.
158 **/
159static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
160{
161 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
162 struct timespec64 now;
163
164 mutex_lock(&pf->tmreg_lock);
165
166 i40e_ptp_read(pf, &now);
167 timespec64_add_ns(&now, delta);
168 i40e_ptp_write(pf, (const struct timespec64 *)&now);
169
170 mutex_unlock(&pf->tmreg_lock);
171
172 return 0;
173}
174
175/**
176 * i40e_ptp_gettime - Get the time of the PHC
177 * @ptp: The PTP clock structure
178 * @ts: timespec structure to hold the current time value
179 *
180 * Read the device clock and return the correct value on ns, after converting it
181 * into a timespec struct.
182 **/
183static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
184{
185 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
186
187 mutex_lock(&pf->tmreg_lock);
188 i40e_ptp_read(pf, ts);
189 mutex_unlock(&pf->tmreg_lock);
190
191 return 0;
192}
193
194/**
195 * i40e_ptp_settime - Set the time of the PHC
196 * @ptp: The PTP clock structure
197 * @ts: timespec structure that holds the new time value
198 *
199 * Set the device clock to the user input value. The conversion from timespec
200 * to ns happens in the write function.
201 **/
202static int i40e_ptp_settime(struct ptp_clock_info *ptp,
203 const struct timespec64 *ts)
204{
205 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
206
207 mutex_lock(&pf->tmreg_lock);
208 i40e_ptp_write(pf, ts);
209 mutex_unlock(&pf->tmreg_lock);
210
211 return 0;
212}
213
214/**
215 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
216 * @ptp: The PTP clock structure
217 * @rq: The requested feature to change
218 * @on: Enable/disable flag
219 *
220 * The XL710 does not support any of the ancillary features of the PHC
221 * subsystem, so this function may just return.
222 **/
223static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
224 struct ptp_clock_request *rq, int on)
225{
226 return -EOPNOTSUPP;
227}
228
229/**
230 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events
231 * @pf: the PF data structure
232 *
233 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers
234 * for noticed latch events. This allows the driver to keep track of the first
235 * time a latch event was noticed which will be used to help clear out Rx
236 * timestamps for packets that got dropped or lost.
237 *
238 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is
239 * expected to be called only while under the ptp_rx_lock.
240 **/
241static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
242{
243 struct i40e_hw *hw = &pf->hw;
244 u32 prttsyn_stat, new_latch_events;
245 int i;
246
247 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
248 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
249
250 /* Update the jiffies time for any newly latched timestamp. This
251 * ensures that we store the time that we first discovered a timestamp
252 * was latched by the hardware. The service task will later determine
253 * if we should free the latch and drop that timestamp should too much
254 * time pass. This flow ensures that we only update jiffies for new
255 * events latched since the last time we checked, and not all events
256 * currently latched, so that the service task accounting remains
257 * accurate.
258 */
259 for (i = 0; i < 4; i++) {
260 if (new_latch_events & BIT(i))
261 pf->latch_events[i] = jiffies;
262 }
263
264 /* Finally, we store the current status of the Rx timestamp latches */
265 pf->latch_event_flags = prttsyn_stat;
266
267 return prttsyn_stat;
268}
269
270/**
271 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
272 * @pf: The PF private data structure
273 * @vsi: The VSI with the rings relevant to 1588
274 *
275 * This watchdog task is scheduled to detect error case where hardware has
276 * dropped an Rx packet that was timestamped when the ring is full. The
277 * particular error is rare but leaves the device in a state unable to timestamp
278 * any future packets.
279 **/
280void i40e_ptp_rx_hang(struct i40e_pf *pf)
281{
282 struct i40e_hw *hw = &pf->hw;
283 unsigned int i, cleared = 0;
284
285 /* Since we cannot turn off the Rx timestamp logic if the device is
286 * configured for Tx timestamping, we check if Rx timestamping is
287 * configured. We don't want to spuriously warn about Rx timestamp
288 * hangs if we don't care about the timestamps.
289 */
290 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
291 return;
292
293 spin_lock_bh(&pf->ptp_rx_lock);
294
295 /* Update current latch times for Rx events */
296 i40e_ptp_get_rx_events(pf);
297
298 /* Check all the currently latched Rx events and see whether they have
299 * been latched for over a second. It is assumed that any timestamp
300 * should have been cleared within this time, or else it was captured
301 * for a dropped frame that the driver never received. Thus, we will
302 * clear any timestamp that has been latched for over 1 second.
303 */
304 for (i = 0; i < 4; i++) {
305 if ((pf->latch_event_flags & BIT(i)) &&
306 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
307 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
308 pf->latch_event_flags &= ~BIT(i);
309 cleared++;
310 }
311 }
312
313 spin_unlock_bh(&pf->ptp_rx_lock);
314
315 /* Log a warning if more than 2 timestamps got dropped in the same
316 * check. We don't want to warn about all drops because it can occur
317 * in normal scenarios such as PTP frames on multicast addresses we
318 * aren't listening to. However, administrator should know if this is
319 * the reason packets aren't receiving timestamps.
320 */
321 if (cleared > 2)
322 dev_dbg(&pf->pdev->dev,
323 "Dropped %d missed RXTIME timestamp events\n",
324 cleared);
325
326 /* Finally, update the rx_hwtstamp_cleared counter */
327 pf->rx_hwtstamp_cleared += cleared;
328}
329
330/**
331 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung
332 * @pf: The PF private data structure
333 *
334 * This watchdog task is run periodically to make sure that we clear the Tx
335 * timestamp logic if we don't obtain a timestamp in a reasonable amount of
336 * time. It is unexpected in the normal case but if it occurs it results in
337 * permanently prevent timestamps of future packets
338 **/
339void i40e_ptp_tx_hang(struct i40e_pf *pf)
340{
341 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
342 return;
343
344 /* Nothing to do if we're not already waiting for a timestamp */
345 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
346 return;
347
348 /* We already have a handler routine which is run when we are notified
349 * of a Tx timestamp in the hardware. If we don't get an interrupt
350 * within a second it is reasonable to assume that we never will.
351 */
352 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
353 dev_kfree_skb_any(pf->ptp_tx_skb);
354 pf->ptp_tx_skb = NULL;
355 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
356 pf->tx_hwtstamp_timeouts++;
357 }
358}
359
360/**
361 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
362 * @pf: Board private structure
363 *
364 * Read the value of the Tx timestamp from the registers, convert it into a
365 * value consumable by the stack, and store that result into the shhwtstamps
366 * struct before returning it up the stack.
367 **/
368void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
369{
370 struct skb_shared_hwtstamps shhwtstamps;
371 struct sk_buff *skb = pf->ptp_tx_skb;
372 struct i40e_hw *hw = &pf->hw;
373 u32 hi, lo;
374 u64 ns;
375
376 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
377 return;
378
379 /* don't attempt to timestamp if we don't have an skb */
380 if (!pf->ptp_tx_skb)
381 return;
382
383 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
384 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
385
386 ns = (((u64)hi) << 32) | lo;
387 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
388
389 /* Clear the bit lock as soon as possible after reading the register,
390 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise
391 * applications might wake up and attempt to request another transmit
392 * timestamp prior to the bit lock being cleared.
393 */
394 pf->ptp_tx_skb = NULL;
395 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
396
397 /* Notify the stack and free the skb after we've unlocked */
398 skb_tstamp_tx(skb, &shhwtstamps);
399 dev_kfree_skb_any(skb);
400}
401
402/**
403 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
404 * @pf: Board private structure
405 * @skb: Particular skb to send timestamp with
406 * @index: Index into the receive timestamp registers for the timestamp
407 *
408 * The XL710 receives a notification in the receive descriptor with an offset
409 * into the set of RXTIME registers where the timestamp is for that skb. This
410 * function goes and fetches the receive timestamp from that offset, if a valid
411 * one exists. The RXTIME registers are in ns, so we must convert the result
412 * first.
413 **/
414void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
415{
416 u32 prttsyn_stat, hi, lo;
417 struct i40e_hw *hw;
418 u64 ns;
419
420 /* Since we cannot turn off the Rx timestamp logic if the device is
421 * doing Tx timestamping, check if Rx timestamping is configured.
422 */
423 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
424 return;
425
426 hw = &pf->hw;
427
428 spin_lock_bh(&pf->ptp_rx_lock);
429
430 /* Get current Rx events and update latch times */
431 prttsyn_stat = i40e_ptp_get_rx_events(pf);
432
433 /* TODO: Should we warn about missing Rx timestamp event? */
434 if (!(prttsyn_stat & BIT(index))) {
435 spin_unlock_bh(&pf->ptp_rx_lock);
436 return;
437 }
438
439 /* Clear the latched event since we're about to read its register */
440 pf->latch_event_flags &= ~BIT(index);
441
442 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
443 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
444
445 spin_unlock_bh(&pf->ptp_rx_lock);
446
447 ns = (((u64)hi) << 32) | lo;
448
449 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
450}
451
452/**
453 * i40e_ptp_set_increment - Utility function to update clock increment rate
454 * @pf: Board private structure
455 *
456 * During a link change, the DMA frequency that drives the 1588 logic will
457 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
458 * we must update the increment value per clock tick.
459 **/
460void i40e_ptp_set_increment(struct i40e_pf *pf)
461{
462 struct i40e_link_status *hw_link_info;
463 struct i40e_hw *hw = &pf->hw;
464 u64 incval;
465
466 hw_link_info = &hw->phy.link_info;
467
468 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
469
470 switch (hw_link_info->link_speed) {
471 case I40E_LINK_SPEED_10GB:
472 incval = I40E_PTP_10GB_INCVAL;
473 break;
474 case I40E_LINK_SPEED_1GB:
475 incval = I40E_PTP_1GB_INCVAL;
476 break;
477 case I40E_LINK_SPEED_100MB:
478 {
479 static int warn_once;
480
481 if (!warn_once) {
482 dev_warn(&pf->pdev->dev,
483 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
484 warn_once++;
485 }
486 incval = 0;
487 break;
488 }
489 case I40E_LINK_SPEED_40GB:
490 default:
491 incval = I40E_PTP_40GB_INCVAL;
492 break;
493 }
494
495 /* Write the new increment value into the increment register. The
496 * hardware will not update the clock until both registers have been
497 * written.
498 */
499 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
500 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
501
502 /* Update the base adjustement value. */
503 WRITE_ONCE(pf->ptp_base_adj, incval);
504 smp_mb(); /* Force the above update. */
505}
506
507/**
508 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
509 * @pf: Board private structure
510 * @ifreq: ioctl data
511 *
512 * Obtain the current hardware timestamping settigs as requested. To do this,
513 * keep a shadow copy of the timestamp settings rather than attempting to
514 * deconstruct it from the registers.
515 **/
516int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
517{
518 struct hwtstamp_config *config = &pf->tstamp_config;
519
520 if (!(pf->flags & I40E_FLAG_PTP))
521 return -EOPNOTSUPP;
522
523 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
524 -EFAULT : 0;
525}
526
527/**
528 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
529 * @pf: Board private structure
530 * @config: hwtstamp settings requested or saved
531 *
532 * Control hardware registers to enter the specific mode requested by the
533 * user. Also used during reset path to ensure that timestamp settings are
534 * maintained.
535 *
536 * Note: modifies config in place, and may update the requested mode to be
537 * more broad if the specific filter is not directly supported.
538 **/
539static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
540 struct hwtstamp_config *config)
541{
542 struct i40e_hw *hw = &pf->hw;
543 u32 tsyntype, regval;
544
545 /* Reserved for future extensions. */
546 if (config->flags)
547 return -EINVAL;
548
549 switch (config->tx_type) {
550 case HWTSTAMP_TX_OFF:
551 pf->ptp_tx = false;
552 break;
553 case HWTSTAMP_TX_ON:
554 pf->ptp_tx = true;
555 break;
556 default:
557 return -ERANGE;
558 }
559
560 switch (config->rx_filter) {
561 case HWTSTAMP_FILTER_NONE:
562 pf->ptp_rx = false;
563 /* We set the type to V1, but do not enable UDP packet
564 * recognition. In this way, we should be as close to
565 * disabling PTP Rx timestamps as possible since V1 packets
566 * are always UDP, since L2 packets are a V2 feature.
567 */
568 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
569 break;
570 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
571 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
572 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
573 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
574 return -ERANGE;
575 pf->ptp_rx = true;
576 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
577 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
578 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
579 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
580 break;
581 case HWTSTAMP_FILTER_PTP_V2_EVENT:
582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
583 case HWTSTAMP_FILTER_PTP_V2_SYNC:
584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
586 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
587 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
588 return -ERANGE;
589 /* fall through */
590 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
591 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
592 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
593 pf->ptp_rx = true;
594 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
595 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
596 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
597 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
598 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
599 } else {
600 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
601 }
602 break;
603 case HWTSTAMP_FILTER_NTP_ALL:
604 case HWTSTAMP_FILTER_ALL:
605 default:
606 return -ERANGE;
607 }
608
609 /* Clear out all 1588-related registers to clear and unlatch them. */
610 spin_lock_bh(&pf->ptp_rx_lock);
611 rd32(hw, I40E_PRTTSYN_STAT_0);
612 rd32(hw, I40E_PRTTSYN_TXTIME_H);
613 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
614 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
615 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
616 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
617 pf->latch_event_flags = 0;
618 spin_unlock_bh(&pf->ptp_rx_lock);
619
620 /* Enable/disable the Tx timestamp interrupt based on user input. */
621 regval = rd32(hw, I40E_PRTTSYN_CTL0);
622 if (pf->ptp_tx)
623 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
624 else
625 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
626 wr32(hw, I40E_PRTTSYN_CTL0, regval);
627
628 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
629 if (pf->ptp_tx)
630 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
631 else
632 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
633 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
634
635 /* Although there is no simple on/off switch for Rx, we "disable" Rx
636 * timestamps by setting to V1 only mode and clear the UDP
637 * recognition. This ought to disable all PTP Rx timestamps as V1
638 * packets are always over UDP. Note that software is configured to
639 * ignore Rx timestamps via the pf->ptp_rx flag.
640 */
641 regval = rd32(hw, I40E_PRTTSYN_CTL1);
642 /* clear everything but the enable bit */
643 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
644 /* now enable bits for desired Rx timestamps */
645 regval |= tsyntype;
646 wr32(hw, I40E_PRTTSYN_CTL1, regval);
647
648 return 0;
649}
650
651/**
652 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
653 * @pf: Board private structure
654 * @ifreq: ioctl data
655 *
656 * Respond to the user filter requests and make the appropriate hardware
657 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
658 * logic, so keep track in software of whether to indicate these timestamps
659 * or not.
660 *
661 * It is permissible to "upgrade" the user request to a broader filter, as long
662 * as the user receives the timestamps they care about and the user is notified
663 * the filter has been broadened.
664 **/
665int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
666{
667 struct hwtstamp_config config;
668 int err;
669
670 if (!(pf->flags & I40E_FLAG_PTP))
671 return -EOPNOTSUPP;
672
673 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
674 return -EFAULT;
675
676 err = i40e_ptp_set_timestamp_mode(pf, &config);
677 if (err)
678 return err;
679
680 /* save these settings for future reference */
681 pf->tstamp_config = config;
682
683 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
684 -EFAULT : 0;
685}
686
687/**
688 * i40e_ptp_create_clock - Create PTP clock device for userspace
689 * @pf: Board private structure
690 *
691 * This function creates a new PTP clock device. It only creates one if we
692 * don't already have one, so it is safe to call. Will return error if it
693 * can't create one, but success if we already have a device. Should be used
694 * by i40e_ptp_init to create clock initially, and prevent global resets from
695 * creating new clock devices.
696 **/
697static long i40e_ptp_create_clock(struct i40e_pf *pf)
698{
699 /* no need to create a clock device if we already have one */
700 if (!IS_ERR_OR_NULL(pf->ptp_clock))
701 return 0;
702
703 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name));
704 pf->ptp_caps.owner = THIS_MODULE;
705 pf->ptp_caps.max_adj = 999999999;
706 pf->ptp_caps.n_ext_ts = 0;
707 pf->ptp_caps.pps = 0;
708 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
709 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
710 pf->ptp_caps.gettime64 = i40e_ptp_gettime;
711 pf->ptp_caps.settime64 = i40e_ptp_settime;
712 pf->ptp_caps.enable = i40e_ptp_feature_enable;
713
714 /* Attempt to register the clock before enabling the hardware. */
715 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
716 if (IS_ERR(pf->ptp_clock))
717 return PTR_ERR(pf->ptp_clock);
718
719 /* clear the hwtstamp settings here during clock create, instead of
720 * during regular init, so that we can maintain settings across a
721 * reset or suspend.
722 */
723 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
724 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
725
726 return 0;
727}
728
729/**
730 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
731 * @pf: Board private structure
732 *
733 * This function sets device up for 1588 support. The first time it is run, it
734 * will create a PHC clock device. It does not create a clock device if one
735 * already exists. It also reconfigures the device after a reset.
736 **/
737void i40e_ptp_init(struct i40e_pf *pf)
738{
739 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
740 struct i40e_hw *hw = &pf->hw;
741 u32 pf_id;
742 long err;
743
744 /* Only one PF is assigned to control 1588 logic per port. Do not
745 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
746 */
747 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
748 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
749 if (hw->pf_id != pf_id) {
750 pf->flags &= ~I40E_FLAG_PTP;
751 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
752 __func__,
753 netdev->name);
754 return;
755 }
756
757 mutex_init(&pf->tmreg_lock);
758 spin_lock_init(&pf->ptp_rx_lock);
759
760 /* ensure we have a clock device */
761 err = i40e_ptp_create_clock(pf);
762 if (err) {
763 pf->ptp_clock = NULL;
764 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
765 __func__);
766 } else if (pf->ptp_clock) {
767 struct timespec64 ts;
768 u32 regval;
769
770 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
771 dev_info(&pf->pdev->dev, "PHC enabled\n");
772 pf->flags |= I40E_FLAG_PTP;
773
774 /* Ensure the clocks are running. */
775 regval = rd32(hw, I40E_PRTTSYN_CTL0);
776 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
777 wr32(hw, I40E_PRTTSYN_CTL0, regval);
778 regval = rd32(hw, I40E_PRTTSYN_CTL1);
779 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
780 wr32(hw, I40E_PRTTSYN_CTL1, regval);
781
782 /* Set the increment value per clock tick. */
783 i40e_ptp_set_increment(pf);
784
785 /* reset timestamping mode */
786 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
787
788 /* Set the clock value. */
789 ts = ktime_to_timespec64(ktime_get_real());
790 i40e_ptp_settime(&pf->ptp_caps, &ts);
791 }
792}
793
794/**
795 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
796 * @pf: Board private structure
797 *
798 * This function handles the cleanup work required from the initialization by
799 * clearing out the important information and unregistering the PHC.
800 **/
801void i40e_ptp_stop(struct i40e_pf *pf)
802{
803 pf->flags &= ~I40E_FLAG_PTP;
804 pf->ptp_tx = false;
805 pf->ptp_rx = false;
806
807 if (pf->ptp_tx_skb) {
808 dev_kfree_skb_any(pf->ptp_tx_skb);
809 pf->ptp_tx_skb = NULL;
810 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
811 }
812
813 if (pf->ptp_clock) {
814 ptp_clock_unregister(pf->ptp_clock);
815 pf->ptp_clock = NULL;
816 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
817 pf->vsi[pf->lan_vsi]->netdev->name);
818 }
819}