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1/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/acpi.h>
19#include <linux/cpu.h>
20#include <linux/cpu_pm.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/irqdomain.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/percpu.h>
28#include <linux/slab.h>
29
30#include <linux/irqchip.h>
31#include <linux/irqchip/arm-gic-v3.h>
32
33#include <asm/cputype.h>
34#include <asm/exception.h>
35#include <asm/smp_plat.h>
36#include <asm/virt.h>
37
38#include "irq-gic-common.h"
39
40struct redist_region {
41 void __iomem *redist_base;
42 phys_addr_t phys_base;
43 bool single_redist;
44};
45
46struct gic_chip_data {
47 void __iomem *dist_base;
48 struct redist_region *redist_regions;
49 struct rdists rdists;
50 struct irq_domain *domain;
51 u64 redist_stride;
52 u32 nr_redist_regions;
53 unsigned int irq_nr;
54};
55
56static struct gic_chip_data gic_data __read_mostly;
57static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
58
59#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
60#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
61#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
62
63/* Our default, arbitrary priority value. Linux only uses one anyway. */
64#define DEFAULT_PMR_VALUE 0xf0
65
66static inline unsigned int gic_irq(struct irq_data *d)
67{
68 return d->hwirq;
69}
70
71static inline int gic_irq_in_rdist(struct irq_data *d)
72{
73 return gic_irq(d) < 32;
74}
75
76static inline void __iomem *gic_dist_base(struct irq_data *d)
77{
78 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
79 return gic_data_rdist_sgi_base();
80
81 if (d->hwirq <= 1023) /* SPI -> dist_base */
82 return gic_data.dist_base;
83
84 return NULL;
85}
86
87static void gic_do_wait_for_rwp(void __iomem *base)
88{
89 u32 count = 1000000; /* 1s! */
90
91 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
92 count--;
93 if (!count) {
94 pr_err_ratelimited("RWP timeout, gone fishing\n");
95 return;
96 }
97 cpu_relax();
98 udelay(1);
99 };
100}
101
102/* Wait for completion of a distributor change */
103static void gic_dist_wait_for_rwp(void)
104{
105 gic_do_wait_for_rwp(gic_data.dist_base);
106}
107
108/* Wait for completion of a redistributor change */
109static void gic_redist_wait_for_rwp(void)
110{
111 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
112}
113
114#ifdef CONFIG_ARM64
115static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);
116
117static u64 __maybe_unused gic_read_iar(void)
118{
119 if (static_branch_unlikely(&is_cavium_thunderx))
120 return gic_read_iar_cavium_thunderx();
121 else
122 return gic_read_iar_common();
123}
124#endif
125
126static void gic_enable_redist(bool enable)
127{
128 void __iomem *rbase;
129 u32 count = 1000000; /* 1s! */
130 u32 val;
131
132 rbase = gic_data_rdist_rd_base();
133
134 val = readl_relaxed(rbase + GICR_WAKER);
135 if (enable)
136 /* Wake up this CPU redistributor */
137 val &= ~GICR_WAKER_ProcessorSleep;
138 else
139 val |= GICR_WAKER_ProcessorSleep;
140 writel_relaxed(val, rbase + GICR_WAKER);
141
142 if (!enable) { /* Check that GICR_WAKER is writeable */
143 val = readl_relaxed(rbase + GICR_WAKER);
144 if (!(val & GICR_WAKER_ProcessorSleep))
145 return; /* No PM support in this redistributor */
146 }
147
148 while (count--) {
149 val = readl_relaxed(rbase + GICR_WAKER);
150 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
151 break;
152 cpu_relax();
153 udelay(1);
154 };
155 if (!count)
156 pr_err_ratelimited("redistributor failed to %s...\n",
157 enable ? "wakeup" : "sleep");
158}
159
160/*
161 * Routines to disable, enable, EOI and route interrupts
162 */
163static int gic_peek_irq(struct irq_data *d, u32 offset)
164{
165 u32 mask = 1 << (gic_irq(d) % 32);
166 void __iomem *base;
167
168 if (gic_irq_in_rdist(d))
169 base = gic_data_rdist_sgi_base();
170 else
171 base = gic_data.dist_base;
172
173 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
174}
175
176static void gic_poke_irq(struct irq_data *d, u32 offset)
177{
178 u32 mask = 1 << (gic_irq(d) % 32);
179 void (*rwp_wait)(void);
180 void __iomem *base;
181
182 if (gic_irq_in_rdist(d)) {
183 base = gic_data_rdist_sgi_base();
184 rwp_wait = gic_redist_wait_for_rwp;
185 } else {
186 base = gic_data.dist_base;
187 rwp_wait = gic_dist_wait_for_rwp;
188 }
189
190 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
191 rwp_wait();
192}
193
194static void gic_mask_irq(struct irq_data *d)
195{
196 gic_poke_irq(d, GICD_ICENABLER);
197}
198
199static void gic_eoimode1_mask_irq(struct irq_data *d)
200{
201 gic_mask_irq(d);
202 /*
203 * When masking a forwarded interrupt, make sure it is
204 * deactivated as well.
205 *
206 * This ensures that an interrupt that is getting
207 * disabled/masked will not get "stuck", because there is
208 * noone to deactivate it (guest is being terminated).
209 */
210 if (irqd_is_forwarded_to_vcpu(d))
211 gic_poke_irq(d, GICD_ICACTIVER);
212}
213
214static void gic_unmask_irq(struct irq_data *d)
215{
216 gic_poke_irq(d, GICD_ISENABLER);
217}
218
219static int gic_irq_set_irqchip_state(struct irq_data *d,
220 enum irqchip_irq_state which, bool val)
221{
222 u32 reg;
223
224 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
225 return -EINVAL;
226
227 switch (which) {
228 case IRQCHIP_STATE_PENDING:
229 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
230 break;
231
232 case IRQCHIP_STATE_ACTIVE:
233 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
234 break;
235
236 case IRQCHIP_STATE_MASKED:
237 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
238 break;
239
240 default:
241 return -EINVAL;
242 }
243
244 gic_poke_irq(d, reg);
245 return 0;
246}
247
248static int gic_irq_get_irqchip_state(struct irq_data *d,
249 enum irqchip_irq_state which, bool *val)
250{
251 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
252 return -EINVAL;
253
254 switch (which) {
255 case IRQCHIP_STATE_PENDING:
256 *val = gic_peek_irq(d, GICD_ISPENDR);
257 break;
258
259 case IRQCHIP_STATE_ACTIVE:
260 *val = gic_peek_irq(d, GICD_ISACTIVER);
261 break;
262
263 case IRQCHIP_STATE_MASKED:
264 *val = !gic_peek_irq(d, GICD_ISENABLER);
265 break;
266
267 default:
268 return -EINVAL;
269 }
270
271 return 0;
272}
273
274static void gic_eoi_irq(struct irq_data *d)
275{
276 gic_write_eoir(gic_irq(d));
277}
278
279static void gic_eoimode1_eoi_irq(struct irq_data *d)
280{
281 /*
282 * No need to deactivate an LPI, or an interrupt that
283 * is is getting forwarded to a vcpu.
284 */
285 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
286 return;
287 gic_write_dir(gic_irq(d));
288}
289
290static int gic_set_type(struct irq_data *d, unsigned int type)
291{
292 unsigned int irq = gic_irq(d);
293 void (*rwp_wait)(void);
294 void __iomem *base;
295
296 /* Interrupt configuration for SGIs can't be changed */
297 if (irq < 16)
298 return -EINVAL;
299
300 /* SPIs have restrictions on the supported types */
301 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
302 type != IRQ_TYPE_EDGE_RISING)
303 return -EINVAL;
304
305 if (gic_irq_in_rdist(d)) {
306 base = gic_data_rdist_sgi_base();
307 rwp_wait = gic_redist_wait_for_rwp;
308 } else {
309 base = gic_data.dist_base;
310 rwp_wait = gic_dist_wait_for_rwp;
311 }
312
313 return gic_configure_irq(irq, type, base, rwp_wait);
314}
315
316static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
317{
318 if (vcpu)
319 irqd_set_forwarded_to_vcpu(d);
320 else
321 irqd_clr_forwarded_to_vcpu(d);
322 return 0;
323}
324
325static u64 gic_mpidr_to_affinity(unsigned long mpidr)
326{
327 u64 aff;
328
329 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
330 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
331 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
332 MPIDR_AFFINITY_LEVEL(mpidr, 0));
333
334 return aff;
335}
336
337static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
338{
339 u32 irqnr;
340
341 do {
342 irqnr = gic_read_iar();
343
344 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
345 int err;
346
347 if (static_key_true(&supports_deactivate))
348 gic_write_eoir(irqnr);
349
350 err = handle_domain_irq(gic_data.domain, irqnr, regs);
351 if (err) {
352 WARN_ONCE(true, "Unexpected interrupt received!\n");
353 if (static_key_true(&supports_deactivate)) {
354 if (irqnr < 8192)
355 gic_write_dir(irqnr);
356 } else {
357 gic_write_eoir(irqnr);
358 }
359 }
360 continue;
361 }
362 if (irqnr < 16) {
363 gic_write_eoir(irqnr);
364 if (static_key_true(&supports_deactivate))
365 gic_write_dir(irqnr);
366#ifdef CONFIG_SMP
367 handle_IPI(irqnr, regs);
368#else
369 WARN_ONCE(true, "Unexpected SGI received!\n");
370#endif
371 continue;
372 }
373 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
374}
375
376static void __init gic_dist_init(void)
377{
378 unsigned int i;
379 u64 affinity;
380 void __iomem *base = gic_data.dist_base;
381
382 /* Disable the distributor */
383 writel_relaxed(0, base + GICD_CTLR);
384 gic_dist_wait_for_rwp();
385
386 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
387
388 /* Enable distributor with ARE, Group1 */
389 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
390 base + GICD_CTLR);
391
392 /*
393 * Set all global interrupts to the boot CPU only. ARE must be
394 * enabled.
395 */
396 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
397 for (i = 32; i < gic_data.irq_nr; i++)
398 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
399}
400
401static int gic_populate_rdist(void)
402{
403 unsigned long mpidr = cpu_logical_map(smp_processor_id());
404 u64 typer;
405 u32 aff;
406 int i;
407
408 /*
409 * Convert affinity to a 32bit value that can be matched to
410 * GICR_TYPER bits [63:32].
411 */
412 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
413 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
414 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
415 MPIDR_AFFINITY_LEVEL(mpidr, 0));
416
417 for (i = 0; i < gic_data.nr_redist_regions; i++) {
418 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
419 u32 reg;
420
421 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
422 if (reg != GIC_PIDR2_ARCH_GICv3 &&
423 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
424 pr_warn("No redistributor present @%p\n", ptr);
425 break;
426 }
427
428 do {
429 typer = gic_read_typer(ptr + GICR_TYPER);
430 if ((typer >> 32) == aff) {
431 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
432 gic_data_rdist_rd_base() = ptr;
433 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
434 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
435 smp_processor_id(), mpidr, i,
436 &gic_data_rdist()->phys_base);
437 return 0;
438 }
439
440 if (gic_data.redist_regions[i].single_redist)
441 break;
442
443 if (gic_data.redist_stride) {
444 ptr += gic_data.redist_stride;
445 } else {
446 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
447 if (typer & GICR_TYPER_VLPIS)
448 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
449 }
450 } while (!(typer & GICR_TYPER_LAST));
451 }
452
453 /* We couldn't even deal with ourselves... */
454 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
455 smp_processor_id(), mpidr);
456 return -ENODEV;
457}
458
459static void gic_cpu_sys_reg_init(void)
460{
461 /*
462 * Need to check that the SRE bit has actually been set. If
463 * not, it means that SRE is disabled at EL2. We're going to
464 * die painfully, and there is nothing we can do about it.
465 *
466 * Kindly inform the luser.
467 */
468 if (!gic_enable_sre())
469 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
470
471 /* Set priority mask register */
472 gic_write_pmr(DEFAULT_PMR_VALUE);
473
474 if (static_key_true(&supports_deactivate)) {
475 /* EOI drops priority only (mode 1) */
476 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
477 } else {
478 /* EOI deactivates interrupt too (mode 0) */
479 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
480 }
481
482 /* ... and let's hit the road... */
483 gic_write_grpen1(1);
484}
485
486static int gic_dist_supports_lpis(void)
487{
488 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
489}
490
491static void gic_cpu_init(void)
492{
493 void __iomem *rbase;
494
495 /* Register ourselves with the rest of the world */
496 if (gic_populate_rdist())
497 return;
498
499 gic_enable_redist(true);
500
501 rbase = gic_data_rdist_sgi_base();
502
503 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
504
505 /* Give LPIs a spin */
506 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
507 its_cpu_init();
508
509 /* initialise system registers */
510 gic_cpu_sys_reg_init();
511}
512
513#ifdef CONFIG_SMP
514static int gic_secondary_init(struct notifier_block *nfb,
515 unsigned long action, void *hcpu)
516{
517 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
518 gic_cpu_init();
519 return NOTIFY_OK;
520}
521
522/*
523 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
524 * priority because the GIC needs to be up before the ARM generic timers.
525 */
526static struct notifier_block gic_cpu_notifier = {
527 .notifier_call = gic_secondary_init,
528 .priority = 100,
529};
530
531static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
532 unsigned long cluster_id)
533{
534 int cpu = *base_cpu;
535 unsigned long mpidr = cpu_logical_map(cpu);
536 u16 tlist = 0;
537
538 while (cpu < nr_cpu_ids) {
539 /*
540 * If we ever get a cluster of more than 16 CPUs, just
541 * scream and skip that CPU.
542 */
543 if (WARN_ON((mpidr & 0xff) >= 16))
544 goto out;
545
546 tlist |= 1 << (mpidr & 0xf);
547
548 cpu = cpumask_next(cpu, mask);
549 if (cpu >= nr_cpu_ids)
550 goto out;
551
552 mpidr = cpu_logical_map(cpu);
553
554 if (cluster_id != (mpidr & ~0xffUL)) {
555 cpu--;
556 goto out;
557 }
558 }
559out:
560 *base_cpu = cpu;
561 return tlist;
562}
563
564#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
565 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
566 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
567
568static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
569{
570 u64 val;
571
572 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
573 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
574 irq << ICC_SGI1R_SGI_ID_SHIFT |
575 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
576 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
577
578 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
579 gic_write_sgi1r(val);
580}
581
582static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
583{
584 int cpu;
585
586 if (WARN_ON(irq >= 16))
587 return;
588
589 /*
590 * Ensure that stores to Normal memory are visible to the
591 * other CPUs before issuing the IPI.
592 */
593 smp_wmb();
594
595 for_each_cpu(cpu, mask) {
596 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL;
597 u16 tlist;
598
599 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
600 gic_send_sgi(cluster_id, tlist, irq);
601 }
602
603 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
604 isb();
605}
606
607static void gic_smp_init(void)
608{
609 set_smp_cross_call(gic_raise_softirq);
610 register_cpu_notifier(&gic_cpu_notifier);
611}
612
613static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
614 bool force)
615{
616 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
617 void __iomem *reg;
618 int enabled;
619 u64 val;
620
621 if (gic_irq_in_rdist(d))
622 return -EINVAL;
623
624 /* If interrupt was enabled, disable it first */
625 enabled = gic_peek_irq(d, GICD_ISENABLER);
626 if (enabled)
627 gic_mask_irq(d);
628
629 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
630 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
631
632 gic_write_irouter(val, reg);
633
634 /*
635 * If the interrupt was enabled, enabled it again. Otherwise,
636 * just wait for the distributor to have digested our changes.
637 */
638 if (enabled)
639 gic_unmask_irq(d);
640 else
641 gic_dist_wait_for_rwp();
642
643 return IRQ_SET_MASK_OK_DONE;
644}
645#else
646#define gic_set_affinity NULL
647#define gic_smp_init() do { } while(0)
648#endif
649
650#ifdef CONFIG_CPU_PM
651static int gic_cpu_pm_notifier(struct notifier_block *self,
652 unsigned long cmd, void *v)
653{
654 if (cmd == CPU_PM_EXIT) {
655 gic_enable_redist(true);
656 gic_cpu_sys_reg_init();
657 } else if (cmd == CPU_PM_ENTER) {
658 gic_write_grpen1(0);
659 gic_enable_redist(false);
660 }
661 return NOTIFY_OK;
662}
663
664static struct notifier_block gic_cpu_pm_notifier_block = {
665 .notifier_call = gic_cpu_pm_notifier,
666};
667
668static void gic_cpu_pm_init(void)
669{
670 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
671}
672
673#else
674static inline void gic_cpu_pm_init(void) { }
675#endif /* CONFIG_CPU_PM */
676
677static struct irq_chip gic_chip = {
678 .name = "GICv3",
679 .irq_mask = gic_mask_irq,
680 .irq_unmask = gic_unmask_irq,
681 .irq_eoi = gic_eoi_irq,
682 .irq_set_type = gic_set_type,
683 .irq_set_affinity = gic_set_affinity,
684 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
685 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
686 .flags = IRQCHIP_SET_TYPE_MASKED,
687};
688
689static struct irq_chip gic_eoimode1_chip = {
690 .name = "GICv3",
691 .irq_mask = gic_eoimode1_mask_irq,
692 .irq_unmask = gic_unmask_irq,
693 .irq_eoi = gic_eoimode1_eoi_irq,
694 .irq_set_type = gic_set_type,
695 .irq_set_affinity = gic_set_affinity,
696 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
697 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
698 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
699 .flags = IRQCHIP_SET_TYPE_MASKED,
700};
701
702#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
703
704static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
705 irq_hw_number_t hw)
706{
707 struct irq_chip *chip = &gic_chip;
708
709 if (static_key_true(&supports_deactivate))
710 chip = &gic_eoimode1_chip;
711
712 /* SGIs are private to the core kernel */
713 if (hw < 16)
714 return -EPERM;
715 /* Nothing here */
716 if (hw >= gic_data.irq_nr && hw < 8192)
717 return -EPERM;
718 /* Off limits */
719 if (hw >= GIC_ID_NR)
720 return -EPERM;
721
722 /* PPIs */
723 if (hw < 32) {
724 irq_set_percpu_devid(irq);
725 irq_domain_set_info(d, irq, hw, chip, d->host_data,
726 handle_percpu_devid_irq, NULL, NULL);
727 irq_set_status_flags(irq, IRQ_NOAUTOEN);
728 }
729 /* SPIs */
730 if (hw >= 32 && hw < gic_data.irq_nr) {
731 irq_domain_set_info(d, irq, hw, chip, d->host_data,
732 handle_fasteoi_irq, NULL, NULL);
733 irq_set_probe(irq);
734 }
735 /* LPIs */
736 if (hw >= 8192 && hw < GIC_ID_NR) {
737 if (!gic_dist_supports_lpis())
738 return -EPERM;
739 irq_domain_set_info(d, irq, hw, chip, d->host_data,
740 handle_fasteoi_irq, NULL, NULL);
741 }
742
743 return 0;
744}
745
746static int gic_irq_domain_translate(struct irq_domain *d,
747 struct irq_fwspec *fwspec,
748 unsigned long *hwirq,
749 unsigned int *type)
750{
751 if (is_of_node(fwspec->fwnode)) {
752 if (fwspec->param_count < 3)
753 return -EINVAL;
754
755 switch (fwspec->param[0]) {
756 case 0: /* SPI */
757 *hwirq = fwspec->param[1] + 32;
758 break;
759 case 1: /* PPI */
760 *hwirq = fwspec->param[1] + 16;
761 break;
762 case GIC_IRQ_TYPE_LPI: /* LPI */
763 *hwirq = fwspec->param[1];
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
770 return 0;
771 }
772
773 if (is_fwnode_irqchip(fwspec->fwnode)) {
774 if(fwspec->param_count != 2)
775 return -EINVAL;
776
777 *hwirq = fwspec->param[0];
778 *type = fwspec->param[1];
779 return 0;
780 }
781
782 return -EINVAL;
783}
784
785static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
786 unsigned int nr_irqs, void *arg)
787{
788 int i, ret;
789 irq_hw_number_t hwirq;
790 unsigned int type = IRQ_TYPE_NONE;
791 struct irq_fwspec *fwspec = arg;
792
793 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
794 if (ret)
795 return ret;
796
797 for (i = 0; i < nr_irqs; i++)
798 gic_irq_domain_map(domain, virq + i, hwirq + i);
799
800 return 0;
801}
802
803static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
804 unsigned int nr_irqs)
805{
806 int i;
807
808 for (i = 0; i < nr_irqs; i++) {
809 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
810 irq_set_handler(virq + i, NULL);
811 irq_domain_reset_irq_data(d);
812 }
813}
814
815static const struct irq_domain_ops gic_irq_domain_ops = {
816 .translate = gic_irq_domain_translate,
817 .alloc = gic_irq_domain_alloc,
818 .free = gic_irq_domain_free,
819};
820
821static void gicv3_enable_quirks(void)
822{
823#ifdef CONFIG_ARM64
824 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))
825 static_branch_enable(&is_cavium_thunderx);
826#endif
827}
828
829static int __init gic_init_bases(void __iomem *dist_base,
830 struct redist_region *rdist_regs,
831 u32 nr_redist_regions,
832 u64 redist_stride,
833 struct fwnode_handle *handle)
834{
835 struct device_node *node;
836 u32 typer;
837 int gic_irqs;
838 int err;
839
840 if (!is_hyp_mode_available())
841 static_key_slow_dec(&supports_deactivate);
842
843 if (static_key_true(&supports_deactivate))
844 pr_info("GIC: Using split EOI/Deactivate mode\n");
845
846 gic_data.dist_base = dist_base;
847 gic_data.redist_regions = rdist_regs;
848 gic_data.nr_redist_regions = nr_redist_regions;
849 gic_data.redist_stride = redist_stride;
850
851 gicv3_enable_quirks();
852
853 /*
854 * Find out how many interrupts are supported.
855 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
856 */
857 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
858 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
859 gic_irqs = GICD_TYPER_IRQS(typer);
860 if (gic_irqs > 1020)
861 gic_irqs = 1020;
862 gic_data.irq_nr = gic_irqs;
863
864 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
865 &gic_data);
866 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
867
868 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
869 err = -ENOMEM;
870 goto out_free;
871 }
872
873 set_handle_irq(gic_handle_irq);
874
875 node = to_of_node(handle);
876 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
877 node) /* Temp hack to prevent ITS init for ACPI */
878 its_init(node, &gic_data.rdists, gic_data.domain);
879
880 gic_smp_init();
881 gic_dist_init();
882 gic_cpu_init();
883 gic_cpu_pm_init();
884
885 return 0;
886
887out_free:
888 if (gic_data.domain)
889 irq_domain_remove(gic_data.domain);
890 free_percpu(gic_data.rdists.rdist);
891 return err;
892}
893
894static int __init gic_validate_dist_version(void __iomem *dist_base)
895{
896 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
897
898 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
899 return -ENODEV;
900
901 return 0;
902}
903
904static int __init gic_of_init(struct device_node *node, struct device_node *parent)
905{
906 void __iomem *dist_base;
907 struct redist_region *rdist_regs;
908 u64 redist_stride;
909 u32 nr_redist_regions;
910 int err, i;
911
912 dist_base = of_iomap(node, 0);
913 if (!dist_base) {
914 pr_err("%s: unable to map gic dist registers\n",
915 node->full_name);
916 return -ENXIO;
917 }
918
919 err = gic_validate_dist_version(dist_base);
920 if (err) {
921 pr_err("%s: no distributor detected, giving up\n",
922 node->full_name);
923 goto out_unmap_dist;
924 }
925
926 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
927 nr_redist_regions = 1;
928
929 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
930 if (!rdist_regs) {
931 err = -ENOMEM;
932 goto out_unmap_dist;
933 }
934
935 for (i = 0; i < nr_redist_regions; i++) {
936 struct resource res;
937 int ret;
938
939 ret = of_address_to_resource(node, 1 + i, &res);
940 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
941 if (ret || !rdist_regs[i].redist_base) {
942 pr_err("%s: couldn't map region %d\n",
943 node->full_name, i);
944 err = -ENODEV;
945 goto out_unmap_rdist;
946 }
947 rdist_regs[i].phys_base = res.start;
948 }
949
950 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
951 redist_stride = 0;
952
953 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
954 redist_stride, &node->fwnode);
955 if (!err)
956 return 0;
957
958out_unmap_rdist:
959 for (i = 0; i < nr_redist_regions; i++)
960 if (rdist_regs[i].redist_base)
961 iounmap(rdist_regs[i].redist_base);
962 kfree(rdist_regs);
963out_unmap_dist:
964 iounmap(dist_base);
965 return err;
966}
967
968IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
969
970#ifdef CONFIG_ACPI
971static void __iomem *dist_base;
972static struct redist_region *redist_regs __initdata;
973static u32 nr_redist_regions __initdata;
974static bool single_redist;
975
976static void __init
977gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
978{
979 static int count = 0;
980
981 redist_regs[count].phys_base = phys_base;
982 redist_regs[count].redist_base = redist_base;
983 redist_regs[count].single_redist = single_redist;
984 count++;
985}
986
987static int __init
988gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
989 const unsigned long end)
990{
991 struct acpi_madt_generic_redistributor *redist =
992 (struct acpi_madt_generic_redistributor *)header;
993 void __iomem *redist_base;
994
995 redist_base = ioremap(redist->base_address, redist->length);
996 if (!redist_base) {
997 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
998 return -ENOMEM;
999 }
1000
1001 gic_acpi_register_redist(redist->base_address, redist_base);
1002 return 0;
1003}
1004
1005static int __init
1006gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1007 const unsigned long end)
1008{
1009 struct acpi_madt_generic_interrupt *gicc =
1010 (struct acpi_madt_generic_interrupt *)header;
1011 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1012 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1013 void __iomem *redist_base;
1014
1015 redist_base = ioremap(gicc->gicr_base_address, size);
1016 if (!redist_base)
1017 return -ENOMEM;
1018
1019 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1020 return 0;
1021}
1022
1023static int __init gic_acpi_collect_gicr_base(void)
1024{
1025 acpi_tbl_entry_handler redist_parser;
1026 enum acpi_madt_type type;
1027
1028 if (single_redist) {
1029 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1030 redist_parser = gic_acpi_parse_madt_gicc;
1031 } else {
1032 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1033 redist_parser = gic_acpi_parse_madt_redist;
1034 }
1035
1036 /* Collect redistributor base addresses in GICR entries */
1037 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1038 return 0;
1039
1040 pr_info("No valid GICR entries exist\n");
1041 return -ENODEV;
1042}
1043
1044static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1045 const unsigned long end)
1046{
1047 /* Subtable presence means that redist exists, that's it */
1048 return 0;
1049}
1050
1051static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1052 const unsigned long end)
1053{
1054 struct acpi_madt_generic_interrupt *gicc =
1055 (struct acpi_madt_generic_interrupt *)header;
1056
1057 /*
1058 * If GICC is enabled and has valid gicr base address, then it means
1059 * GICR base is presented via GICC
1060 */
1061 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1062 return 0;
1063
1064 return -ENODEV;
1065}
1066
1067static int __init gic_acpi_count_gicr_regions(void)
1068{
1069 int count;
1070
1071 /*
1072 * Count how many redistributor regions we have. It is not allowed
1073 * to mix redistributor description, GICR and GICC subtables have to be
1074 * mutually exclusive.
1075 */
1076 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1077 gic_acpi_match_gicr, 0);
1078 if (count > 0) {
1079 single_redist = false;
1080 return count;
1081 }
1082
1083 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1084 gic_acpi_match_gicc, 0);
1085 if (count > 0)
1086 single_redist = true;
1087
1088 return count;
1089}
1090
1091static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1092 struct acpi_probe_entry *ape)
1093{
1094 struct acpi_madt_generic_distributor *dist;
1095 int count;
1096
1097 dist = (struct acpi_madt_generic_distributor *)header;
1098 if (dist->version != ape->driver_data)
1099 return false;
1100
1101 /* We need to do that exercise anyway, the sooner the better */
1102 count = gic_acpi_count_gicr_regions();
1103 if (count <= 0)
1104 return false;
1105
1106 nr_redist_regions = count;
1107 return true;
1108}
1109
1110#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1111
1112static int __init
1113gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1114{
1115 struct acpi_madt_generic_distributor *dist;
1116 struct fwnode_handle *domain_handle;
1117 int i, err;
1118
1119 /* Get distributor base address */
1120 dist = (struct acpi_madt_generic_distributor *)header;
1121 dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE);
1122 if (!dist_base) {
1123 pr_err("Unable to map GICD registers\n");
1124 return -ENOMEM;
1125 }
1126
1127 err = gic_validate_dist_version(dist_base);
1128 if (err) {
1129 pr_err("No distributor detected at @%p, giving up", dist_base);
1130 goto out_dist_unmap;
1131 }
1132
1133 redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions,
1134 GFP_KERNEL);
1135 if (!redist_regs) {
1136 err = -ENOMEM;
1137 goto out_dist_unmap;
1138 }
1139
1140 err = gic_acpi_collect_gicr_base();
1141 if (err)
1142 goto out_redist_unmap;
1143
1144 domain_handle = irq_domain_alloc_fwnode(dist_base);
1145 if (!domain_handle) {
1146 err = -ENOMEM;
1147 goto out_redist_unmap;
1148 }
1149
1150 err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
1151 domain_handle);
1152 if (err)
1153 goto out_fwhandle_free;
1154
1155 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1156 return 0;
1157
1158out_fwhandle_free:
1159 irq_domain_free_fwnode(domain_handle);
1160out_redist_unmap:
1161 for (i = 0; i < nr_redist_regions; i++)
1162 if (redist_regs[i].redist_base)
1163 iounmap(redist_regs[i].redist_base);
1164 kfree(redist_regs);
1165out_dist_unmap:
1166 iounmap(dist_base);
1167 return err;
1168}
1169IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1170 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1171 gic_acpi_init);
1172IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1173 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1174 gic_acpi_init);
1175IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1176 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
1177 gic_acpi_init);
1178#endif
1/*
2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#define pr_fmt(fmt) "GICv3: " fmt
19
20#include <linux/acpi.h>
21#include <linux/cpu.h>
22#include <linux/cpu_pm.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/irqdomain.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/percpu.h>
30#include <linux/slab.h>
31
32#include <linux/irqchip.h>
33#include <linux/irqchip/arm-gic-common.h>
34#include <linux/irqchip/arm-gic-v3.h>
35#include <linux/irqchip/irq-partition-percpu.h>
36
37#include <asm/cputype.h>
38#include <asm/exception.h>
39#include <asm/smp_plat.h>
40#include <asm/virt.h>
41
42#include "irq-gic-common.h"
43
44struct redist_region {
45 void __iomem *redist_base;
46 phys_addr_t phys_base;
47 bool single_redist;
48};
49
50struct gic_chip_data {
51 struct fwnode_handle *fwnode;
52 void __iomem *dist_base;
53 struct redist_region *redist_regions;
54 struct rdists rdists;
55 struct irq_domain *domain;
56 u64 redist_stride;
57 u32 nr_redist_regions;
58 bool has_rss;
59 unsigned int irq_nr;
60 struct partition_desc *ppi_descs[16];
61};
62
63static struct gic_chip_data gic_data __read_mostly;
64static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
65
66static struct gic_kvm_info gic_v3_kvm_info;
67static DEFINE_PER_CPU(bool, has_rss);
68
69#define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
70#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
71#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
72#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
73
74/* Our default, arbitrary priority value. Linux only uses one anyway. */
75#define DEFAULT_PMR_VALUE 0xf0
76
77static inline unsigned int gic_irq(struct irq_data *d)
78{
79 return d->hwirq;
80}
81
82static inline int gic_irq_in_rdist(struct irq_data *d)
83{
84 return gic_irq(d) < 32;
85}
86
87static inline void __iomem *gic_dist_base(struct irq_data *d)
88{
89 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
90 return gic_data_rdist_sgi_base();
91
92 if (d->hwirq <= 1023) /* SPI -> dist_base */
93 return gic_data.dist_base;
94
95 return NULL;
96}
97
98static void gic_do_wait_for_rwp(void __iomem *base)
99{
100 u32 count = 1000000; /* 1s! */
101
102 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
103 count--;
104 if (!count) {
105 pr_err_ratelimited("RWP timeout, gone fishing\n");
106 return;
107 }
108 cpu_relax();
109 udelay(1);
110 };
111}
112
113/* Wait for completion of a distributor change */
114static void gic_dist_wait_for_rwp(void)
115{
116 gic_do_wait_for_rwp(gic_data.dist_base);
117}
118
119/* Wait for completion of a redistributor change */
120static void gic_redist_wait_for_rwp(void)
121{
122 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
123}
124
125#ifdef CONFIG_ARM64
126
127static u64 __maybe_unused gic_read_iar(void)
128{
129 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
130 return gic_read_iar_cavium_thunderx();
131 else
132 return gic_read_iar_common();
133}
134#endif
135
136static void gic_enable_redist(bool enable)
137{
138 void __iomem *rbase;
139 u32 count = 1000000; /* 1s! */
140 u32 val;
141
142 rbase = gic_data_rdist_rd_base();
143
144 val = readl_relaxed(rbase + GICR_WAKER);
145 if (enable)
146 /* Wake up this CPU redistributor */
147 val &= ~GICR_WAKER_ProcessorSleep;
148 else
149 val |= GICR_WAKER_ProcessorSleep;
150 writel_relaxed(val, rbase + GICR_WAKER);
151
152 if (!enable) { /* Check that GICR_WAKER is writeable */
153 val = readl_relaxed(rbase + GICR_WAKER);
154 if (!(val & GICR_WAKER_ProcessorSleep))
155 return; /* No PM support in this redistributor */
156 }
157
158 while (--count) {
159 val = readl_relaxed(rbase + GICR_WAKER);
160 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
161 break;
162 cpu_relax();
163 udelay(1);
164 };
165 if (!count)
166 pr_err_ratelimited("redistributor failed to %s...\n",
167 enable ? "wakeup" : "sleep");
168}
169
170/*
171 * Routines to disable, enable, EOI and route interrupts
172 */
173static int gic_peek_irq(struct irq_data *d, u32 offset)
174{
175 u32 mask = 1 << (gic_irq(d) % 32);
176 void __iomem *base;
177
178 if (gic_irq_in_rdist(d))
179 base = gic_data_rdist_sgi_base();
180 else
181 base = gic_data.dist_base;
182
183 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
184}
185
186static void gic_poke_irq(struct irq_data *d, u32 offset)
187{
188 u32 mask = 1 << (gic_irq(d) % 32);
189 void (*rwp_wait)(void);
190 void __iomem *base;
191
192 if (gic_irq_in_rdist(d)) {
193 base = gic_data_rdist_sgi_base();
194 rwp_wait = gic_redist_wait_for_rwp;
195 } else {
196 base = gic_data.dist_base;
197 rwp_wait = gic_dist_wait_for_rwp;
198 }
199
200 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
201 rwp_wait();
202}
203
204static void gic_mask_irq(struct irq_data *d)
205{
206 gic_poke_irq(d, GICD_ICENABLER);
207}
208
209static void gic_eoimode1_mask_irq(struct irq_data *d)
210{
211 gic_mask_irq(d);
212 /*
213 * When masking a forwarded interrupt, make sure it is
214 * deactivated as well.
215 *
216 * This ensures that an interrupt that is getting
217 * disabled/masked will not get "stuck", because there is
218 * noone to deactivate it (guest is being terminated).
219 */
220 if (irqd_is_forwarded_to_vcpu(d))
221 gic_poke_irq(d, GICD_ICACTIVER);
222}
223
224static void gic_unmask_irq(struct irq_data *d)
225{
226 gic_poke_irq(d, GICD_ISENABLER);
227}
228
229static int gic_irq_set_irqchip_state(struct irq_data *d,
230 enum irqchip_irq_state which, bool val)
231{
232 u32 reg;
233
234 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
235 return -EINVAL;
236
237 switch (which) {
238 case IRQCHIP_STATE_PENDING:
239 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
240 break;
241
242 case IRQCHIP_STATE_ACTIVE:
243 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
244 break;
245
246 case IRQCHIP_STATE_MASKED:
247 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
248 break;
249
250 default:
251 return -EINVAL;
252 }
253
254 gic_poke_irq(d, reg);
255 return 0;
256}
257
258static int gic_irq_get_irqchip_state(struct irq_data *d,
259 enum irqchip_irq_state which, bool *val)
260{
261 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
262 return -EINVAL;
263
264 switch (which) {
265 case IRQCHIP_STATE_PENDING:
266 *val = gic_peek_irq(d, GICD_ISPENDR);
267 break;
268
269 case IRQCHIP_STATE_ACTIVE:
270 *val = gic_peek_irq(d, GICD_ISACTIVER);
271 break;
272
273 case IRQCHIP_STATE_MASKED:
274 *val = !gic_peek_irq(d, GICD_ISENABLER);
275 break;
276
277 default:
278 return -EINVAL;
279 }
280
281 return 0;
282}
283
284static void gic_eoi_irq(struct irq_data *d)
285{
286 gic_write_eoir(gic_irq(d));
287}
288
289static void gic_eoimode1_eoi_irq(struct irq_data *d)
290{
291 /*
292 * No need to deactivate an LPI, or an interrupt that
293 * is is getting forwarded to a vcpu.
294 */
295 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
296 return;
297 gic_write_dir(gic_irq(d));
298}
299
300static int gic_set_type(struct irq_data *d, unsigned int type)
301{
302 unsigned int irq = gic_irq(d);
303 void (*rwp_wait)(void);
304 void __iomem *base;
305
306 /* Interrupt configuration for SGIs can't be changed */
307 if (irq < 16)
308 return -EINVAL;
309
310 /* SPIs have restrictions on the supported types */
311 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
312 type != IRQ_TYPE_EDGE_RISING)
313 return -EINVAL;
314
315 if (gic_irq_in_rdist(d)) {
316 base = gic_data_rdist_sgi_base();
317 rwp_wait = gic_redist_wait_for_rwp;
318 } else {
319 base = gic_data.dist_base;
320 rwp_wait = gic_dist_wait_for_rwp;
321 }
322
323 return gic_configure_irq(irq, type, base, rwp_wait);
324}
325
326static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
327{
328 if (vcpu)
329 irqd_set_forwarded_to_vcpu(d);
330 else
331 irqd_clr_forwarded_to_vcpu(d);
332 return 0;
333}
334
335static u64 gic_mpidr_to_affinity(unsigned long mpidr)
336{
337 u64 aff;
338
339 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
340 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
341 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
342 MPIDR_AFFINITY_LEVEL(mpidr, 0));
343
344 return aff;
345}
346
347static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
348{
349 u32 irqnr;
350
351 do {
352 irqnr = gic_read_iar();
353
354 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
355 int err;
356
357 if (static_branch_likely(&supports_deactivate_key))
358 gic_write_eoir(irqnr);
359 else
360 isb();
361
362 err = handle_domain_irq(gic_data.domain, irqnr, regs);
363 if (err) {
364 WARN_ONCE(true, "Unexpected interrupt received!\n");
365 if (static_branch_likely(&supports_deactivate_key)) {
366 if (irqnr < 8192)
367 gic_write_dir(irqnr);
368 } else {
369 gic_write_eoir(irqnr);
370 }
371 }
372 continue;
373 }
374 if (irqnr < 16) {
375 gic_write_eoir(irqnr);
376 if (static_branch_likely(&supports_deactivate_key))
377 gic_write_dir(irqnr);
378#ifdef CONFIG_SMP
379 /*
380 * Unlike GICv2, we don't need an smp_rmb() here.
381 * The control dependency from gic_read_iar to
382 * the ISB in gic_write_eoir is enough to ensure
383 * that any shared data read by handle_IPI will
384 * be read after the ACK.
385 */
386 handle_IPI(irqnr, regs);
387#else
388 WARN_ONCE(true, "Unexpected SGI received!\n");
389#endif
390 continue;
391 }
392 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
393}
394
395static void __init gic_dist_init(void)
396{
397 unsigned int i;
398 u64 affinity;
399 void __iomem *base = gic_data.dist_base;
400
401 /* Disable the distributor */
402 writel_relaxed(0, base + GICD_CTLR);
403 gic_dist_wait_for_rwp();
404
405 /*
406 * Configure SPIs as non-secure Group-1. This will only matter
407 * if the GIC only has a single security state. This will not
408 * do the right thing if the kernel is running in secure mode,
409 * but that's not the intended use case anyway.
410 */
411 for (i = 32; i < gic_data.irq_nr; i += 32)
412 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
413
414 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
415
416 /* Enable distributor with ARE, Group1 */
417 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
418 base + GICD_CTLR);
419
420 /*
421 * Set all global interrupts to the boot CPU only. ARE must be
422 * enabled.
423 */
424 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
425 for (i = 32; i < gic_data.irq_nr; i++)
426 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
427}
428
429static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
430{
431 int ret = -ENODEV;
432 int i;
433
434 for (i = 0; i < gic_data.nr_redist_regions; i++) {
435 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
436 u64 typer;
437 u32 reg;
438
439 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
440 if (reg != GIC_PIDR2_ARCH_GICv3 &&
441 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
442 pr_warn("No redistributor present @%p\n", ptr);
443 break;
444 }
445
446 do {
447 typer = gic_read_typer(ptr + GICR_TYPER);
448 ret = fn(gic_data.redist_regions + i, ptr);
449 if (!ret)
450 return 0;
451
452 if (gic_data.redist_regions[i].single_redist)
453 break;
454
455 if (gic_data.redist_stride) {
456 ptr += gic_data.redist_stride;
457 } else {
458 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
459 if (typer & GICR_TYPER_VLPIS)
460 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
461 }
462 } while (!(typer & GICR_TYPER_LAST));
463 }
464
465 return ret ? -ENODEV : 0;
466}
467
468static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
469{
470 unsigned long mpidr = cpu_logical_map(smp_processor_id());
471 u64 typer;
472 u32 aff;
473
474 /*
475 * Convert affinity to a 32bit value that can be matched to
476 * GICR_TYPER bits [63:32].
477 */
478 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
479 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
480 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
481 MPIDR_AFFINITY_LEVEL(mpidr, 0));
482
483 typer = gic_read_typer(ptr + GICR_TYPER);
484 if ((typer >> 32) == aff) {
485 u64 offset = ptr - region->redist_base;
486 gic_data_rdist_rd_base() = ptr;
487 gic_data_rdist()->phys_base = region->phys_base + offset;
488
489 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
490 smp_processor_id(), mpidr,
491 (int)(region - gic_data.redist_regions),
492 &gic_data_rdist()->phys_base);
493 return 0;
494 }
495
496 /* Try next one */
497 return 1;
498}
499
500static int gic_populate_rdist(void)
501{
502 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
503 return 0;
504
505 /* We couldn't even deal with ourselves... */
506 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
507 smp_processor_id(),
508 (unsigned long)cpu_logical_map(smp_processor_id()));
509 return -ENODEV;
510}
511
512static int __gic_update_vlpi_properties(struct redist_region *region,
513 void __iomem *ptr)
514{
515 u64 typer = gic_read_typer(ptr + GICR_TYPER);
516 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
517 gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
518
519 return 1;
520}
521
522static void gic_update_vlpi_properties(void)
523{
524 gic_iterate_rdists(__gic_update_vlpi_properties);
525 pr_info("%sVLPI support, %sdirect LPI support\n",
526 !gic_data.rdists.has_vlpis ? "no " : "",
527 !gic_data.rdists.has_direct_lpi ? "no " : "");
528}
529
530static void gic_cpu_sys_reg_init(void)
531{
532 int i, cpu = smp_processor_id();
533 u64 mpidr = cpu_logical_map(cpu);
534 u64 need_rss = MPIDR_RS(mpidr);
535 bool group0;
536 u32 val, pribits;
537
538 /*
539 * Need to check that the SRE bit has actually been set. If
540 * not, it means that SRE is disabled at EL2. We're going to
541 * die painfully, and there is nothing we can do about it.
542 *
543 * Kindly inform the luser.
544 */
545 if (!gic_enable_sre())
546 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
547
548 pribits = gic_read_ctlr();
549 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
550 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
551 pribits++;
552
553 /*
554 * Let's find out if Group0 is under control of EL3 or not by
555 * setting the highest possible, non-zero priority in PMR.
556 *
557 * If SCR_EL3.FIQ is set, the priority gets shifted down in
558 * order for the CPU interface to set bit 7, and keep the
559 * actual priority in the non-secure range. In the process, it
560 * looses the least significant bit and the actual priority
561 * becomes 0x80. Reading it back returns 0, indicating that
562 * we're don't have access to Group0.
563 */
564 write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
565 val = read_gicreg(ICC_PMR_EL1);
566 group0 = val != 0;
567
568 /* Set priority mask register */
569 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
570
571 /*
572 * Some firmwares hand over to the kernel with the BPR changed from
573 * its reset value (and with a value large enough to prevent
574 * any pre-emptive interrupts from working at all). Writing a zero
575 * to BPR restores is reset value.
576 */
577 gic_write_bpr1(0);
578
579 if (static_branch_likely(&supports_deactivate_key)) {
580 /* EOI drops priority only (mode 1) */
581 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
582 } else {
583 /* EOI deactivates interrupt too (mode 0) */
584 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
585 }
586
587 /* Always whack Group0 before Group1 */
588 if (group0) {
589 switch(pribits) {
590 case 8:
591 case 7:
592 write_gicreg(0, ICC_AP0R3_EL1);
593 write_gicreg(0, ICC_AP0R2_EL1);
594 case 6:
595 write_gicreg(0, ICC_AP0R1_EL1);
596 case 5:
597 case 4:
598 write_gicreg(0, ICC_AP0R0_EL1);
599 }
600
601 isb();
602 }
603
604 switch(pribits) {
605 case 8:
606 case 7:
607 write_gicreg(0, ICC_AP1R3_EL1);
608 write_gicreg(0, ICC_AP1R2_EL1);
609 case 6:
610 write_gicreg(0, ICC_AP1R1_EL1);
611 case 5:
612 case 4:
613 write_gicreg(0, ICC_AP1R0_EL1);
614 }
615
616 isb();
617
618 /* ... and let's hit the road... */
619 gic_write_grpen1(1);
620
621 /* Keep the RSS capability status in per_cpu variable */
622 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
623
624 /* Check all the CPUs have capable of sending SGIs to other CPUs */
625 for_each_online_cpu(i) {
626 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
627
628 need_rss |= MPIDR_RS(cpu_logical_map(i));
629 if (need_rss && (!have_rss))
630 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
631 cpu, (unsigned long)mpidr,
632 i, (unsigned long)cpu_logical_map(i));
633 }
634
635 /**
636 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
637 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
638 * UNPREDICTABLE choice of :
639 * - The write is ignored.
640 * - The RS field is treated as 0.
641 */
642 if (need_rss && (!gic_data.has_rss))
643 pr_crit_once("RSS is required but GICD doesn't support it\n");
644}
645
646static bool gicv3_nolpi;
647
648static int __init gicv3_nolpi_cfg(char *buf)
649{
650 return strtobool(buf, &gicv3_nolpi);
651}
652early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
653
654static int gic_dist_supports_lpis(void)
655{
656 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi;
657}
658
659static void gic_cpu_init(void)
660{
661 void __iomem *rbase;
662
663 /* Register ourselves with the rest of the world */
664 if (gic_populate_rdist())
665 return;
666
667 gic_enable_redist(true);
668
669 rbase = gic_data_rdist_sgi_base();
670
671 /* Configure SGIs/PPIs as non-secure Group-1 */
672 writel_relaxed(~0, rbase + GICR_IGROUPR0);
673
674 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
675
676 /* Give LPIs a spin */
677 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
678 its_cpu_init();
679
680 /* initialise system registers */
681 gic_cpu_sys_reg_init();
682}
683
684#ifdef CONFIG_SMP
685
686#define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
687#define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
688
689static int gic_starting_cpu(unsigned int cpu)
690{
691 gic_cpu_init();
692 return 0;
693}
694
695static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
696 unsigned long cluster_id)
697{
698 int next_cpu, cpu = *base_cpu;
699 unsigned long mpidr = cpu_logical_map(cpu);
700 u16 tlist = 0;
701
702 while (cpu < nr_cpu_ids) {
703 tlist |= 1 << (mpidr & 0xf);
704
705 next_cpu = cpumask_next(cpu, mask);
706 if (next_cpu >= nr_cpu_ids)
707 goto out;
708 cpu = next_cpu;
709
710 mpidr = cpu_logical_map(cpu);
711
712 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
713 cpu--;
714 goto out;
715 }
716 }
717out:
718 *base_cpu = cpu;
719 return tlist;
720}
721
722#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
723 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
724 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
725
726static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
727{
728 u64 val;
729
730 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
731 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
732 irq << ICC_SGI1R_SGI_ID_SHIFT |
733 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
734 MPIDR_TO_SGI_RS(cluster_id) |
735 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
736
737 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
738 gic_write_sgi1r(val);
739}
740
741static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
742{
743 int cpu;
744
745 if (WARN_ON(irq >= 16))
746 return;
747
748 /*
749 * Ensure that stores to Normal memory are visible to the
750 * other CPUs before issuing the IPI.
751 */
752 wmb();
753
754 for_each_cpu(cpu, mask) {
755 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
756 u16 tlist;
757
758 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
759 gic_send_sgi(cluster_id, tlist, irq);
760 }
761
762 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
763 isb();
764}
765
766static void gic_smp_init(void)
767{
768 set_smp_cross_call(gic_raise_softirq);
769 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
770 "irqchip/arm/gicv3:starting",
771 gic_starting_cpu, NULL);
772}
773
774static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
775 bool force)
776{
777 unsigned int cpu;
778 void __iomem *reg;
779 int enabled;
780 u64 val;
781
782 if (force)
783 cpu = cpumask_first(mask_val);
784 else
785 cpu = cpumask_any_and(mask_val, cpu_online_mask);
786
787 if (cpu >= nr_cpu_ids)
788 return -EINVAL;
789
790 if (gic_irq_in_rdist(d))
791 return -EINVAL;
792
793 /* If interrupt was enabled, disable it first */
794 enabled = gic_peek_irq(d, GICD_ISENABLER);
795 if (enabled)
796 gic_mask_irq(d);
797
798 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
799 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
800
801 gic_write_irouter(val, reg);
802
803 /*
804 * If the interrupt was enabled, enabled it again. Otherwise,
805 * just wait for the distributor to have digested our changes.
806 */
807 if (enabled)
808 gic_unmask_irq(d);
809 else
810 gic_dist_wait_for_rwp();
811
812 irq_data_update_effective_affinity(d, cpumask_of(cpu));
813
814 return IRQ_SET_MASK_OK_DONE;
815}
816#else
817#define gic_set_affinity NULL
818#define gic_smp_init() do { } while(0)
819#endif
820
821#ifdef CONFIG_CPU_PM
822/* Check whether it's single security state view */
823static bool gic_dist_security_disabled(void)
824{
825 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
826}
827
828static int gic_cpu_pm_notifier(struct notifier_block *self,
829 unsigned long cmd, void *v)
830{
831 if (cmd == CPU_PM_EXIT) {
832 if (gic_dist_security_disabled())
833 gic_enable_redist(true);
834 gic_cpu_sys_reg_init();
835 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
836 gic_write_grpen1(0);
837 gic_enable_redist(false);
838 }
839 return NOTIFY_OK;
840}
841
842static struct notifier_block gic_cpu_pm_notifier_block = {
843 .notifier_call = gic_cpu_pm_notifier,
844};
845
846static void gic_cpu_pm_init(void)
847{
848 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
849}
850
851#else
852static inline void gic_cpu_pm_init(void) { }
853#endif /* CONFIG_CPU_PM */
854
855static struct irq_chip gic_chip = {
856 .name = "GICv3",
857 .irq_mask = gic_mask_irq,
858 .irq_unmask = gic_unmask_irq,
859 .irq_eoi = gic_eoi_irq,
860 .irq_set_type = gic_set_type,
861 .irq_set_affinity = gic_set_affinity,
862 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
863 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
864 .flags = IRQCHIP_SET_TYPE_MASKED,
865};
866
867static struct irq_chip gic_eoimode1_chip = {
868 .name = "GICv3",
869 .irq_mask = gic_eoimode1_mask_irq,
870 .irq_unmask = gic_unmask_irq,
871 .irq_eoi = gic_eoimode1_eoi_irq,
872 .irq_set_type = gic_set_type,
873 .irq_set_affinity = gic_set_affinity,
874 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
875 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
876 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
877 .flags = IRQCHIP_SET_TYPE_MASKED,
878};
879
880#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
881
882static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
883 irq_hw_number_t hw)
884{
885 struct irq_chip *chip = &gic_chip;
886
887 if (static_branch_likely(&supports_deactivate_key))
888 chip = &gic_eoimode1_chip;
889
890 /* SGIs are private to the core kernel */
891 if (hw < 16)
892 return -EPERM;
893 /* Nothing here */
894 if (hw >= gic_data.irq_nr && hw < 8192)
895 return -EPERM;
896 /* Off limits */
897 if (hw >= GIC_ID_NR)
898 return -EPERM;
899
900 /* PPIs */
901 if (hw < 32) {
902 irq_set_percpu_devid(irq);
903 irq_domain_set_info(d, irq, hw, chip, d->host_data,
904 handle_percpu_devid_irq, NULL, NULL);
905 irq_set_status_flags(irq, IRQ_NOAUTOEN);
906 }
907 /* SPIs */
908 if (hw >= 32 && hw < gic_data.irq_nr) {
909 irq_domain_set_info(d, irq, hw, chip, d->host_data,
910 handle_fasteoi_irq, NULL, NULL);
911 irq_set_probe(irq);
912 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
913 }
914 /* LPIs */
915 if (hw >= 8192 && hw < GIC_ID_NR) {
916 if (!gic_dist_supports_lpis())
917 return -EPERM;
918 irq_domain_set_info(d, irq, hw, chip, d->host_data,
919 handle_fasteoi_irq, NULL, NULL);
920 }
921
922 return 0;
923}
924
925#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
926
927static int gic_irq_domain_translate(struct irq_domain *d,
928 struct irq_fwspec *fwspec,
929 unsigned long *hwirq,
930 unsigned int *type)
931{
932 if (is_of_node(fwspec->fwnode)) {
933 if (fwspec->param_count < 3)
934 return -EINVAL;
935
936 switch (fwspec->param[0]) {
937 case 0: /* SPI */
938 *hwirq = fwspec->param[1] + 32;
939 break;
940 case 1: /* PPI */
941 case GIC_IRQ_TYPE_PARTITION:
942 *hwirq = fwspec->param[1] + 16;
943 break;
944 case GIC_IRQ_TYPE_LPI: /* LPI */
945 *hwirq = fwspec->param[1];
946 break;
947 default:
948 return -EINVAL;
949 }
950
951 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
952
953 /*
954 * Make it clear that broken DTs are... broken.
955 * Partitionned PPIs are an unfortunate exception.
956 */
957 WARN_ON(*type == IRQ_TYPE_NONE &&
958 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
959 return 0;
960 }
961
962 if (is_fwnode_irqchip(fwspec->fwnode)) {
963 if(fwspec->param_count != 2)
964 return -EINVAL;
965
966 *hwirq = fwspec->param[0];
967 *type = fwspec->param[1];
968
969 WARN_ON(*type == IRQ_TYPE_NONE);
970 return 0;
971 }
972
973 return -EINVAL;
974}
975
976static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
977 unsigned int nr_irqs, void *arg)
978{
979 int i, ret;
980 irq_hw_number_t hwirq;
981 unsigned int type = IRQ_TYPE_NONE;
982 struct irq_fwspec *fwspec = arg;
983
984 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
985 if (ret)
986 return ret;
987
988 for (i = 0; i < nr_irqs; i++) {
989 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
990 if (ret)
991 return ret;
992 }
993
994 return 0;
995}
996
997static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
998 unsigned int nr_irqs)
999{
1000 int i;
1001
1002 for (i = 0; i < nr_irqs; i++) {
1003 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1004 irq_set_handler(virq + i, NULL);
1005 irq_domain_reset_irq_data(d);
1006 }
1007}
1008
1009static int gic_irq_domain_select(struct irq_domain *d,
1010 struct irq_fwspec *fwspec,
1011 enum irq_domain_bus_token bus_token)
1012{
1013 /* Not for us */
1014 if (fwspec->fwnode != d->fwnode)
1015 return 0;
1016
1017 /* If this is not DT, then we have a single domain */
1018 if (!is_of_node(fwspec->fwnode))
1019 return 1;
1020
1021 /*
1022 * If this is a PPI and we have a 4th (non-null) parameter,
1023 * then we need to match the partition domain.
1024 */
1025 if (fwspec->param_count >= 4 &&
1026 fwspec->param[0] == 1 && fwspec->param[3] != 0)
1027 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1028
1029 return d == gic_data.domain;
1030}
1031
1032static const struct irq_domain_ops gic_irq_domain_ops = {
1033 .translate = gic_irq_domain_translate,
1034 .alloc = gic_irq_domain_alloc,
1035 .free = gic_irq_domain_free,
1036 .select = gic_irq_domain_select,
1037};
1038
1039static int partition_domain_translate(struct irq_domain *d,
1040 struct irq_fwspec *fwspec,
1041 unsigned long *hwirq,
1042 unsigned int *type)
1043{
1044 struct device_node *np;
1045 int ret;
1046
1047 np = of_find_node_by_phandle(fwspec->param[3]);
1048 if (WARN_ON(!np))
1049 return -EINVAL;
1050
1051 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1052 of_node_to_fwnode(np));
1053 if (ret < 0)
1054 return ret;
1055
1056 *hwirq = ret;
1057 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1058
1059 return 0;
1060}
1061
1062static const struct irq_domain_ops partition_domain_ops = {
1063 .translate = partition_domain_translate,
1064 .select = gic_irq_domain_select,
1065};
1066
1067static int __init gic_init_bases(void __iomem *dist_base,
1068 struct redist_region *rdist_regs,
1069 u32 nr_redist_regions,
1070 u64 redist_stride,
1071 struct fwnode_handle *handle)
1072{
1073 u32 typer;
1074 int gic_irqs;
1075 int err;
1076
1077 if (!is_hyp_mode_available())
1078 static_branch_disable(&supports_deactivate_key);
1079
1080 if (static_branch_likely(&supports_deactivate_key))
1081 pr_info("GIC: Using split EOI/Deactivate mode\n");
1082
1083 gic_data.fwnode = handle;
1084 gic_data.dist_base = dist_base;
1085 gic_data.redist_regions = rdist_regs;
1086 gic_data.nr_redist_regions = nr_redist_regions;
1087 gic_data.redist_stride = redist_stride;
1088
1089 /*
1090 * Find out how many interrupts are supported.
1091 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1092 */
1093 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1094 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
1095 gic_irqs = GICD_TYPER_IRQS(typer);
1096 if (gic_irqs > 1020)
1097 gic_irqs = 1020;
1098 gic_data.irq_nr = gic_irqs;
1099
1100 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1101 &gic_data);
1102 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1103 gic_data.rdists.has_vlpis = true;
1104 gic_data.rdists.has_direct_lpi = true;
1105
1106 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1107 err = -ENOMEM;
1108 goto out_free;
1109 }
1110
1111 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1112 pr_info("Distributor has %sRange Selector support\n",
1113 gic_data.has_rss ? "" : "no ");
1114
1115 set_handle_irq(gic_handle_irq);
1116
1117 gic_update_vlpi_properties();
1118
1119 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
1120 its_init(handle, &gic_data.rdists, gic_data.domain);
1121
1122 gic_smp_init();
1123 gic_dist_init();
1124 gic_cpu_init();
1125 gic_cpu_pm_init();
1126
1127 return 0;
1128
1129out_free:
1130 if (gic_data.domain)
1131 irq_domain_remove(gic_data.domain);
1132 free_percpu(gic_data.rdists.rdist);
1133 return err;
1134}
1135
1136static int __init gic_validate_dist_version(void __iomem *dist_base)
1137{
1138 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1139
1140 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1141 return -ENODEV;
1142
1143 return 0;
1144}
1145
1146/* Create all possible partitions at boot time */
1147static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1148{
1149 struct device_node *parts_node, *child_part;
1150 int part_idx = 0, i;
1151 int nr_parts;
1152 struct partition_affinity *parts;
1153
1154 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1155 if (!parts_node)
1156 return;
1157
1158 nr_parts = of_get_child_count(parts_node);
1159
1160 if (!nr_parts)
1161 goto out_put_node;
1162
1163 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL);
1164 if (WARN_ON(!parts))
1165 goto out_put_node;
1166
1167 for_each_child_of_node(parts_node, child_part) {
1168 struct partition_affinity *part;
1169 int n;
1170
1171 part = &parts[part_idx];
1172
1173 part->partition_id = of_node_to_fwnode(child_part);
1174
1175 pr_info("GIC: PPI partition %s[%d] { ",
1176 child_part->name, part_idx);
1177
1178 n = of_property_count_elems_of_size(child_part, "affinity",
1179 sizeof(u32));
1180 WARN_ON(n <= 0);
1181
1182 for (i = 0; i < n; i++) {
1183 int err, cpu;
1184 u32 cpu_phandle;
1185 struct device_node *cpu_node;
1186
1187 err = of_property_read_u32_index(child_part, "affinity",
1188 i, &cpu_phandle);
1189 if (WARN_ON(err))
1190 continue;
1191
1192 cpu_node = of_find_node_by_phandle(cpu_phandle);
1193 if (WARN_ON(!cpu_node))
1194 continue;
1195
1196 cpu = of_cpu_node_to_id(cpu_node);
1197 if (WARN_ON(cpu < 0))
1198 continue;
1199
1200 pr_cont("%pOF[%d] ", cpu_node, cpu);
1201
1202 cpumask_set_cpu(cpu, &part->mask);
1203 }
1204
1205 pr_cont("}\n");
1206 part_idx++;
1207 }
1208
1209 for (i = 0; i < 16; i++) {
1210 unsigned int irq;
1211 struct partition_desc *desc;
1212 struct irq_fwspec ppi_fwspec = {
1213 .fwnode = gic_data.fwnode,
1214 .param_count = 3,
1215 .param = {
1216 [0] = GIC_IRQ_TYPE_PARTITION,
1217 [1] = i,
1218 [2] = IRQ_TYPE_NONE,
1219 },
1220 };
1221
1222 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1223 if (WARN_ON(!irq))
1224 continue;
1225 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1226 irq, &partition_domain_ops);
1227 if (WARN_ON(!desc))
1228 continue;
1229
1230 gic_data.ppi_descs[i] = desc;
1231 }
1232
1233out_put_node:
1234 of_node_put(parts_node);
1235}
1236
1237static void __init gic_of_setup_kvm_info(struct device_node *node)
1238{
1239 int ret;
1240 struct resource r;
1241 u32 gicv_idx;
1242
1243 gic_v3_kvm_info.type = GIC_V3;
1244
1245 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1246 if (!gic_v3_kvm_info.maint_irq)
1247 return;
1248
1249 if (of_property_read_u32(node, "#redistributor-regions",
1250 &gicv_idx))
1251 gicv_idx = 1;
1252
1253 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1254 ret = of_address_to_resource(node, gicv_idx, &r);
1255 if (!ret)
1256 gic_v3_kvm_info.vcpu = r;
1257
1258 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1259 gic_set_kvm_info(&gic_v3_kvm_info);
1260}
1261
1262static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1263{
1264 void __iomem *dist_base;
1265 struct redist_region *rdist_regs;
1266 u64 redist_stride;
1267 u32 nr_redist_regions;
1268 int err, i;
1269
1270 dist_base = of_iomap(node, 0);
1271 if (!dist_base) {
1272 pr_err("%pOF: unable to map gic dist registers\n", node);
1273 return -ENXIO;
1274 }
1275
1276 err = gic_validate_dist_version(dist_base);
1277 if (err) {
1278 pr_err("%pOF: no distributor detected, giving up\n", node);
1279 goto out_unmap_dist;
1280 }
1281
1282 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1283 nr_redist_regions = 1;
1284
1285 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
1286 if (!rdist_regs) {
1287 err = -ENOMEM;
1288 goto out_unmap_dist;
1289 }
1290
1291 for (i = 0; i < nr_redist_regions; i++) {
1292 struct resource res;
1293 int ret;
1294
1295 ret = of_address_to_resource(node, 1 + i, &res);
1296 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1297 if (ret || !rdist_regs[i].redist_base) {
1298 pr_err("%pOF: couldn't map region %d\n", node, i);
1299 err = -ENODEV;
1300 goto out_unmap_rdist;
1301 }
1302 rdist_regs[i].phys_base = res.start;
1303 }
1304
1305 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1306 redist_stride = 0;
1307
1308 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1309 redist_stride, &node->fwnode);
1310 if (err)
1311 goto out_unmap_rdist;
1312
1313 gic_populate_ppi_partitions(node);
1314
1315 if (static_branch_likely(&supports_deactivate_key))
1316 gic_of_setup_kvm_info(node);
1317 return 0;
1318
1319out_unmap_rdist:
1320 for (i = 0; i < nr_redist_regions; i++)
1321 if (rdist_regs[i].redist_base)
1322 iounmap(rdist_regs[i].redist_base);
1323 kfree(rdist_regs);
1324out_unmap_dist:
1325 iounmap(dist_base);
1326 return err;
1327}
1328
1329IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1330
1331#ifdef CONFIG_ACPI
1332static struct
1333{
1334 void __iomem *dist_base;
1335 struct redist_region *redist_regs;
1336 u32 nr_redist_regions;
1337 bool single_redist;
1338 u32 maint_irq;
1339 int maint_irq_mode;
1340 phys_addr_t vcpu_base;
1341} acpi_data __initdata;
1342
1343static void __init
1344gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1345{
1346 static int count = 0;
1347
1348 acpi_data.redist_regs[count].phys_base = phys_base;
1349 acpi_data.redist_regs[count].redist_base = redist_base;
1350 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
1351 count++;
1352}
1353
1354static int __init
1355gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
1356 const unsigned long end)
1357{
1358 struct acpi_madt_generic_redistributor *redist =
1359 (struct acpi_madt_generic_redistributor *)header;
1360 void __iomem *redist_base;
1361
1362 redist_base = ioremap(redist->base_address, redist->length);
1363 if (!redist_base) {
1364 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1365 return -ENOMEM;
1366 }
1367
1368 gic_acpi_register_redist(redist->base_address, redist_base);
1369 return 0;
1370}
1371
1372static int __init
1373gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1374 const unsigned long end)
1375{
1376 struct acpi_madt_generic_interrupt *gicc =
1377 (struct acpi_madt_generic_interrupt *)header;
1378 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1379 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1380 void __iomem *redist_base;
1381
1382 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1383 if (!(gicc->flags & ACPI_MADT_ENABLED))
1384 return 0;
1385
1386 redist_base = ioremap(gicc->gicr_base_address, size);
1387 if (!redist_base)
1388 return -ENOMEM;
1389
1390 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1391 return 0;
1392}
1393
1394static int __init gic_acpi_collect_gicr_base(void)
1395{
1396 acpi_tbl_entry_handler redist_parser;
1397 enum acpi_madt_type type;
1398
1399 if (acpi_data.single_redist) {
1400 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1401 redist_parser = gic_acpi_parse_madt_gicc;
1402 } else {
1403 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1404 redist_parser = gic_acpi_parse_madt_redist;
1405 }
1406
1407 /* Collect redistributor base addresses in GICR entries */
1408 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1409 return 0;
1410
1411 pr_info("No valid GICR entries exist\n");
1412 return -ENODEV;
1413}
1414
1415static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1416 const unsigned long end)
1417{
1418 /* Subtable presence means that redist exists, that's it */
1419 return 0;
1420}
1421
1422static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1423 const unsigned long end)
1424{
1425 struct acpi_madt_generic_interrupt *gicc =
1426 (struct acpi_madt_generic_interrupt *)header;
1427
1428 /*
1429 * If GICC is enabled and has valid gicr base address, then it means
1430 * GICR base is presented via GICC
1431 */
1432 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1433 return 0;
1434
1435 /*
1436 * It's perfectly valid firmware can pass disabled GICC entry, driver
1437 * should not treat as errors, skip the entry instead of probe fail.
1438 */
1439 if (!(gicc->flags & ACPI_MADT_ENABLED))
1440 return 0;
1441
1442 return -ENODEV;
1443}
1444
1445static int __init gic_acpi_count_gicr_regions(void)
1446{
1447 int count;
1448
1449 /*
1450 * Count how many redistributor regions we have. It is not allowed
1451 * to mix redistributor description, GICR and GICC subtables have to be
1452 * mutually exclusive.
1453 */
1454 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1455 gic_acpi_match_gicr, 0);
1456 if (count > 0) {
1457 acpi_data.single_redist = false;
1458 return count;
1459 }
1460
1461 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1462 gic_acpi_match_gicc, 0);
1463 if (count > 0)
1464 acpi_data.single_redist = true;
1465
1466 return count;
1467}
1468
1469static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1470 struct acpi_probe_entry *ape)
1471{
1472 struct acpi_madt_generic_distributor *dist;
1473 int count;
1474
1475 dist = (struct acpi_madt_generic_distributor *)header;
1476 if (dist->version != ape->driver_data)
1477 return false;
1478
1479 /* We need to do that exercise anyway, the sooner the better */
1480 count = gic_acpi_count_gicr_regions();
1481 if (count <= 0)
1482 return false;
1483
1484 acpi_data.nr_redist_regions = count;
1485 return true;
1486}
1487
1488static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
1489 const unsigned long end)
1490{
1491 struct acpi_madt_generic_interrupt *gicc =
1492 (struct acpi_madt_generic_interrupt *)header;
1493 int maint_irq_mode;
1494 static int first_madt = true;
1495
1496 /* Skip unusable CPUs */
1497 if (!(gicc->flags & ACPI_MADT_ENABLED))
1498 return 0;
1499
1500 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1501 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1502
1503 if (first_madt) {
1504 first_madt = false;
1505
1506 acpi_data.maint_irq = gicc->vgic_interrupt;
1507 acpi_data.maint_irq_mode = maint_irq_mode;
1508 acpi_data.vcpu_base = gicc->gicv_base_address;
1509
1510 return 0;
1511 }
1512
1513 /*
1514 * The maintenance interrupt and GICV should be the same for every CPU
1515 */
1516 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
1517 (acpi_data.maint_irq_mode != maint_irq_mode) ||
1518 (acpi_data.vcpu_base != gicc->gicv_base_address))
1519 return -EINVAL;
1520
1521 return 0;
1522}
1523
1524static bool __init gic_acpi_collect_virt_info(void)
1525{
1526 int count;
1527
1528 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1529 gic_acpi_parse_virt_madt_gicc, 0);
1530
1531 return (count > 0);
1532}
1533
1534#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1535#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1536#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1537
1538static void __init gic_acpi_setup_kvm_info(void)
1539{
1540 int irq;
1541
1542 if (!gic_acpi_collect_virt_info()) {
1543 pr_warn("Unable to get hardware information used for virtualization\n");
1544 return;
1545 }
1546
1547 gic_v3_kvm_info.type = GIC_V3;
1548
1549 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1550 acpi_data.maint_irq_mode,
1551 ACPI_ACTIVE_HIGH);
1552 if (irq <= 0)
1553 return;
1554
1555 gic_v3_kvm_info.maint_irq = irq;
1556
1557 if (acpi_data.vcpu_base) {
1558 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
1559
1560 vcpu->flags = IORESOURCE_MEM;
1561 vcpu->start = acpi_data.vcpu_base;
1562 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1563 }
1564
1565 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1566 gic_set_kvm_info(&gic_v3_kvm_info);
1567}
1568
1569static int __init
1570gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1571{
1572 struct acpi_madt_generic_distributor *dist;
1573 struct fwnode_handle *domain_handle;
1574 size_t size;
1575 int i, err;
1576
1577 /* Get distributor base address */
1578 dist = (struct acpi_madt_generic_distributor *)header;
1579 acpi_data.dist_base = ioremap(dist->base_address,
1580 ACPI_GICV3_DIST_MEM_SIZE);
1581 if (!acpi_data.dist_base) {
1582 pr_err("Unable to map GICD registers\n");
1583 return -ENOMEM;
1584 }
1585
1586 err = gic_validate_dist_version(acpi_data.dist_base);
1587 if (err) {
1588 pr_err("No distributor detected at @%p, giving up\n",
1589 acpi_data.dist_base);
1590 goto out_dist_unmap;
1591 }
1592
1593 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
1594 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
1595 if (!acpi_data.redist_regs) {
1596 err = -ENOMEM;
1597 goto out_dist_unmap;
1598 }
1599
1600 err = gic_acpi_collect_gicr_base();
1601 if (err)
1602 goto out_redist_unmap;
1603
1604 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
1605 if (!domain_handle) {
1606 err = -ENOMEM;
1607 goto out_redist_unmap;
1608 }
1609
1610 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
1611 acpi_data.nr_redist_regions, 0, domain_handle);
1612 if (err)
1613 goto out_fwhandle_free;
1614
1615 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1616
1617 if (static_branch_likely(&supports_deactivate_key))
1618 gic_acpi_setup_kvm_info();
1619
1620 return 0;
1621
1622out_fwhandle_free:
1623 irq_domain_free_fwnode(domain_handle);
1624out_redist_unmap:
1625 for (i = 0; i < acpi_data.nr_redist_regions; i++)
1626 if (acpi_data.redist_regs[i].redist_base)
1627 iounmap(acpi_data.redist_regs[i].redist_base);
1628 kfree(acpi_data.redist_regs);
1629out_dist_unmap:
1630 iounmap(acpi_data.dist_base);
1631 return err;
1632}
1633IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1634 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1635 gic_acpi_init);
1636IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1637 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1638 gic_acpi_init);
1639IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1640 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
1641 gic_acpi_init);
1642#endif