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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26 */
27
28#include <linux/kernel.h>
29#include "intel_drv.h"
30#include "i915_drv.h"
31#include "intel_dsi.h"
32
33int dsi_pixel_format_bpp(int pixel_format)
34{
35 int bpp;
36
37 switch (pixel_format) {
38 default:
39 case VID_MODE_FORMAT_RGB888:
40 case VID_MODE_FORMAT_RGB666_LOOSE:
41 bpp = 24;
42 break;
43 case VID_MODE_FORMAT_RGB666:
44 bpp = 18;
45 break;
46 case VID_MODE_FORMAT_RGB565:
47 bpp = 16;
48 break;
49 }
50
51 return bpp;
52}
53
54struct dsi_mnp {
55 u32 dsi_pll_ctrl;
56 u32 dsi_pll_div;
57};
58
59static const u32 lfsr_converts[] = {
60 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
61 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
62 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
63 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
64};
65
66/* Get DSI clock from pixel clock */
67static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
68{
69 u32 dsi_clk_khz;
70 u32 bpp = dsi_pixel_format_bpp(pixel_format);
71
72 /* DSI data rate = pixel clock * bits per pixel / lane count
73 pixel clock is converted from KHz to Hz */
74 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
75
76 return dsi_clk_khz;
77}
78
79static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
80 struct dsi_mnp *dsi_mnp, int target_dsi_clk)
81{
82 unsigned int calc_m = 0, calc_p = 0;
83 unsigned int m_min, m_max, p_min = 2, p_max = 6;
84 unsigned int m, n, p;
85 int ref_clk;
86 int delta = target_dsi_clk;
87 u32 m_seed;
88
89 /* target_dsi_clk is expected in kHz */
90 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
91 DRM_ERROR("DSI CLK Out of Range\n");
92 return -ECHRNG;
93 }
94
95 if (IS_CHERRYVIEW(dev_priv)) {
96 ref_clk = 100000;
97 n = 4;
98 m_min = 70;
99 m_max = 96;
100 } else {
101 ref_clk = 25000;
102 n = 1;
103 m_min = 62;
104 m_max = 92;
105 }
106
107 for (m = m_min; m <= m_max && delta; m++) {
108 for (p = p_min; p <= p_max && delta; p++) {
109 /*
110 * Find the optimal m and p divisors with minimal delta
111 * +/- the required clock
112 */
113 int calc_dsi_clk = (m * ref_clk) / (p * n);
114 int d = abs(target_dsi_clk - calc_dsi_clk);
115 if (d < delta) {
116 delta = d;
117 calc_m = m;
118 calc_p = p;
119 }
120 }
121 }
122
123 /* register has log2(N1), this works fine for powers of two */
124 n = ffs(n) - 1;
125 m_seed = lfsr_converts[calc_m - 62];
126 dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
127 dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
128 m_seed << DSI_PLL_M1_DIV_SHIFT;
129
130 return 0;
131}
132
133/*
134 * XXX: The muxing and gating is hard coded for now. Need to add support for
135 * sharing PLLs with two DSI outputs.
136 */
137static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
138{
139 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
140 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
141 int ret;
142 struct dsi_mnp dsi_mnp;
143 u32 dsi_clk;
144
145 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
146 intel_dsi->lane_count);
147
148 ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
149 if (ret) {
150 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
151 return;
152 }
153
154 if (intel_dsi->ports & (1 << PORT_A))
155 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
156
157 if (intel_dsi->ports & (1 << PORT_C))
158 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
159
160 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
161 dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
162
163 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
165 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
166}
167
168static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
169{
170 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
171 u32 tmp;
172
173 DRM_DEBUG_KMS("\n");
174
175 mutex_lock(&dev_priv->sb_lock);
176
177 vlv_configure_dsi_pll(encoder);
178
179 /* wait at least 0.5 us after ungating before enabling VCO */
180 usleep_range(1, 10);
181
182 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
183 tmp |= DSI_PLL_VCO_EN;
184 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
185
186 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
187 DSI_PLL_LOCK, 20)) {
188
189 mutex_unlock(&dev_priv->sb_lock);
190 DRM_ERROR("DSI PLL lock failed\n");
191 return;
192 }
193 mutex_unlock(&dev_priv->sb_lock);
194
195 DRM_DEBUG_KMS("DSI PLL locked\n");
196}
197
198static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
199{
200 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
201 u32 tmp;
202
203 DRM_DEBUG_KMS("\n");
204
205 mutex_lock(&dev_priv->sb_lock);
206
207 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
208 tmp &= ~DSI_PLL_VCO_EN;
209 tmp |= DSI_PLL_LDO_GATE;
210 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
211
212 mutex_unlock(&dev_priv->sb_lock);
213}
214
215static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
216{
217 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
218 u32 val;
219
220 DRM_DEBUG_KMS("\n");
221
222 val = I915_READ(BXT_DSI_PLL_ENABLE);
223 val &= ~BXT_DSI_PLL_DO_ENABLE;
224 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
225
226 /*
227 * PLL lock should deassert within 200us.
228 * Wait up to 1ms before timing out.
229 */
230 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
231 & BXT_DSI_PLL_LOCKED) == 0, 1))
232 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
233}
234
235static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
236{
237 int bpp = dsi_pixel_format_bpp(pixel_format);
238
239 WARN(bpp != pipe_bpp,
240 "bpp match assertion failure (expected %d, current %d)\n",
241 bpp, pipe_bpp);
242}
243
244static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
245{
246 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
247 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
248 u32 dsi_clock, pclk;
249 u32 pll_ctl, pll_div;
250 u32 m = 0, p = 0, n;
251 int refclk = 25000;
252 int i;
253
254 DRM_DEBUG_KMS("\n");
255
256 mutex_lock(&dev_priv->sb_lock);
257 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
258 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
259 mutex_unlock(&dev_priv->sb_lock);
260
261 /* mask out other bits and extract the P1 divisor */
262 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
263 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
264
265 /* N1 divisor */
266 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
267 n = 1 << n; /* register has log2(N1) */
268
269 /* mask out the other bits and extract the M1 divisor */
270 pll_div &= DSI_PLL_M1_DIV_MASK;
271 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
272
273 while (pll_ctl) {
274 pll_ctl = pll_ctl >> 1;
275 p++;
276 }
277 p--;
278
279 if (!p) {
280 DRM_ERROR("wrong P1 divisor\n");
281 return 0;
282 }
283
284 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
285 if (lfsr_converts[i] == pll_div)
286 break;
287 }
288
289 if (i == ARRAY_SIZE(lfsr_converts)) {
290 DRM_ERROR("wrong m_seed programmed\n");
291 return 0;
292 }
293
294 m = i + 62;
295
296 dsi_clock = (m * refclk) / (p * n);
297
298 /* pixel_format and pipe_bpp should agree */
299 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
300
301 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
302
303 return pclk;
304}
305
306static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
307{
308 u32 pclk;
309 u32 dsi_clk;
310 u32 dsi_ratio;
311 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
312 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
313
314 /* Divide by zero */
315 if (!pipe_bpp) {
316 DRM_ERROR("Invalid BPP(0)\n");
317 return 0;
318 }
319
320 dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
321 BXT_DSI_PLL_RATIO_MASK;
322
323 /* Invalid DSI ratio ? */
324 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
325 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
326 DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
327 return 0;
328 }
329
330 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
331
332 /* pixel_format and pipe_bpp should agree */
333 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
334
335 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
336
337 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
338 return pclk;
339}
340
341u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
342{
343 if (IS_BROXTON(encoder->base.dev))
344 return bxt_dsi_get_pclk(encoder, pipe_bpp);
345 else
346 return vlv_dsi_get_pclk(encoder, pipe_bpp);
347}
348
349static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
350{
351 u32 temp;
352 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
353 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
354
355 temp = I915_READ(MIPI_CTRL(port));
356 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
357 I915_WRITE(MIPI_CTRL(port), temp |
358 intel_dsi->escape_clk_div <<
359 ESCAPE_CLOCK_DIVIDER_SHIFT);
360}
361
362/* Program BXT Mipi clocks and dividers */
363static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
364{
365 u32 tmp;
366 u32 divider;
367 u32 dsi_rate;
368 u32 pll_ratio;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370
371 /* Clear old configurations */
372 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
373 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
374 tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
375 tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
376 tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
377
378 /* Get the current DSI rate(actual) */
379 pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
380 BXT_DSI_PLL_RATIO_MASK;
381 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
382
383 /* Max possible output of clock is 39.5 MHz, program value -1 */
384 divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
385 tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
386
387 /*
388 * Tx escape clock must be as close to 20MHz possible, but should
389 * not exceed it. Hence select divide by 2
390 */
391 tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
392
393 tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
394
395 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
396}
397
398static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
399{
400 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
401 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
402 u8 dsi_ratio;
403 u32 dsi_clk;
404 u32 val;
405
406 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
407 intel_dsi->lane_count);
408
409 /*
410 * From clock diagram, to get PLL ratio divider, divide double of DSI
411 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
412 * round 'up' the result
413 */
414 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
415 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
416 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
417 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
418 return false;
419 }
420
421 /*
422 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
423 * Spec says both have to be programmed, even if one is not getting
424 * used. Configure MIPI_CLOCK_CTL dividers in modeset
425 */
426 val = I915_READ(BXT_DSI_PLL_CTL);
427 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
428 val &= ~BXT_DSI_FREQ_SEL_MASK;
429 val &= ~BXT_DSI_PLL_RATIO_MASK;
430 val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
431
432 /* As per recommendation from hardware team,
433 * Prog PVD ratio =1 if dsi ratio <= 50
434 */
435 if (dsi_ratio <= 50) {
436 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
437 val |= BXT_DSI_PLL_PVD_RATIO_1;
438 }
439
440 I915_WRITE(BXT_DSI_PLL_CTL, val);
441 POSTING_READ(BXT_DSI_PLL_CTL);
442
443 return true;
444}
445
446static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
447{
448 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
449 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
450 enum port port;
451 u32 val;
452
453 DRM_DEBUG_KMS("\n");
454
455 val = I915_READ(BXT_DSI_PLL_ENABLE);
456
457 if (val & BXT_DSI_PLL_DO_ENABLE) {
458 WARN(1, "DSI PLL already enabled. Disabling it.\n");
459 val &= ~BXT_DSI_PLL_DO_ENABLE;
460 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
461 }
462
463 /* Configure PLL vales */
464 if (!bxt_configure_dsi_pll(encoder)) {
465 DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
466 return;
467 }
468
469 /* Program TX, RX, Dphy clocks */
470 for_each_dsi_port(port, intel_dsi->ports)
471 bxt_dsi_program_clocks(encoder->base.dev, port);
472
473 /* Enable DSI PLL */
474 val = I915_READ(BXT_DSI_PLL_ENABLE);
475 val |= BXT_DSI_PLL_DO_ENABLE;
476 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
477
478 /* Timeout and fail if PLL not locked */
479 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
480 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
481 return;
482 }
483
484 DRM_DEBUG_KMS("DSI PLL locked\n");
485}
486
487void intel_enable_dsi_pll(struct intel_encoder *encoder)
488{
489 struct drm_device *dev = encoder->base.dev;
490
491 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
492 vlv_enable_dsi_pll(encoder);
493 else if (IS_BROXTON(dev))
494 bxt_enable_dsi_pll(encoder);
495}
496
497void intel_disable_dsi_pll(struct intel_encoder *encoder)
498{
499 struct drm_device *dev = encoder->base.dev;
500
501 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
502 vlv_disable_dsi_pll(encoder);
503 else if (IS_BROXTON(dev))
504 bxt_disable_dsi_pll(encoder);
505}
506
507static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
508{
509 u32 tmp;
510 struct drm_device *dev = encoder->base.dev;
511 struct drm_i915_private *dev_priv = dev->dev_private;
512
513 /* Clear old configurations */
514 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
515 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
516 tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
517 tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
518 tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
519 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
520 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
521}
522
523void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
524{
525 struct drm_device *dev = encoder->base.dev;
526
527 if (IS_BROXTON(dev))
528 bxt_dsi_reset_clocks(encoder, port);
529 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
530 vlv_dsi_reset_clocks(encoder, port);
531}
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26 */
27
28#include <linux/kernel.h>
29#include "intel_drv.h"
30#include "i915_drv.h"
31#include "intel_dsi.h"
32
33static const u16 lfsr_converts[] = {
34 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
35 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
36 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
37 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
38};
39
40/* Get DSI clock from pixel clock */
41static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
42 int lane_count)
43{
44 u32 dsi_clk_khz;
45 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
46
47 /* DSI data rate = pixel clock * bits per pixel / lane count
48 pixel clock is converted from KHz to Hz */
49 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
50
51 return dsi_clk_khz;
52}
53
54static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
55 struct intel_crtc_state *config,
56 int target_dsi_clk)
57{
58 unsigned int m_min, m_max, p_min = 2, p_max = 6;
59 unsigned int m, n, p;
60 unsigned int calc_m, calc_p;
61 int delta, ref_clk;
62
63 /* target_dsi_clk is expected in kHz */
64 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
65 DRM_ERROR("DSI CLK Out of Range\n");
66 return -ECHRNG;
67 }
68
69 if (IS_CHERRYVIEW(dev_priv)) {
70 ref_clk = 100000;
71 n = 4;
72 m_min = 70;
73 m_max = 96;
74 } else {
75 ref_clk = 25000;
76 n = 1;
77 m_min = 62;
78 m_max = 92;
79 }
80
81 calc_p = p_min;
82 calc_m = m_min;
83 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
84
85 for (m = m_min; m <= m_max && delta; m++) {
86 for (p = p_min; p <= p_max && delta; p++) {
87 /*
88 * Find the optimal m and p divisors with minimal delta
89 * +/- the required clock
90 */
91 int calc_dsi_clk = (m * ref_clk) / (p * n);
92 int d = abs(target_dsi_clk - calc_dsi_clk);
93 if (d < delta) {
94 delta = d;
95 calc_m = m;
96 calc_p = p;
97 }
98 }
99 }
100
101 /* register has log2(N1), this works fine for powers of two */
102 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
103 config->dsi_pll.div =
104 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
105 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
106
107 return 0;
108}
109
110/*
111 * XXX: The muxing and gating is hard coded for now. Need to add support for
112 * sharing PLLs with two DSI outputs.
113 */
114static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
115 struct intel_crtc_state *config)
116{
117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
118 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
119 int ret;
120 u32 dsi_clk;
121
122 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
123 intel_dsi->lane_count);
124
125 ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
126 if (ret) {
127 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
128 return ret;
129 }
130
131 if (intel_dsi->ports & (1 << PORT_A))
132 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
133
134 if (intel_dsi->ports & (1 << PORT_C))
135 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
136
137 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
138
139 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
140 config->dsi_pll.div, config->dsi_pll.ctrl);
141
142 return 0;
143}
144
145static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
146 const struct intel_crtc_state *config)
147{
148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
149
150 DRM_DEBUG_KMS("\n");
151
152 mutex_lock(&dev_priv->sb_lock);
153
154 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
155 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
156 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
157 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
158
159 /* wait at least 0.5 us after ungating before enabling VCO,
160 * allow hrtimer subsystem optimization by relaxing timing
161 */
162 usleep_range(10, 50);
163
164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
165
166 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
167 DSI_PLL_LOCK, 20)) {
168
169 mutex_unlock(&dev_priv->sb_lock);
170 DRM_ERROR("DSI PLL lock failed\n");
171 return;
172 }
173 mutex_unlock(&dev_priv->sb_lock);
174
175 DRM_DEBUG_KMS("DSI PLL locked\n");
176}
177
178static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
179{
180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
181 u32 tmp;
182
183 DRM_DEBUG_KMS("\n");
184
185 mutex_lock(&dev_priv->sb_lock);
186
187 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
188 tmp &= ~DSI_PLL_VCO_EN;
189 tmp |= DSI_PLL_LDO_GATE;
190 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
191
192 mutex_unlock(&dev_priv->sb_lock);
193}
194
195static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
196{
197 bool enabled;
198 u32 val;
199 u32 mask;
200
201 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
202 val = I915_READ(BXT_DSI_PLL_ENABLE);
203 enabled = (val & mask) == mask;
204
205 if (!enabled)
206 return false;
207
208 /*
209 * Dividers must be programmed with valid values. As per BSEPC, for
210 * GEMINLAKE only PORT A divider values are checked while for BXT
211 * both divider values are validated. Check this here for
212 * paranoia, since BIOS is known to misconfigure PLLs in this way at
213 * times, and since accessing DSI registers with invalid dividers
214 * causes a system hang.
215 */
216 val = I915_READ(BXT_DSI_PLL_CTL);
217 if (IS_GEMINILAKE(dev_priv)) {
218 if (!(val & BXT_DSIA_16X_MASK)) {
219 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
220 enabled = false;
221 }
222 } else {
223 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
224 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
225 enabled = false;
226 }
227 }
228
229 return enabled;
230}
231
232static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
233{
234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
235 u32 val;
236
237 DRM_DEBUG_KMS("\n");
238
239 val = I915_READ(BXT_DSI_PLL_ENABLE);
240 val &= ~BXT_DSI_PLL_DO_ENABLE;
241 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
242
243 /*
244 * PLL lock should deassert within 200us.
245 * Wait up to 1ms before timing out.
246 */
247 if (intel_wait_for_register(dev_priv,
248 BXT_DSI_PLL_ENABLE,
249 BXT_DSI_PLL_LOCKED,
250 0,
251 1))
252 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
253}
254
255static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
256{
257 int bpp = mipi_dsi_pixel_format_to_bpp(fmt);
258
259 WARN(bpp != pipe_bpp,
260 "bpp match assertion failure (expected %d, current %d)\n",
261 bpp, pipe_bpp);
262}
263
264static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
265 struct intel_crtc_state *config)
266{
267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
269 u32 dsi_clock, pclk;
270 u32 pll_ctl, pll_div;
271 u32 m = 0, p = 0, n;
272 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
273 int i;
274
275 DRM_DEBUG_KMS("\n");
276
277 mutex_lock(&dev_priv->sb_lock);
278 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
279 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
280 mutex_unlock(&dev_priv->sb_lock);
281
282 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
283 config->dsi_pll.div = pll_div;
284
285 /* mask out other bits and extract the P1 divisor */
286 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
287 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
288
289 /* N1 divisor */
290 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
291 n = 1 << n; /* register has log2(N1) */
292
293 /* mask out the other bits and extract the M1 divisor */
294 pll_div &= DSI_PLL_M1_DIV_MASK;
295 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
296
297 while (pll_ctl) {
298 pll_ctl = pll_ctl >> 1;
299 p++;
300 }
301 p--;
302
303 if (!p) {
304 DRM_ERROR("wrong P1 divisor\n");
305 return 0;
306 }
307
308 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
309 if (lfsr_converts[i] == pll_div)
310 break;
311 }
312
313 if (i == ARRAY_SIZE(lfsr_converts)) {
314 DRM_ERROR("wrong m_seed programmed\n");
315 return 0;
316 }
317
318 m = i + 62;
319
320 dsi_clock = (m * refclk) / (p * n);
321
322 /* pixel_format and pipe_bpp should agree */
323 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
324
325 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
326
327 return pclk;
328}
329
330static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
331 struct intel_crtc_state *config)
332{
333 u32 pclk;
334 u32 dsi_clk;
335 u32 dsi_ratio;
336 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
338
339 /* Divide by zero */
340 if (!pipe_bpp) {
341 DRM_ERROR("Invalid BPP(0)\n");
342 return 0;
343 }
344
345 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
346
347 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
348
349 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
350
351 /* pixel_format and pipe_bpp should agree */
352 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
353
354 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
355
356 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
357 return pclk;
358}
359
360u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
361 struct intel_crtc_state *config)
362{
363 if (IS_GEN9_LP(to_i915(encoder->base.dev)))
364 return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
365 else
366 return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
367}
368
369static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
370{
371 u32 temp;
372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
373 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
374
375 temp = I915_READ(MIPI_CTRL(port));
376 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
377 I915_WRITE(MIPI_CTRL(port), temp |
378 intel_dsi->escape_clk_div <<
379 ESCAPE_CLOCK_DIVIDER_SHIFT);
380}
381
382static void glk_dsi_program_esc_clock(struct drm_device *dev,
383 const struct intel_crtc_state *config)
384{
385 struct drm_i915_private *dev_priv = to_i915(dev);
386 u32 dsi_rate = 0;
387 u32 pll_ratio = 0;
388 u32 ddr_clk = 0;
389 u32 div1_value = 0;
390 u32 div2_value = 0;
391 u32 txesc1_div = 0;
392 u32 txesc2_div = 0;
393
394 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
395
396 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
397
398 ddr_clk = dsi_rate / 2;
399
400 /* Variable divider value */
401 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
402
403 /* Calculate TXESC1 divider */
404 if (div1_value <= 10)
405 txesc1_div = div1_value;
406 else if ((div1_value > 10) && (div1_value <= 20))
407 txesc1_div = DIV_ROUND_UP(div1_value, 2);
408 else if ((div1_value > 20) && (div1_value <= 30))
409 txesc1_div = DIV_ROUND_UP(div1_value, 4);
410 else if ((div1_value > 30) && (div1_value <= 40))
411 txesc1_div = DIV_ROUND_UP(div1_value, 6);
412 else if ((div1_value > 40) && (div1_value <= 50))
413 txesc1_div = DIV_ROUND_UP(div1_value, 8);
414 else
415 txesc1_div = 10;
416
417 /* Calculate TXESC2 divider */
418 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
419
420 if (div2_value < 10)
421 txesc2_div = div2_value;
422 else
423 txesc2_div = 10;
424
425 I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
426 I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
427}
428
429/* Program BXT Mipi clocks and dividers */
430static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
431 const struct intel_crtc_state *config)
432{
433 struct drm_i915_private *dev_priv = to_i915(dev);
434 u32 tmp;
435 u32 dsi_rate = 0;
436 u32 pll_ratio = 0;
437 u32 rx_div;
438 u32 tx_div;
439 u32 rx_div_upper;
440 u32 rx_div_lower;
441 u32 mipi_8by3_divider;
442
443 /* Clear old configurations */
444 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
445 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
446 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
447 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
448 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
449
450 /* Get the current DSI rate(actual) */
451 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
452 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
453
454 /*
455 * tx clock should be <= 20MHz and the div value must be
456 * subtracted by 1 as per bspec
457 */
458 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
459 /*
460 * rx clock should be <= 150MHz and the div value must be
461 * subtracted by 1 as per bspec
462 */
463 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
464
465 /*
466 * rx divider value needs to be updated in the
467 * two differnt bit fields in the register hence splitting the
468 * rx divider value accordingly
469 */
470 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
471 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
472
473 mipi_8by3_divider = 0x2;
474
475 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
476 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
477 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
478 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
479
480 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
481}
482
483static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
484 struct intel_crtc_state *config)
485{
486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
487 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
488 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
489 u32 dsi_clk;
490
491 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
492 intel_dsi->lane_count);
493
494 /*
495 * From clock diagram, to get PLL ratio divider, divide double of DSI
496 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
497 * round 'up' the result
498 */
499 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
500
501 if (IS_BROXTON(dev_priv)) {
502 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
503 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
504 } else {
505 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
506 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
507 }
508
509 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
510 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
511 return -ECHRNG;
512 } else
513 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
514
515 /*
516 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
517 * Spec says both have to be programmed, even if one is not getting
518 * used. Configure MIPI_CLOCK_CTL dividers in modeset
519 */
520 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
521
522 /* As per recommendation from hardware team,
523 * Prog PVD ratio =1 if dsi ratio <= 50
524 */
525 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
526 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
527
528 return 0;
529}
530
531static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
532 const struct intel_crtc_state *config)
533{
534 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
535 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
536 enum port port;
537 u32 val;
538
539 DRM_DEBUG_KMS("\n");
540
541 /* Configure PLL vales */
542 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
543 POSTING_READ(BXT_DSI_PLL_CTL);
544
545 /* Program TX, RX, Dphy clocks */
546 if (IS_BROXTON(dev_priv)) {
547 for_each_dsi_port(port, intel_dsi->ports)
548 bxt_dsi_program_clocks(encoder->base.dev, port, config);
549 } else {
550 glk_dsi_program_esc_clock(encoder->base.dev, config);
551 }
552
553 /* Enable DSI PLL */
554 val = I915_READ(BXT_DSI_PLL_ENABLE);
555 val |= BXT_DSI_PLL_DO_ENABLE;
556 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
557
558 /* Timeout and fail if PLL not locked */
559 if (intel_wait_for_register(dev_priv,
560 BXT_DSI_PLL_ENABLE,
561 BXT_DSI_PLL_LOCKED,
562 BXT_DSI_PLL_LOCKED,
563 1)) {
564 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
565 return;
566 }
567
568 DRM_DEBUG_KMS("DSI PLL locked\n");
569}
570
571bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
572{
573 if (IS_GEN9_LP(dev_priv))
574 return bxt_dsi_pll_is_enabled(dev_priv);
575
576 MISSING_CASE(INTEL_DEVID(dev_priv));
577
578 return false;
579}
580
581int intel_compute_dsi_pll(struct intel_encoder *encoder,
582 struct intel_crtc_state *config)
583{
584 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
585
586 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
587 return vlv_compute_dsi_pll(encoder, config);
588 else if (IS_GEN9_LP(dev_priv))
589 return gen9lp_compute_dsi_pll(encoder, config);
590
591 return -ENODEV;
592}
593
594void intel_enable_dsi_pll(struct intel_encoder *encoder,
595 const struct intel_crtc_state *config)
596{
597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
598
599 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
600 vlv_enable_dsi_pll(encoder, config);
601 else if (IS_GEN9_LP(dev_priv))
602 gen9lp_enable_dsi_pll(encoder, config);
603}
604
605void intel_disable_dsi_pll(struct intel_encoder *encoder)
606{
607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
608
609 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
610 vlv_disable_dsi_pll(encoder);
611 else if (IS_GEN9_LP(dev_priv))
612 bxt_disable_dsi_pll(encoder);
613}
614
615static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
616 enum port port)
617{
618 u32 tmp;
619 struct drm_device *dev = encoder->base.dev;
620 struct drm_i915_private *dev_priv = to_i915(dev);
621
622 /* Clear old configurations */
623 if (IS_BROXTON(dev_priv)) {
624 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
625 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
626 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
627 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
628 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
629 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
630 } else {
631 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
632 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
633 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
634
635 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
636 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
637 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
638 }
639 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
640}
641
642void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
643{
644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
645
646 if (IS_GEN9_LP(dev_priv))
647 gen9lp_dsi_reset_clocks(encoder, port);
648 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
649 vlv_dsi_reset_clocks(encoder, port);
650}