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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <drm/drm_print.h>
26
27#include "intel_device_info.h"
28#include "i915_drv.h"
29
30#define PLATFORM_NAME(x) [INTEL_##x] = #x
31static const char * const platform_names[] = {
32 PLATFORM_NAME(I830),
33 PLATFORM_NAME(I845G),
34 PLATFORM_NAME(I85X),
35 PLATFORM_NAME(I865G),
36 PLATFORM_NAME(I915G),
37 PLATFORM_NAME(I915GM),
38 PLATFORM_NAME(I945G),
39 PLATFORM_NAME(I945GM),
40 PLATFORM_NAME(G33),
41 PLATFORM_NAME(PINEVIEW),
42 PLATFORM_NAME(I965G),
43 PLATFORM_NAME(I965GM),
44 PLATFORM_NAME(G45),
45 PLATFORM_NAME(GM45),
46 PLATFORM_NAME(IRONLAKE),
47 PLATFORM_NAME(SANDYBRIDGE),
48 PLATFORM_NAME(IVYBRIDGE),
49 PLATFORM_NAME(VALLEYVIEW),
50 PLATFORM_NAME(HASWELL),
51 PLATFORM_NAME(BROADWELL),
52 PLATFORM_NAME(CHERRYVIEW),
53 PLATFORM_NAME(SKYLAKE),
54 PLATFORM_NAME(BROXTON),
55 PLATFORM_NAME(KABYLAKE),
56 PLATFORM_NAME(GEMINILAKE),
57 PLATFORM_NAME(COFFEELAKE),
58 PLATFORM_NAME(CANNONLAKE),
59 PLATFORM_NAME(ICELAKE),
60};
61#undef PLATFORM_NAME
62
63const char *intel_platform_name(enum intel_platform platform)
64{
65 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
66
67 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
68 platform_names[platform] == NULL))
69 return "<unknown>";
70
71 return platform_names[platform];
72}
73
74void intel_device_info_dump_flags(const struct intel_device_info *info,
75 struct drm_printer *p)
76{
77#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
78 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
79#undef PRINT_FLAG
80}
81
82static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
83{
84 int s;
85
86 drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
87 drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
88 drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
89 for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) {
90 drm_printf(p, "slice%d %u subslices mask=%04x\n",
91 s, hweight8(sseu->subslice_mask[s]),
92 sseu->subslice_mask[s]);
93 }
94 drm_printf(p, "EU total: %u\n", sseu->eu_total);
95 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
96 drm_printf(p, "has slice power gating: %s\n",
97 yesno(sseu->has_slice_pg));
98 drm_printf(p, "has subslice power gating: %s\n",
99 yesno(sseu->has_subslice_pg));
100 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
101}
102
103void intel_device_info_dump_runtime(const struct intel_device_info *info,
104 struct drm_printer *p)
105{
106 sseu_dump(&info->sseu, p);
107
108 drm_printf(p, "CS timestamp frequency: %u kHz\n",
109 info->cs_timestamp_frequency_khz);
110}
111
112void intel_device_info_dump(const struct intel_device_info *info,
113 struct drm_printer *p)
114{
115 struct drm_i915_private *dev_priv =
116 container_of(info, struct drm_i915_private, info);
117
118 drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
119 INTEL_DEVID(dev_priv),
120 INTEL_REVID(dev_priv),
121 intel_platform_name(info->platform),
122 info->gen);
123
124 intel_device_info_dump_flags(info, p);
125}
126
127void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
128 struct drm_printer *p)
129{
130 int s, ss;
131
132 if (sseu->max_slices == 0) {
133 drm_printf(p, "Unavailable\n");
134 return;
135 }
136
137 for (s = 0; s < sseu->max_slices; s++) {
138 drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
139 s, hweight8(sseu->subslice_mask[s]),
140 sseu->subslice_mask[s]);
141
142 for (ss = 0; ss < sseu->max_subslices; ss++) {
143 u16 enabled_eus = sseu_get_eus(sseu, s, ss);
144
145 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
146 ss, hweight16(enabled_eus), enabled_eus);
147 }
148 }
149}
150
151static u16 compute_eu_total(const struct sseu_dev_info *sseu)
152{
153 u16 i, total = 0;
154
155 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
156 total += hweight8(sseu->eu_mask[i]);
157
158 return total;
159}
160
161static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
162{
163 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
164 const u32 fuse2 = I915_READ(GEN8_FUSE2);
165 int s, ss;
166 const int eu_mask = 0xff;
167 u32 subslice_mask, eu_en;
168
169 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
170 GEN10_F2_S_ENA_SHIFT;
171 sseu->max_slices = 6;
172 sseu->max_subslices = 4;
173 sseu->max_eus_per_subslice = 8;
174
175 subslice_mask = (1 << 4) - 1;
176 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
177 GEN10_F2_SS_DIS_SHIFT);
178
179 /*
180 * Slice0 can have up to 3 subslices, but there are only 2 in
181 * slice1/2.
182 */
183 sseu->subslice_mask[0] = subslice_mask;
184 for (s = 1; s < sseu->max_slices; s++)
185 sseu->subslice_mask[s] = subslice_mask & 0x3;
186
187 /* Slice0 */
188 eu_en = ~I915_READ(GEN8_EU_DISABLE0);
189 for (ss = 0; ss < sseu->max_subslices; ss++)
190 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
191 /* Slice1 */
192 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
193 eu_en = ~I915_READ(GEN8_EU_DISABLE1);
194 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
195 /* Slice2 */
196 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
197 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
198 /* Slice3 */
199 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
200 eu_en = ~I915_READ(GEN8_EU_DISABLE2);
201 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
202 /* Slice4 */
203 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
204 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
205 /* Slice5 */
206 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
207 eu_en = ~I915_READ(GEN10_EU_DISABLE3);
208 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
209
210 /* Do a second pass where we mark the subslices disabled if all their
211 * eus are off.
212 */
213 for (s = 0; s < sseu->max_slices; s++) {
214 for (ss = 0; ss < sseu->max_subslices; ss++) {
215 if (sseu_get_eus(sseu, s, ss) == 0)
216 sseu->subslice_mask[s] &= ~BIT(ss);
217 }
218 }
219
220 sseu->eu_total = compute_eu_total(sseu);
221
222 /*
223 * CNL is expected to always have a uniform distribution
224 * of EU across subslices with the exception that any one
225 * EU in any one subslice may be fused off for die
226 * recovery.
227 */
228 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
229 DIV_ROUND_UP(sseu->eu_total,
230 sseu_subslice_total(sseu)) : 0;
231
232 /* No restrictions on Power Gating */
233 sseu->has_slice_pg = 1;
234 sseu->has_subslice_pg = 1;
235 sseu->has_eu_pg = 1;
236}
237
238static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
239{
240 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
241 u32 fuse;
242
243 fuse = I915_READ(CHV_FUSE_GT);
244
245 sseu->slice_mask = BIT(0);
246 sseu->max_slices = 1;
247 sseu->max_subslices = 2;
248 sseu->max_eus_per_subslice = 8;
249
250 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
251 u8 disabled_mask =
252 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
253 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
254 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
255 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
256
257 sseu->subslice_mask[0] |= BIT(0);
258 sseu_set_eus(sseu, 0, 0, ~disabled_mask);
259 }
260
261 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
262 u8 disabled_mask =
263 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
264 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
265 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
266 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
267
268 sseu->subslice_mask[0] |= BIT(1);
269 sseu_set_eus(sseu, 0, 1, ~disabled_mask);
270 }
271
272 sseu->eu_total = compute_eu_total(sseu);
273
274 /*
275 * CHV expected to always have a uniform distribution of EU
276 * across subslices.
277 */
278 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
279 sseu->eu_total / sseu_subslice_total(sseu) :
280 0;
281 /*
282 * CHV supports subslice power gating on devices with more than
283 * one subslice, and supports EU power gating on devices with
284 * more than one EU pair per subslice.
285 */
286 sseu->has_slice_pg = 0;
287 sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
288 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
289}
290
291static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
292{
293 struct intel_device_info *info = mkwrite_device_info(dev_priv);
294 struct sseu_dev_info *sseu = &info->sseu;
295 int s, ss;
296 u32 fuse2, eu_disable, subslice_mask;
297 const u8 eu_mask = 0xff;
298
299 fuse2 = I915_READ(GEN8_FUSE2);
300 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
301
302 /* BXT has a single slice and at most 3 subslices. */
303 sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
304 sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
305 sseu->max_eus_per_subslice = 8;
306
307 /*
308 * The subslice disable field is global, i.e. it applies
309 * to each of the enabled slices.
310 */
311 subslice_mask = (1 << sseu->max_subslices) - 1;
312 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
313 GEN9_F2_SS_DIS_SHIFT);
314
315 /*
316 * Iterate through enabled slices and subslices to
317 * count the total enabled EU.
318 */
319 for (s = 0; s < sseu->max_slices; s++) {
320 if (!(sseu->slice_mask & BIT(s)))
321 /* skip disabled slice */
322 continue;
323
324 sseu->subslice_mask[s] = subslice_mask;
325
326 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
327 for (ss = 0; ss < sseu->max_subslices; ss++) {
328 int eu_per_ss;
329 u8 eu_disabled_mask;
330
331 if (!(sseu->subslice_mask[s] & BIT(ss)))
332 /* skip disabled subslice */
333 continue;
334
335 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
336
337 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
338
339 eu_per_ss = sseu->max_eus_per_subslice -
340 hweight8(eu_disabled_mask);
341
342 /*
343 * Record which subslice(s) has(have) 7 EUs. we
344 * can tune the hash used to spread work among
345 * subslices if they are unbalanced.
346 */
347 if (eu_per_ss == 7)
348 sseu->subslice_7eu[s] |= BIT(ss);
349 }
350 }
351
352 sseu->eu_total = compute_eu_total(sseu);
353
354 /*
355 * SKL is expected to always have a uniform distribution
356 * of EU across subslices with the exception that any one
357 * EU in any one subslice may be fused off for die
358 * recovery. BXT is expected to be perfectly uniform in EU
359 * distribution.
360 */
361 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
362 DIV_ROUND_UP(sseu->eu_total,
363 sseu_subslice_total(sseu)) : 0;
364 /*
365 * SKL+ supports slice power gating on devices with more than
366 * one slice, and supports EU power gating on devices with
367 * more than one EU pair per subslice. BXT+ supports subslice
368 * power gating on devices with more than one subslice, and
369 * supports EU power gating on devices with more than one EU
370 * pair per subslice.
371 */
372 sseu->has_slice_pg =
373 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
374 sseu->has_subslice_pg =
375 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
376 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
377
378 if (IS_GEN9_LP(dev_priv)) {
379#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
380 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
381
382 sseu->min_eu_in_pool = 0;
383 if (info->has_pooled_eu) {
384 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
385 sseu->min_eu_in_pool = 3;
386 else if (IS_SS_DISABLED(1))
387 sseu->min_eu_in_pool = 6;
388 else
389 sseu->min_eu_in_pool = 9;
390 }
391#undef IS_SS_DISABLED
392 }
393}
394
395static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
396{
397 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
398 int s, ss;
399 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
400
401 fuse2 = I915_READ(GEN8_FUSE2);
402 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
403 sseu->max_slices = 3;
404 sseu->max_subslices = 3;
405 sseu->max_eus_per_subslice = 8;
406
407 /*
408 * The subslice disable field is global, i.e. it applies
409 * to each of the enabled slices.
410 */
411 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
412 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
413 GEN8_F2_SS_DIS_SHIFT);
414
415 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
416 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
417 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
418 (32 - GEN8_EU_DIS0_S1_SHIFT));
419 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
420 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
421 (32 - GEN8_EU_DIS1_S2_SHIFT));
422
423 /*
424 * Iterate through enabled slices and subslices to
425 * count the total enabled EU.
426 */
427 for (s = 0; s < sseu->max_slices; s++) {
428 if (!(sseu->slice_mask & BIT(s)))
429 /* skip disabled slice */
430 continue;
431
432 sseu->subslice_mask[s] = subslice_mask;
433
434 for (ss = 0; ss < sseu->max_subslices; ss++) {
435 u8 eu_disabled_mask;
436 u32 n_disabled;
437
438 if (!(sseu->subslice_mask[ss] & BIT(ss)))
439 /* skip disabled subslice */
440 continue;
441
442 eu_disabled_mask =
443 eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
444
445 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
446
447 n_disabled = hweight8(eu_disabled_mask);
448
449 /*
450 * Record which subslices have 7 EUs.
451 */
452 if (sseu->max_eus_per_subslice - n_disabled == 7)
453 sseu->subslice_7eu[s] |= 1 << ss;
454 }
455 }
456
457 sseu->eu_total = compute_eu_total(sseu);
458
459 /*
460 * BDW is expected to always have a uniform distribution of EU across
461 * subslices with the exception that any one EU in any one subslice may
462 * be fused off for die recovery.
463 */
464 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
465 DIV_ROUND_UP(sseu->eu_total,
466 sseu_subslice_total(sseu)) : 0;
467
468 /*
469 * BDW supports slice power gating on devices with more than
470 * one slice.
471 */
472 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
473 sseu->has_subslice_pg = 0;
474 sseu->has_eu_pg = 0;
475}
476
477static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
478{
479 struct intel_device_info *info = mkwrite_device_info(dev_priv);
480 struct sseu_dev_info *sseu = &info->sseu;
481 u32 fuse1;
482 int s, ss;
483
484 /*
485 * There isn't a register to tell us how many slices/subslices. We
486 * work off the PCI-ids here.
487 */
488 switch (info->gt) {
489 default:
490 MISSING_CASE(info->gt);
491 /* fall through */
492 case 1:
493 sseu->slice_mask = BIT(0);
494 sseu->subslice_mask[0] = BIT(0);
495 break;
496 case 2:
497 sseu->slice_mask = BIT(0);
498 sseu->subslice_mask[0] = BIT(0) | BIT(1);
499 break;
500 case 3:
501 sseu->slice_mask = BIT(0) | BIT(1);
502 sseu->subslice_mask[0] = BIT(0) | BIT(1);
503 sseu->subslice_mask[1] = BIT(0) | BIT(1);
504 break;
505 }
506
507 sseu->max_slices = hweight8(sseu->slice_mask);
508 sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
509
510 fuse1 = I915_READ(HSW_PAVP_FUSE1);
511 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
512 default:
513 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
514 HSW_F1_EU_DIS_SHIFT);
515 /* fall through */
516 case HSW_F1_EU_DIS_10EUS:
517 sseu->eu_per_subslice = 10;
518 break;
519 case HSW_F1_EU_DIS_8EUS:
520 sseu->eu_per_subslice = 8;
521 break;
522 case HSW_F1_EU_DIS_6EUS:
523 sseu->eu_per_subslice = 6;
524 break;
525 }
526 sseu->max_eus_per_subslice = sseu->eu_per_subslice;
527
528 for (s = 0; s < sseu->max_slices; s++) {
529 for (ss = 0; ss < sseu->max_subslices; ss++) {
530 sseu_set_eus(sseu, s, ss,
531 (1UL << sseu->eu_per_subslice) - 1);
532 }
533 }
534
535 sseu->eu_total = compute_eu_total(sseu);
536
537 /* No powergating for you. */
538 sseu->has_slice_pg = 0;
539 sseu->has_subslice_pg = 0;
540 sseu->has_eu_pg = 0;
541}
542
543static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
544{
545 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
546 u32 base_freq, frac_freq;
547
548 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
549 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
550 base_freq *= 1000;
551
552 frac_freq = ((ts_override &
553 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
554 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
555 frac_freq = 1000 / (frac_freq + 1);
556
557 return base_freq + frac_freq;
558}
559
560static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
561{
562 u32 f12_5_mhz = 12500;
563 u32 f19_2_mhz = 19200;
564 u32 f24_mhz = 24000;
565
566 if (INTEL_GEN(dev_priv) <= 4) {
567 /* PRMs say:
568 *
569 * "The value in this register increments once every 16
570 * hclks." (through the “Clocking Configuration”
571 * (“CLKCFG”) MCHBAR register)
572 */
573 return dev_priv->rawclk_freq / 16;
574 } else if (INTEL_GEN(dev_priv) <= 8) {
575 /* PRMs say:
576 *
577 * "The PCU TSC counts 10ns increments; this timestamp
578 * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
579 * rolling over every 1.5 hours).
580 */
581 return f12_5_mhz;
582 } else if (INTEL_GEN(dev_priv) <= 9) {
583 u32 ctc_reg = I915_READ(CTC_MODE);
584 u32 freq = 0;
585
586 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
587 freq = read_reference_ts_freq(dev_priv);
588 } else {
589 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
590
591 /* Now figure out how the command stream's timestamp
592 * register increments from this frequency (it might
593 * increment only every few clock cycle).
594 */
595 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
596 CTC_SHIFT_PARAMETER_SHIFT);
597 }
598
599 return freq;
600 } else if (INTEL_GEN(dev_priv) <= 10) {
601 u32 ctc_reg = I915_READ(CTC_MODE);
602 u32 freq = 0;
603 u32 rpm_config_reg = 0;
604
605 /* First figure out the reference frequency. There are 2 ways
606 * we can compute the frequency, either through the
607 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
608 * tells us which one we should use.
609 */
610 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
611 freq = read_reference_ts_freq(dev_priv);
612 } else {
613 u32 crystal_clock;
614
615 rpm_config_reg = I915_READ(RPM_CONFIG0);
616 crystal_clock = (rpm_config_reg &
617 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
618 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
619 switch (crystal_clock) {
620 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
621 freq = f19_2_mhz;
622 break;
623 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
624 freq = f24_mhz;
625 break;
626 }
627
628 /* Now figure out how the command stream's timestamp
629 * register increments from this frequency (it might
630 * increment only every few clock cycle).
631 */
632 freq >>= 3 - ((rpm_config_reg &
633 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
634 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
635 }
636
637 return freq;
638 }
639
640 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
641 return 0;
642}
643
644/**
645 * intel_device_info_runtime_init - initialize runtime info
646 * @info: intel device info struct
647 *
648 * Determine various intel_device_info fields at runtime.
649 *
650 * Use it when either:
651 * - it's judged too laborious to fill n static structures with the limit
652 * when a simple if statement does the job,
653 * - run-time checks (eg read fuse/strap registers) are needed.
654 *
655 * This function needs to be called:
656 * - after the MMIO has been setup as we are reading registers,
657 * - after the PCH has been detected,
658 * - before the first usage of the fields it can tweak.
659 */
660void intel_device_info_runtime_init(struct intel_device_info *info)
661{
662 struct drm_i915_private *dev_priv =
663 container_of(info, struct drm_i915_private, info);
664 enum pipe pipe;
665
666 if (INTEL_GEN(dev_priv) >= 10) {
667 for_each_pipe(dev_priv, pipe)
668 info->num_scalers[pipe] = 2;
669 } else if (INTEL_GEN(dev_priv) == 9) {
670 info->num_scalers[PIPE_A] = 2;
671 info->num_scalers[PIPE_B] = 2;
672 info->num_scalers[PIPE_C] = 1;
673 }
674
675 BUILD_BUG_ON(I915_NUM_ENGINES >
676 sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
677
678 /*
679 * Skylake and Broxton currently don't expose the topmost plane as its
680 * use is exclusive with the legacy cursor and we only want to expose
681 * one of those, not both. Until we can safely expose the topmost plane
682 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
683 * we don't expose the topmost plane at all to prevent ABI breakage
684 * down the line.
685 */
686 if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
687 for_each_pipe(dev_priv, pipe)
688 info->num_sprites[pipe] = 3;
689 else if (IS_BROXTON(dev_priv)) {
690 info->num_sprites[PIPE_A] = 2;
691 info->num_sprites[PIPE_B] = 2;
692 info->num_sprites[PIPE_C] = 1;
693 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
694 for_each_pipe(dev_priv, pipe)
695 info->num_sprites[pipe] = 2;
696 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
697 for_each_pipe(dev_priv, pipe)
698 info->num_sprites[pipe] = 1;
699 }
700
701 if (i915_modparams.disable_display) {
702 DRM_INFO("Display disabled (module parameter)\n");
703 info->num_pipes = 0;
704 } else if (info->num_pipes > 0 &&
705 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
706 HAS_PCH_SPLIT(dev_priv)) {
707 u32 fuse_strap = I915_READ(FUSE_STRAP);
708 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
709
710 /*
711 * SFUSE_STRAP is supposed to have a bit signalling the display
712 * is fused off. Unfortunately it seems that, at least in
713 * certain cases, fused off display means that PCH display
714 * reads don't land anywhere. In that case, we read 0s.
715 *
716 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
717 * should be set when taking over after the firmware.
718 */
719 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
720 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
721 (HAS_PCH_CPT(dev_priv) &&
722 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
723 DRM_INFO("Display fused off, disabling\n");
724 info->num_pipes = 0;
725 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
726 DRM_INFO("PipeC fused off\n");
727 info->num_pipes -= 1;
728 }
729 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
730 u32 dfsm = I915_READ(SKL_DFSM);
731 u8 disabled_mask = 0;
732 bool invalid;
733 int num_bits;
734
735 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
736 disabled_mask |= BIT(PIPE_A);
737 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
738 disabled_mask |= BIT(PIPE_B);
739 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
740 disabled_mask |= BIT(PIPE_C);
741
742 num_bits = hweight8(disabled_mask);
743
744 switch (disabled_mask) {
745 case BIT(PIPE_A):
746 case BIT(PIPE_B):
747 case BIT(PIPE_A) | BIT(PIPE_B):
748 case BIT(PIPE_A) | BIT(PIPE_C):
749 invalid = true;
750 break;
751 default:
752 invalid = false;
753 }
754
755 if (num_bits > info->num_pipes || invalid)
756 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
757 disabled_mask);
758 else
759 info->num_pipes -= num_bits;
760 }
761
762 /* Initialize slice/subslice/EU info */
763 if (IS_HASWELL(dev_priv))
764 haswell_sseu_info_init(dev_priv);
765 else if (IS_CHERRYVIEW(dev_priv))
766 cherryview_sseu_info_init(dev_priv);
767 else if (IS_BROADWELL(dev_priv))
768 broadwell_sseu_info_init(dev_priv);
769 else if (INTEL_GEN(dev_priv) == 9)
770 gen9_sseu_info_init(dev_priv);
771 else if (INTEL_GEN(dev_priv) >= 10)
772 gen10_sseu_info_init(dev_priv);
773
774 /* Initialize command stream timestamp frequency */
775 info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
776}
777
778void intel_driver_caps_print(const struct intel_driver_caps *caps,
779 struct drm_printer *p)
780{
781 drm_printf(p, "scheduler: %x\n", caps->scheduler);
782}