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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Mika Kuoppala <mika.kuoppala@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_renderstate.h"
30
31static const struct intel_renderstate_rodata *
32render_state_get_rodata(struct drm_device *dev, const int gen)
33{
34 switch (gen) {
35 case 6:
36 return &gen6_null_state;
37 case 7:
38 return &gen7_null_state;
39 case 8:
40 return &gen8_null_state;
41 case 9:
42 return &gen9_null_state;
43 }
44
45 return NULL;
46}
47
48static int render_state_init(struct render_state *so, struct drm_device *dev)
49{
50 int ret;
51
52 so->gen = INTEL_INFO(dev)->gen;
53 so->rodata = render_state_get_rodata(dev, so->gen);
54 if (so->rodata == NULL)
55 return 0;
56
57 if (so->rodata->batch_items * 4 > 4096)
58 return -EINVAL;
59
60 so->obj = i915_gem_alloc_object(dev, 4096);
61 if (so->obj == NULL)
62 return -ENOMEM;
63
64 ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
65 if (ret)
66 goto free_gem;
67
68 so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);
69 return 0;
70
71free_gem:
72 drm_gem_object_unreference(&so->obj->base);
73 return ret;
74}
75
76/*
77 * Macro to add commands to auxiliary batch.
78 * This macro only checks for page overflow before inserting the commands,
79 * this is sufficient as the null state generator makes the final batch
80 * with two passes to build command and state separately. At this point
81 * the size of both are known and it compacts them by relocating the state
82 * right after the commands taking care of aligment so we should sufficient
83 * space below them for adding new commands.
84 */
85#define OUT_BATCH(batch, i, val) \
86 do { \
87 if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) { \
88 ret = -ENOSPC; \
89 goto err_out; \
90 } \
91 (batch)[(i)++] = (val); \
92 } while(0)
93
94static int render_state_setup(struct render_state *so)
95{
96 const struct intel_renderstate_rodata *rodata = so->rodata;
97 unsigned int i = 0, reloc_index = 0;
98 struct page *page;
99 u32 *d;
100 int ret;
101
102 ret = i915_gem_object_set_to_cpu_domain(so->obj, true);
103 if (ret)
104 return ret;
105
106 page = i915_gem_object_get_dirty_page(so->obj, 0);
107 d = kmap(page);
108
109 while (i < rodata->batch_items) {
110 u32 s = rodata->batch[i];
111
112 if (i * 4 == rodata->reloc[reloc_index]) {
113 u64 r = s + so->ggtt_offset;
114 s = lower_32_bits(r);
115 if (so->gen >= 8) {
116 if (i + 1 >= rodata->batch_items ||
117 rodata->batch[i + 1] != 0) {
118 ret = -EINVAL;
119 goto err_out;
120 }
121
122 d[i++] = s;
123 s = upper_32_bits(r);
124 }
125
126 reloc_index++;
127 }
128
129 d[i++] = s;
130 }
131
132 while (i % CACHELINE_DWORDS)
133 OUT_BATCH(d, i, MI_NOOP);
134
135 so->aux_batch_offset = i * sizeof(u32);
136
137 OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
138 so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
139
140 /*
141 * Since we are sending length, we need to strictly conform to
142 * all requirements. For Gen2 this must be a multiple of 8.
143 */
144 so->aux_batch_size = ALIGN(so->aux_batch_size, 8);
145
146 kunmap(page);
147
148 ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
149 if (ret)
150 return ret;
151
152 if (rodata->reloc[reloc_index] != -1) {
153 DRM_ERROR("only %d relocs resolved\n", reloc_index);
154 return -EINVAL;
155 }
156
157 return 0;
158
159err_out:
160 kunmap(page);
161 return ret;
162}
163
164#undef OUT_BATCH
165
166void i915_gem_render_state_fini(struct render_state *so)
167{
168 i915_gem_object_ggtt_unpin(so->obj);
169 drm_gem_object_unreference(&so->obj->base);
170}
171
172int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
173 struct render_state *so)
174{
175 int ret;
176
177 if (WARN_ON(ring->id != RCS))
178 return -ENOENT;
179
180 ret = render_state_init(so, ring->dev);
181 if (ret)
182 return ret;
183
184 if (so->rodata == NULL)
185 return 0;
186
187 ret = render_state_setup(so);
188 if (ret) {
189 i915_gem_render_state_fini(so);
190 return ret;
191 }
192
193 return 0;
194}
195
196int i915_gem_render_state_init(struct drm_i915_gem_request *req)
197{
198 struct render_state so;
199 int ret;
200
201 ret = i915_gem_render_state_prepare(req->ring, &so);
202 if (ret)
203 return ret;
204
205 if (so.rodata == NULL)
206 return 0;
207
208 ret = req->ring->dispatch_execbuffer(req, so.ggtt_offset,
209 so.rodata->batch_items * 4,
210 I915_DISPATCH_SECURE);
211 if (ret)
212 goto out;
213
214 if (so.aux_batch_size > 8) {
215 ret = req->ring->dispatch_execbuffer(req,
216 (so.ggtt_offset +
217 so.aux_batch_offset),
218 so.aux_batch_size,
219 I915_DISPATCH_SECURE);
220 if (ret)
221 goto out;
222 }
223
224 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
225
226out:
227 i915_gem_render_state_fini(&so);
228 return ret;
229}
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Mika Kuoppala <mika.kuoppala@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "i915_gem_render_state.h"
30#include "intel_renderstate.h"
31
32struct intel_render_state {
33 const struct intel_renderstate_rodata *rodata;
34 struct drm_i915_gem_object *obj;
35 struct i915_vma *vma;
36 u32 batch_offset;
37 u32 batch_size;
38 u32 aux_offset;
39 u32 aux_size;
40};
41
42static const struct intel_renderstate_rodata *
43render_state_get_rodata(const struct intel_engine_cs *engine)
44{
45 if (engine->id != RCS)
46 return NULL;
47
48 switch (INTEL_GEN(engine->i915)) {
49 case 6:
50 return &gen6_null_state;
51 case 7:
52 return &gen7_null_state;
53 case 8:
54 return &gen8_null_state;
55 case 9:
56 return &gen9_null_state;
57 }
58
59 return NULL;
60}
61
62/*
63 * Macro to add commands to auxiliary batch.
64 * This macro only checks for page overflow before inserting the commands,
65 * this is sufficient as the null state generator makes the final batch
66 * with two passes to build command and state separately. At this point
67 * the size of both are known and it compacts them by relocating the state
68 * right after the commands taking care of alignment so we should sufficient
69 * space below them for adding new commands.
70 */
71#define OUT_BATCH(batch, i, val) \
72 do { \
73 if ((i) >= PAGE_SIZE / sizeof(u32)) \
74 goto err; \
75 (batch)[(i)++] = (val); \
76 } while(0)
77
78static int render_state_setup(struct intel_render_state *so,
79 struct drm_i915_private *i915)
80{
81 const struct intel_renderstate_rodata *rodata = so->rodata;
82 unsigned int i = 0, reloc_index = 0;
83 unsigned int needs_clflush;
84 u32 *d;
85 int ret;
86
87 ret = i915_gem_obj_prepare_shmem_write(so->obj, &needs_clflush);
88 if (ret)
89 return ret;
90
91 d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
92
93 while (i < rodata->batch_items) {
94 u32 s = rodata->batch[i];
95
96 if (i * 4 == rodata->reloc[reloc_index]) {
97 u64 r = s + so->vma->node.start;
98 s = lower_32_bits(r);
99 if (HAS_64BIT_RELOC(i915)) {
100 if (i + 1 >= rodata->batch_items ||
101 rodata->batch[i + 1] != 0)
102 goto err;
103
104 d[i++] = s;
105 s = upper_32_bits(r);
106 }
107
108 reloc_index++;
109 }
110
111 d[i++] = s;
112 }
113
114 if (rodata->reloc[reloc_index] != -1) {
115 DRM_ERROR("only %d relocs resolved\n", reloc_index);
116 goto err;
117 }
118
119 so->batch_offset = i915_ggtt_offset(so->vma);
120 so->batch_size = rodata->batch_items * sizeof(u32);
121
122 while (i % CACHELINE_DWORDS)
123 OUT_BATCH(d, i, MI_NOOP);
124
125 so->aux_offset = i * sizeof(u32);
126
127 if (HAS_POOLED_EU(i915)) {
128 /*
129 * We always program 3x6 pool config but depending upon which
130 * subslice is disabled HW drops down to appropriate config
131 * shown below.
132 *
133 * In the below table 2x6 config always refers to
134 * fused-down version, native 2x6 is not available and can
135 * be ignored
136 *
137 * SNo subslices config eu pool configuration
138 * -----------------------------------------------------------
139 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9)
140 * 2 ss0 disabled (2x6) - 0x00777000 (3+9)
141 * 3 ss1 disabled (2x6) - 0x00770000 (6+6)
142 * 4 ss2 disabled (2x6) - 0x00007000 (9+3)
143 */
144 u32 eu_pool_config = 0x00777000;
145
146 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
147 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
148 OUT_BATCH(d, i, eu_pool_config);
149 OUT_BATCH(d, i, 0);
150 OUT_BATCH(d, i, 0);
151 OUT_BATCH(d, i, 0);
152 }
153
154 OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
155 so->aux_size = i * sizeof(u32) - so->aux_offset;
156 so->aux_offset += so->batch_offset;
157 /*
158 * Since we are sending length, we need to strictly conform to
159 * all requirements. For Gen2 this must be a multiple of 8.
160 */
161 so->aux_size = ALIGN(so->aux_size, 8);
162
163 if (needs_clflush)
164 drm_clflush_virt_range(d, i * sizeof(u32));
165 kunmap_atomic(d);
166
167 ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
168out:
169 i915_gem_obj_finish_shmem_access(so->obj);
170 return ret;
171
172err:
173 kunmap_atomic(d);
174 ret = -EINVAL;
175 goto out;
176}
177
178#undef OUT_BATCH
179
180int i915_gem_render_state_emit(struct i915_request *rq)
181{
182 struct intel_engine_cs *engine = rq->engine;
183 struct intel_render_state so = {}; /* keep the compiler happy */
184 int err;
185
186 so.rodata = render_state_get_rodata(engine);
187 if (!so.rodata)
188 return 0;
189
190 if (so.rodata->batch_items * 4 > PAGE_SIZE)
191 return -EINVAL;
192
193 so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
194 if (IS_ERR(so.obj))
195 return PTR_ERR(so.obj);
196
197 so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.base, NULL);
198 if (IS_ERR(so.vma)) {
199 err = PTR_ERR(so.vma);
200 goto err_obj;
201 }
202
203 err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
204 if (err)
205 goto err_vma;
206
207 err = render_state_setup(&so, rq->i915);
208 if (err)
209 goto err_unpin;
210
211 err = engine->emit_bb_start(rq,
212 so.batch_offset, so.batch_size,
213 I915_DISPATCH_SECURE);
214 if (err)
215 goto err_unpin;
216
217 if (so.aux_size > 8) {
218 err = engine->emit_bb_start(rq,
219 so.aux_offset, so.aux_size,
220 I915_DISPATCH_SECURE);
221 if (err)
222 goto err_unpin;
223 }
224
225 i915_vma_move_to_active(so.vma, rq, 0);
226err_unpin:
227 i915_vma_unpin(so.vma);
228err_vma:
229 i915_vma_close(so.vma);
230err_obj:
231 __i915_gem_object_release_unless_active(so.obj);
232 return err;
233}