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1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/spinlock.h>
19
20#include <asm/mach-ath79/ath79.h>
21#include <asm/mach-ath79/ar71xx_regs.h>
22#include "common.h"
23
24static DEFINE_SPINLOCK(ath79_device_reset_lock);
25
26u32 ath79_cpu_freq;
27EXPORT_SYMBOL_GPL(ath79_cpu_freq);
28
29u32 ath79_ahb_freq;
30EXPORT_SYMBOL_GPL(ath79_ahb_freq);
31
32u32 ath79_ddr_freq;
33EXPORT_SYMBOL_GPL(ath79_ddr_freq);
34
35enum ath79_soc_type ath79_soc;
36unsigned int ath79_soc_rev;
37
38void __iomem *ath79_pll_base;
39void __iomem *ath79_reset_base;
40EXPORT_SYMBOL_GPL(ath79_reset_base);
41static void __iomem *ath79_ddr_base;
42static void __iomem *ath79_ddr_wb_flush_base;
43static void __iomem *ath79_ddr_pci_win_base;
44
45void ath79_ddr_ctrl_init(void)
46{
47 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
48 AR71XX_DDR_CTRL_SIZE);
49 if (soc_is_ar71xx() || soc_is_ar934x()) {
50 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
51 ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
52 } else {
53 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
54 ath79_ddr_pci_win_base = 0;
55 }
56}
57EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
58
59void ath79_ddr_wb_flush(u32 reg)
60{
61 void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
62
63 /* Flush the DDR write buffer. */
64 __raw_writel(0x1, flush_reg);
65 while (__raw_readl(flush_reg) & 0x1)
66 ;
67
68 /* It must be run twice. */
69 __raw_writel(0x1, flush_reg);
70 while (__raw_readl(flush_reg) & 0x1)
71 ;
72}
73EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
74
75void ath79_ddr_set_pci_windows(void)
76{
77 BUG_ON(!ath79_ddr_pci_win_base);
78
79 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
80 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
81 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
82 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
83 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
84 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
85 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
86 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
87}
88EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
89
90void ath79_device_reset_set(u32 mask)
91{
92 unsigned long flags;
93 u32 reg;
94 u32 t;
95
96 if (soc_is_ar71xx())
97 reg = AR71XX_RESET_REG_RESET_MODULE;
98 else if (soc_is_ar724x())
99 reg = AR724X_RESET_REG_RESET_MODULE;
100 else if (soc_is_ar913x())
101 reg = AR913X_RESET_REG_RESET_MODULE;
102 else if (soc_is_ar933x())
103 reg = AR933X_RESET_REG_RESET_MODULE;
104 else if (soc_is_ar934x())
105 reg = AR934X_RESET_REG_RESET_MODULE;
106 else if (soc_is_qca955x())
107 reg = QCA955X_RESET_REG_RESET_MODULE;
108 else
109 BUG();
110
111 spin_lock_irqsave(&ath79_device_reset_lock, flags);
112 t = ath79_reset_rr(reg);
113 ath79_reset_wr(reg, t | mask);
114 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
115}
116EXPORT_SYMBOL_GPL(ath79_device_reset_set);
117
118void ath79_device_reset_clear(u32 mask)
119{
120 unsigned long flags;
121 u32 reg;
122 u32 t;
123
124 if (soc_is_ar71xx())
125 reg = AR71XX_RESET_REG_RESET_MODULE;
126 else if (soc_is_ar724x())
127 reg = AR724X_RESET_REG_RESET_MODULE;
128 else if (soc_is_ar913x())
129 reg = AR913X_RESET_REG_RESET_MODULE;
130 else if (soc_is_ar933x())
131 reg = AR933X_RESET_REG_RESET_MODULE;
132 else if (soc_is_ar934x())
133 reg = AR934X_RESET_REG_RESET_MODULE;
134 else if (soc_is_qca955x())
135 reg = QCA955X_RESET_REG_RESET_MODULE;
136 else
137 BUG();
138
139 spin_lock_irqsave(&ath79_device_reset_lock, flags);
140 t = ath79_reset_rr(reg);
141 ath79_reset_wr(reg, t & ~mask);
142 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
143}
144EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/export.h>
17#include <linux/types.h>
18#include <linux/spinlock.h>
19
20#include <asm/mach-ath79/ath79.h>
21#include <asm/mach-ath79/ar71xx_regs.h>
22#include "common.h"
23
24static DEFINE_SPINLOCK(ath79_device_reset_lock);
25
26u32 ath79_cpu_freq;
27EXPORT_SYMBOL_GPL(ath79_cpu_freq);
28
29u32 ath79_ahb_freq;
30EXPORT_SYMBOL_GPL(ath79_ahb_freq);
31
32u32 ath79_ddr_freq;
33EXPORT_SYMBOL_GPL(ath79_ddr_freq);
34
35enum ath79_soc_type ath79_soc;
36unsigned int ath79_soc_rev;
37
38void __iomem *ath79_pll_base;
39void __iomem *ath79_reset_base;
40EXPORT_SYMBOL_GPL(ath79_reset_base);
41static void __iomem *ath79_ddr_base;
42static void __iomem *ath79_ddr_wb_flush_base;
43static void __iomem *ath79_ddr_pci_win_base;
44
45void ath79_ddr_ctrl_init(void)
46{
47 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
48 AR71XX_DDR_CTRL_SIZE);
49 if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
50 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
51 ath79_ddr_pci_win_base = 0;
52 } else {
53 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
54 ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
55 }
56}
57EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
58
59void ath79_ddr_wb_flush(u32 reg)
60{
61 void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
62
63 /* Flush the DDR write buffer. */
64 __raw_writel(0x1, flush_reg);
65 while (__raw_readl(flush_reg) & 0x1)
66 ;
67
68 /* It must be run twice. */
69 __raw_writel(0x1, flush_reg);
70 while (__raw_readl(flush_reg) & 0x1)
71 ;
72}
73EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
74
75void ath79_ddr_set_pci_windows(void)
76{
77 BUG_ON(!ath79_ddr_pci_win_base);
78
79 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
80 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
81 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
82 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
83 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
84 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
85 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
86 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
87}
88EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
89
90void ath79_device_reset_set(u32 mask)
91{
92 unsigned long flags;
93 u32 reg;
94 u32 t;
95
96 if (soc_is_ar71xx())
97 reg = AR71XX_RESET_REG_RESET_MODULE;
98 else if (soc_is_ar724x())
99 reg = AR724X_RESET_REG_RESET_MODULE;
100 else if (soc_is_ar913x())
101 reg = AR913X_RESET_REG_RESET_MODULE;
102 else if (soc_is_ar933x())
103 reg = AR933X_RESET_REG_RESET_MODULE;
104 else if (soc_is_ar934x())
105 reg = AR934X_RESET_REG_RESET_MODULE;
106 else if (soc_is_qca955x())
107 reg = QCA955X_RESET_REG_RESET_MODULE;
108 else
109 BUG();
110
111 spin_lock_irqsave(&ath79_device_reset_lock, flags);
112 t = ath79_reset_rr(reg);
113 ath79_reset_wr(reg, t | mask);
114 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
115}
116EXPORT_SYMBOL_GPL(ath79_device_reset_set);
117
118void ath79_device_reset_clear(u32 mask)
119{
120 unsigned long flags;
121 u32 reg;
122 u32 t;
123
124 if (soc_is_ar71xx())
125 reg = AR71XX_RESET_REG_RESET_MODULE;
126 else if (soc_is_ar724x())
127 reg = AR724X_RESET_REG_RESET_MODULE;
128 else if (soc_is_ar913x())
129 reg = AR913X_RESET_REG_RESET_MODULE;
130 else if (soc_is_ar933x())
131 reg = AR933X_RESET_REG_RESET_MODULE;
132 else if (soc_is_ar934x())
133 reg = AR934X_RESET_REG_RESET_MODULE;
134 else if (soc_is_qca955x())
135 reg = QCA955X_RESET_REG_RESET_MODULE;
136 else
137 BUG();
138
139 spin_lock_irqsave(&ath79_device_reset_lock, flags);
140 t = ath79_reset_rr(reg);
141 ath79_reset_wr(reg, t & ~mask);
142 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
143}
144EXPORT_SYMBOL_GPL(ath79_device_reset_clear);