1/*
 2 * This header provides constants for Samsung audio subsystem
 3 * clock controller.
 4 *
 5 * The constants defined in this header are being used in dts
 6 * and exynos audss driver.
 7 */
 8
 9#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
10#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
11
12#define EXYNOS_MOUT_AUDSS	0
13#define EXYNOS_MOUT_I2S	1
14#define EXYNOS_DOUT_SRP	2
15#define EXYNOS_DOUT_AUD_BUS	3
16#define EXYNOS_DOUT_I2S	4
17#define EXYNOS_SRP_CLK		5
18#define EXYNOS_I2S_BUS		6
19#define EXYNOS_SCLK_I2S	7
20#define EXYNOS_PCM_BUS		8
21#define EXYNOS_SCLK_PCM	9
22#define EXYNOS_ADMA		10
23
24#define EXYNOS_AUDSS_MAX_CLKS	11
25
26#endif

 1/*
 2 * This header provides constants for Samsung audio subsystem
 3 * clock controller.
 4 *
 5 * The constants defined in this header are being used in dts
 6 * and exynos audss driver.
 7 */
 8
 9#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
10#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
11
12#define EXYNOS_MOUT_AUDSS	0
13#define EXYNOS_MOUT_I2S	1
14#define EXYNOS_DOUT_SRP	2
15#define EXYNOS_DOUT_AUD_BUS	3
16#define EXYNOS_DOUT_I2S	4
17#define EXYNOS_SRP_CLK		5
18#define EXYNOS_I2S_BUS		6
19#define EXYNOS_SCLK_I2S	7
20#define EXYNOS_PCM_BUS		8
21#define EXYNOS_SCLK_PCM	9
22#define EXYNOS_ADMA		10
23
24#define EXYNOS_AUDSS_MAX_CLKS	11
25
26#endif